1 /* SPDX-License-Identifier: Apache-2.0 OR MIT */
2 /*
3 * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
4 */
5
6 #define MODULE_TAG "vdpu383_com"
7
8 #include <string.h>
9
10 #include "mpp_log.h"
11 #include "mpp_buffer.h"
12 #include "mpp_common.h"
13 #include "mpp_compat_impl.h"
14 #include "mpp_frame_impl.h"
15
16 #include "vdpu383_com.h"
17
18 static RK_U32 rcb_coeff[RCB_BUF_COUNT] = {
19 [RCB_STRMD_ROW] = 3,
20 [RCB_STRMD_TILE_ROW] = 3,
21 [RCB_INTER_ROW] = 6,
22 [RCB_INTER_TILE_ROW] = 6,
23 [RCB_INTRA_ROW] = 5,
24 [RCB_INTRA_TILE_ROW] = 5,
25 [RCB_FILTERD_ROW] = 60,
26 [RCB_FILTERD_PROTECT_ROW] = 60,
27 [RCB_FILTERD_TILE_ROW] = 60,
28 [RCB_FILTERD_TILE_COL] = 90,
29 [RCB_FILTERD_AV1_UP_TILE_COL] = 0,
30 };
31
update_size_offset(Vdpu383RcbInfo * info,RK_U32 reg_idx,RK_S32 offset,RK_S32 len,RK_S32 idx)32 static RK_S32 update_size_offset(Vdpu383RcbInfo *info, RK_U32 reg_idx,
33 RK_S32 offset, RK_S32 len, RK_S32 idx)
34 {
35 RK_S32 buf_size = 0;
36
37 buf_size = 2 * MPP_ALIGN(len * rcb_coeff[idx], RCB_ALLINE_SIZE);
38 info[idx].reg_idx = reg_idx;
39 info[idx].offset = offset;
40 info[idx].size = buf_size;
41
42 return buf_size;
43 }
44
vdpu383_get_rcb_buf_size(Vdpu383RcbInfo * info,RK_S32 width,RK_S32 height)45 RK_S32 vdpu383_get_rcb_buf_size(Vdpu383RcbInfo *info, RK_S32 width, RK_S32 height)
46 {
47 RK_S32 offset = 0;
48
49 offset += update_size_offset(info, 140, offset, width, RCB_STRMD_ROW);
50 offset += update_size_offset(info, 142, offset, width, RCB_STRMD_TILE_ROW);
51 offset += update_size_offset(info, 144, offset, width, RCB_INTER_ROW);
52 offset += update_size_offset(info, 146, offset, width, RCB_INTER_TILE_ROW);
53 offset += update_size_offset(info, 148, offset, width, RCB_INTRA_ROW);
54 offset += update_size_offset(info, 150, offset, width, RCB_INTRA_TILE_ROW);
55 offset += update_size_offset(info, 152, offset, width, RCB_FILTERD_ROW);
56 offset += update_size_offset(info, 154, offset, width, RCB_FILTERD_PROTECT_ROW);
57 offset += update_size_offset(info, 156, offset, width, RCB_FILTERD_TILE_ROW);
58 offset += update_size_offset(info, 158, offset, height, RCB_FILTERD_TILE_COL);
59 offset += update_size_offset(info, 160, offset, height, RCB_FILTERD_AV1_UP_TILE_COL);
60
61 return offset;
62 }
63
vdpu383_setup_rcb(Vdpu383RegCommonAddr * reg,MppDev dev,MppBuffer buf,Vdpu383RcbInfo * info)64 void vdpu383_setup_rcb(Vdpu383RegCommonAddr *reg, MppDev dev,
65 MppBuffer buf, Vdpu383RcbInfo *info)
66 {
67 RK_U32 i;
68
69 reg->reg140_rcb_strmd_row_offset = mpp_buffer_get_fd(buf);
70 reg->reg142_rcb_strmd_tile_row_offset = mpp_buffer_get_fd(buf);
71 reg->reg144_rcb_inter_row_offset = mpp_buffer_get_fd(buf);
72 reg->reg146_rcb_inter_tile_row_offset = mpp_buffer_get_fd(buf);
73 reg->reg148_rcb_intra_row_offset = mpp_buffer_get_fd(buf);
74 reg->reg150_rcb_intra_tile_row_offset = mpp_buffer_get_fd(buf);
75 reg->reg152_rcb_filterd_row_offset = mpp_buffer_get_fd(buf);
76 reg->reg154_rcb_filterd_protect_row_offset = mpp_buffer_get_fd(buf);
77 reg->reg156_rcb_filterd_tile_row_offset = mpp_buffer_get_fd(buf);
78 reg->reg158_rcb_filterd_tile_col_offset = mpp_buffer_get_fd(buf);
79 reg->reg160_rcb_filterd_av1_upscale_tile_col_offset = mpp_buffer_get_fd(buf);
80
81 reg->reg141_rcb_strmd_row_len = info[RCB_STRMD_ROW].size ;
82 reg->reg143_rcb_strmd_tile_row_len = info[RCB_STRMD_TILE_ROW].size ;
83 reg->reg145_rcb_inter_row_len = info[RCB_INTER_ROW].size ;
84 reg->reg147_rcb_inter_tile_row_len = info[RCB_INTER_TILE_ROW].size ;
85 reg->reg149_rcb_intra_row_len = info[RCB_INTRA_ROW].size ;
86 reg->reg151_rcb_intra_tile_row_len = info[RCB_INTRA_TILE_ROW].size ;
87 reg->reg153_rcb_filterd_row_len = info[RCB_FILTERD_ROW].size ;
88 reg->reg155_rcb_filterd_protect_row_len = info[RCB_FILTERD_PROTECT_ROW].size;
89 reg->reg157_rcb_filterd_tile_row_len = info[RCB_FILTERD_TILE_ROW].size ;
90 reg->reg159_rcb_filterd_tile_col_len = info[RCB_FILTERD_TILE_COL].size ;
91 reg->reg161_rcb_filterd_av1_upscale_tile_col_len = info[RCB_FILTERD_AV1_UP_TILE_COL].size;
92
93 for (i = 0; i < RCB_BUF_COUNT; i++) {
94 if (info[i].offset)
95 mpp_dev_set_reg_offset(dev, info[i].reg_idx, info[i].offset);
96 }
97 }
98
vdpu383_compare_rcb_size(const void * a,const void * b)99 RK_S32 vdpu383_compare_rcb_size(const void *a, const void *b)
100 {
101 RK_S32 val = 0;
102 Vdpu383RcbInfo *p0 = (Vdpu383RcbInfo *)a;
103 Vdpu383RcbInfo *p1 = (Vdpu383RcbInfo *)b;
104
105 val = (p0->size > p1->size) ? -1 : 1;
106
107 return val;
108 }
109
vdpu383_setup_statistic(Vdpu383CtrlReg * ctrl_regs)110 void vdpu383_setup_statistic(Vdpu383CtrlReg *ctrl_regs)
111 {
112 ctrl_regs->reg28.axi_perf_work_e = 1;
113 ctrl_regs->reg28.axi_cnt_type = 1;
114 ctrl_regs->reg28.rd_latency_id = 11;
115
116 ctrl_regs->reg29.addr_align_type = 1;
117 ctrl_regs->reg29.ar_cnt_id_type = 0;
118 ctrl_regs->reg29.aw_cnt_id_type = 1;
119 ctrl_regs->reg29.ar_count_id = 17;
120 ctrl_regs->reg29.aw_count_id = 0;
121 ctrl_regs->reg29.rd_band_width_mode = 0;
122
123 /* set hurry */
124 ctrl_regs->reg30.axi_wr_qos = 0;
125 ctrl_regs->reg30.axi_rd_qos = 0;
126 }
127
vdpu383_afbc_align_calc(MppBufSlots slots,MppFrame frame,RK_U32 expand)128 void vdpu383_afbc_align_calc(MppBufSlots slots, MppFrame frame, RK_U32 expand)
129 {
130 RK_U32 ver_stride = 0;
131 RK_U32 img_height = mpp_frame_get_height(frame);
132 RK_U32 img_width = mpp_frame_get_width(frame);
133 RK_U32 hdr_stride = (*compat_ext_fbc_hdr_256_odd) ?
134 (MPP_ALIGN(img_width, 256) | 256) :
135 (MPP_ALIGN(img_width, 64));
136
137 mpp_slots_set_prop(slots, SLOTS_HOR_ALIGN, mpp_align_64);
138 mpp_slots_set_prop(slots, SLOTS_VER_ALIGN, mpp_align_16);
139
140 mpp_frame_set_fbc_hdr_stride(frame, hdr_stride);
141
142 ver_stride = mpp_align_16(img_height);
143 if (*compat_ext_fbc_buf_size) {
144 ver_stride += expand;
145 }
146 mpp_frame_set_ver_stride(frame, ver_stride);
147 }
148
vdpu383_set_rcbinfo(MppDev dev,Vdpu383RcbInfo * rcb_info)149 RK_S32 vdpu383_set_rcbinfo(MppDev dev, Vdpu383RcbInfo *rcb_info)
150 {
151 MppDevRcbInfoCfg rcb_cfg;
152 RK_U32 i;
153
154 Vdpu383RcbSetMode_e set_rcb_mode = RCB_SET_BY_PRIORITY_MODE;
155
156 RK_U32 rcb_priority[RCB_BUF_COUNT] = {
157 RCB_FILTERD_ROW,
158 RCB_INTER_ROW,
159 RCB_INTRA_ROW,
160 RCB_STRMD_ROW,
161 RCB_INTER_TILE_ROW,
162 RCB_INTRA_TILE_ROW,
163 RCB_STRMD_TILE_ROW,
164 RCB_FILTERD_TILE_ROW,
165 RCB_FILTERD_TILE_COL,
166 RCB_FILTERD_AV1_UP_TILE_COL,
167 RCB_FILTERD_PROTECT_ROW,
168 };
169 /*
170 * RCB_SET_BY_SIZE_SORT_MODE: by size sort
171 * RCB_SET_BY_PRIORITY_MODE: by priority
172 */
173
174 switch (set_rcb_mode) {
175 case RCB_SET_BY_SIZE_SORT_MODE : {
176 Vdpu383RcbInfo info[RCB_BUF_COUNT];
177
178 memcpy(info, rcb_info, sizeof(info));
179 qsort(info, MPP_ARRAY_ELEMS(info),
180 sizeof(info[0]), vdpu383_compare_rcb_size);
181
182 for (i = 0; i < MPP_ARRAY_ELEMS(info); i++) {
183 rcb_cfg.reg_idx = info[i].reg_idx;
184 rcb_cfg.size = info[i].size;
185 if (rcb_cfg.size > 0) {
186 mpp_dev_ioctl(dev, MPP_DEV_RCB_INFO, &rcb_cfg);
187 } else
188 break;
189 }
190 } break;
191 case RCB_SET_BY_PRIORITY_MODE : {
192 Vdpu383RcbInfo *info = rcb_info;
193 RK_U32 index = 0;
194
195 for (i = 0; i < MPP_ARRAY_ELEMS(rcb_priority); i ++) {
196 index = rcb_priority[i];
197
198 rcb_cfg.reg_idx = info[index].reg_idx;
199 rcb_cfg.size = info[index].size;
200 if (rcb_cfg.size > 0) {
201 mpp_dev_ioctl(dev, MPP_DEV_RCB_INFO, &rcb_cfg);
202 }
203 }
204 } break;
205 default:
206 break;
207 }
208
209 return 0;
210 }
211
vdpu383_update_thumbnail_frame_info(MppFrame frame)212 void vdpu383_update_thumbnail_frame_info(MppFrame frame)
213 {
214 RK_U32 down_scale_height = mpp_frame_get_height(frame) >> 1;
215 RK_U32 down_scale_width = mpp_frame_get_width(frame) >> 1;
216 RK_U32 down_scale_ver = MPP_ALIGN(down_scale_height, 16);
217 RK_U32 down_scale_hor = MPP_ALIGN(down_scale_width, 16);
218 RK_U32 down_scale_buf_size = 0;
219
220 if (!MPP_FRAME_FMT_IS_FBC(mpp_frame_get_fmt(frame))) {
221 down_scale_hor = mpp_align_128_odd_plus_64(down_scale_hor);
222 down_scale_ver = mpp_frame_get_ver_stride(frame) >> 1;
223 }
224
225 down_scale_buf_size = down_scale_hor * down_scale_ver * 3 / 2;
226 /*
227 * no matter what format, scale down image will output as 8bit raster format;
228 */
229 mpp_frame_set_fmt(frame, MPP_FMT_YUV420SP);
230 mpp_frame_set_width(frame, down_scale_width);
231 mpp_frame_set_height(frame, down_scale_height);
232 mpp_frame_set_hor_stride(frame, down_scale_hor);
233 mpp_frame_set_ver_stride(frame, down_scale_ver);
234 mpp_frame_set_buf_size(frame, down_scale_buf_size);
235 }
236
vdpu383_setup_down_scale(MppFrame frame,MppDev dev,Vdpu383CtrlReg * com,void * comParas)237 void vdpu383_setup_down_scale(MppFrame frame, MppDev dev, Vdpu383CtrlReg *com, void* comParas)
238 {
239 RK_U32 down_scale_height = mpp_frame_get_height(frame) >> 1;
240 RK_U32 down_scale_width = mpp_frame_get_width(frame) >> 1;
241 RK_U32 down_scale_ver = MPP_ALIGN(down_scale_height, 16);
242 RK_U32 down_scale_hor = MPP_ALIGN(down_scale_width, 16);
243
244 Vdpu383RegCommParas* paras = (Vdpu383RegCommParas*)comParas;
245 MppFrameFormat fmt = mpp_frame_get_fmt(frame);
246 MppMeta meta = mpp_frame_get_meta(frame);
247 RK_U32 down_scale_y_offset = 0;
248 RK_U32 down_scale_uv_offset = 0;
249 RK_U32 down_scale_y_virstride = down_scale_ver * down_scale_hor;
250 RK_U32 downscale_buf_size;
251
252 if (!MPP_FRAME_FMT_IS_FBC(mpp_frame_get_fmt(frame))) {
253 down_scale_hor = mpp_align_128_odd_plus_64(down_scale_hor);
254 down_scale_ver = mpp_frame_get_ver_stride(frame) >> 1;
255 down_scale_y_virstride = down_scale_ver * down_scale_hor;
256 }
257 /*
258 * no matter what format, scale down image will output as 8bit raster format;
259 * down_scale image buffer size was already added to the buf_size of mpp_frame,
260 * which was calculated in mpp_buf_slot.cpp: (size = original_size + scaledown_size)
261 */
262 switch ((fmt & MPP_FRAME_FMT_MASK)) {
263 case MPP_FMT_YUV400 : {
264 downscale_buf_size = down_scale_y_virstride;
265 } break;
266 case MPP_FMT_YUV420SP_10BIT :
267 case MPP_FMT_YUV420SP : {
268 downscale_buf_size = down_scale_y_virstride * 3 / 2;
269 } break;
270 case MPP_FMT_YUV422SP_10BIT :
271 case MPP_FMT_YUV422SP : {
272 downscale_buf_size = down_scale_y_virstride * 2;
273 } break;
274 case MPP_FMT_YUV444SP : {
275 downscale_buf_size = down_scale_y_virstride * 3;
276 } break;
277 default : {
278 downscale_buf_size = down_scale_y_virstride * 3 / 2;
279 } break;
280 }
281 downscale_buf_size = MPP_ALIGN(downscale_buf_size, 16);
282
283 down_scale_y_offset = MPP_ALIGN((mpp_frame_get_buf_size(frame) - downscale_buf_size), 16);
284 down_scale_uv_offset = down_scale_y_offset + down_scale_y_virstride;
285
286 com->reg9.scale_down_en = 1;
287 com->reg9.av1_fgs_en = 0;
288 paras->reg71_scl_ref_hor_virstride = down_scale_hor >> 4;
289 paras->reg72_scl_ref_raster_uv_hor_virstride = down_scale_hor >> 4;
290 if ((fmt & MPP_FRAME_FMT_MASK) == MPP_FMT_YUV444SP)
291 paras->reg72_scl_ref_raster_uv_hor_virstride = down_scale_hor >> 3;
292 paras->reg73_scl_ref_virstride = down_scale_y_virstride >> 4;
293 if (mpp_frame_get_thumbnail_en(frame) == MPP_FRAME_THUMBNAIL_MIXED) {
294 mpp_dev_set_reg_offset(dev, 133, down_scale_y_offset);
295 mpp_meta_set_s32(meta, KEY_DEC_TBN_Y_OFFSET, down_scale_y_offset);
296 mpp_meta_set_s32(meta, KEY_DEC_TBN_UV_OFFSET, down_scale_uv_offset);
297 }
298 }
299
300 #ifdef DUMP_VDPU383_DATAS
301 RK_U32 dump_cur_frame = 0;
302 char dump_cur_dir[128];
303 char dump_cur_fname_path[512];
304
flip_string(char * str)305 MPP_RET flip_string(char *str)
306 {
307 RK_U32 len = strlen(str);
308 RK_U32 i, j;
309
310 for (i = 0, j = len - 1; i <= j; i++, j--) {
311 // swapping characters
312 char c = str[i];
313 str[i] = str[j];
314 str[j] = c;
315 }
316
317 return MPP_OK;
318 }
319
dump_data_to_file(char * fname_path,void * data,RK_U32 data_bit_size,RK_U32 line_bits,RK_U32 big_end)320 MPP_RET dump_data_to_file(char *fname_path, void *data, RK_U32 data_bit_size,
321 RK_U32 line_bits, RK_U32 big_end)
322 {
323 RK_U8 *buf_p = (RK_U8 *)data;
324 RK_U8 cur_data;
325 RK_U32 i;
326 RK_U32 loop_cnt;
327 FILE *dump_fp = NULL;
328 char line_tmp[256];
329 RK_U32 str_idx = 0;
330
331 dump_fp = fopen(fname_path, "w+");
332 if (!dump_fp) {
333 mpp_err_f("open file: %s error!\n", fname_path);
334 return MPP_NOK;
335 }
336
337 if ((data_bit_size % 4 != 0) || (line_bits % 8 != 0)) {
338 mpp_err_f("line bits not align to 4!\n");
339 return MPP_NOK;
340 }
341
342 loop_cnt = data_bit_size / 8;
343 for (i = 0; i < loop_cnt; i++) {
344 cur_data = buf_p[i];
345
346 sprintf(&line_tmp[str_idx++], "%0x", cur_data & 0xf);
347 if ((i * 8 + 4) % line_bits == 0) {
348 line_tmp[str_idx++] = '\0';
349 str_idx = 0;
350 if (!big_end)
351 flip_string(line_tmp);
352 fprintf(dump_fp, "%s\n", line_tmp);
353 }
354 sprintf(&line_tmp[str_idx++], "%0x", (cur_data >> 4) & 0xf);
355 if ((i * 8 + 8) % line_bits == 0) {
356 line_tmp[str_idx++] = '\0';
357 str_idx = 0;
358 if (!big_end)
359 flip_string(line_tmp);
360 fprintf(dump_fp, "%s\n", line_tmp);
361 }
362 }
363
364 // last line
365 if (data_bit_size % 4) {
366 cur_data = buf_p[i];
367 sprintf(&line_tmp[str_idx++], "%0x", cur_data & 0xf);
368 if ((i * 8 + 8) % line_bits == 0) {
369 line_tmp[str_idx++] = '\0';
370 str_idx = 0;
371 if (!big_end)
372 flip_string(line_tmp);
373 fprintf(dump_fp, "%s\n", line_tmp);
374 }
375 }
376 if (data_bit_size % line_bits) {
377 loop_cnt = (line_bits - (data_bit_size % line_bits)) / 4;
378 for (i = 0; i < loop_cnt; i++)
379 sprintf(&line_tmp[str_idx++], "%0x", 0);
380 line_tmp[str_idx++] = '\0';
381 str_idx = 0;
382 if (!big_end)
383 flip_string(line_tmp);
384 fprintf(dump_fp, "%s\n", line_tmp);
385 }
386
387 fclose(dump_fp);
388
389 return MPP_OK;
390 }
391 #endif