1 /*
2 *
3 * Copyright 2015 Rockchip Electronics Co. LTD
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at
8 *
9 * http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16 */
17
18 #define MODULE_TAG "hal_h264d_vdpu_reg"
19
20 #include <stdio.h>
21 #include <stdlib.h>
22 #include <string.h>
23
24 #include "rk_type.h"
25 #include "mpp_err.h"
26 #include "mpp_mem.h"
27 #include "mpp_soc.h"
28 #include "mpp_common.h"
29
30 #include "hal_h264d_global.h"
31 #include "hal_h264d_api.h"
32 #include "hal_h264d_vdpu_com.h"
33 #include "hal_h264d_vdpu2.h"
34 #include "hal_h264d_vdpu2_reg.h"
35 #include "mpp_dec_cb_param.h"
36
37 const RK_U32 vdpu2_ref_idx[16] = {
38 84, 85, 86, 87, 88, 89, 90, 91,
39 92, 93, 94, 95, 96, 97, 98, 99
40 };
41
set_device_regs(H264dHalCtx_t * p_hal,H264dVdpuRegs_t * p_reg)42 static MPP_RET set_device_regs(H264dHalCtx_t *p_hal, H264dVdpuRegs_t *p_reg)
43 {
44 MPP_RET ret = MPP_ERR_UNKNOW;
45
46 p_reg->sw53.dec_fmt_sel = 0; //!< set H264 mode
47 p_reg->sw54.dec_out_endian = 1; //!< little endian
48 p_reg->sw54.dec_in_endian = 0; //!< big endian
49 p_reg->sw54.dec_strendian_e = 1; //!< little endian
50 p_reg->sw50.dec_tiled_msb = 0; //!< 0: raster scan 1: tiled
51 p_reg->sw56.dec_max_burlen = 16; //!< (0, 4, 8, 16) choice one
52 p_reg->sw50.dec_ascmd0_dis = 0; //!< disable
53 p_reg->sw50.adv_pref_dis = 0; //!< disable
54 p_reg->sw52.adv_pref_thrd = 8;
55 p_reg->sw50.adtion_latency = 0; //!< compensation for bus latency; values up to 63
56 p_reg->sw56.dec_data_discd_en = 0;
57 p_reg->sw54.dec_out_wordsp = 1;//!< little endian
58 p_reg->sw54.dec_in_wordsp = 1;//!< little endian
59 p_reg->sw54.dec_strm_wordsp = 1;//!< little endian
60 p_reg->sw57.timeout_sts_en = 1;
61 p_reg->sw57.dec_clkgate_en = 1;
62 p_reg->sw55.dec_irq_dis = 0;
63 //!< set AXI RW IDs
64 p_reg->sw56.dec_axi_id_rd = (0xFF & 0xFFU); //!< 0-255
65 p_reg->sw56.dec_axi_id_wr = (0x0 & 0xFFU); //!< 0-255
66 ///!< Set prediction filter taps
67 {
68 RK_U32 val = 0;
69 p_reg->sw59.pflt_set0_tap0 = 1;
70 val = (RK_U32)(-5);
71 p_reg->sw59.pflt_set0_tap1 = val;
72 p_reg->sw59.pflt_set0_tap2 = 20;
73 }
74 p_reg->sw50.adtion_latency = 0;
75 //!< clock_gating 0:clock always on, 1: clock gating module control the key(turn off when decoder free)
76 p_reg->sw57.dec_clkgate_en = 1;
77 p_reg->sw50.dec_tiled_msb = 0; //!< 0: raster scan 1: tiled
78 //!< bus_burst_length = 16, bus burst
79 p_reg->sw56.dec_max_burlen = 16;
80 p_reg->sw56.dec_data_discd_en = 0;
81 (void)p_hal;
82
83 return ret = MPP_OK;
84 }
85
set_refer_pic_idx(H264dVdpuRegs_t * p_regs,RK_U32 i,RK_U16 val)86 static MPP_RET set_refer_pic_idx(H264dVdpuRegs_t *p_regs, RK_U32 i, RK_U16 val)
87 {
88 switch (i) {
89 case 0:
90 p_regs->sw76.num_ref_idx0 = val;
91 break;
92 case 1:
93 p_regs->sw76.num_ref_idx1 = val;
94 break;
95 case 2:
96 p_regs->sw77.num_ref_idx2 = val;
97 break;
98 case 3:
99 p_regs->sw77.num_ref_idx3 = val;
100 break;
101 case 4:
102 p_regs->sw78.num_ref_idx4 = val;
103 break;
104 case 5:
105 p_regs->sw78.num_ref_idx5 = val;
106 break;
107 case 6:
108 p_regs->sw79.num_ref_idx6 = val;
109 break;
110 case 7:
111 p_regs->sw79.num_ref_idx7 = val;
112 break;
113 case 8:
114 p_regs->sw80.num_ref_idx8 = val;
115 break;
116 case 9:
117 p_regs->sw80.num_ref_idx9 = val;
118 break;
119 case 10:
120 p_regs->sw81.num_ref_idx10 = val;
121 break;
122 case 11:
123 p_regs->sw81.num_ref_idx11 = val;
124 break;
125 case 12:
126 p_regs->sw82.num_ref_idx12 = val;
127 break;
128 case 13:
129 p_regs->sw82.num_ref_idx13 = val;
130 break;
131 case 14:
132 p_regs->sw83.num_ref_idx14 = val;
133 break;
134 case 15:
135 p_regs->sw83.num_ref_idx15 = val;
136 break;
137 default:
138 break;
139 }
140
141 return MPP_OK;
142 }
143
set_refer_pic_list_p(H264dVdpuRegs_t * p_regs,RK_U32 i,RK_U16 val)144 static MPP_RET set_refer_pic_list_p(H264dVdpuRegs_t *p_regs, RK_U32 i,
145 RK_U16 val)
146 {
147 switch (i) {
148 case 0:
149 p_regs->sw106.init_reflist_pf0 = val;
150 break;
151 case 1:
152 p_regs->sw106.init_reflist_pf1 = val;
153 break;
154 case 2:
155 p_regs->sw106.init_reflist_pf2 = val;
156 break;
157 case 3:
158 p_regs->sw106.init_reflist_pf3 = val;
159 break;
160 case 4:
161 p_regs->sw74.init_reflist_pf4 = val;
162 break;
163 case 5:
164 p_regs->sw74.init_reflist_pf5 = val;
165 break;
166 case 6:
167 p_regs->sw74.init_reflist_pf6 = val;
168 break;
169 case 7:
170 p_regs->sw74.init_reflist_pf7 = val;
171 break;
172 case 8:
173 p_regs->sw74.init_reflist_pf8 = val;
174 break;
175 case 9:
176 p_regs->sw74.init_reflist_pf9 = val;
177 break;
178 case 10:
179 p_regs->sw75.init_reflist_pf10 = val;
180 break;
181 case 11:
182 p_regs->sw75.init_reflist_pf11 = val;
183 break;
184 case 12:
185 p_regs->sw75.init_reflist_pf12 = val;
186 break;
187 case 13:
188 p_regs->sw75.init_reflist_pf13 = val;
189 break;
190 case 14:
191 p_regs->sw75.init_reflist_pf14 = val;
192 break;
193 case 15:
194 p_regs->sw75.init_reflist_pf15 = val;
195 break;
196 default:
197 break;
198 }
199
200 return MPP_OK;
201 }
202
set_refer_pic_list_b0(H264dVdpuRegs_t * p_regs,RK_U32 i,RK_U16 val)203 static MPP_RET set_refer_pic_list_b0(H264dVdpuRegs_t *p_regs, RK_U32 i,
204 RK_U16 val)
205 {
206 switch (i) {
207 case 0:
208 p_regs->sw100.init_reflist_df0 = val;
209 break;
210 case 1:
211 p_regs->sw100.init_reflist_df1 = val;
212 break;
213 case 2:
214 p_regs->sw100.init_reflist_df2 = val;
215 break;
216 case 3:
217 p_regs->sw100.init_reflist_df3 = val;
218 break;
219 case 4:
220 p_regs->sw100.init_reflist_df4 = val;
221 break;
222 case 5:
223 p_regs->sw100.init_reflist_df5 = val;
224 break;
225 case 6:
226 p_regs->sw101.init_reflist_df6 = val;
227 break;
228 case 7:
229 p_regs->sw101.init_reflist_df7 = val;
230 break;
231 case 8:
232 p_regs->sw101.init_reflist_df8 = val;
233 break;
234 case 9:
235 p_regs->sw101.init_reflist_df9 = val;
236 break;
237 case 10:
238 p_regs->sw101.init_reflist_df10 = val;
239 break;
240 case 11:
241 p_regs->sw101.init_reflist_df11 = val;
242 break;
243 case 12:
244 p_regs->sw102.init_reflist_df12 = val;
245 break;
246 case 13:
247 p_regs->sw102.init_reflist_df13 = val;
248 break;
249 case 14:
250 p_regs->sw102.init_reflist_df14 = val;
251 break;
252 case 15:
253 p_regs->sw102.init_reflist_df15 = val;
254 break;
255 default:
256 break;
257 }
258
259 return MPP_OK;
260 }
261
set_refer_pic_list_b1(H264dVdpuRegs_t * p_regs,RK_U32 i,RK_U16 val)262 static MPP_RET set_refer_pic_list_b1(H264dVdpuRegs_t *p_regs, RK_U32 i,
263 RK_U16 val)
264 {
265 switch (i) {
266 case 0:
267 p_regs->sw103.init_reflist_db0 = val;
268 break;
269 case 1:
270 p_regs->sw103.init_reflist_db1 = val;
271 break;
272 case 2:
273 p_regs->sw103.init_reflist_db2 = val;
274 break;
275 case 3:
276 p_regs->sw103.init_reflist_db3 = val;
277 break;
278 case 4:
279 p_regs->sw103.init_reflist_db4 = val;
280 break;
281 case 5:
282 p_regs->sw103.init_reflist_db5 = val;
283 break;
284 case 6:
285 p_regs->sw104.init_reflist_db6 = val;
286 break;
287 case 7:
288 p_regs->sw104.init_reflist_db7 = val;
289 break;
290 case 8:
291 p_regs->sw104.init_reflist_db8 = val;
292 break;
293 case 9:
294 p_regs->sw104.init_reflist_db9 = val;
295 break;
296 case 10:
297 p_regs->sw104.init_reflist_db10 = val;
298 break;
299 case 11:
300 p_regs->sw104.init_reflist_db11 = val;
301 break;
302 case 12:
303 p_regs->sw105.init_reflist_db12 = val;
304 break;
305 case 13:
306 p_regs->sw105.init_reflist_db13 = val;
307 break;
308 case 14:
309 p_regs->sw105.init_reflist_db14 = val;
310 break;
311 case 15:
312 p_regs->sw105.init_reflist_db15 = val;
313 break;
314 default:
315 break;
316 }
317
318 return MPP_OK;
319 }
320
set_refer_pic_base_addr(H264dVdpuRegs_t * p_regs,RK_U32 i,RK_U32 val)321 static MPP_RET set_refer_pic_base_addr(H264dVdpuRegs_t *p_regs, RK_U32 i,
322 RK_U32 val)
323 {
324 switch (i) {
325 case 0:
326 p_regs->sw84.ref0_st_addr = val;
327 break;
328 case 1:
329 p_regs->sw85.ref1_st_addr = val;
330 break;
331 case 2:
332 p_regs->sw86.ref2_st_addr = val;
333 break;
334 case 3:
335 p_regs->sw87.ref3_st_addr = val;
336 break;
337 case 4:
338 p_regs->sw88.ref4_st_addr = val;
339 break;
340 case 5:
341 p_regs->sw89.ref5_st_addr = val;
342 break;
343 case 6:
344 p_regs->sw90.ref6_st_addr = val;
345 break;
346 case 7:
347 p_regs->sw91.ref7_st_addr = val;
348 break;
349 case 8:
350 p_regs->sw92.ref8_st_addr = val;
351 break;
352 case 9:
353 p_regs->sw93.ref9_st_addr = val;
354 break;
355 case 10:
356 p_regs->sw94.ref10_st_addr = val;
357 break;
358 case 11:
359 p_regs->sw95.ref11_st_addr = val;
360 break;
361 case 12:
362 p_regs->sw96.ref12_st_addr = val;
363 break;
364 case 13:
365 p_regs->sw97.ref13_st_addr = val;
366 break;
367 case 14:
368 p_regs->sw98.ref14_st_addr = val;
369 break;
370 case 15:
371 p_regs->sw99.ref15_st_addr = val;
372 break;
373 default:
374 break;
375 }
376 return MPP_OK;
377 }
378
set_pic_regs(H264dHalCtx_t * p_hal,H264dVdpuRegs_t * p_regs)379 static MPP_RET set_pic_regs(H264dHalCtx_t *p_hal, H264dVdpuRegs_t *p_regs)
380 {
381 MPP_RET ret = MPP_ERR_UNKNOW;
382
383 p_regs->sw110.pic_mb_w = p_hal->pp->wFrameWidthInMbsMinus1 + 1;
384 p_regs->sw110.pic_mb_h = (2 - p_hal->pp->frame_mbs_only_flag)
385 * (p_hal->pp->wFrameHeightInMbsMinus1 + 1);
386
387 return ret = MPP_OK;
388 }
389
set_vlc_regs(H264dHalCtx_t * p_hal,H264dVdpuRegs_t * p_regs)390 static MPP_RET set_vlc_regs(H264dHalCtx_t *p_hal, H264dVdpuRegs_t *p_regs)
391 {
392 RK_U32 i = 0;
393 MPP_RET ret = MPP_ERR_UNKNOW;
394 DXVA_PicParams_H264_MVC *pp = p_hal->pp;
395 RK_U32 validFlags = 0;
396 RK_U32 longTermTmp = 0, longTermflags = 0;
397
398 p_regs->sw57.dec_wr_extmen_dis = 0;
399 p_regs->sw57.rlc_mode_en = 0;
400 p_regs->sw51.qp_init_val = pp->pic_init_qp_minus26 + 26;
401 p_regs->sw114.max_refidx0 = pp->num_ref_idx_l0_active_minus1 + 1;
402 p_regs->sw111.max_refnum = pp->num_ref_frames;
403 p_regs->sw112.cur_frm_len = pp->log2_max_frame_num_minus4 + 4;
404 p_regs->sw112.curfrm_num = pp->frame_num;
405 p_regs->sw115.const_intra_en = pp->constrained_intra_pred_flag;
406 p_regs->sw112.dblk_ctrl_flag = pp->deblocking_filter_control_present_flag;
407 p_regs->sw112.rpcp_flag = pp->redundant_pic_cnt_present_flag;
408 p_regs->sw113.refpic_mk_len = p_hal->slice_long[0].drpm_used_bitlen;
409 p_regs->sw115.idr_pic_flag = p_hal->slice_long[0].idr_flag;
410 p_regs->sw113.idr_pic_id = p_hal->slice_long[0].idr_pic_id;
411 p_regs->sw114.pps_id = p_hal->slice_long[0].active_pps_id;
412 p_regs->sw114.poc_field_len = p_hal->slice_long[0].poc_used_bitlen;
413 /* reference picture flags, TODO separate fields */
414 if (pp->field_pic_flag) {
415 for (i = 0; i < 32; i++) {
416 if (pp->RefFrameList[i / 2].bPicEntry == 0xff) { //!< invalid
417 longTermflags <<= 1;
418 validFlags <<= 1;
419 } else {
420 longTermTmp = pp->RefFrameList[i / 2].AssociatedFlag; //!< get long term flag
421 longTermflags = (longTermflags << 1) | longTermTmp;
422
423 validFlags = (validFlags << 1)
424 | ((pp->UsedForReferenceFlags >> i) & 0x01);
425 }
426 }
427 p_regs->sw107.refpic_term_flag = longTermflags;
428 p_regs->sw108.refpic_valid_flag = validFlags;
429 } else {
430 for (i = 0; i < 16; i++) {
431 if (pp->RefFrameList[i].bPicEntry == 0xff) { //!< invalid
432 longTermflags <<= 1;
433 validFlags <<= 1;
434 } else {
435 RK_U32 use_flag = (pp->UsedForReferenceFlags >> (2 * i)) & 0x03;
436
437 longTermTmp = pp->RefFrameList[i].AssociatedFlag;
438 longTermflags = (longTermflags << 1) | longTermTmp;
439 validFlags = (validFlags << 1) | (use_flag > 0);
440 }
441 }
442 p_regs->sw107.refpic_term_flag = (longTermflags << 16);
443 p_regs->sw108.refpic_valid_flag = (validFlags << 16);
444 }
445
446 for (i = 0; i < 16; i++) {
447 if (pp->RefFrameList[i].bPicEntry != 0xff) { //!< valid
448 if (pp->RefFrameList[i].AssociatedFlag) { //!< longterm flag
449 set_refer_pic_idx(p_regs, i, pp->LongTermPicNumList[i]); //!< pic_num
450 } else {
451 set_refer_pic_idx(p_regs, i, pp->FrameNumList[i]); //< frame_num
452 }
453 }
454 }
455 p_regs->sw57.rd_cnt_tab_en = 1;
456 //!< set poc to buffer
457 {
458 H264dVdpuRegCtx_t *reg_ctx = (H264dVdpuRegCtx_t *)p_hal->reg_ctx;
459 RK_U32 *ptr = (RK_U32 *)reg_ctx->poc_ptr;
460
461 //!< set reference reorder poc
462 for (i = 0; i < 32; i++) {
463 if (pp->RefFrameList[i / 2].bPicEntry != 0xff) {
464 *ptr++ = pp->FieldOrderCntList[i / 2][i & 0x1];
465 } else {
466 *ptr++ = 0;
467 }
468 }
469 //!< set current poc
470 if (pp->field_pic_flag || !pp->MbaffFrameFlag) {
471 if (pp->field_pic_flag)
472 *ptr++ = pp->CurrFieldOrderCnt[pp->CurrPic.AssociatedFlag ? 1 : 0];
473 else
474 *ptr++ = MPP_MIN(pp->CurrFieldOrderCnt[0], pp->CurrFieldOrderCnt[1]);
475 } else {
476 *ptr++ = pp->CurrFieldOrderCnt[0];
477 *ptr++ = pp->CurrFieldOrderCnt[1];
478 }
479
480 #if DEBUG_REF_LIST
481 {
482 H264dVdpuRegCtx_t *reg_ctx = (H264dVdpuRegCtx_t *)p_hal->reg_ctx;
483 RK_U32 *ptr_tmp = (RK_U32 *)reg_ctx->poc_ptr;
484 RK_U32 *ref_reg = &p_regs->sw76;
485 char file_name[128];
486 sprintf(file_name, "/sdcard/test/mpp_pocbase_log.txt");
487 FILE *fp = fopen(file_name, "ab");
488 char buf[1024];
489 RK_S32 buf_len = 0, buf_size = sizeof(buf) - 1;
490
491 buf_len += snprintf(buf + buf_len, buf_size - buf_len, "=== poc_base filed %d fram_num %d ===\n",
492 pp->field_pic_flag || !pp->MbaffFrameFlag, pp->frame_num);
493 for (; ptr_tmp < ptr; ptr_tmp++)
494 buf_len += snprintf(buf + buf_len, buf_size - buf_len, "poc 0x%08x\n", *ptr_tmp);
495 buf_len += snprintf(buf + buf_len, buf_size - buf_len, "term_flag 0x%08x refpic_valid_flag 0x%08x \n",
496 longTermflags, validFlags);
497 for (i = 0; i < 8; i++)
498 buf_len += snprintf(buf + buf_len, buf_size - buf_len, "ref[%d] 0x%08x\n", i, ref_reg[i]);
499 fprintf(fp, "%s", buf);
500
501 fflush(fp);
502 fclose(fp);
503 }
504 #endif
505 }
506 p_regs->sw115.cabac_en = pp->entropy_coding_mode_flag;
507 //!< stream position update
508 {
509 MppBuffer bitstream_buf = NULL;
510 p_regs->sw57.st_code_exit = 1;
511 mpp_buf_slot_get_prop(p_hal->packet_slots,
512 p_hal->in_task->input,
513 SLOT_BUFFER, &bitstream_buf);
514 p_regs->sw109.strm_start_bit = 0; //!< sodb stream start bit
515 p_regs->sw64.rlc_vlc_st_adr = mpp_buffer_get_fd(bitstream_buf);
516 p_regs->sw51.stream_len = p_hal->strm_len;
517 }
518
519 return ret = MPP_OK;
520 }
521
set_ref_regs(H264dHalCtx_t * p_hal,H264dVdpuRegs_t * p_regs)522 static MPP_RET set_ref_regs(H264dHalCtx_t *p_hal, H264dVdpuRegs_t *p_regs)
523 {
524 MPP_RET ret = MPP_ERR_UNKNOW;
525 RK_U32 i = 0;
526 RK_U32 num_refs = 0;
527 RK_U32 num_reorder = 0;
528 H264dRefsList_t m_lists[3][16];
529 DXVA_PicParams_H264_MVC *pp = p_hal->pp;
530 RK_U32 max_frame_num = 1 << (pp->log2_max_frame_num_minus4 + 4);
531
532 // init list
533 memset(m_lists, 0, sizeof(m_lists));
534 for (i = 0; i < 16; i++) {
535 RK_U32 ref_flag = pp->UsedForReferenceFlags >> (2 * i) & 0x3;
536
537 m_lists[0][i].idx = i;
538 if (ref_flag) {
539 num_refs++;
540 m_lists[0][i].cur_poc = pp->CurrPic.AssociatedFlag
541 ? pp->CurrFieldOrderCnt[1] : pp->CurrFieldOrderCnt[0];
542 m_lists[0][i].ref_flag = ref_flag;
543 m_lists[0][i].lt_flag = pp->RefFrameList[i].AssociatedFlag;
544 if (m_lists[0][i].lt_flag) {
545 m_lists[0][i].ref_picnum = pp->LongTermPicNumList[i];
546 } else {
547 m_lists[0][i].ref_picnum = pp->FrameNumList[i] > pp->frame_num ?
548 (pp->FrameNumList[i] - max_frame_num) :
549 pp->FrameNumList[i];
550 }
551
552 if (ref_flag == 3) {
553 m_lists[0][i].ref_poc = MPP_MIN(pp->FieldOrderCntList[i][0], pp->FieldOrderCntList[i][1]);
554 } else if (ref_flag & 0x1) {
555 m_lists[0][i].ref_poc = pp->FieldOrderCntList[i][0];
556 } else if (ref_flag & 0x2) {
557 m_lists[0][i].ref_poc = pp->FieldOrderCntList[i][1];
558 }
559 #if DEBUG_REF_LIST
560 mpp_log("i %d ref_pic_num %d lt_flag %d ref_flag %d ref_poc %d cur_poc %d\n",
561 i, m_lists[0][i].ref_picnum, m_lists[0][i].lt_flag, ref_flag,
562 m_lists[0][i].ref_poc, m_lists[0][i].cur_poc);
563 #endif
564 num_reorder = i + 1;
565 }
566 }
567 /*
568 * the value of num_reorder may be greater than num_refs,
569 * e.g. v: valid x: invalid
570 * num_refs = 3, num_reorder = 4
571 * the index 1 will be reorder to the end
572 * ┌─┬─┬─┬─┬─┬─┬─┐
573 * │0│1│2│3│.│.│F│
574 * ├─┼─┼─┼─┼─┼─┼─┤
575 * │v│x│v│v│x│x│x│
576 * └─┴─┴─┴─┴─┴─┴─┘
577 */
578 memcpy(m_lists[1], m_lists[0], sizeof(m_lists[0]));
579 memcpy(m_lists[2], m_lists[0], sizeof(m_lists[0]));
580 qsort(m_lists[0], num_reorder, sizeof(m_lists[0][0]), compare_p);
581 qsort(m_lists[1], num_reorder, sizeof(m_lists[1][0]), compare_b0);
582 qsort(m_lists[2], num_reorder, sizeof(m_lists[2][0]), compare_b1);
583 if (num_refs > 1 && !p_hal->pp->field_pic_flag) {
584 if (!memcmp(m_lists[1], m_lists[2], sizeof(m_lists[1]))) {
585 MPP_SWAP(H264dRefsList_t, m_lists[2][0], m_lists[2][1]);
586 }
587 }
588
589 //!< list0 list1 listP
590 for (i = 0; i < 16; i++) {
591 set_refer_pic_list_p(p_regs, i, m_lists[0][i].idx);
592 set_refer_pic_list_b0(p_regs, i, m_lists[1][i].idx);
593 set_refer_pic_list_b1(p_regs, i, m_lists[2][i].idx);
594 }
595 #if DEBUG_REF_LIST
596 {
597 char file_name[128]; \
598 sprintf(file_name, "/sdcard/test/mpp2_RefPicList_log.txt"); \
599 FILE *fp = fopen(file_name, "ab"); \
600 char buf[1024];
601 RK_S32 buf_len = 0, buf_size = sizeof(buf) - 1;
602 // fwrite(buf, 1, size, fp);
603 buf_len += snprintf(buf + buf_len, buf_size - buf_len, "frame_num %d field %d bottom %d\n",
604 pp->frame_num, pp->field_pic_flag, pp->CurrPic.AssociatedFlag);
605 buf_len += snprintf(buf + buf_len, buf_size - buf_len, "list0 : ");
606 for (i = 0; i < 16; i++)
607 buf_len += snprintf(buf + buf_len, buf_size - buf_len, " %04d", m_lists[1][i]);
608 fprintf(fp, "%s\n", buf);
609
610 buf_len = 0;
611 buf_len += snprintf(buf + buf_len, buf_size - buf_len, "list1 : ");
612 for (i = 0; i < 16; i++)
613 buf_len += snprintf(buf + buf_len, buf_size - buf_len, " %04d", m_lists[2][i]);
614 fprintf(fp, "%s\n", buf);
615
616 buf_len = 0;
617 buf_len += snprintf(buf + buf_len, buf_size - buf_len, "listP : ");
618 for (i = 0; i < 16; i++)
619 buf_len += snprintf(buf + buf_len, buf_size - buf_len, " %04d", m_lists[0][i]);
620 fprintf(fp, "%s\n", buf);
621
622 fflush(fp); \
623 fclose(fp); \
624 }
625 #endif
626
627 return ret = MPP_OK;
628 }
629
set_asic_regs(H264dHalCtx_t * p_hal,H264dVdpuRegs_t * p_regs)630 static MPP_RET set_asic_regs(H264dHalCtx_t *p_hal, H264dVdpuRegs_t *p_regs)
631 {
632 RK_U32 i = 0, j = 0;
633 RK_U32 outPhyAddr = 0;
634 MppBuffer frame_buf = NULL;
635 MPP_RET ret = MPP_ERR_UNKNOW;
636 DXVA_PicParams_H264_MVC *pp = p_hal->pp;
637 DXVA_Slice_H264_Long *p_long = &p_hal->slice_long[0];
638
639 {
640 #if DEBUG_REF_LIST
641 char file_name[128]; \
642 sprintf(file_name, "/sdcard/test/mpp2_dpb_log.txt"); \
643 FILE *fp = fopen(file_name, "ab"); \
644 char buf[2048];
645 static RK_U32 num = 0;
646 RK_S32 buf_len = 0, buf_size = sizeof(buf) - 1;
647
648 buf_len += snprintf(buf + buf_len, buf_size - buf_len, "cnt %d frame_num %d field %d bottom %d\n",
649 num++, pp->frame_num, pp->field_pic_flag, pp->CurrPic.AssociatedFlag);
650 #endif
651 for (i = 0, j = 0xff; i < MPP_ARRAY_ELEMS(pp->RefFrameList); i++) {
652 RK_U32 val = 0;
653 RK_U32 top_closer = 0;
654 RK_U32 field_flag = 0;
655 RK_S32 cur_poc = 0;
656 RK_U32 used_flag = 0;
657
658 if (pp->RefFrameList[i].bPicEntry != 0xff) {
659 mpp_buf_slot_get_prop(p_hal->frame_slots,
660 pp->RefFrameList[i].Index7Bits,
661 SLOT_BUFFER, &frame_buf); //!< reference phy addr
662 j = i;
663 #if DEBUG_REF_LIST
664 buf_len += snprintf(buf + buf_len, buf_size - buf_len, "refPicList[%d], frame_num=%d, poc0=%d, poc1=%d\n",
665 i, pp->FrameNumList[i], pp->FieldOrderCntList[i][0], pp->FieldOrderCntList[i][1]);
666 #endif
667 } else {
668 mpp_buf_slot_get_prop(p_hal->frame_slots,
669 pp->CurrPic.Index7Bits,
670 SLOT_BUFFER, &frame_buf); //!< current out phy addr
671 }
672
673 field_flag = ((pp->RefPicFiledFlags >> i) & 0x1) ? 0x2 : 0;
674 cur_poc = pp->CurrPic.AssociatedFlag
675 ? pp->CurrFieldOrderCnt[1] : pp->CurrFieldOrderCnt[0];
676 used_flag = ((pp->UsedForReferenceFlags >> (2 * i)) & 0x3);
677 if (used_flag & 0x3) {
678 top_closer = MPP_ABS(pp->FieldOrderCntList[i][0] - cur_poc) <
679 MPP_ABS(pp->FieldOrderCntList[i][1] - cur_poc) ? 0x1 : 0;
680 } else if (used_flag & 0x2) {
681 top_closer = 0;
682 } else if (used_flag & 0x1) {
683 top_closer = 1;
684 }
685 val = top_closer | field_flag;
686 if (val) {
687 mpp_dev_set_reg_offset(p_hal->dev, vdpu2_ref_idx[i], val);
688 #if DEBUG_REF_LIST
689 buf_len += snprintf(buf + buf_len, buf_size - buf_len, "ref_offset[%d] %d\n",
690 i, val);
691 #endif
692 }
693 set_refer_pic_base_addr(p_regs, i, mpp_buffer_get_fd(frame_buf));
694 }
695 #if DEBUG_REF_LIST
696 fprintf(fp, "%s\n", buf);
697 fflush(fp);
698 fclose(fp);
699 #endif
700 }
701 /* inter-view reference picture */
702 {
703 H264dVdpuPriv_t *priv = (H264dVdpuPriv_t *)p_hal->priv;
704 if (pp->curr_layer_id && priv->ilt_dpb && priv->ilt_dpb->valid) {
705 mpp_buf_slot_get_prop(p_hal->frame_slots,
706 priv->ilt_dpb->slot_index,
707 SLOT_BUFFER, &frame_buf);
708 p_regs->sw99.ref15_st_addr = mpp_buffer_get_fd(frame_buf); //!< inter-view base, ref15
709 p_regs->sw108.refpic_valid_flag |= (pp->field_pic_flag
710 ? 0x3 : 0x10000);
711 }
712 }
713 p_regs->sw50.dec_fixed_quant = pp->curr_layer_id; //!< VDPU_MVC_E
714 p_regs->sw50.dblk_flt_dis = 0; //!< filterDisable = 0;
715 mpp_buf_slot_get_prop(p_hal->frame_slots,
716 pp->CurrPic.Index7Bits,
717 SLOT_BUFFER, &frame_buf); //!< current out phy addr
718 outPhyAddr = mpp_buffer_get_fd(frame_buf);
719 if (pp->field_pic_flag && pp->CurrPic.AssociatedFlag) {
720 mpp_dev_set_reg_offset(p_hal->dev, 63, ((pp->wFrameWidthInMbsMinus1 + 1) * 16));
721 }
722 p_regs->sw63.dec_out_st_adr = outPhyAddr; //!< outPhyAddr, pp->CurrPic.Index7Bits
723 p_regs->sw110.flt_offset_cb_qp = pp->chroma_qp_index_offset;
724 p_regs->sw110.flt_offset_cr_qp = pp->second_chroma_qp_index_offset;
725 /* set default value for register[41] to avoid illegal translation fd */
726 {
727 RK_U32 dirMvOffset = 0;
728 RK_U32 picSizeInMbs = 0;
729
730 picSizeInMbs = p_hal->pp->wFrameWidthInMbsMinus1 + 1;
731 picSizeInMbs = picSizeInMbs
732 * (2 - pp->frame_mbs_only_flag) * (pp->wFrameHeightInMbsMinus1 + 1);
733 dirMvOffset = picSizeInMbs
734 * ((p_hal->pp->chroma_format_idc == 0) ? 256 : 384);
735 dirMvOffset += (pp->field_pic_flag && pp->CurrPic.AssociatedFlag)
736 ? (picSizeInMbs * 32) : 0;
737 if (dirMvOffset) {
738 RK_U32 offset = mpp_get_ioctl_version() ? dirMvOffset : dirMvOffset >> 4;
739 mpp_dev_set_reg_offset(p_hal->dev, 62, offset);
740 }
741 p_regs->sw62.dmmv_st_adr = mpp_buffer_get_fd(frame_buf);
742 }
743 p_regs->sw57.dmmv_wr_en = (p_long->nal_ref_idc != 0) ? 1 : 0; //!< defalut set 1
744 p_regs->sw115.dlmv_method_en = pp->direct_8x8_inference_flag;
745 p_regs->sw115.weight_pred_en = pp->weighted_pred_flag;
746 p_regs->sw111.wp_bslice_sel = pp->weighted_bipred_idc;
747 p_regs->sw114.max_refidx1 = (pp->num_ref_idx_l1_active_minus1 + 1);
748 p_regs->sw115.fieldpic_flag_exist = (!pp->frame_mbs_only_flag) ? 1 : 0;
749 p_regs->sw57.curpic_code_sel = (!pp->frame_mbs_only_flag
750 && (pp->MbaffFrameFlag || pp->field_pic_flag)) ? 1 : 0;
751 p_regs->sw57.curpic_stru_sel = pp->field_pic_flag;
752 p_regs->sw57.pic_decfield_sel = (!pp->CurrPic.AssociatedFlag) ? 1 : 0; //!< bottomFieldFlag
753 p_regs->sw57.sequ_mbaff_en = pp->MbaffFrameFlag;
754 p_regs->sw115.tranf_8x8_flag_en = pp->transform_8x8_mode_flag;
755 p_regs->sw115.monochr_en = (p_long->profileIdc >= 100
756 && pp->chroma_format_idc == 0) ? 1 : 0;
757 p_regs->sw115.scl_matrix_en = pp->scaleing_list_enable_flag;
758 {
759 H264dVdpuRegCtx_t *reg_ctx = (H264dVdpuRegCtx_t *)p_hal->reg_ctx;
760 if (p_hal->pp->scaleing_list_enable_flag) {
761 RK_U32 temp = 0;
762 RK_U32 *ptr = (RK_U32 *)reg_ctx->sclst_ptr;
763
764 for (i = 0; i < 6; i++) {
765 for (j = 0; j < 4; j++) {
766 temp = (p_hal->qm->bScalingLists4x4[i][4 * j + 0] << 24) |
767 (p_hal->qm->bScalingLists4x4[i][4 * j + 1] << 16) |
768 (p_hal->qm->bScalingLists4x4[i][4 * j + 2] << 8) |
769 (p_hal->qm->bScalingLists4x4[i][4 * j + 3]);
770 *ptr++ = temp;
771 }
772 }
773 for (i = 0; i < 2; i++) {
774 for (j = 0; j < 16; j++) {
775 temp = (p_hal->qm->bScalingLists8x8[i][4 * j + 0] << 24) |
776 (p_hal->qm->bScalingLists8x8[i][4 * j + 1] << 16) |
777 (p_hal->qm->bScalingLists8x8[i][4 * j + 2] << 8) |
778 (p_hal->qm->bScalingLists8x8[i][4 * j + 3]);
779 *ptr++ = temp;
780 }
781 }
782 }
783 p_regs->sw61.qtable_st_adr = mpp_buffer_get_fd(reg_ctx->buf);
784 }
785 p_regs->sw57.dec_wr_extmen_dis = 0; //!< set defalut 0
786 p_regs->sw57.addit_ch_fmt_wen = 0;
787 p_regs->sw57.dec_st_work = 1;
788
789 return ret = MPP_OK;
790 }
791
792 /*!
793 ***********************************************************************
794 * \brief
795 * init VDPU granite decoder
796 ***********************************************************************
797 */
798 //extern "C"
vdpu2_h264d_init(void * hal,MppHalCfg * cfg)799 MPP_RET vdpu2_h264d_init(void *hal, MppHalCfg *cfg)
800 {
801 MPP_RET ret = MPP_ERR_UNKNOW;
802 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
803 INP_CHECK(ret, NULL == hal);
804
805 MEM_CHECK(ret, p_hal->priv = mpp_calloc_size(void,
806 sizeof(H264dVdpuPriv_t)));
807 MEM_CHECK(ret, p_hal->reg_ctx = mpp_calloc_size(void, sizeof(H264dVdpuRegCtx_t)));
808 H264dVdpuRegCtx_t *reg_ctx = (H264dVdpuRegCtx_t *)p_hal->reg_ctx;
809 //!< malloc buffers
810 {
811 RK_U32 i = 0;
812 RK_U32 loop = p_hal->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->reg_buf) : 1;
813
814 RK_U32 buf_size = VDPU_CABAC_TAB_SIZE + VDPU_POC_BUF_SIZE + VDPU_SCALING_LIST_SIZE;
815 for (i = 0; i < loop; i++) {
816 FUN_CHECK(ret = mpp_buffer_get(p_hal->buf_group, ®_ctx->reg_buf[i].buf, buf_size));
817 reg_ctx->reg_buf[i].cabac_ptr = mpp_buffer_get_ptr(reg_ctx->reg_buf[i].buf);
818 reg_ctx->reg_buf[i].poc_ptr = reg_ctx->reg_buf[i].cabac_ptr + VDPU_CABAC_TAB_SIZE;
819 reg_ctx->reg_buf[i].sclst_ptr = reg_ctx->reg_buf[i].poc_ptr + VDPU_POC_BUF_SIZE;
820 reg_ctx->reg_buf[i].regs = mpp_calloc_size(void, sizeof(H264dVdpuRegs_t));
821 //!< copy cabac table bytes
822 memcpy(reg_ctx->reg_buf[i].cabac_ptr, (void *)vdpu_cabac_table, sizeof(vdpu_cabac_table));
823 }
824 }
825
826 if (!p_hal->fast_mode) {
827 reg_ctx->buf = reg_ctx->reg_buf[0].buf;
828 reg_ctx->cabac_ptr = reg_ctx->reg_buf[0].cabac_ptr;
829 reg_ctx->poc_ptr = reg_ctx->reg_buf[0].poc_ptr;
830 reg_ctx->sclst_ptr = reg_ctx->reg_buf[0].sclst_ptr;
831 reg_ctx->regs = reg_ctx->reg_buf[0].regs;
832 }
833
834 mpp_slots_set_prop(p_hal->frame_slots, SLOTS_HOR_ALIGN, vdpu_hor_align);
835 mpp_slots_set_prop(p_hal->frame_slots, SLOTS_VER_ALIGN, vdpu_ver_align);
836
837 {
838 // report hw_info to parser
839 const MppSocInfo *info = mpp_get_soc_info();
840 const void *hw_info = NULL;
841 RK_U32 i;
842
843 for (i = 0; i < MPP_ARRAY_ELEMS(info->dec_caps); i++) {
844 if (info->dec_caps[i] && info->dec_caps[i]->type == VPU_CLIENT_VDPU2) {
845 hw_info = info->dec_caps[i];
846 break;
847 }
848 }
849
850 mpp_assert(hw_info);
851 cfg->hw_info = hw_info;
852 }
853
854 __RETURN:
855 return MPP_OK;
856 __FAILED:
857 vdpu2_h264d_deinit(hal);
858
859 return ret;
860 }
861
862
863 /*!
864 ***********************************************************************
865 * \brief
866 * deinit
867 ***********************************************************************
868 */
869 //extern "C"
vdpu2_h264d_deinit(void * hal)870 MPP_RET vdpu2_h264d_deinit(void *hal)
871 {
872 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
873 H264dVdpuRegCtx_t *reg_ctx = (H264dVdpuRegCtx_t *)p_hal->reg_ctx;
874
875 RK_U32 i = 0;
876 RK_U32 loop = p_hal->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->reg_buf) : 1;
877 for (i = 0; i < loop; i++) {
878 MPP_FREE(reg_ctx->reg_buf[i].regs);
879 mpp_buffer_put(reg_ctx->reg_buf[i].buf);
880 }
881
882 MPP_FREE(p_hal->reg_ctx);
883 MPP_FREE(p_hal->priv);
884
885 return MPP_OK;
886 }
887 /*!
888 ***********************************************************************
889 * \brief
890 * generate register
891 ***********************************************************************
892 */
893 //extern "C"
vdpu2_h264d_gen_regs(void * hal,HalTaskInfo * task)894 MPP_RET vdpu2_h264d_gen_regs(void *hal, HalTaskInfo *task)
895 {
896 MPP_RET ret = MPP_ERR_UNKNOW;
897
898 H264dVdpuPriv_t *priv = NULL;
899 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
900 INP_CHECK(ret, NULL == p_hal);
901 p_hal->in_task = &task->dec;
902
903 if (task->dec.flags.parse_err ||
904 task->dec.flags.ref_err) {
905 goto __RETURN;
906 }
907 priv = p_hal->priv;
908 priv->layed_id = p_hal->pp->curr_layer_id;
909
910 H264dVdpuRegCtx_t *reg_ctx = (H264dVdpuRegCtx_t *)p_hal->reg_ctx;
911 if (p_hal->fast_mode) {
912 RK_U32 i = 0;
913 for (i = 0; i < MPP_ARRAY_ELEMS(reg_ctx->reg_buf); i++) {
914 if (!reg_ctx->reg_buf[i].valid) {
915 task->dec.reg_index = i;
916 reg_ctx->buf = reg_ctx->reg_buf[i].buf;
917 reg_ctx->cabac_ptr = reg_ctx->reg_buf[i].cabac_ptr;
918 reg_ctx->poc_ptr = reg_ctx->reg_buf[i].poc_ptr;
919 reg_ctx->sclst_ptr = reg_ctx->reg_buf[i].sclst_ptr;
920 reg_ctx->regs = reg_ctx->reg_buf[i].regs;
921 reg_ctx->reg_buf[i].valid = 1;
922 break;
923 }
924 }
925 }
926
927 FUN_CHECK(ret = adjust_input(priv, &p_hal->slice_long[0], p_hal->pp));
928 FUN_CHECK(ret = set_device_regs(p_hal, (H264dVdpuRegs_t *)reg_ctx->regs));
929 FUN_CHECK(ret = set_pic_regs(p_hal, (H264dVdpuRegs_t *)reg_ctx->regs));
930 FUN_CHECK(ret = set_vlc_regs(p_hal, (H264dVdpuRegs_t *)reg_ctx->regs));
931 FUN_CHECK(ret = set_ref_regs(p_hal, (H264dVdpuRegs_t *)reg_ctx->regs));
932 FUN_CHECK(ret = set_asic_regs(p_hal, (H264dVdpuRegs_t *)reg_ctx->regs));
933
934 __RETURN:
935 return ret = MPP_OK;
936 __FAILED:
937 return ret;
938 }
939 /*!
940 ***********************************************************************
941 * \brief h
942 * start hard
943 ***********************************************************************
944 */
945 //extern "C"
vdpu2_h264d_start(void * hal,HalTaskInfo * task)946 MPP_RET vdpu2_h264d_start(void *hal, HalTaskInfo *task)
947 {
948 MPP_RET ret = MPP_ERR_UNKNOW;
949 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
950 H264dVdpuRegCtx_t *reg_ctx = (H264dVdpuRegCtx_t *)p_hal->reg_ctx;
951 H264dVdpuRegs_t *p_regs = p_hal->fast_mode ?
952 (H264dVdpuRegs_t *)reg_ctx->reg_buf[task->dec.reg_index].regs :
953 (H264dVdpuRegs_t *)reg_ctx->regs;
954 RK_U32 w = p_regs->sw110.pic_mb_w * 16;
955 RK_U32 h = p_regs->sw110.pic_mb_h * 16;
956 RK_U32 cache_en = 1;
957 const char *soc_name = NULL;
958
959 if (task->dec.flags.parse_err ||
960 task->dec.flags.ref_err) {
961 goto __RETURN;
962 }
963
964 soc_name = mpp_get_soc_name();
965 if (strstr(soc_name, "rk3326") || strstr(soc_name, "px30") || strstr(soc_name, "rk3228H"))
966 cache_en = ((w * h) >= (1280 * 720)) ? 1 : 0;
967
968 p_regs->sw57.cache_en = cache_en;
969 p_regs->sw57.pref_sigchan = 1;
970 p_regs->sw56.bus_pos_sel = 1;
971 p_regs->sw57.intra_dbl3t = 1;
972 p_regs->sw57.inter_dblspeed = 1;
973 p_regs->sw57.intra_dblspeed = 1;
974
975 #if DEBUG_REF_LIST
976 {
977 char file_name[128];
978 sprintf(file_name, "/sdcard/test/mpp2_reg_dump_log.txt");
979 FILE *fp = fopen(file_name, "ab");
980 char buf[2048];
981 RK_S32 buf_len = 0, buf_size = sizeof(buf) - 1;
982 RK_U32 *reg_tmp = (RK_U32*)reg_ctx->regs;
983 RK_U32 i;
984
985 buf_len += snprintf(buf + buf_len, buf_size - buf_len, "=== reg dump fram_num %d ===\n",
986 p_hal->pp->frame_num);
987 for (i = 50; i < 116; i++) {
988 buf_len += snprintf(buf + buf_len, buf_size - buf_len, "Regs[%d] = 0x%08x\n", i, reg_tmp[i]);
989 }
990 fprintf(fp, "%s", buf);
991
992 fflush(fp);
993 fclose(fp);
994 }
995 #endif
996 do {
997 MppDevRegWrCfg wr_cfg;
998 MppDevRegRdCfg rd_cfg;
999 RK_U32 reg_size = DEC_VDPU_REGISTERS * sizeof(RK_U32);
1000
1001 wr_cfg.reg = reg_ctx->regs;
1002 wr_cfg.size = reg_size;
1003 wr_cfg.offset = 0;
1004
1005 ret = mpp_dev_ioctl(p_hal->dev, MPP_DEV_REG_WR, &wr_cfg);
1006 if (ret) {
1007 mpp_err_f("set register write failed %d\n", ret);
1008 break;
1009 }
1010
1011 rd_cfg.reg = reg_ctx->regs;
1012 rd_cfg.size = reg_size;
1013 rd_cfg.offset = 0;
1014
1015 ret = mpp_dev_ioctl(p_hal->dev, MPP_DEV_REG_RD, &rd_cfg);
1016 if (ret) {
1017 mpp_err_f("set register read failed %d\n", ret);
1018 break;
1019 }
1020
1021 ret = mpp_dev_ioctl(p_hal->dev, MPP_DEV_CMD_SEND, NULL);
1022 if (ret) {
1023 mpp_err_f("send cmd failed %d\n", ret);
1024 break;
1025 }
1026 } while (0);
1027
1028 __RETURN:
1029 (void)task;
1030 return ret = MPP_OK;
1031 }
1032 /*!
1033 ***********************************************************************
1034 * \brief
1035 * wait hard
1036 ***********************************************************************
1037 */
1038 //extern "C"
vdpu2_h264d_wait(void * hal,HalTaskInfo * task)1039 MPP_RET vdpu2_h264d_wait(void *hal, HalTaskInfo *task)
1040 {
1041 MPP_RET ret = MPP_ERR_UNKNOW;
1042 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
1043 H264dVdpuRegCtx_t *reg_ctx = (H264dVdpuRegCtx_t *)p_hal->reg_ctx;
1044 H264dVdpuRegs_t *p_regs = (H264dVdpuRegs_t *)(p_hal->fast_mode ?
1045 reg_ctx->reg_buf[task->dec.reg_index].regs :
1046 reg_ctx->regs);
1047
1048 if (task->dec.flags.parse_err ||
1049 task->dec.flags.ref_err) {
1050 goto __SKIP_HARD;
1051 }
1052
1053 ret = mpp_dev_ioctl(p_hal->dev, MPP_DEV_CMD_POLL, NULL);
1054 if (ret)
1055 mpp_err_f("poll cmd failed %d\n", ret);
1056
1057 __SKIP_HARD:
1058 if (p_hal->dec_cb) {
1059 DecCbHalDone param;
1060
1061 param.task = (void *)&task->dec;
1062 param.regs = (RK_U32 *)reg_ctx->regs;
1063 param.hard_err = !p_regs->sw55.dec_rdy_sts;
1064
1065 mpp_callback(p_hal->dec_cb, ¶m);
1066 }
1067 memset(&p_regs->sw55, 0, sizeof(RK_U32));
1068 if (p_hal->fast_mode) {
1069 reg_ctx->reg_buf[task->dec.reg_index].valid = 0;
1070 }
1071
1072 (void)task;
1073
1074 return ret = MPP_OK;
1075 }
1076 /*!
1077 ***********************************************************************
1078 * \brief
1079 * reset
1080 ***********************************************************************
1081 */
1082 //extern "C"
vdpu2_h264d_reset(void * hal)1083 MPP_RET vdpu2_h264d_reset(void *hal)
1084 {
1085 MPP_RET ret = MPP_ERR_UNKNOW;
1086 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
1087
1088 INP_CHECK(ret, NULL == p_hal);
1089
1090 memset(p_hal->priv, 0, sizeof(H264dVdpuPriv_t));
1091
1092 __RETURN:
1093 return ret = MPP_OK;
1094 }
1095 /*!
1096 ***********************************************************************
1097 * \brief
1098 * flush
1099 ***********************************************************************
1100 */
1101 //extern "C"
vdpu2_h264d_flush(void * hal)1102 MPP_RET vdpu2_h264d_flush(void *hal)
1103 {
1104 MPP_RET ret = MPP_ERR_UNKNOW;
1105 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
1106
1107 INP_CHECK(ret, NULL == p_hal);
1108
1109 __RETURN:
1110 return ret = MPP_OK;
1111 }
1112 /*!
1113 ***********************************************************************
1114 * \brief
1115 * control
1116 ***********************************************************************
1117 */
1118 //extern "C"
vdpu2_h264d_control(void * hal,MpiCmd cmd_type,void * param)1119 MPP_RET vdpu2_h264d_control(void *hal, MpiCmd cmd_type, void *param)
1120 {
1121 MPP_RET ret = MPP_ERR_UNKNOW;
1122 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
1123
1124 INP_CHECK(ret, NULL == p_hal);
1125
1126 (void)hal;
1127 (void)cmd_type;
1128 (void)param;
1129 __RETURN:
1130 return ret = MPP_OK;
1131 }
1132