1 /*
2 *
3 * Copyright 2015 Rockchip Electronics Co. LTD
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at
8 *
9 * http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16 */
17
18 #define MODULE_TAG "hal_h264d_vdpu1_reg"
19
20 #include <stdio.h>
21 #include <stdlib.h>
22 #include <string.h>
23
24 #include "rk_type.h"
25 #include "mpp_err.h"
26 #include "mpp_mem.h"
27 #include "mpp_common.h"
28
29 #include "hal_h264d_global.h"
30 #include "hal_h264d_api.h"
31 #include "hal_h264d_vdpu_com.h"
32 #include "hal_h264d_vdpu1.h"
33 #include "hal_h264d_vdpu1_reg.h"
34 #include "mpp_dec_cb_param.h"
35
36 const RK_U32 vdpu1_ref_idx[16] = {
37 14, 15, 16, 17, 18, 19, 20, 21,
38 22, 23, 24, 25, 26, 27, 28, 29
39 };
40
vdpu1_set_refer_pic_idx(H264dVdpu1Regs_t * p_regs,RK_U32 i,RK_U16 val)41 static MPP_RET vdpu1_set_refer_pic_idx(H264dVdpu1Regs_t *p_regs, RK_U32 i,
42 RK_U16 val)
43 {
44 switch (i) {
45 case 0:
46 p_regs->SwReg30.sw_refer0_nbr = val;
47 break;
48 case 1:
49 p_regs->SwReg30.sw_refer1_nbr = val;
50 break;
51 case 2:
52 p_regs->SwReg31.sw_refer2_nbr = val;
53 break;
54 case 3:
55 p_regs->SwReg31.sw_refer3_nbr = val;
56 break;
57 case 4:
58 p_regs->SwReg32.sw_refer4_nbr = val;
59 break;
60 case 5:
61 p_regs->SwReg32.sw_refer5_nbr = val;
62 break;
63 case 6:
64 p_regs->SwReg33.sw_refer6_nbr = val;
65 break;
66 case 7:
67 p_regs->SwReg33.sw_refer7_nbr = val;
68 break;
69 case 8:
70 p_regs->SwReg34.sw_refer8_nbr = val;
71 break;
72 case 9:
73 p_regs->SwReg34.sw_refer9_nbr = val;
74 break;
75 case 10:
76 p_regs->SwReg35.sw_refer10_nbr = val;
77 break;
78 case 11:
79 p_regs->SwReg35.sw_refer11_nbr = val;
80 break;
81 case 12:
82 p_regs->SwReg36.sw_refer12_nbr = val;
83 break;
84 case 13:
85 p_regs->SwReg36.sw_refer13_nbr = val;
86 break;
87 case 14:
88 p_regs->SwReg37.sw_refer14_nbr = val;
89 break;
90 case 15:
91 p_regs->SwReg37.sw_refer15_nbr = val;
92 break;
93 default:
94 break;
95 }
96
97 return MPP_OK;
98 }
99
vdpu1_set_refer_pic_list_p(H264dVdpu1Regs_t * p_regs,RK_U32 i,RK_U16 val)100 static MPP_RET vdpu1_set_refer_pic_list_p(H264dVdpu1Regs_t *p_regs, RK_U32 i,
101 RK_U16 val)
102 {
103 switch (i) {
104 case 0:
105 p_regs->SwReg47.sw_pinit_rlist_f0 = val;
106 break;
107 case 1:
108 p_regs->SwReg47.sw_pinit_rlist_f1 = val;
109 break;
110 case 2:
111 p_regs->SwReg47.sw_pinit_rlist_f2 = val;
112 break;
113 case 3:
114 p_regs->SwReg47.sw_pinit_rlist_f3 = val;
115 break;
116 case 4:
117 p_regs->SwReg10.sw_pinit_rlist_f4 = val;
118 break;
119 case 5:
120 p_regs->SwReg10.sw_pinit_rlist_f5 = val;
121 break;
122 case 6:
123 p_regs->SwReg10.sw_pinit_rlist_f6 = val;
124 break;
125 case 7:
126 p_regs->SwReg10.sw_pinit_rlist_f7 = val;
127 break;
128 case 8:
129 p_regs->SwReg10.sw_pinit_rlist_f8 = val;
130 break;
131 case 9:
132 p_regs->SwReg10.sw_pinit_rlist_f9 = val;
133 break;
134 case 10:
135 p_regs->SwReg11.sw_pinit_rlist_f10 = val;
136 break;
137 case 11:
138 p_regs->SwReg11.sw_pinit_rlist_f11 = val;
139 break;
140 case 12:
141 p_regs->SwReg11.sw_pinit_rlist_f12 = val;
142 break;
143 case 13:
144 p_regs->SwReg11.sw_pinit_rlist_f13 = val;
145 break;
146 case 14:
147 p_regs->SwReg11.sw_pinit_rlist_f14 = val;
148 break;
149 case 15:
150 p_regs->SwReg11.sw_pinit_rlist_f15 = val;
151 break;
152 default:
153 break;
154 }
155
156 return MPP_OK;
157 }
158
vdpu1_set_refer_pic_list_b0(H264dVdpu1Regs_t * p_regs,RK_U32 i,RK_U16 val)159 static MPP_RET vdpu1_set_refer_pic_list_b0(H264dVdpu1Regs_t *p_regs, RK_U32 i,
160 RK_U16 val)
161 {
162 switch (i) {
163 case 0:
164 p_regs->SwReg42.sw_binit_rlist_f0 = val;
165 break;
166 case 1:
167 p_regs->SwReg42.sw_binit_rlist_f1 = val;
168 break;
169 case 2:
170 p_regs->SwReg42.sw_binit_rlist_f2 = val;
171 break;
172 case 3:
173 p_regs->SwReg43.sw_binit_rlist_f3 = val;
174 break;
175 case 4:
176 p_regs->SwReg43.sw_binit_rlist_f4 = val;
177 break;
178 case 5:
179 p_regs->SwReg43.sw_binit_rlist_f5 = val;
180 break;
181 case 6:
182 p_regs->SwReg44.sw_binit_rlist_f6 = val;
183 break;
184 case 7:
185 p_regs->SwReg44.sw_binit_rlist_f7 = val;
186 break;
187 case 8:
188 p_regs->SwReg44.sw_binit_rlist_f8 = val;
189 break;
190 case 9:
191 p_regs->SwReg45.sw_binit_rlist_f9 = val;
192 break;
193 case 10:
194 p_regs->SwReg45.sw_binit_rlist_f10 = val;
195 break;
196 case 11:
197 p_regs->SwReg45.sw_binit_rlist_f11 = val;
198 break;
199 case 12:
200 p_regs->SwReg46.sw_binit_rlist_f12 = val;
201 break;
202 case 13:
203 p_regs->SwReg46.sw_binit_rlist_f13 = val;
204 break;
205 case 14:
206 p_regs->SwReg46.sw_binit_rlist_f14 = val;
207 break;
208 case 15:
209 p_regs->SwReg47.sw_binit_rlist_f15 = val;
210 break;
211 default:
212 break;
213 }
214
215 return MPP_OK;
216 }
217
vdpu1_set_refer_pic_list_b1(H264dVdpu1Regs_t * p_regs,RK_U32 i,RK_U16 val)218 static MPP_RET vdpu1_set_refer_pic_list_b1(H264dVdpu1Regs_t *p_regs, RK_U32 i,
219 RK_U16 val)
220 {
221 switch (i) {
222 case 0:
223 p_regs->SwReg42.sw_binit_rlist_b0 = val;
224 break;
225 case 1:
226 p_regs->SwReg42.sw_binit_rlist_b1 = val;
227 break;
228 case 2:
229 p_regs->SwReg42.sw_binit_rlist_b2 = val;
230 break;
231 case 3:
232 p_regs->SwReg43.sw_binit_rlist_b3 = val;
233 break;
234 case 4:
235 p_regs->SwReg43.sw_binit_rlist_b4 = val;
236 break;
237 case 5:
238 p_regs->SwReg43.sw_binit_rlist_b5 = val;
239 break;
240 case 6:
241 p_regs->SwReg44.sw_binit_rlist_b6 = val;
242 break;
243 case 7:
244 p_regs->SwReg44.sw_binit_rlist_b7 = val;
245 break;
246 case 8:
247 p_regs->SwReg44.sw_binit_rlist_b8 = val;
248 break;
249 case 9:
250 p_regs->SwReg45.sw_binit_rlist_b9 = val;
251 break;
252 case 10:
253 p_regs->SwReg45.sw_binit_rlist_b10 = val;
254 break;
255 case 11:
256 p_regs->SwReg45.sw_binit_rlist_b11 = val;
257 break;
258 case 12:
259 p_regs->SwReg46.sw_binit_rlist_b12 = val;
260 break;
261 case 13:
262 p_regs->SwReg46.sw_binit_rlist_b13 = val;
263 break;
264 case 14:
265 p_regs->SwReg46.sw_binit_rlist_b14 = val;
266 break;
267 case 15:
268 p_regs->SwReg47.sw_binit_rlist_b15 = val;
269 break;
270 default:
271 break;
272 }
273
274 return MPP_OK;
275 }
276
vdpu1_set_refer_pic_base_addr(H264dVdpu1Regs_t * p_regs,RK_U32 i,RK_U32 val)277 static MPP_RET vdpu1_set_refer_pic_base_addr(H264dVdpu1Regs_t *p_regs, RK_U32 i,
278 RK_U32 val)
279 {
280 switch (i) {
281 case 0:
282 p_regs->SwReg14.sw_refer0_base = val;
283 break;
284 case 1:
285 p_regs->SwReg15.sw_refer1_base = val;
286 break;
287 case 2:
288 p_regs->SwReg16.sw_refer2_base = val;
289 break;
290 case 3:
291 p_regs->SwReg17.sw_refer3_base = val;
292 break;
293 case 4:
294 p_regs->SwReg18.sw_refer4_base = val;
295 break;
296 case 5:
297 p_regs->SwReg19.sw_refer5_base = val;
298 break;
299 case 6:
300 p_regs->SwReg20.sw_refer6_base = val;
301 break;
302 case 7:
303 p_regs->SwReg21.sw_refer7_base = val;
304 break;
305 case 8:
306 p_regs->SwReg22.sw_refer8_base = val;
307 break;
308 case 9:
309 p_regs->SwReg23.sw_refer9_base = val;
310 break;
311 case 10:
312 p_regs->SwReg24.sw_refer10_base = val;
313 break;
314 case 11:
315 p_regs->SwReg25.sw_refer11_base = val;
316 break;
317 case 12:
318 p_regs->SwReg26.sw_refer12_base = val;
319 break;
320 case 13:
321 p_regs->SwReg27.sw_refer13_base = val;
322 break;
323 case 14:
324 p_regs->SwReg28.sw_refer14_base = val;
325 break;
326 case 15:
327 p_regs->SwReg29.sw_refer15_base = val;
328 break;
329 default:
330 break;
331 }
332 return MPP_OK;
333 }
334
vdpu1_set_pic_regs(H264dHalCtx_t * p_hal,H264dVdpu1Regs_t * p_regs)335 static MPP_RET vdpu1_set_pic_regs(H264dHalCtx_t *p_hal,
336 H264dVdpu1Regs_t *p_regs)
337 {
338 MPP_RET ret = MPP_ERR_UNKNOW;
339
340 p_regs->SwReg04.sw_pic_mb_width = p_hal->pp->wFrameWidthInMbsMinus1 + 1;
341 p_regs->SwReg04.sw_pic_mb_height_p = (2 - p_hal->pp->frame_mbs_only_flag)
342 * (p_hal->pp->wFrameHeightInMbsMinus1 + 1);
343
344 return ret = MPP_OK;
345 }
346
vdpu1_set_vlc_regs(H264dHalCtx_t * p_hal,H264dVdpu1Regs_t * p_regs)347 static MPP_RET vdpu1_set_vlc_regs(H264dHalCtx_t *p_hal,
348 H264dVdpu1Regs_t *p_regs)
349 {
350 RK_U32 i = 0;
351 MPP_RET ret = MPP_ERR_UNKNOW;
352 DXVA_PicParams_H264_MVC *pp = p_hal->pp;
353
354 p_regs->SwReg03.sw_dec_out_dis = 0;
355 p_regs->SwReg03.sw_rlc_mode_e = 0;
356 p_regs->SwReg06.sw_init_qp = pp->pic_init_qp_minus26 + 26;
357 p_regs->SwReg09.sw_refidx0_active = pp->num_ref_idx_l0_active_minus1 + 1;
358 p_regs->SwReg04.sw_ref_frames = pp->num_ref_frames;
359
360 p_regs->SwReg07.sw_framenum_len = pp->log2_max_frame_num_minus4 + 4;
361 p_regs->SwReg07.sw_framenum = pp->frame_num;
362
363 p_regs->SwReg08.sw_const_intra_e = pp->constrained_intra_pred_flag;
364 p_regs->SwReg08.sw_filt_ctrl_pres =
365 pp->deblocking_filter_control_present_flag;
366 p_regs->SwReg08.sw_rdpic_cnt_pres = pp->redundant_pic_cnt_present_flag;
367 p_regs->SwReg08.sw_refpic_mk_len = p_hal->slice_long[0].drpm_used_bitlen;
368 p_regs->SwReg08.sw_idr_pic_e = p_hal->slice_long[0].idr_flag;
369 p_regs->SwReg08.sw_idr_pic_id = p_hal->slice_long[0].idr_pic_id;
370
371 p_regs->SwReg09.sw_pps_id = p_hal->slice_long[0].active_pps_id;
372 p_regs->SwReg09.sw_poc_length = p_hal->slice_long[0].poc_used_bitlen;
373
374 /* reference picture flags, TODO separate fields */
375 if (pp->field_pic_flag) {
376 RK_U32 validTmp = 0, validFlags = 0;
377 RK_U32 longTermTmp = 0, longTermflags = 0;
378 for (i = 0; i < 32; i++) {
379 if (pp->RefFrameList[i / 2].bPicEntry == 0xff) { //!< invalid
380 longTermflags <<= 1;
381 validFlags <<= 1;
382 } else {
383 longTermTmp = pp->RefFrameList[i / 2].AssociatedFlag; //!< get long term flag
384 longTermflags = (longTermflags << 1) | longTermTmp;
385
386 validTmp = ((pp->UsedForReferenceFlags >> i) & 0x01);
387 validFlags = (validFlags << 1) | validTmp;
388 }
389 }
390 p_regs->SwReg38.refpic_term_flag = longTermflags;
391 p_regs->SwReg39.refpic_valid_flag = validFlags;
392 } else {
393 RK_U32 validTmp = 0, validFlags = 0;
394 RK_U32 longTermTmp = 0, longTermflags = 0;
395 for (i = 0; i < 16; i++) {
396 if (pp->RefFrameList[i].bPicEntry == 0xff) { //!< invalid
397 longTermflags <<= 1;
398 validFlags <<= 1;
399 } else {
400 longTermTmp = pp->RefFrameList[i].AssociatedFlag;
401 longTermflags = (longTermflags << 1) | longTermTmp;
402 validTmp = ((pp->UsedForReferenceFlags >> (2 * i)) & 0x03) > 0;
403 validFlags = (validFlags << 1) | validTmp;
404 }
405 }
406 p_regs->SwReg38.refpic_term_flag = (longTermflags << 16);
407 p_regs->SwReg39.refpic_valid_flag = (validFlags << 16);
408 }
409
410 for (i = 0; i < 16; i++) {
411 if (pp->RefFrameList[i].bPicEntry != 0xff) { //!< valid
412 if (pp->RefFrameList[i].AssociatedFlag) { //!< longterm flag
413 vdpu1_set_refer_pic_idx(p_regs, i, pp->LongTermPicNumList[i]); //!< pic_num
414 } else {
415 vdpu1_set_refer_pic_idx(p_regs, i, pp->FrameNumList[i]); //< frame_num
416 }
417 }
418 }
419 p_regs->SwReg03.sw_picord_count_e = 1;
420 //!< set poc to buffer
421 {
422 H264dVdpuRegCtx_t *reg_ctx = (H264dVdpuRegCtx_t *)p_hal->reg_ctx;
423 RK_U32 *pocBase = (RK_U32 *)reg_ctx->poc_ptr;
424
425 //!< set reference reorder poc
426 for (i = 0; i < 32; i++) {
427 if (pp->RefFrameList[i / 2].bPicEntry != 0xff) {
428 *pocBase++ = pp->FieldOrderCntList[i / 2][i & 0x1];
429 } else {
430 *pocBase++ = 0;
431 }
432 }
433
434 //!< set current poc
435 if (pp->field_pic_flag || !pp->MbaffFrameFlag) {
436 if (pp->field_pic_flag)
437 *pocBase++ = pp->CurrFieldOrderCnt[pp->CurrPic.AssociatedFlag ? 1 : 0];
438 else
439 *pocBase++ = MPP_MIN(pp->CurrFieldOrderCnt[0], pp->CurrFieldOrderCnt[1]);
440 } else {
441 *pocBase++ = pp->CurrFieldOrderCnt[0];
442 *pocBase++ = pp->CurrFieldOrderCnt[1];
443 }
444 }
445
446 p_regs->SwReg07.sw_cabac_e = pp->entropy_coding_mode_flag;
447
448 //!< stream position update
449 {
450 MppBuffer bitstream_buf = NULL;
451 p_regs->SwReg06.sw_start_code_e = 1;
452
453 mpp_buf_slot_get_prop(p_hal->packet_slots, p_hal->in_task->input,
454 SLOT_BUFFER, &bitstream_buf);
455
456 p_regs->SwReg05.sw_strm_start_bit = 0; /* sodb stream start bit */
457 p_regs->SwReg12.rlc_vlc_st_adr = mpp_buffer_get_fd(bitstream_buf);
458
459 p_regs->SwReg06.sw_stream_len = p_hal->strm_len;
460 }
461
462 return ret = MPP_OK;
463 }
464
vdpu1_set_ref_regs(H264dHalCtx_t * p_hal,H264dVdpu1Regs_t * p_regs)465 static MPP_RET vdpu1_set_ref_regs(H264dHalCtx_t *p_hal,
466 H264dVdpu1Regs_t *p_regs)
467 {
468 MPP_RET ret = MPP_ERR_UNKNOW;
469 RK_U32 i = 0;
470 RK_U32 num_refs = 0;
471 RK_U32 num_reorder = 0;
472 H264dRefsList_t m_lists[3][16];
473 DXVA_PicParams_H264_MVC *pp = p_hal->pp;
474 RK_U32 max_frame_num = 1 << (pp->log2_max_frame_num_minus4 + 4);
475
476 // init list
477 memset(m_lists, 0, sizeof(m_lists));
478 for (i = 0; i < 16; i++) {
479 RK_U32 ref_flag = pp->UsedForReferenceFlags >> (2 * i) & 0x3;
480
481 m_lists[0][i].idx = i;
482 if (ref_flag) {
483 num_refs++;
484 m_lists[0][i].cur_poc = pp->CurrPic.AssociatedFlag
485 ? pp->CurrFieldOrderCnt[1] : pp->CurrFieldOrderCnt[0];
486 m_lists[0][i].ref_flag = ref_flag;
487 m_lists[0][i].lt_flag = pp->RefFrameList[i].AssociatedFlag;
488 if (m_lists[0][i].lt_flag) {
489 m_lists[0][i].ref_picnum = pp->LongTermPicNumList[i];
490 } else {
491 m_lists[0][i].ref_picnum = pp->FrameNumList[i] > pp->frame_num ?
492 (pp->FrameNumList[i] - max_frame_num) :
493 pp->FrameNumList[i];
494 }
495
496 if (ref_flag == 3) {
497 m_lists[0][i].ref_poc = MPP_MIN(pp->FieldOrderCntList[i][0], pp->FieldOrderCntList[i][1]);
498 } else if (ref_flag & 0x1) {
499 m_lists[0][i].ref_poc = pp->FieldOrderCntList[i][0];
500 } else if (ref_flag & 0x2) {
501 m_lists[0][i].ref_poc = pp->FieldOrderCntList[i][1];
502 }
503 num_reorder = i + 1;
504 }
505 }
506 /*
507 * the value of num_reorder may be greater than num_refs,
508 * e.g. v: valid x: invalid
509 * num_refs = 3, num_reorder = 4
510 * the index 1 will be reorder to the end
511 * ┌─┬─┬─┬─┬─┬─┬─┐
512 * │0│1│2│3│.│.│F│
513 * ├─┼─┼─┼─┼─┼─┼─┤
514 * │v│x│v│v│x│x│x│
515 * └─┴─┴─┴─┴─┴─┴─┘
516 */
517 memcpy(m_lists[1], m_lists[0], sizeof(m_lists[0]));
518 memcpy(m_lists[2], m_lists[0], sizeof(m_lists[0]));
519 qsort(m_lists[0], num_reorder, sizeof(m_lists[0][0]), compare_p);
520 qsort(m_lists[1], num_reorder, sizeof(m_lists[1][0]), compare_b0);
521 qsort(m_lists[2], num_reorder, sizeof(m_lists[2][0]), compare_b1);
522 if (num_refs > 1 && !p_hal->pp->field_pic_flag) {
523 if (!memcmp(m_lists[1], m_lists[2], sizeof(m_lists[1]))) {
524 MPP_SWAP(H264dRefsList_t, m_lists[2][0], m_lists[2][1]);
525 }
526 }
527 //!< list0 list1 listP
528 for (i = 0; i < 16; i++) {
529 vdpu1_set_refer_pic_list_p(p_regs, i, m_lists[0][i].idx);
530 vdpu1_set_refer_pic_list_b0(p_regs, i, m_lists[1][i].idx);
531 vdpu1_set_refer_pic_list_b1(p_regs, i, m_lists[2][i].idx);
532 }
533
534 return ret = MPP_OK;
535 }
536
vdpu1_set_asic_regs(H264dHalCtx_t * p_hal,H264dVdpu1Regs_t * p_regs)537 static MPP_RET vdpu1_set_asic_regs(H264dHalCtx_t *p_hal,
538 H264dVdpu1Regs_t *p_regs)
539 {
540 RK_U32 i = 0, j = 0;
541 RK_U32 outPhyAddr = 0;
542 MppBuffer frame_buf = NULL;
543 MPP_RET ret = MPP_ERR_UNKNOW;
544 DXVA_PicParams_H264_MVC *pp = p_hal->pp;
545 DXVA_Slice_H264_Long *p_long = &p_hal->slice_long[0];
546
547 /* reference picture physic address */
548 for (i = 0, j = 0xff; i < MPP_ARRAY_ELEMS(pp->RefFrameList); i++) {
549 RK_U32 val = 0;
550 RK_U32 top_closer = 0;
551 RK_U32 field_flag = 0;
552 RK_S32 cur_poc = 0;
553 RK_U32 used_flag = 0;
554
555 if (pp->RefFrameList[i].bPicEntry != 0xff) {
556 mpp_buf_slot_get_prop(p_hal->frame_slots,
557 pp->RefFrameList[i].Index7Bits,
558 SLOT_BUFFER, &frame_buf); //!< reference phy addr
559 j = i;
560 } else {
561 mpp_buf_slot_get_prop(p_hal->frame_slots,
562 pp->CurrPic.Index7Bits,
563 SLOT_BUFFER, &frame_buf); //!< current out phy addr
564 }
565
566 field_flag = ((pp->RefPicFiledFlags >> i) & 0x1) ? 0x2 : 0;
567 cur_poc = pp->CurrPic.AssociatedFlag
568 ? pp->CurrFieldOrderCnt[1] : pp->CurrFieldOrderCnt[0];
569 used_flag = ((pp->UsedForReferenceFlags >> (2 * i)) & 0x3);
570 if (used_flag & 0x3) {
571 top_closer = MPP_ABS(pp->FieldOrderCntList[i][0] - cur_poc) <
572 MPP_ABS(pp->FieldOrderCntList[i][1] - cur_poc) ? 0x1 : 0;
573 } else if (used_flag & 0x2) {
574 top_closer = 0;
575 } else if (used_flag & 0x1) {
576 top_closer = 1;
577 }
578 val = top_closer | field_flag;
579 if (val)
580 mpp_dev_set_reg_offset(p_hal->dev, vdpu1_ref_idx[i], val);
581 vdpu1_set_refer_pic_base_addr(p_regs, i, mpp_buffer_get_fd(frame_buf));
582 }
583
584 /* inter-view reference picture */
585 {
586 H264dVdpuPriv_t *priv = (H264dVdpuPriv_t *)p_hal->priv;
587 if (pp->curr_layer_id && priv->ilt_dpb && priv->ilt_dpb->valid /*pp->inter_view_flag*/) {
588 mpp_buf_slot_get_prop(p_hal->frame_slots,
589 priv->ilt_dpb->slot_index,
590 SLOT_BUFFER, &frame_buf);
591 p_regs->SwReg29.sw_refer15_base = mpp_buffer_get_fd(frame_buf); //!< inter-view base, ref15
592 p_regs->SwReg39.refpic_valid_flag |=
593 (pp->field_pic_flag ? 0x3 : 0x10000);
594 }
595 }
596
597 p_regs->SwReg03.sw_pic_fixed_quant = pp->curr_layer_id; //!< VDPU_MVC_E
598 p_regs->SwReg03.sw_filtering_dis = 0;
599
600 mpp_buf_slot_get_prop(p_hal->frame_slots,
601 pp->CurrPic.Index7Bits,
602 SLOT_BUFFER, &frame_buf); //!< current out phy addr
603 outPhyAddr = mpp_buffer_get_fd(frame_buf);
604 if (pp->field_pic_flag && pp->CurrPic.AssociatedFlag) {
605 mpp_dev_set_reg_offset(p_hal->dev, 13, ((pp->wFrameWidthInMbsMinus1 + 1) * 16));
606 }
607 p_regs->SwReg13.dec_out_st_adr = outPhyAddr; //!< outPhyAddr, pp->CurrPic.Index7Bits
608
609 p_regs->SwReg05.sw_ch_qp_offset = pp->chroma_qp_index_offset;
610 p_regs->SwReg05.sw_ch_qp_offset2 = pp->second_chroma_qp_index_offset;
611
612 /* set default value for register[41] to avoid illegal translation fd */
613 {
614 RK_U32 dirMvOffset = 0;
615 RK_U32 picSizeInMbs = 0;
616
617 picSizeInMbs = p_hal->pp->wFrameWidthInMbsMinus1 + 1;
618 picSizeInMbs = picSizeInMbs * (2 - pp->frame_mbs_only_flag)
619 * (pp->wFrameHeightInMbsMinus1 + 1);
620 dirMvOffset = picSizeInMbs
621 * ((p_hal->pp->chroma_format_idc == 0) ? 256 : 384);
622 dirMvOffset += (pp->field_pic_flag && pp->CurrPic.AssociatedFlag)
623 ? (picSizeInMbs * 32) : 0;
624 if (dirMvOffset) {
625 RK_U32 offset = mpp_get_ioctl_version() ? dirMvOffset : dirMvOffset >> 4;
626 mpp_dev_set_reg_offset(p_hal->dev, 41, offset);
627 }
628 p_regs->SwReg41.dmmv_st_adr = mpp_buffer_get_fd(frame_buf);
629 }
630
631 p_regs->SwReg03.sw_write_mvs_e = (p_long->nal_ref_idc != 0) ? 1 : 0; /* defalut set 1 */
632 p_regs->SwReg07.sw_dir_8x8_infer_e = pp->direct_8x8_inference_flag;
633 p_regs->SwReg07.sw_weight_pred_e = pp->weighted_pred_flag;
634 p_regs->SwReg07.sw_weight_bipr_idc = pp->weighted_bipred_idc;
635 p_regs->SwReg09.sw_refidx1_active = (pp->num_ref_idx_l1_active_minus1 + 1);
636 p_regs->SwReg05.sw_fieldpic_flag_e = (!pp->frame_mbs_only_flag) ? 1 : 0;
637
638 p_regs->SwReg03.sw_pic_interlace_e =
639 (!pp->frame_mbs_only_flag
640 && (pp->MbaffFrameFlag || pp->field_pic_flag)) ? 1 : 0;
641 p_regs->SwReg03.sw_pic_fieldmode_e = pp->field_pic_flag;
642 p_regs->SwReg03.sw_pic_topfield_e = (!pp->CurrPic.AssociatedFlag) ? 1 : 0; /* bottomFieldFlag */
643 p_regs->SwReg03.sw_seq_mbaff_e = pp->MbaffFrameFlag;
644 p_regs->SwReg08.sw_8x8trans_flag_e = pp->transform_8x8_mode_flag;
645 p_regs->SwReg07.sw_blackwhite_e = (p_long->profileIdc >= 100
646 && pp->chroma_format_idc == 0) ? 1 : 0;
647 p_regs->SwReg05.sw_type1_quant_e = pp->scaleing_list_enable_flag;
648
649 {
650 H264dVdpuRegCtx_t *reg_ctx = (H264dVdpuRegCtx_t *)p_hal->reg_ctx;
651 if (p_hal->pp->scaleing_list_enable_flag) {
652 RK_U32 temp = 0;
653 RK_U32 *ptr = (RK_U32 *)reg_ctx->sclst_ptr;
654
655 for (i = 0; i < 6; i++) {
656 for (j = 0; j < 4; j++) {
657 temp = (p_hal->qm->bScalingLists4x4[i][4 * j + 0] << 24) |
658 (p_hal->qm->bScalingLists4x4[i][4 * j + 1] << 16) |
659 (p_hal->qm->bScalingLists4x4[i][4 * j + 2] << 8) |
660 (p_hal->qm->bScalingLists4x4[i][4 * j + 3]);
661 *ptr++ = temp;
662 }
663 }
664
665 for (i = 0; i < 2; i++) {
666 for (j = 0; j < 16; j++) {
667 temp = (p_hal->qm->bScalingLists8x8[i][4 * j + 0] << 24) |
668 (p_hal->qm->bScalingLists8x8[i][4 * j + 1] << 16) |
669 (p_hal->qm->bScalingLists8x8[i][4 * j + 2] << 8) |
670 (p_hal->qm->bScalingLists8x8[i][4 * j + 3]);
671 *ptr++ = temp;
672 }
673 }
674 }
675 p_regs->SwReg40.qtable_st_adr = mpp_buffer_get_fd(reg_ctx->buf);
676 }
677
678 p_regs->SwReg03.sw_dec_out_dis = 0; /* set defalut 0 */
679 p_regs->SwReg06.sw_ch_8pix_ileav_e = 0;
680 p_regs->SwReg01.sw_dec_en = 1;
681
682 return ret = MPP_OK;
683 }
684
vdpu1_set_device_regs(H264dHalCtx_t * p_hal,H264dVdpu1Regs_t * p_reg)685 static MPP_RET vdpu1_set_device_regs(H264dHalCtx_t *p_hal,
686 H264dVdpu1Regs_t *p_reg)
687 {
688 MPP_RET ret = MPP_ERR_UNKNOW;
689
690 p_reg->SwReg03.sw_dec_mode = 0; /* set H264 mode */
691 p_reg->SwReg02.sw_dec_out_endian = 1; /* little endian */
692 p_reg->SwReg02.sw_dec_in_endian = 0; /* big endian */
693 p_reg->SwReg02.sw_dec_strendian_e = 1; //!< little endian
694 p_reg->SwReg02.sw_tiled_mode_msb = 0; /* 0: raster scan 1: tiled */
695
696 /* bus_burst_length = 16, bus burst */
697 p_reg->SwReg02.sw_dec_max_burst = 16; /* (0, 4, 8, 16) choice one */
698 p_reg->SwReg02.sw_dec_scmd_dis = 0; /* disable */
699 p_reg->SwReg02.sw_dec_adv_pre_dis = 0; /* disable */
700 p_reg->SwReg55.sw_apf_threshold = 8;
701 p_reg->SwReg02.sw_dec_latency = 0; /* compensation for bus latency; values up to 63 */
702 p_reg->SwReg02.sw_dec_data_disc_e = 0;
703 p_reg->SwReg02.sw_dec_out_endian = 1; /* little endian */
704 p_reg->SwReg02.sw_dec_inswap32_e = 1; /* little endian */
705 p_reg->SwReg02.sw_dec_outswap32_e = 1;
706 p_reg->SwReg02.sw_dec_strswap32_e = 1;
707 p_reg->SwReg02.sw_dec_strendian_e = 1; /* little endian */
708 p_reg->SwReg02.sw_dec_timeout_e = 1;
709
710 /* clock_gating 0:clock always on, 1: clock gating module control the key(turn off when decoder free) */
711 p_reg->SwReg02.sw_dec_clk_gate_e = 1;
712 p_reg->SwReg01.sw_dec_irq_dis_cfg = 0;
713
714 //!< set AXI RW IDs
715 p_reg->SwReg02.sw_dec_axi_rd_id = (0xFF & 0xFFU); /* 0-255 */
716 p_reg->SwReg03.sw_dec_axi_wr_id = (0x00 & 0xFFU); /* 0-255 */
717
718 ///!< Set prediction filter taps
719 {
720 RK_U32 val = 0;
721 p_reg->SwReg49.sw_pred_bc_tap_0_0 = 1;
722
723 val = (RK_U32)(-5);
724 p_reg->SwReg49.sw_pred_bc_tap_0_1 = val;
725 p_reg->SwReg49.sw_pred_bc_tap_0_2 = 20;
726 }
727
728 (void)p_hal;
729
730 return ret = MPP_OK;
731 }
732
733 /*!
734 ***********************************************************************
735 * \brief
736 * init VDPU granite decoder
737 ***********************************************************************
738 */
739 //extern "C"
vdpu1_h264d_init(void * hal,MppHalCfg * cfg)740 MPP_RET vdpu1_h264d_init(void *hal, MppHalCfg *cfg)
741 {
742 MPP_RET ret = MPP_ERR_UNKNOW;
743 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
744 INP_CHECK(ret, NULL == hal);
745
746 //!< malloc init registers
747 MEM_CHECK(ret, p_hal->priv =
748 mpp_calloc_size(void, sizeof(H264dVdpuPriv_t)));
749
750 MEM_CHECK(ret, p_hal->reg_ctx = mpp_calloc_size(void, sizeof(H264dVdpuRegCtx_t)));
751 H264dVdpuRegCtx_t *reg_ctx = (H264dVdpuRegCtx_t *)p_hal->reg_ctx;
752 //!< malloc buffers
753 {
754 RK_U32 i = 0;
755 RK_U32 loop = p_hal->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->reg_buf) : 1;
756
757 RK_U32 buf_size = VDPU_CABAC_TAB_SIZE + VDPU_POC_BUF_SIZE + VDPU_SCALING_LIST_SIZE;
758 for (i = 0; i < loop; i++) {
759 FUN_CHECK(ret = mpp_buffer_get(p_hal->buf_group, ®_ctx->reg_buf[i].buf, buf_size));
760 reg_ctx->reg_buf[i].cabac_ptr = mpp_buffer_get_ptr(reg_ctx->reg_buf[i].buf);
761 reg_ctx->reg_buf[i].poc_ptr = reg_ctx->reg_buf[i].cabac_ptr + VDPU_CABAC_TAB_SIZE;
762 reg_ctx->reg_buf[i].sclst_ptr = reg_ctx->reg_buf[i].poc_ptr + VDPU_POC_BUF_SIZE;
763 reg_ctx->reg_buf[i].regs = mpp_calloc_size(void, sizeof(H264dVdpu1Regs_t));
764 //!< copy cabac table bytes
765 memcpy(reg_ctx->reg_buf[i].cabac_ptr, (void *)vdpu_cabac_table, sizeof(vdpu_cabac_table));
766 }
767 }
768 if (!p_hal->fast_mode) {
769 reg_ctx->buf = reg_ctx->reg_buf[0].buf;
770 reg_ctx->cabac_ptr = reg_ctx->reg_buf[0].cabac_ptr;
771 reg_ctx->poc_ptr = reg_ctx->reg_buf[0].poc_ptr;
772 reg_ctx->sclst_ptr = reg_ctx->reg_buf[0].sclst_ptr;
773 reg_ctx->regs = reg_ctx->reg_buf[0].regs;
774 }
775
776 mpp_slots_set_prop(p_hal->frame_slots, SLOTS_HOR_ALIGN, vdpu_hor_align);
777 mpp_slots_set_prop(p_hal->frame_slots, SLOTS_VER_ALIGN, vdpu_ver_align);
778
779 {
780 // report hw_info to parser
781 const MppSocInfo *info = mpp_get_soc_info();
782 const void *hw_info = NULL;
783 RK_U32 i;
784
785 for (i = 0; i < MPP_ARRAY_ELEMS(info->dec_caps); i++) {
786 if (info->dec_caps[i] && info->dec_caps[i]->type == VPU_CLIENT_VDPU1) {
787 hw_info = info->dec_caps[i];
788 break;
789 }
790 }
791
792 mpp_assert(hw_info);
793 cfg->hw_info = hw_info;
794 }
795
796 __RETURN:
797 return MPP_OK;
798 __FAILED:
799 vdpu1_h264d_deinit(hal);
800
801 return ret;
802 }
803
804 /*!
805 ***********************************************************************
806 * \brief
807 * deinit
808 ***********************************************************************
809 */
810 //extern "C"
vdpu1_h264d_deinit(void * hal)811 MPP_RET vdpu1_h264d_deinit(void *hal)
812 {
813 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
814 H264dVdpuRegCtx_t *reg_ctx = (H264dVdpuRegCtx_t *)p_hal->reg_ctx;
815
816 RK_U32 i = 0;
817 RK_U32 loop = p_hal->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->reg_buf) : 1;
818 for (i = 0; i < loop; i++) {
819 MPP_FREE(reg_ctx->reg_buf[i].regs);
820 mpp_buffer_put(reg_ctx->reg_buf[i].buf);
821 }
822 MPP_FREE(p_hal->reg_ctx);
823 MPP_FREE(p_hal->priv);
824
825 return MPP_OK;
826 }
827
828 /*!
829 ***********************************************************************
830 * \brief
831 * generate register
832 ***********************************************************************
833 */
834 //extern "C"
vdpu1_h264d_gen_regs(void * hal,HalTaskInfo * task)835 MPP_RET vdpu1_h264d_gen_regs(void *hal, HalTaskInfo *task)
836 {
837 MPP_RET ret = MPP_ERR_UNKNOW;
838
839 H264dVdpuPriv_t *priv = NULL;
840 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
841 INP_CHECK(ret, NULL == p_hal);
842 p_hal->in_task = &task->dec;
843 if (task->dec.flags.parse_err ||
844 task->dec.flags.ref_err) {
845 goto __RETURN;
846 }
847 priv = p_hal->priv;
848 priv->layed_id = p_hal->pp->curr_layer_id;
849
850 H264dVdpuRegCtx_t *reg_ctx = (H264dVdpuRegCtx_t *)p_hal->reg_ctx;
851 if (p_hal->fast_mode) {
852 RK_U32 i = 0;
853 for (i = 0; i < MPP_ARRAY_ELEMS(reg_ctx->reg_buf); i++) {
854 if (!reg_ctx->reg_buf[i].valid) {
855 task->dec.reg_index = i;
856 reg_ctx->buf = reg_ctx->reg_buf[i].buf;
857 reg_ctx->cabac_ptr = reg_ctx->reg_buf[i].cabac_ptr;
858 reg_ctx->poc_ptr = reg_ctx->reg_buf[i].poc_ptr;
859 reg_ctx->sclst_ptr = reg_ctx->reg_buf[i].sclst_ptr;
860 reg_ctx->regs = reg_ctx->reg_buf[i].regs;
861 reg_ctx->reg_buf[i].valid = 1;
862 break;
863 }
864 }
865 }
866
867 FUN_CHECK(ret = adjust_input(priv, &p_hal->slice_long[0], p_hal->pp));
868 FUN_CHECK(ret = vdpu1_set_device_regs(p_hal, (H264dVdpu1Regs_t *)reg_ctx->regs));
869 FUN_CHECK(ret = vdpu1_set_pic_regs(p_hal, (H264dVdpu1Regs_t *)reg_ctx->regs));
870 FUN_CHECK(ret = vdpu1_set_vlc_regs(p_hal, (H264dVdpu1Regs_t *)reg_ctx->regs));
871 FUN_CHECK(ret = vdpu1_set_ref_regs(p_hal, (H264dVdpu1Regs_t *)reg_ctx->regs));
872 FUN_CHECK(ret = vdpu1_set_asic_regs(p_hal, (H264dVdpu1Regs_t *)reg_ctx->regs));
873
874 __RETURN:
875 return ret = MPP_OK;
876 __FAILED:
877 return ret;
878 }
879
880 /*!
881 ***********************************************************************
882 * \brief h
883 * start hard
884 ***********************************************************************
885 */
886 //extern "C"
vdpu1_h264d_start(void * hal,HalTaskInfo * task)887 MPP_RET vdpu1_h264d_start(void *hal, HalTaskInfo *task)
888 {
889 MPP_RET ret = MPP_ERR_UNKNOW;
890 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
891 H264dVdpuRegCtx_t *reg_ctx = (H264dVdpuRegCtx_t *)p_hal->reg_ctx;
892 H264dVdpu1Regs_t *p_regs = (H264dVdpu1Regs_t *)(p_hal->fast_mode ?
893 reg_ctx->reg_buf[task->dec.reg_index].regs :
894 reg_ctx->regs);
895
896 if (task->dec.flags.parse_err ||
897 task->dec.flags.ref_err) {
898 goto __RETURN;
899 }
900
901 p_regs->SwReg57.sw_cache_en = 1;
902 p_regs->SwReg57.sw_pref_sigchan = 1;
903 p_regs->SwReg57.sw_intra_dbl3t = 1;
904 p_regs->SwReg57.sw_inter_dblspeed = 1;
905 p_regs->SwReg57.sw_intra_dblspeed = 1;
906 p_regs->SwReg57.sw_paral_bus = 1;
907
908 do {
909 MppDevRegWrCfg wr_cfg;
910 MppDevRegRdCfg rd_cfg;
911 RK_U32 reg_size = DEC_VDPU1_REGISTERS * sizeof(RK_U32);
912
913 wr_cfg.reg = reg_ctx->regs;
914 wr_cfg.size = reg_size;
915 wr_cfg.offset = 0;
916
917 ret = mpp_dev_ioctl(p_hal->dev, MPP_DEV_REG_WR, &wr_cfg);
918 if (ret) {
919 mpp_err_f("set register write failed %d\n", ret);
920 break;
921 }
922
923 rd_cfg.reg = reg_ctx->regs;
924 rd_cfg.size = reg_size;
925 rd_cfg.offset = 0;
926
927 ret = mpp_dev_ioctl(p_hal->dev, MPP_DEV_REG_RD, &rd_cfg);
928 if (ret) {
929 mpp_err_f("set register read failed %d\n", ret);
930 break;
931 }
932
933 ret = mpp_dev_ioctl(p_hal->dev, MPP_DEV_CMD_SEND, NULL);
934 if (ret) {
935 mpp_err_f("send cmd failed %d\n", ret);
936 break;
937 }
938 } while (0);
939
940 __RETURN:
941 (void)task;
942 return ret = MPP_OK;
943 }
944
945 /*!
946 ***********************************************************************
947 * \brief
948 * wait hard
949 ***********************************************************************
950 */
951 //extern "C"
vdpu1_h264d_wait(void * hal,HalTaskInfo * task)952 MPP_RET vdpu1_h264d_wait(void *hal, HalTaskInfo *task)
953 {
954 MPP_RET ret = MPP_ERR_UNKNOW;
955 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
956 H264dVdpuRegCtx_t *reg_ctx = (H264dVdpuRegCtx_t *)p_hal->reg_ctx;
957 H264dVdpu1Regs_t *p_regs = (H264dVdpu1Regs_t *)(p_hal->fast_mode ?
958 reg_ctx->reg_buf[task->dec.reg_index].regs :
959 reg_ctx->regs);
960
961 if (task->dec.flags.parse_err ||
962 task->dec.flags.ref_err) {
963 goto __SKIP_HARD;
964 }
965
966 ret = mpp_dev_ioctl(p_hal->dev, MPP_DEV_CMD_POLL, NULL);
967 if (ret)
968 mpp_err_f("poll cmd failed %d\n", ret);
969
970 __SKIP_HARD:
971 if (p_hal->dec_cb) {
972 DecCbHalDone param;
973
974 param.task = (void *)&task->dec;
975 param.regs = (RK_U32 *)reg_ctx->regs;
976 param.hard_err = !p_regs->SwReg01.sw_dec_rdy_int;
977
978 mpp_callback(p_hal->dec_cb, ¶m);
979 }
980 memset(&p_regs->SwReg01, 0, sizeof(RK_U32));
981 if (p_hal->fast_mode) {
982 reg_ctx->reg_buf[task->dec.reg_index].valid = 0;
983 }
984 (void)task;
985
986 return ret = MPP_OK;
987 }
988
989 /*!
990 ***********************************************************************
991 * \brief
992 * reset
993 ***********************************************************************
994 */
995 //extern "C"
vdpu1_h264d_reset(void * hal)996 MPP_RET vdpu1_h264d_reset(void *hal)
997 {
998 MPP_RET ret = MPP_ERR_UNKNOW;
999 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
1000
1001 INP_CHECK(ret, NULL == p_hal);
1002 memset(p_hal->priv, 0, sizeof(H264dVdpuPriv_t));
1003
1004 __RETURN:
1005 return ret = MPP_OK;
1006 }
1007
1008 /*!
1009 ***********************************************************************
1010 * \brief
1011 * flush
1012 ***********************************************************************
1013 */
1014 //extern "C"
vdpu1_h264d_flush(void * hal)1015 MPP_RET vdpu1_h264d_flush(void *hal)
1016 {
1017 MPP_RET ret = MPP_ERR_UNKNOW;
1018 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
1019
1020 INP_CHECK(ret, NULL == p_hal);
1021
1022
1023
1024 __RETURN:
1025 return ret = MPP_OK;
1026 }
1027
1028 /*!
1029 ***********************************************************************
1030 * \brief
1031 * control
1032 ***********************************************************************
1033 */
1034 //extern "C"
vdpu1_h264d_control(void * hal,MpiCmd cmd_type,void * param)1035 MPP_RET vdpu1_h264d_control(void *hal, MpiCmd cmd_type, void *param)
1036 {
1037 MPP_RET ret = MPP_ERR_UNKNOW;
1038 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
1039
1040 INP_CHECK(ret, NULL == p_hal);
1041
1042 (void)hal;
1043 (void)cmd_type;
1044 (void)param;
1045 __RETURN:
1046 return ret = MPP_OK;
1047 }
1048