1 /*
2 * Copyright 2017 Rockchip Electronics Co., Ltd
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7 #include <common.h>
8 #include <dm.h>
9 #include <dm/lists.h>
10 #include <generic-phy.h>
11 #include <linux/ioport.h>
12 #include <power/regulator.h>
13 #include <regmap.h>
14 #include <syscon.h>
15 #include <asm/io.h>
16 #include <asm/arch/clock.h>
17 #include <asm/arch/cpu.h>
18 #include <asm/gpio.h>
19 #include <reset-uclass.h>
20
21 #include "../usb/gadget/dwc2_udc_otg_priv.h"
22
23 #define U2PHY_BIT_WRITEABLE_SHIFT 16
24 #define CHG_DCD_MAX_RETRIES 6
25 #define CHG_PRI_MAX_RETRIES 2
26 #define CHG_DCD_POLL_TIME 100 /* millisecond */
27 #define CHG_PRIMARY_DET_TIME 40 /* millisecond */
28 #define CHG_SECONDARY_DET_TIME 40 /* millisecond */
29
30 struct rockchip_usb2phy;
31
32 enum power_supply_type {
33 POWER_SUPPLY_TYPE_UNKNOWN = 0,
34 POWER_SUPPLY_TYPE_USB, /* Standard Downstream Port */
35 POWER_SUPPLY_TYPE_USB_DCP, /* Dedicated Charging Port */
36 POWER_SUPPLY_TYPE_USB_CDP, /* Charging Downstream Port */
37 POWER_SUPPLY_TYPE_USB_FLOATING, /* DCP without shorting D+/D- */
38 };
39
40 enum rockchip_usb2phy_port_id {
41 USB2PHY_PORT_OTG,
42 USB2PHY_PORT_HOST,
43 USB2PHY_NUM_PORTS,
44 };
45
46 struct usb2phy_reg {
47 u32 offset;
48 u32 bitend;
49 u32 bitstart;
50 u32 disable;
51 u32 enable;
52 };
53
54 /**
55 * struct rockchip_chg_det_reg: usb charger detect registers
56 * @cp_det: charging port detected successfully.
57 * @dcp_det: dedicated charging port detected successfully.
58 * @dp_det: assert data pin connect successfully.
59 * @idm_sink_en: open dm sink curren.
60 * @idp_sink_en: open dp sink current.
61 * @idp_src_en: open dm source current.
62 * @rdm_pdwn_en: open dm pull down resistor.
63 * @vdm_src_en: open dm voltage source.
64 * @vdp_src_en: open dp voltage source.
65 * @opmode: utmi operational mode.
66 */
67 struct rockchip_chg_det_reg {
68 struct usb2phy_reg cp_det;
69 struct usb2phy_reg dcp_det;
70 struct usb2phy_reg dp_det;
71 struct usb2phy_reg idm_sink_en;
72 struct usb2phy_reg idp_sink_en;
73 struct usb2phy_reg idp_src_en;
74 struct usb2phy_reg rdm_pdwn_en;
75 struct usb2phy_reg vdm_src_en;
76 struct usb2phy_reg vdp_src_en;
77 struct usb2phy_reg opmode;
78 };
79
80 /**
81 * struct rockchip_usb2phy_port_cfg: usb-phy port configuration.
82 * @phy_sus: phy suspend register.
83 * @bvalid_det_en: vbus valid rise detection enable register.
84 * @bvalid_det_st: vbus valid rise detection status register.
85 * @bvalid_det_clr: vbus valid rise detection clear register.
86 * @ls_det_en: linestate detection enable register.
87 * @ls_det_st: linestate detection state register.
88 * @ls_det_clr: linestate detection clear register.
89 * @iddig_output: iddig output from grf.
90 * @iddig_en: utmi iddig select between grf and phy,
91 * 0: from phy; 1: from grf
92 * @idfall_det_en: id fall detection enable register.
93 * @idfall_det_st: id fall detection state register.
94 * @idfall_det_clr: id fall detection clear register.
95 * @idrise_det_en: id rise detection enable register.
96 * @idrise_det_st: id rise detection state register.
97 * @idrise_det_clr: id rise detection clear register.
98 * @utmi_avalid: utmi vbus avalid status register.
99 * @utmi_bvalid: utmi vbus bvalid status register.
100 * @utmi_iddig: otg port id pin status register.
101 * @utmi_ls: utmi linestate state register.
102 * @utmi_hstdet: utmi host disconnect register.
103 * @vbus_det_en: vbus detect function power down register.
104 */
105 struct rockchip_usb2phy_port_cfg {
106 struct usb2phy_reg phy_sus;
107 struct usb2phy_reg bvalid_det_en;
108 struct usb2phy_reg bvalid_det_st;
109 struct usb2phy_reg bvalid_det_clr;
110 struct usb2phy_reg ls_det_en;
111 struct usb2phy_reg ls_det_st;
112 struct usb2phy_reg ls_det_clr;
113 struct usb2phy_reg iddig_output;
114 struct usb2phy_reg iddig_en;
115 struct usb2phy_reg idfall_det_en;
116 struct usb2phy_reg idfall_det_st;
117 struct usb2phy_reg idfall_det_clr;
118 struct usb2phy_reg idrise_det_en;
119 struct usb2phy_reg idrise_det_st;
120 struct usb2phy_reg idrise_det_clr;
121 struct usb2phy_reg utmi_avalid;
122 struct usb2phy_reg utmi_bvalid;
123 struct usb2phy_reg utmi_iddig;
124 struct usb2phy_reg utmi_ls;
125 struct usb2phy_reg utmi_hstdet;
126 struct usb2phy_reg vbus_det_en;
127 };
128
129 /**
130 * struct rockchip_usb2phy_cfg: usb-phy configuration.
131 * @reg: the address offset of grf for usb-phy config.
132 * @num_ports: specify how many ports that the phy has.
133 * @phy_tuning: phy default parameters tunning.
134 * @clkout_ctl: keep on/turn off output clk of phy.
135 * @chg_det: charger detection registers.
136 */
137 struct rockchip_usb2phy_cfg {
138 u32 reg;
139 u32 num_ports;
140 int (*phy_tuning)(struct rockchip_usb2phy *);
141 struct usb2phy_reg clkout_ctl;
142 const struct rockchip_usb2phy_port_cfg port_cfgs[USB2PHY_NUM_PORTS];
143 const struct rockchip_chg_det_reg chg_det;
144 };
145
146 /**
147 * @dcd_retries: The retry count used to track Data contact
148 * detection process.
149 * @primary_retries: The retry count used to do usb bc detection
150 * primary stage.
151 * @grf: General Register Files register base.
152 * @usbgrf_base : USB General Register Files register base.
153 * @phy_base: the base address of USB PHY.
154 * @phy_rst: phy reset control.
155 * @vbus_det_gpio: VBUS detection via GPIO.
156 * @phy_cfg: phy register configuration, assigned by driver data.
157 */
158 struct rockchip_usb2phy {
159 u8 dcd_retries;
160 u8 primary_retries;
161 struct regmap *grf_base;
162 struct regmap *usbgrf_base;
163 void __iomem *phy_base;
164 struct udevice *vbus_supply[USB2PHY_NUM_PORTS];
165 struct reset_ctl phy_rst;
166 struct gpio_desc vbus_det_gpio;
167 const struct rockchip_usb2phy_cfg *phy_cfg;
168 };
169
get_reg_base(struct rockchip_usb2phy * rphy)170 static inline struct regmap *get_reg_base(struct rockchip_usb2phy *rphy)
171 {
172 return !rphy->usbgrf_base ? rphy->grf_base : rphy->usbgrf_base;
173 }
174
property_enable(struct regmap * base,const struct usb2phy_reg * reg,bool en)175 static inline int property_enable(struct regmap *base,
176 const struct usb2phy_reg *reg, bool en)
177 {
178 u32 val, mask, tmp;
179
180 tmp = en ? reg->enable : reg->disable;
181 mask = GENMASK(reg->bitend, reg->bitstart);
182 val = (tmp << reg->bitstart) | (mask << U2PHY_BIT_WRITEABLE_SHIFT);
183
184 return regmap_write(base, reg->offset, val);
185 }
186
property_enabled(struct regmap * base,const struct usb2phy_reg * reg)187 static inline bool property_enabled(struct regmap *base,
188 const struct usb2phy_reg *reg)
189 {
190 u32 tmp, orig;
191 u32 mask = GENMASK(reg->bitend, reg->bitstart);
192
193 regmap_read(base, reg->offset, &orig);
194
195 tmp = (orig & mask) >> reg->bitstart;
196
197 return tmp == reg->enable;
198 }
199
phy_clear_bits(void __iomem * reg,u32 bits)200 static inline void phy_clear_bits(void __iomem *reg, u32 bits)
201 {
202 u32 tmp = readl(reg);
203
204 tmp &= ~bits;
205 writel(tmp, reg);
206 }
207
phy_set_bits(void __iomem * reg,u32 bits)208 static inline void phy_set_bits(void __iomem *reg, u32 bits)
209 {
210 u32 tmp = readl(reg);
211
212 tmp |= bits;
213 writel(tmp, reg);
214 }
215
phy_update_bits(void __iomem * reg,u32 mask,u32 val)216 static inline void phy_update_bits(void __iomem *reg, u32 mask, u32 val)
217 {
218 u32 tmp = readl(reg);
219
220 tmp &= ~mask;
221 tmp |= val & mask;
222 writel(tmp, reg);
223 }
224
chg_to_string(enum power_supply_type chg_type)225 static const char *chg_to_string(enum power_supply_type chg_type)
226 {
227 switch (chg_type) {
228 case POWER_SUPPLY_TYPE_USB:
229 return "USB_SDP_CHARGER";
230 case POWER_SUPPLY_TYPE_USB_DCP:
231 return "USB_DCP_CHARGER";
232 case POWER_SUPPLY_TYPE_USB_CDP:
233 return "USB_CDP_CHARGER";
234 case POWER_SUPPLY_TYPE_USB_FLOATING:
235 return "USB_FLOATING_CHARGER";
236 default:
237 return "INVALID_CHARGER";
238 }
239 }
240
rockchip_chg_enable_dcd(struct rockchip_usb2phy * rphy,bool en)241 static void rockchip_chg_enable_dcd(struct rockchip_usb2phy *rphy,
242 bool en)
243 {
244 struct regmap *base = get_reg_base(rphy);
245
246 property_enable(base, &rphy->phy_cfg->chg_det.rdm_pdwn_en, en);
247 property_enable(base, &rphy->phy_cfg->chg_det.idp_src_en, en);
248 }
249
rockchip_chg_enable_primary_det(struct rockchip_usb2phy * rphy,bool en)250 static void rockchip_chg_enable_primary_det(struct rockchip_usb2phy *rphy,
251 bool en)
252 {
253 struct regmap *base = get_reg_base(rphy);
254
255 property_enable(base, &rphy->phy_cfg->chg_det.vdp_src_en, en);
256 property_enable(base, &rphy->phy_cfg->chg_det.idm_sink_en, en);
257 }
258
rockchip_chg_enable_secondary_det(struct rockchip_usb2phy * rphy,bool en)259 static void rockchip_chg_enable_secondary_det(struct rockchip_usb2phy *rphy,
260 bool en)
261 {
262 struct regmap *base = get_reg_base(rphy);
263
264 property_enable(base, &rphy->phy_cfg->chg_det.vdm_src_en, en);
265 property_enable(base, &rphy->phy_cfg->chg_det.idp_sink_en, en);
266 }
267
rockchip_chg_primary_det_retry(struct rockchip_usb2phy * rphy)268 static bool rockchip_chg_primary_det_retry(struct rockchip_usb2phy *rphy)
269 {
270 bool vout = false;
271 struct regmap *base = get_reg_base(rphy);
272
273 while (rphy->primary_retries--) {
274 /* voltage source on DP, probe on DM */
275 rockchip_chg_enable_primary_det(rphy, true);
276 mdelay(CHG_PRIMARY_DET_TIME);
277 vout = property_enabled(base, &rphy->phy_cfg->chg_det.cp_det);
278 if (vout)
279 break;
280 }
281
282 rockchip_chg_enable_primary_det(rphy, false);
283 return vout;
284 }
285
286 #ifdef CONFIG_ROCKCHIP_RK3506
rockchip_u2phy_get_vbus_gpio(struct udevice * dev)287 static void rockchip_u2phy_get_vbus_gpio(struct udevice *dev)
288 {
289 ofnode otg_node, extcon_usb_node;
290 struct rockchip_usb2phy *rphy = dev_get_priv(dev);
291
292 rphy->vbus_det_gpio.dev = NULL;
293 otg_node = dev_read_subnode(dev, "otg-port");
294 if (!ofnode_valid(otg_node)) {
295 debug("%s: %s otg subnode not found!\n", __func__, dev->name);
296 return;
297 }
298
299 if (ofnode_read_bool(otg_node, "rockchip,gpio-vbus-det")) {
300 extcon_usb_node = ofnode_path("/extcon-usb");
301 if (!ofnode_valid(extcon_usb_node)) {
302 debug("%s: extcon-usb node not found\n", __func__);
303 return;
304 }
305
306 gpio_request_by_name_nodev(extcon_usb_node, "vbus-gpio", 0,
307 &rphy->vbus_det_gpio, GPIOD_IS_IN);
308 }
309 }
310 #endif
311
rockchip_chg_get_type(void)312 int rockchip_chg_get_type(void)
313 {
314 const struct rockchip_usb2phy_port_cfg *port_cfg;
315 enum power_supply_type chg_type;
316 struct rockchip_usb2phy *rphy;
317 struct udevice *udev;
318 struct regmap *base;
319 bool is_dcd, vout;
320 int ret;
321
322 ret = uclass_get_device_by_name(UCLASS_PHY, "usb2-phy", &udev);
323 if (ret == -ENODEV) {
324 ret = uclass_get_device_by_name(UCLASS_PHY, "usb2phy", &udev);
325 if (ret) {
326 pr_err("%s: get usb2 phy node failed: %d\n", __func__, ret);
327 return ret;
328 }
329 }
330
331 rphy = dev_get_priv(udev);
332 base = get_reg_base(rphy);
333 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG];
334
335 #ifdef CONFIG_ROCKCHIP_RK3506
336 rockchip_u2phy_get_vbus_gpio(udev);
337 #else
338 rphy->vbus_det_gpio.dev = NULL;
339 #endif
340
341 /* Check USB-Vbus status first */
342 if (dm_gpio_is_valid(&rphy->vbus_det_gpio)) {
343 if (dm_gpio_get_value(&rphy->vbus_det_gpio)) {
344 pr_info("%s: vbus gpio voltage valid\n", __func__);
345 } else {
346 pr_info("%s: vbus gpio voltage invalid\n", __func__);
347 return POWER_SUPPLY_TYPE_UNKNOWN;
348 }
349 } else if (!property_enabled(base, &port_cfg->utmi_bvalid)) {
350 pr_info("%s: no charger found\n", __func__);
351 return POWER_SUPPLY_TYPE_UNKNOWN;
352 }
353
354 #ifdef CONFIG_ROCKCHIP_RK3036
355 chg_type = POWER_SUPPLY_TYPE_USB;
356 goto out;
357 #endif
358
359 /* Suspend USB-PHY and put the controller in non-driving mode */
360 property_enable(base, &port_cfg->phy_sus, true);
361 property_enable(base, &rphy->phy_cfg->chg_det.opmode, false);
362
363 rphy->dcd_retries = CHG_DCD_MAX_RETRIES;
364 rphy->primary_retries = CHG_PRI_MAX_RETRIES;
365
366 /* stage 1, start DCD processing stage */
367 rockchip_chg_enable_dcd(rphy, true);
368
369 while (rphy->dcd_retries--) {
370 mdelay(CHG_DCD_POLL_TIME);
371
372 /* get data contact detection status */
373 is_dcd = property_enabled(base, &rphy->phy_cfg->chg_det.dp_det);
374
375 if (is_dcd || !rphy->dcd_retries) {
376 /*
377 * stage 2, turn off DCD circuitry, then
378 * voltage source on DP, probe on DM.
379 */
380 rockchip_chg_enable_dcd(rphy, false);
381 rockchip_chg_enable_primary_det(rphy, true);
382 break;
383 }
384 }
385
386 mdelay(CHG_PRIMARY_DET_TIME);
387 vout = property_enabled(base, &rphy->phy_cfg->chg_det.cp_det);
388 rockchip_chg_enable_primary_det(rphy, false);
389 if (vout) {
390 /* stage 3, voltage source on DM, probe on DP */
391 rockchip_chg_enable_secondary_det(rphy, true);
392 } else {
393 if (!rphy->dcd_retries) {
394 /* floating charger found */
395 chg_type = POWER_SUPPLY_TYPE_USB_FLOATING;
396 goto out;
397 } else {
398 /*
399 * Retry some times to make sure that it's
400 * really a USB SDP charger.
401 */
402 vout = rockchip_chg_primary_det_retry(rphy);
403 if (vout) {
404 /* stage 3, voltage source on DM, probe on DP */
405 rockchip_chg_enable_secondary_det(rphy, true);
406 } else {
407 /* USB SDP charger found */
408 chg_type = POWER_SUPPLY_TYPE_USB;
409 goto out;
410 }
411 }
412 }
413
414 mdelay(CHG_SECONDARY_DET_TIME);
415 vout = property_enabled(base, &rphy->phy_cfg->chg_det.dcp_det);
416 /* stage 4, turn off voltage source */
417 rockchip_chg_enable_secondary_det(rphy, false);
418 if (vout)
419 chg_type = POWER_SUPPLY_TYPE_USB_DCP;
420 else
421 chg_type = POWER_SUPPLY_TYPE_USB_CDP;
422
423 out:
424 /* Resume USB-PHY and put the controller in normal mode */
425 property_enable(base, &rphy->phy_cfg->chg_det.opmode, true);
426 property_enable(base, &port_cfg->phy_sus, false);
427
428 debug("charger is %s\n", chg_to_string(chg_type));
429
430 return chg_type;
431 }
432
rockchip_u2phy_vbus_detect(void)433 int rockchip_u2phy_vbus_detect(void)
434 {
435 int chg_type;
436
437 chg_type = rockchip_chg_get_type();
438
439 return (chg_type == POWER_SUPPLY_TYPE_USB ||
440 chg_type == POWER_SUPPLY_TYPE_USB_CDP) ? 1 : 0;
441 }
442
otg_phy_init(struct dwc2_udc * dev)443 void otg_phy_init(struct dwc2_udc *dev)
444 {
445 const struct rockchip_usb2phy_port_cfg *port_cfg;
446 struct rockchip_usb2phy *rphy;
447 struct udevice *udev;
448 struct regmap *base;
449 int ret;
450
451 ret = uclass_get_device_by_name(UCLASS_PHY, "usb2-phy", &udev);
452 if (ret == -ENODEV) {
453 ret = uclass_get_device_by_name(UCLASS_PHY, "usb2phy", &udev);
454 if (ret) {
455 pr_err("%s: get usb2 phy node failed: %d\n", __func__, ret);
456 return;
457 }
458 }
459
460 rphy = dev_get_priv(udev);
461 base = get_reg_base(rphy);
462 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG];
463
464 /* Set the USB-PHY COMMONONN to 1'b0 to ensure USB's clocks */
465 if(rphy->phy_cfg->clkout_ctl.disable)
466 property_enable(base, &rphy->phy_cfg->clkout_ctl, true);
467
468 /* Reset USB-PHY */
469 property_enable(base, &port_cfg->phy_sus, true);
470 udelay(20);
471 property_enable(base, &port_cfg->phy_sus, false);
472 mdelay(2);
473 }
474
rockchip_usb2phy_reset(struct rockchip_usb2phy * rphy)475 static int rockchip_usb2phy_reset(struct rockchip_usb2phy *rphy)
476 {
477 int ret;
478
479 if (rphy->phy_rst.dev) {
480 ret = reset_assert(&rphy->phy_rst);
481 if (ret < 0) {
482 pr_err("u2phy assert reset failed: %d", ret);
483 return ret;
484 }
485
486 udelay(20);
487
488 ret = reset_deassert(&rphy->phy_rst);
489 if (ret < 0) {
490 pr_err("u2phy deassert reset failed: %d", ret);
491 return ret;
492 }
493
494 udelay(100);
495 }
496
497 return 0;
498 }
499
rockchip_usb2phy_init(struct phy * phy)500 static int rockchip_usb2phy_init(struct phy *phy)
501 {
502 struct udevice *parent = phy->dev->parent;
503 struct rockchip_usb2phy *rphy = dev_get_priv(parent);
504 const struct rockchip_usb2phy_port_cfg *port_cfg;
505 struct regmap *base = get_reg_base(rphy);
506
507 if (phy->id == USB2PHY_PORT_OTG) {
508 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG];
509 } else if (phy->id == USB2PHY_PORT_HOST) {
510 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST];
511 } else {
512 dev_err(phy->dev, "phy id %lu not support", phy->id);
513 return -EINVAL;
514 }
515
516 property_enable(base, &port_cfg->phy_sus, false);
517
518 /* waiting for the utmi_clk to become stable */
519 udelay(2000);
520
521 return 0;
522 }
523
rockchip_usb2phy_exit(struct phy * phy)524 static int rockchip_usb2phy_exit(struct phy *phy)
525 {
526 struct udevice *parent = phy->dev->parent;
527 struct rockchip_usb2phy *rphy = dev_get_priv(parent);
528 const struct rockchip_usb2phy_port_cfg *port_cfg;
529 struct regmap *base = get_reg_base(rphy);
530
531 if (phy->id == USB2PHY_PORT_OTG) {
532 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG];
533 } else if (phy->id == USB2PHY_PORT_HOST) {
534 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST];
535 } else {
536 dev_err(phy->dev, "phy id %lu not support", phy->id);
537 return -EINVAL;
538 }
539
540 property_enable(base, &port_cfg->phy_sus, true);
541
542 return 0;
543 }
544
rockchip_usb2phy_power_on(struct phy * phy)545 static int rockchip_usb2phy_power_on(struct phy *phy)
546 {
547 struct udevice *parent = phy->dev->parent;
548 struct rockchip_usb2phy *rphy = dev_get_priv(parent);
549 struct udevice *vbus = rphy->vbus_supply[phy->id];
550 int ret;
551
552 if (vbus) {
553 ret = regulator_set_enable(vbus, true);
554 if (ret) {
555 pr_err("%s: Failed to set VBus supply\n", __func__);
556 return ret;
557 }
558 }
559
560 return 0;
561 }
562
rockchip_usb2phy_power_off(struct phy * phy)563 static int rockchip_usb2phy_power_off(struct phy *phy)
564 {
565 struct udevice *parent = phy->dev->parent;
566 struct rockchip_usb2phy *rphy = dev_get_priv(parent);
567 struct udevice *vbus = rphy->vbus_supply[phy->id];
568 int ret;
569
570 if (vbus) {
571 ret = regulator_set_enable(vbus, false);
572 if (ret) {
573 pr_err("%s: Failed to set VBus supply\n", __func__);
574 return ret;
575 }
576 }
577
578 return 0;
579 }
580
rockchip_usb2phy_of_xlate(struct phy * phy,struct ofnode_phandle_args * args)581 static int rockchip_usb2phy_of_xlate(struct phy *phy,
582 struct ofnode_phandle_args *args)
583 {
584 const char *dev_name = phy->dev->name;
585 struct udevice *parent = phy->dev->parent;
586 struct rockchip_usb2phy *rphy = dev_get_priv(parent);
587
588 if (!strcasecmp(dev_name, "host-port")) {
589 phy->id = USB2PHY_PORT_HOST;
590 device_get_supply_regulator(phy->dev, "phy-supply",
591 &rphy->vbus_supply[USB2PHY_PORT_HOST]);
592 } else if (!strcasecmp(dev_name, "otg-port")) {
593 phy->id = USB2PHY_PORT_OTG;
594 device_get_supply_regulator(phy->dev, "phy-supply",
595 &rphy->vbus_supply[USB2PHY_PORT_OTG]);
596 if (!rphy->vbus_supply[USB2PHY_PORT_OTG])
597 device_get_supply_regulator(phy->dev, "vbus-supply",
598 &rphy->vbus_supply[USB2PHY_PORT_OTG]);
599 } else {
600 pr_err("%s: invalid dev name\n", __func__);
601 return -EINVAL;
602 }
603
604 return 0;
605 }
606
rockchip_usb2phy_bind(struct udevice * dev)607 static int rockchip_usb2phy_bind(struct udevice *dev)
608 {
609 struct udevice *child;
610 ofnode subnode;
611 const char *node_name;
612 int ret;
613
614 dev_for_each_subnode(subnode, dev) {
615 if (!ofnode_valid(subnode)) {
616 debug("%s: %s subnode not found", __func__, dev->name);
617 return -ENXIO;
618 }
619
620 node_name = ofnode_get_name(subnode);
621 debug("%s: subnode %s\n", __func__, node_name);
622
623 ret = device_bind_driver_to_node(dev, "rockchip_usb2phy_port",
624 node_name, subnode, &child);
625 if (ret) {
626 pr_err("%s: '%s' cannot bind 'rockchip_usb2phy_port'\n",
627 __func__, node_name);
628 return ret;
629 }
630 }
631
632 return 0;
633 }
634
rockchip_usb2phy_probe(struct udevice * dev)635 static int rockchip_usb2phy_probe(struct udevice *dev)
636 {
637 const struct rockchip_usb2phy_cfg *phy_cfgs;
638 struct rockchip_usb2phy *rphy = dev_get_priv(dev);
639 struct udevice *parent = dev->parent;
640 struct udevice *syscon;
641 struct resource res;
642 u32 reg, index;
643 int ret;
644
645 rphy->phy_base = (void __iomem *)dev_read_addr(dev);
646 if (IS_ERR(rphy->phy_base)) {
647 dev_err(dev, "get the base address of usb phy failed\n");
648 }
649
650 if (!strncmp(parent->name, "root_driver", 11) &&
651 dev_read_bool(dev, "rockchip,grf")) {
652 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
653 "rockchip,grf", &syscon);
654 if (ret) {
655 dev_err(dev, "get syscon grf failed\n");
656 return ret;
657 }
658
659 rphy->grf_base = syscon_get_regmap(syscon);
660 } else {
661 rphy->grf_base = syscon_get_regmap(parent);
662 }
663
664 if (rphy->grf_base <= 0) {
665 dev_err(dev, "get syscon grf regmap failed\n");
666 return -EINVAL;
667 }
668
669 if (dev_read_bool(dev, "rockchip,usbgrf")) {
670 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
671 "rockchip,usbgrf", &syscon);
672 if (ret) {
673 dev_err(dev, "get syscon usbgrf failed\n");
674 return ret;
675 }
676
677 rphy->usbgrf_base = syscon_get_regmap(syscon);
678 if (rphy->usbgrf_base <= 0) {
679 dev_err(dev, "get syscon usbgrf regmap failed\n");
680 return -EINVAL;
681 }
682 } else {
683 rphy->usbgrf_base = NULL;
684 }
685
686 if (!strncmp(parent->name, "root_driver", 11)) {
687 ret = dev_read_resource(dev, 0, &res);
688 reg = res.start;
689 } else {
690 ret = ofnode_read_u32(dev_ofnode(dev), "reg", ®);
691 }
692
693 if (ret) {
694 dev_err(dev, "could not read reg\n");
695 return -EINVAL;
696 }
697
698 ret = reset_get_by_name(dev, "phy", &rphy->phy_rst);
699 if (ret)
700 dev_dbg(dev, "no u2phy reset control specified\n");
701
702 phy_cfgs =
703 (const struct rockchip_usb2phy_cfg *)dev_get_driver_data(dev);
704 if (!phy_cfgs) {
705 dev_err(dev, "unable to get phy_cfgs\n");
706 return -EINVAL;
707 }
708
709 /* find out a proper config which can be matched with dt. */
710 index = 0;
711 do {
712 if (phy_cfgs[index].reg == reg) {
713 rphy->phy_cfg = &phy_cfgs[index];
714 break;
715 }
716 ++index;
717 } while (phy_cfgs[index].reg);
718
719 if (!rphy->phy_cfg) {
720 dev_err(dev, "no phy-config can be matched\n");
721 return -EINVAL;
722 }
723
724 if (rphy->phy_cfg->phy_tuning)
725 rphy->phy_cfg->phy_tuning(rphy);
726
727 return 0;
728 }
729
rk322x_usb2phy_tuning(struct rockchip_usb2phy * rphy)730 static int rk322x_usb2phy_tuning(struct rockchip_usb2phy *rphy)
731 {
732 struct regmap *base = get_reg_base(rphy);
733 int ret = 0;
734
735 /* Open pre-emphasize in non-chirp state for PHY0 otg port */
736 if (rphy->phy_cfg->reg == 0x760)
737 ret = regmap_write(base, 0x76c, 0x00070004);
738
739 return ret;
740 }
741
rk3308_usb2phy_tuning(struct rockchip_usb2phy * rphy)742 static int rk3308_usb2phy_tuning(struct rockchip_usb2phy *rphy)
743 {
744 struct regmap *base = get_reg_base(rphy);
745 unsigned int tmp, orig;
746 int ret;
747
748 if (soc_is_rk3308bs()) {
749 /* Enable otg/host port pre-emphasis during non-chirp phase */
750 ret = regmap_read(base, 0, &orig);
751 if (ret)
752 return ret;
753 tmp = orig & ~GENMASK(2, 0);
754 tmp |= BIT(2) & GENMASK(2, 0);
755 ret = regmap_write(base, 0, tmp);
756 if (ret)
757 return ret;
758
759 /* Set otg port squelch trigger point configure to 100mv */
760 ret = regmap_read(base, 0x004, &orig);
761 if (ret)
762 return ret;
763 tmp = orig & ~GENMASK(7, 5);
764 tmp |= 0x40 & GENMASK(7, 5);
765 ret = regmap_write(base, 0x004, tmp);
766 if (ret)
767 return ret;
768
769 ret = regmap_read(base, 0x008, &orig);
770 if (ret)
771 return ret;
772 tmp = orig & ~BIT(0);
773 tmp |= 0x1 & BIT(0);
774 ret = regmap_write(base, 0x008, tmp);
775 if (ret)
776 return ret;
777
778 /* Enable host port pre-emphasis during non-chirp phase */
779 ret = regmap_read(base, 0x400, &orig);
780 if (ret)
781 return ret;
782 tmp = orig & ~GENMASK(2, 0);
783 tmp |= BIT(2) & GENMASK(2, 0);
784 ret = regmap_write(base, 0x400, tmp);
785 if (ret)
786 return ret;
787
788 /* Set host port squelch trigger point configure to 100mv */
789 ret = regmap_read(base, 0x404, &orig);
790 if (ret)
791 return ret;
792 tmp = orig & ~GENMASK(7, 5);
793 tmp |= 0x40 & GENMASK(7, 5);
794 ret = regmap_write(base, 0x404, tmp);
795 if (ret)
796 return ret;
797
798 ret = regmap_read(base, 0x408, &orig);
799 if (ret)
800 return ret;
801 tmp = orig & ~BIT(0);
802 tmp |= 0x1 & BIT(0);
803 ret = regmap_write(base, 0x408, tmp);
804 if (ret)
805 return ret;
806 }
807
808 return 0;
809 }
810
rk3328_usb2phy_tuning(struct rockchip_usb2phy * rphy)811 static int rk3328_usb2phy_tuning(struct rockchip_usb2phy *rphy)
812 {
813 struct regmap *base = get_reg_base(rphy);
814 int ret;
815
816 if (soc_is_px30s()) {
817 /* Enable otg/host port pre-emphasis during non-chirp phase */
818 ret = regmap_update_bits(base, 0x8000, GENMASK(2, 0), BIT(2));
819 if (ret)
820 return ret;
821
822 /* Set otg port squelch trigger point configure to 100mv */
823 ret = regmap_update_bits(base, 0x8004, GENMASK(7, 5), 0x40);
824 if (ret)
825 return ret;
826
827 ret = regmap_update_bits(base, 0x8008, BIT(0), 0x1);
828 if (ret)
829 return ret;
830
831 /* Enable host port pre-emphasis during non-chirp phase */
832 ret = regmap_update_bits(base, 0x8400, GENMASK(2, 0), BIT(2));
833 if (ret)
834 return ret;
835
836 /* Set host port squelch trigger point configure to 100mv */
837 ret = regmap_update_bits(base, 0x8404, GENMASK(7, 5), 0x40);
838 if (ret)
839 return ret;
840
841 ret = regmap_update_bits(base, 0x8408, BIT(0), 0x1);
842 if (ret)
843 return ret;
844 } else {
845 /* Open debug mode for tuning */
846 ret = regmap_write(base, 0x2c, 0xffff0400);
847 if (ret)
848 return ret;
849
850 /* Open pre-emphasize in non-chirp state for otg port */
851 ret = regmap_write(base, 0x0, 0x00070004);
852 if (ret)
853 return ret;
854
855 /* Open pre-emphasize in non-chirp state for host port */
856 ret = regmap_write(base, 0x30, 0x00070004);
857 if (ret)
858 return ret;
859 }
860
861 return 0;
862 }
863
rv1103b_usb2phy_tuning(struct rockchip_usb2phy * rphy)864 static int rv1103b_usb2phy_tuning(struct rockchip_usb2phy *rphy)
865 {
866 /* Always enable pre-emphasis in SOF & EOP & chirp & non-chirp state */
867 phy_update_bits(rphy->phy_base + 0x30, GENMASK(2, 0), 0x07);
868
869 /* Set Tx HS pre_emphasize strength to 3'b001 */
870 phy_update_bits(rphy->phy_base + 0x40, GENMASK(5, 3), (0x01 << 3));
871
872 /* Set RX Squelch trigger point configure to 4'b0000(112.5 mV) */
873 phy_update_bits(rphy->phy_base + 0x64, GENMASK(6, 3), (0x00 << 3));
874
875 /* Turn off differential receiver by default to save power */
876 phy_clear_bits(rphy->phy_base + 0x100, BIT(6));
877
878 /* Set 45ohm HS ODT value to 5'b10111 to increase driver strength */
879 phy_update_bits(rphy->phy_base + 0x11c, GENMASK(4, 0), 0x17);
880
881 /* Set Tx HS eye height tuning to 3'b011(462 mV)*/
882 phy_update_bits(rphy->phy_base + 0x124, GENMASK(4, 2), (0x03 << 2));
883
884 /* Bypass Squelch detector calibration */
885 phy_update_bits(rphy->phy_base + 0x1a4, GENMASK(7, 4), (0x01 << 4));
886 phy_update_bits(rphy->phy_base + 0x1b4, GENMASK(7, 4), (0x01 << 4));
887
888 /* Set HS disconnect detect mode to single ended detect mode */
889 phy_set_bits(rphy->phy_base + 0x70, BIT(2));
890
891 /* Set Host Disconnect Detection to 675mV */
892 phy_update_bits(rphy->phy_base + 0x60, GENMASK(1, 0), 0x0);
893 phy_update_bits(rphy->phy_base + 0x64, GENMASK(7, 7), BIT(7));
894 phy_update_bits(rphy->phy_base + 0x68, GENMASK(0, 0), 0x0);
895
896 return 0;
897 }
898
rv1106_usb2phy_tuning(struct rockchip_usb2phy * rphy)899 static int rv1106_usb2phy_tuning(struct rockchip_usb2phy *rphy)
900 {
901 /* Set HS disconnect detect mode to single ended detect mode */
902 phy_set_bits(rphy->phy_base + 0x70, BIT(2));
903
904 return 0;
905 }
906
rv1126b_usb2phy_tuning(struct rockchip_usb2phy * rphy)907 static int rv1126b_usb2phy_tuning(struct rockchip_usb2phy *rphy)
908 {
909 /* Turn off differential receiver by default to save power */
910 phy_clear_bits(rphy->phy_base + 0x0030, BIT(2));
911 phy_clear_bits(rphy->phy_base + 0x0430, BIT(2));
912
913 /* Enable pre-emphasis during non-chirp phase */
914 phy_update_bits(rphy->phy_base, GENMASK(2, 0), 0x04);
915 phy_update_bits(rphy->phy_base + 0x0400, GENMASK(2, 0), 0x04);
916
917 /* Set HS eye height to 425mv(default is 400mv) */
918 phy_update_bits(rphy->phy_base + 0x0030, GENMASK(6, 4), (0x05 << 4));
919 phy_update_bits(rphy->phy_base + 0x0430, GENMASK(6, 4), (0x05 << 4));
920
921 /* Set Rx squelch trigger point configure to 112.5mv */
922 phy_update_bits(rphy->phy_base + 0x0004, GENMASK(7, 5), (0x00 << 5));
923 phy_update_bits(rphy->phy_base + 0x0008, GENMASK(0, 0), (0x00 << 0));
924 phy_update_bits(rphy->phy_base + 0x0404, GENMASK(7, 5), (0x00 << 5));
925 phy_update_bits(rphy->phy_base + 0x0408, GENMASK(0, 0), (0x00 << 0));
926
927 return 0;
928 }
929
rk3506_usb2phy_tuning(struct rockchip_usb2phy * rphy)930 static int rk3506_usb2phy_tuning(struct rockchip_usb2phy *rphy)
931 {
932 /* Turn off otg0 port differential receiver in suspend mode */
933 phy_clear_bits(rphy->phy_base + 0x30, BIT(2));
934
935 /* Turn off otg1 port differential receiver in suspend mode */
936 phy_clear_bits(rphy->phy_base + 0x430, BIT(2));
937
938 /* Set otg0 port HS eye height to 425mv(default is 450mv) */
939 phy_update_bits(rphy->phy_base + 0x30, GENMASK(6, 4), (0x05 << 4));
940
941 /* Set otg1 port HS eye height to 425mv(default is 450mv) */
942 phy_update_bits(rphy->phy_base + 0x430, GENMASK(6, 4), (0x05 << 4));
943
944 /* Choose the Tx fs/ls data as linestate from TX driver for otg0 port */
945 phy_update_bits(rphy->phy_base + 0x94, GENMASK(6, 3), (0x03 << 3));
946
947 /* Choose the Tx fs/ls data as linestate from TX driver for otg1 port */
948 phy_update_bits(rphy->phy_base + 0x494, GENMASK(6, 3), (0x03 << 3));
949
950 return 0;
951 }
952
rk3528_usb2phy_tuning(struct rockchip_usb2phy * rphy)953 static int rk3528_usb2phy_tuning(struct rockchip_usb2phy *rphy)
954 {
955 if (IS_ERR(rphy->phy_base)) {
956 return PTR_ERR(rphy->phy_base);
957 }
958
959 /* Turn off otg port differential receiver in suspend mode */
960 phy_clear_bits(rphy->phy_base + 0x30, BIT(2));
961
962 /* Turn off host port differential receiver in suspend mode */
963 phy_clear_bits(rphy->phy_base + 0x430, BIT(2));
964
965 /* Set otg port HS eye height to 400mv(default is 450mv) */
966 phy_update_bits(rphy->phy_base + 0x30, GENMASK(6, 4), (0x00 << 4));
967
968 /* Set host port HS eye height to 400mv(default is 450mv) */
969 phy_update_bits(rphy->phy_base + 0x430, GENMASK(6, 4), (0x00 << 4));
970
971 /* Choose the Tx fs/ls data as linestate from TX driver for otg port */
972 phy_update_bits(rphy->phy_base + 0x94, GENMASK(6, 3), (0x03 << 3));
973
974 /* Turn on output clk of phy*/
975 phy_update_bits(rphy->phy_base + 0x41c, GENMASK(7, 2), (0x27 << 2));
976
977 return 0;
978 }
979
rk3562_usb2phy_tuning(struct rockchip_usb2phy * rphy)980 static int rk3562_usb2phy_tuning(struct rockchip_usb2phy *rphy)
981 {
982 if (IS_ERR(rphy->phy_base)) {
983 return PTR_ERR(rphy->phy_base);
984 }
985
986 /* Turn off differential receiver by default to save power */
987 phy_clear_bits(rphy->phy_base + 0x0030, BIT(2));
988 phy_clear_bits(rphy->phy_base + 0x0430, BIT(2));
989
990 /* Enable pre-emphasis during non-chirp phase */
991 phy_update_bits(rphy->phy_base, GENMASK(2, 0), 0x04);
992 phy_update_bits(rphy->phy_base + 0x0400, GENMASK(2, 0), 0x04);
993
994 /* Set HS eye height to 425mv(default is 400mv) */
995 phy_update_bits(rphy->phy_base + 0x0030, GENMASK(6, 4), (0x05 << 4));
996 phy_update_bits(rphy->phy_base + 0x0430, GENMASK(6, 4), (0x05 << 4));
997
998 return 0;
999 }
1000
rk3576_usb2phy_tuning(struct rockchip_usb2phy * rphy)1001 static int rk3576_usb2phy_tuning(struct rockchip_usb2phy *rphy)
1002 {
1003 struct regmap *base = get_reg_base(rphy);
1004 int ret;
1005
1006 if (rphy->phy_cfg->reg == 0x0) {
1007 /* Deassert SIDDQ to power on analog block */
1008 ret = regmap_write(base, 0x0010, GENMASK(29, 29) | 0x0000);
1009 if (ret)
1010 return ret;
1011
1012 /* Do reset after exit IDDQ mode */
1013 ret = rockchip_usb2phy_reset(rphy);
1014 if (ret)
1015 return ret;
1016
1017 /* HS DC Voltage Level Adjustment 4'b1001 : +5.89% */
1018 ret = regmap_write(base, 0x000c, GENMASK(27, 24) | 0x0900);
1019 if (ret)
1020 return ret;
1021
1022 /* HS Transmitter Pre-Emphasis Current Control 2'b10 : 2x */
1023 ret = regmap_write(base, 0x0010, GENMASK(20, 19) | 0x0010);
1024 if (ret)
1025 return ret;
1026 } else if (rphy->phy_cfg->reg == 0x2000) {
1027 /* Deassert SIDDQ to power on analog block */
1028 ret = regmap_write(base, 0x2010, GENMASK(29, 29) | 0x0000);
1029 if (ret)
1030 return ret;
1031
1032 /* Do reset after exit IDDQ mode */
1033 ret = rockchip_usb2phy_reset(rphy);
1034 if (ret)
1035 return ret;
1036
1037 /* HS DC Voltage Level Adjustment 4'b1001 : +5.89% */
1038 ret = regmap_write(base, 0x200c, GENMASK(27, 24) | 0x0900);
1039 if (ret)
1040 return ret;
1041
1042 /* HS Transmitter Pre-Emphasis Current Control 2'b10 : 2x */
1043 ret = regmap_write(base, 0x2010, GENMASK(20, 19) | 0x0010);
1044 if (ret)
1045 return ret;
1046 }
1047
1048 return 0;
1049 }
1050
rk3588_usb2phy_tuning(struct rockchip_usb2phy * rphy)1051 static int rk3588_usb2phy_tuning(struct rockchip_usb2phy *rphy)
1052 {
1053 struct regmap *base = get_reg_base(rphy);
1054 int ret;
1055
1056 /* Deassert SIDDQ to power on analog block */
1057 ret = regmap_write(base, 0x0008, GENMASK(29, 29) | 0x0000);
1058 if (ret)
1059 return ret;
1060
1061 /* Do reset after exit IDDQ mode */
1062 ret = rockchip_usb2phy_reset(rphy);
1063 if (ret)
1064 return ret;
1065
1066 /* HS DC Voltage Level Adjustment 4'b1001 : +5.89% */
1067 ret = regmap_write(base, 0x0004, GENMASK(27, 24) | 0x0900);
1068 if (ret)
1069 return ret;
1070
1071 /* HS Transmitter Pre-Emphasis Current Control 2'b10 : 2x */
1072 ret = regmap_write(base, 0x0008, GENMASK(20, 19) | 0x0010);
1073 if (ret)
1074 return ret;
1075
1076 return 0;
1077 }
1078
1079 static struct phy_ops rockchip_usb2phy_ops = {
1080 .init = rockchip_usb2phy_init,
1081 .exit = rockchip_usb2phy_exit,
1082 .power_on = rockchip_usb2phy_power_on,
1083 .power_off = rockchip_usb2phy_power_off,
1084 .of_xlate = rockchip_usb2phy_of_xlate,
1085 };
1086
1087 static const struct rockchip_usb2phy_cfg rk1808_phy_cfgs[] = {
1088 {
1089 .reg = 0x100,
1090 .num_ports = 2,
1091 .clkout_ctl = { 0x108, 4, 4, 1, 0 },
1092 .port_cfgs = {
1093 [USB2PHY_PORT_OTG] = {
1094 .phy_sus = { 0x0100, 8, 0, 0, 0x1d1 },
1095 .bvalid_det_en = { 0x0110, 2, 2, 0, 1 },
1096 .bvalid_det_st = { 0x0114, 2, 2, 0, 1 },
1097 .bvalid_det_clr = { 0x0118, 2, 2, 0, 1 },
1098 .iddig_output = { 0x0100, 10, 10, 0, 1 },
1099 .iddig_en = { 0x0100, 9, 9, 0, 1 },
1100 .idfall_det_en = { 0x0110, 5, 5, 0, 1 },
1101 .idfall_det_st = { 0x0114, 5, 5, 0, 1 },
1102 .idfall_det_clr = { 0x0118, 5, 5, 0, 1 },
1103 .idrise_det_en = { 0x0110, 4, 4, 0, 1 },
1104 .idrise_det_st = { 0x0114, 4, 4, 0, 1 },
1105 .idrise_det_clr = { 0x0118, 4, 4, 0, 1 },
1106 .ls_det_en = { 0x0110, 0, 0, 0, 1 },
1107 .ls_det_st = { 0x0114, 0, 0, 0, 1 },
1108 .ls_det_clr = { 0x0118, 0, 0, 0, 1 },
1109 .utmi_avalid = { 0x0120, 10, 10, 0, 1 },
1110 .utmi_bvalid = { 0x0120, 9, 9, 0, 1 },
1111 .utmi_iddig = { 0x0120, 6, 6, 0, 1 },
1112 .utmi_ls = { 0x0120, 5, 4, 0, 1 },
1113 .vbus_det_en = { 0x001c, 15, 15, 1, 0 },
1114 },
1115 [USB2PHY_PORT_HOST] = {
1116 .phy_sus = { 0x104, 8, 0, 0, 0x1d1 },
1117 .ls_det_en = { 0x110, 1, 1, 0, 1 },
1118 .ls_det_st = { 0x114, 1, 1, 0, 1 },
1119 .ls_det_clr = { 0x118, 1, 1, 0, 1 },
1120 .utmi_ls = { 0x120, 17, 16, 0, 1 },
1121 .utmi_hstdet = { 0x120, 19, 19, 0, 1 }
1122 }
1123 },
1124 .chg_det = {
1125 .opmode = { 0x0100, 3, 0, 5, 1 },
1126 .cp_det = { 0x0120, 24, 24, 0, 1 },
1127 .dcp_det = { 0x0120, 23, 23, 0, 1 },
1128 .dp_det = { 0x0120, 25, 25, 0, 1 },
1129 .idm_sink_en = { 0x0108, 8, 8, 0, 1 },
1130 .idp_sink_en = { 0x0108, 7, 7, 0, 1 },
1131 .idp_src_en = { 0x0108, 9, 9, 0, 1 },
1132 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 },
1133 .vdm_src_en = { 0x0108, 12, 12, 0, 1 },
1134 .vdp_src_en = { 0x0108, 11, 11, 0, 1 },
1135 },
1136 },
1137 { /* sentinel */ }
1138 };
1139
1140 static const struct rockchip_usb2phy_cfg rk3036_phy_cfgs[] = {
1141 {
1142 .reg = 0x17c,
1143 .num_ports = 2,
1144 .clkout_ctl = { 0x017c, 11, 11, 1, 0 },
1145 .port_cfgs = {
1146 [USB2PHY_PORT_OTG] = {
1147 .phy_sus = { 0x017c, 8, 0, 0, 0x1d1 },
1148 .bvalid_det_en = { 0x017c, 14, 14, 0, 1 },
1149 .bvalid_det_st = { 0x017c, 15, 15, 0, 1 },
1150 .bvalid_det_clr = { 0x017c, 15, 15, 0, 1 },
1151 .iddig_output = { 0x017c, 10, 10, 0, 1 },
1152 .iddig_en = { 0x017c, 9, 9, 0, 1 },
1153 .idfall_det_en = { 0x01a0, 2, 2, 0, 1 },
1154 .idfall_det_st = { 0x01a0, 3, 3, 0, 1 },
1155 .idfall_det_clr = { 0x01a0, 3, 3, 0, 1 },
1156 .idrise_det_en = { 0x01a0, 0, 0, 0, 1 },
1157 .idrise_det_st = { 0x01a0, 1, 1, 0, 1 },
1158 .idrise_det_clr = { 0x01a0, 1, 1, 0, 1 },
1159 .ls_det_en = { 0x017c, 12, 12, 0, 1 },
1160 .ls_det_st = { 0x017c, 13, 13, 0, 1 },
1161 .ls_det_clr = { 0x017c, 13, 13, 0, 1 },
1162 .utmi_bvalid = { 0x014c, 5, 5, 0, 1 },
1163 .utmi_iddig = { 0x014c, 8, 8, 0, 1 },
1164 .utmi_ls = { 0x014c, 7, 6, 0, 1 },
1165 },
1166 [USB2PHY_PORT_HOST] = {
1167 .phy_sus = { 0x0194, 8, 0, 0, 0x1d1 },
1168 .ls_det_en = { 0x0194, 14, 14, 0, 1 },
1169 .ls_det_st = { 0x0194, 15, 15, 0, 1 },
1170 .ls_det_clr = { 0x0194, 15, 15, 0, 1 }
1171 }
1172 },
1173 },
1174 { /* sentinel */ }
1175 };
1176
1177 static const struct rockchip_usb2phy_cfg rk312x_phy_cfgs[] = {
1178 {
1179 .reg = 0x17c,
1180 .num_ports = 2,
1181 .clkout_ctl = { 0x0190, 15, 15, 1, 0 },
1182 .port_cfgs = {
1183 [USB2PHY_PORT_OTG] = {
1184 .phy_sus = { 0x017c, 8, 0, 0, 0x1d1 },
1185 .bvalid_det_en = { 0x017c, 14, 14, 0, 1 },
1186 .bvalid_det_st = { 0x017c, 15, 15, 0, 1 },
1187 .bvalid_det_clr = { 0x017c, 15, 15, 0, 1 },
1188 .iddig_output = { 0x017c, 10, 10, 0, 1 },
1189 .iddig_en = { 0x017c, 9, 9, 0, 1 },
1190 .idfall_det_en = { 0x01a0, 2, 2, 0, 1 },
1191 .idfall_det_st = { 0x01a0, 3, 3, 0, 1 },
1192 .idfall_det_clr = { 0x01a0, 3, 3, 0, 1 },
1193 .idrise_det_en = { 0x01a0, 0, 0, 0, 1 },
1194 .idrise_det_st = { 0x01a0, 1, 1, 0, 1 },
1195 .idrise_det_clr = { 0x01a0, 1, 1, 0, 1 },
1196 .ls_det_en = { 0x017c, 12, 12, 0, 1 },
1197 .ls_det_st = { 0x017c, 13, 13, 0, 1 },
1198 .ls_det_clr = { 0x017c, 13, 13, 0, 1 },
1199 .utmi_bvalid = { 0x014c, 5, 5, 0, 1 },
1200 .utmi_iddig = { 0x014c, 8, 8, 0, 1 },
1201 .utmi_ls = { 0x014c, 7, 6, 0, 1 },
1202 },
1203 [USB2PHY_PORT_HOST] = {
1204 .phy_sus = { 0x0194, 8, 0, 0, 0x1d1 },
1205 .ls_det_en = { 0x0194, 14, 14, 0, 1 },
1206 .ls_det_st = { 0x0194, 15, 15, 0, 1 },
1207 .ls_det_clr = { 0x0194, 15, 15, 0, 1 }
1208 }
1209 },
1210 .chg_det = {
1211 .opmode = { 0x017c, 3, 0, 5, 1 },
1212 .cp_det = { 0x02c0, 6, 6, 0, 1 },
1213 .dcp_det = { 0x02c0, 5, 5, 0, 1 },
1214 .dp_det = { 0x02c0, 7, 7, 0, 1 },
1215 .idm_sink_en = { 0x0184, 8, 8, 0, 1 },
1216 .idp_sink_en = { 0x0184, 7, 7, 0, 1 },
1217 .idp_src_en = { 0x0184, 9, 9, 0, 1 },
1218 .rdm_pdwn_en = { 0x0184, 10, 10, 0, 1 },
1219 .vdm_src_en = { 0x0184, 12, 12, 0, 1 },
1220 .vdp_src_en = { 0x0184, 11, 11, 0, 1 },
1221 },
1222 },
1223 { /* sentinel */ }
1224 };
1225
1226 static const struct rockchip_usb2phy_cfg rk322x_phy_cfgs[] = {
1227 {
1228 .reg = 0x760,
1229 .num_ports = 2,
1230 .phy_tuning = rk322x_usb2phy_tuning,
1231 .clkout_ctl = { 0x0768, 4, 4, 1, 0 },
1232 .port_cfgs = {
1233 [USB2PHY_PORT_OTG] = {
1234 .phy_sus = { 0x0760, 8, 0, 0, 0x1d1 },
1235 .bvalid_det_en = { 0x0680, 3, 3, 0, 1 },
1236 .bvalid_det_st = { 0x0690, 3, 3, 0, 1 },
1237 .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 },
1238 .iddig_output = { 0x0760, 10, 10, 0, 1 },
1239 .iddig_en = { 0x0760, 9, 9, 0, 1 },
1240 .idfall_det_en = { 0x0680, 6, 6, 0, 1 },
1241 .idfall_det_st = { 0x0690, 6, 6, 0, 1 },
1242 .idfall_det_clr = { 0x06a0, 6, 6, 0, 1 },
1243 .idrise_det_en = { 0x0680, 5, 5, 0, 1 },
1244 .idrise_det_st = { 0x0690, 5, 5, 0, 1 },
1245 .idrise_det_clr = { 0x06a0, 5, 5, 0, 1 },
1246 .ls_det_en = { 0x0680, 2, 2, 0, 1 },
1247 .ls_det_st = { 0x0690, 2, 2, 0, 1 },
1248 .ls_det_clr = { 0x06a0, 2, 2, 0, 1 },
1249 .utmi_bvalid = { 0x0480, 4, 4, 0, 1 },
1250 .utmi_iddig = { 0x0480, 1, 1, 0, 1 },
1251 .utmi_ls = { 0x0480, 3, 2, 0, 1 },
1252 .vbus_det_en = { 0x0788, 15, 15, 1, 0 },
1253 },
1254 [USB2PHY_PORT_HOST] = {
1255 .phy_sus = { 0x0764, 8, 0, 0, 0x1d1 },
1256 .ls_det_en = { 0x0680, 4, 4, 0, 1 },
1257 .ls_det_st = { 0x0690, 4, 4, 0, 1 },
1258 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 }
1259 }
1260 },
1261 .chg_det = {
1262 .opmode = { 0x0760, 3, 0, 5, 1 },
1263 .cp_det = { 0x0884, 4, 4, 0, 1 },
1264 .dcp_det = { 0x0884, 3, 3, 0, 1 },
1265 .dp_det = { 0x0884, 5, 5, 0, 1 },
1266 .idm_sink_en = { 0x0768, 8, 8, 0, 1 },
1267 .idp_sink_en = { 0x0768, 7, 7, 0, 1 },
1268 .idp_src_en = { 0x0768, 9, 9, 0, 1 },
1269 .rdm_pdwn_en = { 0x0768, 10, 10, 0, 1 },
1270 .vdm_src_en = { 0x0768, 12, 12, 0, 1 },
1271 .vdp_src_en = { 0x0768, 11, 11, 0, 1 },
1272 },
1273 },
1274 {
1275 .reg = 0x800,
1276 .num_ports = 2,
1277 .clkout_ctl = { 0x0808, 4, 4, 1, 0 },
1278 .port_cfgs = {
1279 [USB2PHY_PORT_OTG] = {
1280 .phy_sus = { 0x804, 8, 0, 0, 0x1d1 },
1281 .ls_det_en = { 0x0684, 1, 1, 0, 1 },
1282 .ls_det_st = { 0x0694, 1, 1, 0, 1 },
1283 .ls_det_clr = { 0x06a4, 1, 1, 0, 1 }
1284 },
1285 [USB2PHY_PORT_HOST] = {
1286 .phy_sus = { 0x800, 8, 0, 0, 0x1d1 },
1287 .ls_det_en = { 0x0684, 0, 0, 0, 1 },
1288 .ls_det_st = { 0x0694, 0, 0, 0, 1 },
1289 .ls_det_clr = { 0x06a4, 0, 0, 0, 1 }
1290 }
1291 },
1292 },
1293 { /* sentinel */ }
1294 };
1295
1296 static const struct rockchip_usb2phy_cfg rk3308_phy_cfgs[] = {
1297 {
1298 .reg = 0x100,
1299 .num_ports = 2,
1300 .phy_tuning = rk3308_usb2phy_tuning,
1301 .clkout_ctl = { 0x0108, 4, 4, 1, 0 },
1302 .port_cfgs = {
1303 [USB2PHY_PORT_OTG] = {
1304 .phy_sus = { 0x0100, 8, 0, 0, 0x1d1 },
1305 .bvalid_det_en = { 0x3020, 2, 2, 0, 1 },
1306 .bvalid_det_st = { 0x3024, 2, 2, 0, 1 },
1307 .bvalid_det_clr = { 0x3028, 2, 2, 0, 1 },
1308 .iddig_output = { 0x0100, 10, 10, 0, 1 },
1309 .iddig_en = { 0x0100, 9, 9, 0, 1 },
1310 .idfall_det_en = { 0x3020, 5, 5, 0, 1 },
1311 .idfall_det_st = { 0x3024, 5, 5, 0, 1 },
1312 .idfall_det_clr = { 0x3028, 5, 5, 0, 1 },
1313 .idrise_det_en = { 0x3020, 4, 4, 0, 1 },
1314 .idrise_det_st = { 0x3024, 4, 4, 0, 1 },
1315 .idrise_det_clr = { 0x3028, 4, 4, 0, 1 },
1316 .ls_det_en = { 0x3020, 0, 0, 0, 1 },
1317 .ls_det_st = { 0x3024, 0, 0, 0, 1 },
1318 .ls_det_clr = { 0x3028, 0, 0, 0, 1 },
1319 .utmi_avalid = { 0x0120, 10, 10, 0, 1 },
1320 .utmi_bvalid = { 0x0120, 9, 9, 0, 1 },
1321 .utmi_iddig = { 0x0120, 6, 6, 0, 1 },
1322 .utmi_ls = { 0x0120, 5, 4, 0, 1 },
1323 .vbus_det_en = { 0x001c, 15, 15, 1, 0 },
1324 },
1325 [USB2PHY_PORT_HOST] = {
1326 .phy_sus = { 0x0104, 8, 0, 0, 0x1d1 },
1327 .ls_det_en = { 0x3020, 1, 1, 0, 1 },
1328 .ls_det_st = { 0x3024, 1, 1, 0, 1 },
1329 .ls_det_clr = { 0x3028, 1, 1, 0, 1 },
1330 .utmi_ls = { 0x120, 17, 16, 0, 1 },
1331 .utmi_hstdet = { 0x120, 19, 19, 0, 1 }
1332 }
1333 },
1334 .chg_det = {
1335 .opmode = { 0x0100, 3, 0, 5, 1 },
1336 .cp_det = { 0x0120, 24, 24, 0, 1 },
1337 .dcp_det = { 0x0120, 23, 23, 0, 1 },
1338 .dp_det = { 0x0120, 25, 25, 0, 1 },
1339 .idm_sink_en = { 0x0108, 8, 8, 0, 1 },
1340 .idp_sink_en = { 0x0108, 7, 7, 0, 1 },
1341 .idp_src_en = { 0x0108, 9, 9, 0, 1 },
1342 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 },
1343 .vdm_src_en = { 0x0108, 12, 12, 0, 1 },
1344 .vdp_src_en = { 0x0108, 11, 11, 0, 1 },
1345 },
1346 },
1347 { /* sentinel */ }
1348 };
1349
1350 static const struct rockchip_usb2phy_cfg rk3328_phy_cfgs[] = {
1351 {
1352 .reg = 0x100,
1353 .num_ports = 2,
1354 .phy_tuning = rk3328_usb2phy_tuning,
1355 .clkout_ctl = { 0x108, 4, 4, 1, 0 },
1356 .port_cfgs = {
1357 [USB2PHY_PORT_OTG] = {
1358 .phy_sus = { 0x0100, 8, 0, 0, 0x1d1 },
1359 .bvalid_det_en = { 0x0110, 2, 2, 0, 1 },
1360 .bvalid_det_st = { 0x0114, 2, 2, 0, 1 },
1361 .bvalid_det_clr = { 0x0118, 2, 2, 0, 1 },
1362 .iddig_output = { 0x0100, 10, 10, 0, 1 },
1363 .iddig_en = { 0x0100, 9, 9, 0, 1 },
1364 .idfall_det_en = { 0x0110, 5, 5, 0, 1 },
1365 .idfall_det_st = { 0x0114, 5, 5, 0, 1 },
1366 .idfall_det_clr = { 0x0118, 5, 5, 0, 1 },
1367 .idrise_det_en = { 0x0110, 4, 4, 0, 1 },
1368 .idrise_det_st = { 0x0114, 4, 4, 0, 1 },
1369 .idrise_det_clr = { 0x0118, 4, 4, 0, 1 },
1370 .ls_det_en = { 0x0110, 0, 0, 0, 1 },
1371 .ls_det_st = { 0x0114, 0, 0, 0, 1 },
1372 .ls_det_clr = { 0x0118, 0, 0, 0, 1 },
1373 .utmi_avalid = { 0x0120, 10, 10, 0, 1 },
1374 .utmi_bvalid = { 0x0120, 9, 9, 0, 1 },
1375 .utmi_iddig = { 0x0120, 6, 6, 0, 1 },
1376 .utmi_ls = { 0x0120, 5, 4, 0, 1 },
1377 .vbus_det_en = { 0x001c, 15, 15, 1, 0 },
1378 },
1379 [USB2PHY_PORT_HOST] = {
1380 .phy_sus = { 0x104, 8, 0, 0, 0x1d1 },
1381 .ls_det_en = { 0x110, 1, 1, 0, 1 },
1382 .ls_det_st = { 0x114, 1, 1, 0, 1 },
1383 .ls_det_clr = { 0x118, 1, 1, 0, 1 },
1384 .utmi_ls = { 0x120, 17, 16, 0, 1 },
1385 .utmi_hstdet = { 0x120, 19, 19, 0, 1 }
1386 }
1387 },
1388 .chg_det = {
1389 .opmode = { 0x0100, 3, 0, 5, 1 },
1390 .cp_det = { 0x0120, 24, 24, 0, 1 },
1391 .dcp_det = { 0x0120, 23, 23, 0, 1 },
1392 .dp_det = { 0x0120, 25, 25, 0, 1 },
1393 .idm_sink_en = { 0x0108, 8, 8, 0, 1 },
1394 .idp_sink_en = { 0x0108, 7, 7, 0, 1 },
1395 .idp_src_en = { 0x0108, 9, 9, 0, 1 },
1396 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 },
1397 .vdm_src_en = { 0x0108, 12, 12, 0, 1 },
1398 .vdp_src_en = { 0x0108, 11, 11, 0, 1 },
1399 },
1400 },
1401 { /* sentinel */ }
1402 };
1403
1404 static const struct rockchip_usb2phy_cfg rk3368_phy_cfgs[] = {
1405 {
1406 .reg = 0x700,
1407 .num_ports = 2,
1408 .clkout_ctl = { 0x0724, 15, 15, 1, 0 },
1409 .port_cfgs = {
1410 [USB2PHY_PORT_OTG] = {
1411 .phy_sus = { 0x0700, 8, 0, 0, 0x1d1 },
1412 .bvalid_det_en = { 0x0680, 3, 3, 0, 1 },
1413 .bvalid_det_st = { 0x0690, 3, 3, 0, 1 },
1414 .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 },
1415 .ls_det_en = { 0x0680, 2, 2, 0, 1 },
1416 .ls_det_st = { 0x0690, 2, 2, 0, 1 },
1417 .ls_det_clr = { 0x06a0, 2, 2, 0, 1 },
1418 .utmi_bvalid = { 0x04bc, 23, 23, 0, 1 },
1419 .utmi_ls = { 0x04bc, 25, 24, 0, 1 },
1420 },
1421 [USB2PHY_PORT_HOST] = {
1422 .phy_sus = { 0x0728, 8, 0, 0, 0x1d1 },
1423 .ls_det_en = { 0x0680, 4, 4, 0, 1 },
1424 .ls_det_st = { 0x0690, 4, 4, 0, 1 },
1425 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 }
1426 }
1427 },
1428 .chg_det = {
1429 .opmode = { 0x0700, 3, 0, 5, 1 },
1430 .cp_det = { 0x04b8, 30, 30, 0, 1 },
1431 .dcp_det = { 0x04b8, 29, 29, 0, 1 },
1432 .dp_det = { 0x04b8, 31, 31, 0, 1 },
1433 .idm_sink_en = { 0x0718, 8, 8, 0, 1 },
1434 .idp_sink_en = { 0x0718, 7, 7, 0, 1 },
1435 .idp_src_en = { 0x0718, 9, 9, 0, 1 },
1436 .rdm_pdwn_en = { 0x0718, 10, 10, 0, 1 },
1437 .vdm_src_en = { 0x0718, 12, 12, 0, 1 },
1438 .vdp_src_en = { 0x0718, 11, 11, 0, 1 },
1439 },
1440 },
1441 { /* sentinel */ }
1442 };
1443
1444 static const struct rockchip_usb2phy_cfg rk3399_phy_cfgs[] = {
1445 {
1446 .reg = 0xe450,
1447 .num_ports = 2,
1448 .clkout_ctl = { 0xe450, 4, 4, 1, 0 },
1449 .port_cfgs = {
1450 [USB2PHY_PORT_OTG] = {
1451 .phy_sus = { 0xe454, 8, 0, 0x052, 0x1d1 },
1452 .bvalid_det_en = { 0xe3c0, 3, 3, 0, 1 },
1453 .bvalid_det_st = { 0xe3e0, 3, 3, 0, 1 },
1454 .bvalid_det_clr = { 0xe3d0, 3, 3, 0, 1 },
1455 .idfall_det_en = { 0xe3c0, 5, 5, 0, 1 },
1456 .idfall_det_st = { 0xe3e0, 5, 5, 0, 1 },
1457 .idfall_det_clr = { 0xe3d0, 5, 5, 0, 1 },
1458 .idrise_det_en = { 0xe3c0, 4, 4, 0, 1 },
1459 .idrise_det_st = { 0xe3e0, 4, 4, 0, 1 },
1460 .idrise_det_clr = { 0xe3d0, 4, 4, 0, 1 },
1461 .ls_det_en = { 0xe3c0, 2, 2, 0, 1 },
1462 .ls_det_st = { 0xe3e0, 2, 2, 0, 1 },
1463 .ls_det_clr = { 0xe3d0, 2, 2, 0, 1 },
1464 .utmi_avalid = { 0xe2ac, 7, 7, 0, 1 },
1465 .utmi_bvalid = { 0xe2ac, 12, 12, 0, 1 },
1466 .utmi_iddig = { 0xe2ac, 8, 8, 0, 1 },
1467 .utmi_ls = { 0xe2ac, 14, 13, 0, 1 },
1468 .vbus_det_en = { 0x449c, 15, 15, 1, 0 },
1469 },
1470 [USB2PHY_PORT_HOST] = {
1471 .phy_sus = { 0xe458, 1, 0, 0x2, 0x1 },
1472 .ls_det_en = { 0xe3c0, 6, 6, 0, 1 },
1473 .ls_det_st = { 0xe3e0, 6, 6, 0, 1 },
1474 .ls_det_clr = { 0xe3d0, 6, 6, 0, 1 },
1475 .utmi_ls = { 0xe2ac, 22, 21, 0, 1 },
1476 .utmi_hstdet = { 0xe2ac, 23, 23, 0, 1 }
1477 }
1478 },
1479 .chg_det = {
1480 .opmode = { 0xe454, 3, 0, 5, 1 },
1481 .cp_det = { 0xe2ac, 2, 2, 0, 1 },
1482 .dcp_det = { 0xe2ac, 1, 1, 0, 1 },
1483 .dp_det = { 0xe2ac, 0, 0, 0, 1 },
1484 .idm_sink_en = { 0xe450, 8, 8, 0, 1 },
1485 .idp_sink_en = { 0xe450, 7, 7, 0, 1 },
1486 .idp_src_en = { 0xe450, 9, 9, 0, 1 },
1487 .rdm_pdwn_en = { 0xe450, 10, 10, 0, 1 },
1488 .vdm_src_en = { 0xe450, 12, 12, 0, 1 },
1489 .vdp_src_en = { 0xe450, 11, 11, 0, 1 },
1490 },
1491 },
1492 {
1493 .reg = 0xe460,
1494 .num_ports = 2,
1495 .clkout_ctl = { 0xe460, 4, 4, 1, 0 },
1496 .port_cfgs = {
1497 [USB2PHY_PORT_OTG] = {
1498 .phy_sus = { 0xe464, 8, 0, 0x052, 0x1d1 },
1499 .bvalid_det_en = { 0xe3c0, 8, 8, 0, 1 },
1500 .bvalid_det_st = { 0xe3e0, 8, 8, 0, 1 },
1501 .bvalid_det_clr = { 0xe3d0, 8, 8, 0, 1 },
1502 .idfall_det_en = { 0xe3c0, 10, 10, 0, 1 },
1503 .idfall_det_st = { 0xe3e0, 10, 10, 0, 1 },
1504 .idfall_det_clr = { 0xe3d0, 10, 10, 0, 1 },
1505 .idrise_det_en = { 0xe3c0, 9, 9, 0, 1 },
1506 .idrise_det_st = { 0xe3e0, 9, 9, 0, 1 },
1507 .idrise_det_clr = { 0xe3d0, 9, 9, 0, 1 },
1508 .ls_det_en = { 0xe3c0, 7, 7, 0, 1 },
1509 .ls_det_st = { 0xe3e0, 7, 7, 0, 1 },
1510 .ls_det_clr = { 0xe3d0, 7, 7, 0, 1 },
1511 .utmi_avalid = { 0xe2ac, 10, 10, 0, 1 },
1512 .utmi_bvalid = { 0xe2ac, 16, 16, 0, 1 },
1513 .utmi_iddig = { 0xe2ac, 11, 11, 0, 1 },
1514 .utmi_ls = { 0xe2ac, 18, 17, 0, 1 },
1515 .vbus_det_en = { 0x451c, 15, 15, 1, 0 },
1516 },
1517 [USB2PHY_PORT_HOST] = {
1518 .phy_sus = { 0xe468, 1, 0, 0x2, 0x1 },
1519 .ls_det_en = { 0xe3c0, 11, 11, 0, 1 },
1520 .ls_det_st = { 0xe3e0, 11, 11, 0, 1 },
1521 .ls_det_clr = { 0xe3d0, 11, 11, 0, 1 },
1522 .utmi_ls = { 0xe2ac, 26, 25, 0, 1 },
1523 .utmi_hstdet = { 0xe2ac, 27, 27, 0, 1 }
1524 }
1525 },
1526 .chg_det = {
1527 .opmode = { 0xe464, 3, 0, 5, 1 },
1528 .cp_det = { 0xe2ac, 5, 5, 0, 1 },
1529 .dcp_det = { 0xe2ac, 4, 4, 0, 1 },
1530 .dp_det = { 0xe2ac, 3, 3, 0, 1 },
1531 .idm_sink_en = { 0xe460, 8, 8, 0, 1 },
1532 .idp_sink_en = { 0xe460, 7, 7, 0, 1 },
1533 .idp_src_en = { 0xe460, 9, 9, 0, 1 },
1534 .rdm_pdwn_en = { 0xe460, 10, 10, 0, 1 },
1535 .vdm_src_en = { 0xe460, 12, 12, 0, 1 },
1536 .vdp_src_en = { 0xe460, 11, 11, 0, 1 },
1537 },
1538 },
1539 { /* sentinel */ }
1540 };
1541
1542 static const struct rockchip_usb2phy_cfg rv1103b_phy_cfgs[] = {
1543 {
1544 .reg = 0x20e10000,
1545 .num_ports = 1,
1546 .phy_tuning = rv1103b_usb2phy_tuning,
1547 .clkout_ctl = { 0x50058, 4, 4, 1, 0 },
1548 .port_cfgs = {
1549 [USB2PHY_PORT_OTG] = {
1550 .phy_sus = { 0x50050, 8, 0, 0, 0x1d1 },
1551 .bvalid_det_en = { 0x50100, 2, 2, 0, 1 },
1552 .bvalid_det_st = { 0x50104, 2, 2, 0, 1 },
1553 .bvalid_det_clr = { 0x50108, 2, 2, 0, 1 },
1554 .iddig_output = { 0x50050, 10, 10, 0, 1 },
1555 .iddig_en = { 0x50050, 9, 9, 0, 1 },
1556 .idfall_det_en = { 0x50100, 5, 5, 0, 1 },
1557 .idfall_det_st = { 0x50104, 5, 5, 0, 1 },
1558 .idfall_det_clr = { 0x50108, 5, 5, 0, 1 },
1559 .idrise_det_en = { 0x50100, 4, 4, 0, 1 },
1560 .idrise_det_st = { 0x50104, 4, 4, 0, 1 },
1561 .idrise_det_clr = { 0x50108, 4, 4, 0, 1 },
1562 .ls_det_en = { 0x50100, 0, 0, 0, 1 },
1563 .ls_det_st = { 0x50104, 0, 0, 0, 1 },
1564 .ls_det_clr = { 0x50108, 0, 0, 0, 1 },
1565 .utmi_avalid = { 0x50060, 10, 10, 0, 1 },
1566 .utmi_bvalid = { 0x50060, 9, 9, 0, 1 },
1567 .utmi_iddig = { 0x50060, 6, 6, 0, 1 },
1568 .utmi_ls = { 0x50060, 5, 4, 0, 1 },
1569 },
1570 },
1571 .chg_det = {
1572 .opmode = { 0x50050, 3, 0, 5, 1 },
1573 .cp_det = { 0x50060, 13, 13, 0, 1 },
1574 .dcp_det = { 0x50060, 12, 12, 0, 1 },
1575 .dp_det = { 0x50060, 14, 14, 0, 1 },
1576 .idm_sink_en = { 0x50058, 8, 8, 0, 1 },
1577 .idp_sink_en = { 0x50058, 7, 7, 0, 1 },
1578 .idp_src_en = { 0x50058, 9, 9, 0, 1 },
1579 .rdm_pdwn_en = { 0x50058, 10, 10, 0, 1 },
1580 .vdm_src_en = { 0x50058, 12, 12, 0, 1 },
1581 .vdp_src_en = { 0x50058, 11, 11, 0, 1 },
1582 },
1583 },
1584 { /* sentinel */ }
1585 };
1586
1587 static const struct rockchip_usb2phy_cfg rv1106_phy_cfgs[] = {
1588 {
1589 .reg = 0xff3e0000,
1590 .num_ports = 1,
1591 .phy_tuning = rv1106_usb2phy_tuning,
1592 .clkout_ctl = { 0x0058, 4, 4, 1, 0 },
1593 .port_cfgs = {
1594 [USB2PHY_PORT_OTG] = {
1595 .phy_sus = { 0x0050, 8, 0, 0, 0x1d1 },
1596 .bvalid_det_en = { 0x0100, 2, 2, 0, 1 },
1597 .bvalid_det_st = { 0x0104, 2, 2, 0, 1 },
1598 .bvalid_det_clr = { 0x0108, 2, 2, 0, 1 },
1599 .iddig_output = { 0x0050, 10, 10, 0, 1 },
1600 .iddig_en = { 0x0050, 9, 9, 0, 1 },
1601 .idfall_det_en = { 0x0100, 5, 5, 0, 1 },
1602 .idfall_det_st = { 0x0104, 5, 5, 0, 1 },
1603 .idfall_det_clr = { 0x0108, 5, 5, 0, 1 },
1604 .idrise_det_en = { 0x0100, 4, 4, 0, 1 },
1605 .idrise_det_st = { 0x0104, 4, 4, 0, 1 },
1606 .idrise_det_clr = { 0x0108, 4, 4, 0, 1 },
1607 .ls_det_en = { 0x0100, 0, 0, 0, 1 },
1608 .ls_det_st = { 0x0104, 0, 0, 0, 1 },
1609 .ls_det_clr = { 0x0108, 0, 0, 0, 1 },
1610 .utmi_avalid = { 0x0060, 10, 10, 0, 1 },
1611 .utmi_bvalid = { 0x0060, 9, 9, 0, 1 },
1612 .utmi_iddig = { 0x0060, 6, 6, 0, 1 },
1613 .utmi_ls = { 0x0060, 5, 4, 0, 1 },
1614 },
1615 },
1616 .chg_det = {
1617 .opmode = { 0x0050, 3, 0, 5, 1 },
1618 .cp_det = { 0x0060, 13, 13, 0, 1 },
1619 .dcp_det = { 0x0060, 12, 12, 0, 1 },
1620 .dp_det = { 0x0060, 14, 14, 0, 1 },
1621 .idm_sink_en = { 0x0058, 8, 8, 0, 1 },
1622 .idp_sink_en = { 0x0058, 7, 7, 0, 1 },
1623 .idp_src_en = { 0x0058, 9, 9, 0, 1 },
1624 .rdm_pdwn_en = { 0x0058, 10, 10, 0, 1 },
1625 .vdm_src_en = { 0x0058, 12, 12, 0, 1 },
1626 .vdp_src_en = { 0x0058, 11, 11, 0, 1 },
1627 },
1628 },
1629 { /* sentinel */ }
1630 };
1631
1632 static const struct rockchip_usb2phy_cfg rv1108_phy_cfgs[] = {
1633 {
1634 .reg = 0x100,
1635 .num_ports = 2,
1636 .clkout_ctl = { 0x108, 4, 4, 1, 0 },
1637 .port_cfgs = {
1638 [USB2PHY_PORT_OTG] = {
1639 .phy_sus = { 0x0ffa0100, 8, 0, 0, 0x1d1 },
1640 .bvalid_det_en = { 0x0680, 3, 3, 0, 1 },
1641 .bvalid_det_st = { 0x0690, 3, 3, 0, 1 },
1642 .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 },
1643 .ls_det_en = { 0x0680, 2, 2, 0, 1 },
1644 .ls_det_st = { 0x0690, 2, 2, 0, 1 },
1645 .ls_det_clr = { 0x06a0, 2, 2, 0, 1 },
1646 .utmi_bvalid = { 0x0804, 10, 10, 0, 1 },
1647 .utmi_ls = { 0x0804, 13, 12, 0, 1 },
1648 },
1649 [USB2PHY_PORT_HOST] = {
1650 .phy_sus = { 0x0ffa0104, 8, 0, 0, 0x1d1 },
1651 .ls_det_en = { 0x0680, 4, 4, 0, 1 },
1652 .ls_det_st = { 0x0690, 4, 4, 0, 1 },
1653 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 },
1654 .utmi_ls = { 0x0804, 9, 8, 0, 1 },
1655 .utmi_hstdet = { 0x0804, 7, 7, 0, 1 }
1656 }
1657 },
1658 .chg_det = {
1659 .opmode = { 0x0ffa0100, 3, 0, 5, 1 },
1660 .cp_det = { 0x0804, 1, 1, 0, 1 },
1661 .dcp_det = { 0x0804, 0, 0, 0, 1 },
1662 .dp_det = { 0x0804, 2, 2, 0, 1 },
1663 .idm_sink_en = { 0x0ffa0108, 8, 8, 0, 1 },
1664 .idp_sink_en = { 0x0ffa0108, 7, 7, 0, 1 },
1665 .idp_src_en = { 0x0ffa0108, 9, 9, 0, 1 },
1666 .rdm_pdwn_en = { 0x0ffa0108, 10, 10, 0, 1 },
1667 .vdm_src_en = { 0x0ffa0108, 12, 12, 0, 1 },
1668 .vdp_src_en = { 0x0ffa0108, 11, 11, 0, 1 },
1669 },
1670 },
1671 { /* sentinel */ }
1672 };
1673
1674 static const struct rockchip_usb2phy_cfg rv1126b_phy_cfgs[] = {
1675 {
1676 .reg = 0x21400000,
1677 .num_ports = 2,
1678 .phy_tuning = rv1126b_usb2phy_tuning,
1679 .clkout_ctl = { 0x10028, 3, 3, 1, 0 },
1680 .port_cfgs = {
1681 [USB2PHY_PORT_OTG] = {
1682 .phy_sus = { 0x10020, 8, 0, 0, 0x1d1 },
1683 .bvalid_det_en = { 0x10074, 2, 2, 0, 1 },
1684 .bvalid_det_st = { 0x10078, 2, 2, 0, 1 },
1685 .bvalid_det_clr = { 0x1007c, 2, 2, 0, 1 },
1686 .iddig_output = { 0x10020, 10, 10, 0, 1 },
1687 .iddig_en = { 0x10020, 9, 9, 0, 1 },
1688 .idfall_det_en = { 0x10074, 5, 5, 0, 1 },
1689 .idfall_det_st = { 0x10078, 5, 5, 0, 1 },
1690 .idfall_det_clr = { 0x1007c, 5, 5, 0, 1 },
1691 .idrise_det_en = { 0x10074, 4, 4, 0, 1 },
1692 .idrise_det_st = { 0x10078, 4, 4, 0, 1 },
1693 .idrise_det_clr = { 0x1007c, 4, 4, 0, 1 },
1694 .ls_det_en = { 0x10074, 0, 0, 0, 1 },
1695 .ls_det_st = { 0x10078, 0, 0, 0, 1 },
1696 .ls_det_clr = { 0x1007c, 0, 0, 0, 1 },
1697 .utmi_avalid = { 0x10110, 1, 1, 0, 1 },
1698 .utmi_bvalid = { 0x10110, 0, 0, 0, 1 },
1699 .utmi_iddig = { 0x10110, 6, 6, 0, 1 },
1700 .utmi_ls = { 0x10110, 5, 4, 0, 1 },
1701 },
1702 [USB2PHY_PORT_HOST] = {
1703 .phy_sus = { 0x1001c, 8, 0, 0x1d2, 0x1d1 },
1704 .ls_det_en = { 0x10090, 0, 0, 0, 1 },
1705 .ls_det_st = { 0x10094, 0, 0, 0, 1 },
1706 .ls_det_clr = { 0x10098, 0, 0, 0, 1 },
1707 .utmi_ls = { 0x10110, 13, 12, 0, 1 },
1708 }
1709 },
1710 .chg_det = {
1711 .opmode = { 0x10020, 3, 0, 5, 1 },
1712 .cp_det = { 0x10110, 19, 19, 0, 1 },
1713 .dcp_det = { 0x10110, 18, 18, 0, 1 },
1714 .dp_det = { 0x10110, 20, 20, 0, 1 },
1715 .idm_sink_en = { 0x1002c, 1, 1, 0, 1 },
1716 .idp_sink_en = { 0x1002c, 0, 0, 0, 1 },
1717 .idp_src_en = { 0x1002c, 2, 2, 0, 1 },
1718 .rdm_pdwn_en = { 0x1002c, 3, 3, 0, 1 },
1719 .vdm_src_en = { 0x1002c, 5, 5, 0, 1 },
1720 .vdp_src_en = { 0x1002c, 4, 4, 0, 1 },
1721 },
1722 },
1723 { /* sentinel */ }
1724 };
1725
1726 static const struct rockchip_usb2phy_cfg rk3506_phy_cfgs[] = {
1727 {
1728 .reg = 0xff2b0000,
1729 .num_ports = 2,
1730 .phy_tuning = rk3506_usb2phy_tuning,
1731 .port_cfgs = {
1732 [USB2PHY_PORT_OTG] = {
1733 .phy_sus = { 0x0060, 8, 0, 0, 0x1d1 },
1734 .bvalid_det_en = { 0x0150, 2, 2, 0, 1 },
1735 .bvalid_det_st = { 0x0154, 2, 2, 0, 1 },
1736 .bvalid_det_clr = { 0x0158, 2, 2, 0, 1 },
1737 .iddig_output = { 0x0060, 10, 10, 0, 1 },
1738 .iddig_en = { 0x0060, 9, 9, 0, 1 },
1739 .idfall_det_en = { 0x0150, 5, 5, 0, 1 },
1740 .idfall_det_st = { 0x0154, 5, 5, 0, 1 },
1741 .idfall_det_clr = { 0x0158, 5, 5, 0, 1 },
1742 .idrise_det_en = { 0x0150, 4, 4, 0, 1 },
1743 .idrise_det_st = { 0x0154, 4, 4, 0, 1 },
1744 .idrise_det_clr = { 0x0158, 4, 4, 0, 1 },
1745 .ls_det_en = { 0x0150, 0, 0, 0, 1 },
1746 .ls_det_st = { 0x0154, 0, 0, 0, 1 },
1747 .ls_det_clr = { 0x0158, 0, 0, 0, 1 },
1748 .utmi_avalid = { 0x0118, 1, 1, 0, 1 },
1749 .utmi_bvalid = { 0x0118, 0, 0, 0, 1 },
1750 .utmi_iddig = { 0x0118, 6, 6, 0, 1 },
1751 .utmi_ls = { 0x0118, 5, 4, 0, 1 },
1752 },
1753 [USB2PHY_PORT_HOST] = {
1754 .phy_sus = { 0x0070, 8, 0, 0x1d2, 0x1d1 },
1755 .ls_det_en = { 0x0170, 0, 0, 0, 1 },
1756 .ls_det_st = { 0x0174, 0, 0, 0, 1 },
1757 .ls_det_clr = { 0x0178, 0, 0, 0, 1 },
1758 .utmi_ls = { 0x0118, 13, 12, 0, 1 },
1759 .utmi_hstdet = { 0x0118, 15, 15, 0, 1 }
1760 }
1761 },
1762 .chg_det = {
1763 .opmode = { 0x0060, 3, 0, 5, 1 },
1764 .cp_det = { 0x0118, 19, 19, 0, 1 },
1765 .dcp_det = { 0x0118, 18, 18, 0, 1 },
1766 .dp_det = { 0x0118, 20, 20, 0, 1 },
1767 .idm_sink_en = { 0x006c, 1, 1, 0, 1 },
1768 .idp_sink_en = { 0x006c, 0, 0, 0, 1 },
1769 .idp_src_en = { 0x006c, 2, 2, 0, 1 },
1770 .rdm_pdwn_en = { 0x006c, 3, 3, 0, 1 },
1771 .vdm_src_en = { 0x006c, 5, 5, 0, 1 },
1772 .vdp_src_en = { 0x006c, 4, 4, 0, 1 },
1773 },
1774 }
1775 };
1776
1777 static const struct rockchip_usb2phy_cfg rk3528_phy_cfgs[] = {
1778 {
1779 .reg = 0xffdf0000,
1780 .num_ports = 2,
1781 .phy_tuning = rk3528_usb2phy_tuning,
1782 .port_cfgs = {
1783 [USB2PHY_PORT_OTG] = {
1784 .phy_sus = { 0x6004c, 8, 0, 0, 0x1d1 },
1785 .bvalid_det_en = { 0x60074, 2, 2, 0, 1 },
1786 .bvalid_det_st = { 0x60078, 2, 2, 0, 1 },
1787 .bvalid_det_clr = { 0x6007c, 2, 2, 0, 1 },
1788 .iddig_output = { 0x6004c, 10, 10, 0, 1 },
1789 .iddig_en = { 0x6004c, 9, 9, 0, 1 },
1790 .idfall_det_en = { 0x60074, 5, 5, 0, 1 },
1791 .idfall_det_st = { 0x60078, 5, 5, 0, 1 },
1792 .idfall_det_clr = { 0x6007c, 5, 5, 0, 1 },
1793 .idrise_det_en = { 0x60074, 4, 4, 0, 1 },
1794 .idrise_det_st = { 0x60078, 4, 4, 0, 1 },
1795 .idrise_det_clr = { 0x6007c, 4, 4, 0, 1 },
1796 .ls_det_en = { 0x60074, 0, 0, 0, 1 },
1797 .ls_det_st = { 0x60078, 0, 0, 0, 1 },
1798 .ls_det_clr = { 0x6007c, 0, 0, 0, 1 },
1799 .utmi_avalid = { 0x6006c, 1, 1, 0, 1 },
1800 .utmi_bvalid = { 0x6006c, 0, 0, 0, 1 },
1801 .utmi_iddig = { 0x6006c, 6, 6, 0, 1 },
1802 .utmi_ls = { 0x6006c, 5, 4, 0, 1 },
1803 },
1804 [USB2PHY_PORT_HOST] = {
1805 .phy_sus = { 0x6005c, 8, 0, 0x1d2, 0x1d1 },
1806 .ls_det_en = { 0x60090, 0, 0, 0, 1 },
1807 .ls_det_st = { 0x60094, 0, 0, 0, 1 },
1808 .ls_det_clr = { 0x60098, 0, 0, 0, 1 },
1809 .utmi_ls = { 0x6006c, 13, 12, 0, 1 },
1810 .utmi_hstdet = { 0x6006c, 15, 15, 0, 1 }
1811 }
1812 },
1813 .chg_det = {
1814 .opmode = { 0x6004c, 3, 0, 5, 1 },
1815 .cp_det = { 0x6006c, 19, 19, 0, 1 },
1816 .dcp_det = { 0x6006c, 18, 18, 0, 1 },
1817 .dp_det = { 0x6006c, 20, 20, 0, 1 },
1818 .idm_sink_en = { 0x60058, 1, 1, 0, 1 },
1819 .idp_sink_en = { 0x60058, 0, 0, 0, 1 },
1820 .idp_src_en = { 0x60058, 2, 2, 0, 1 },
1821 .rdm_pdwn_en = { 0x60058, 3, 3, 0, 1 },
1822 .vdm_src_en = { 0x60058, 5, 5, 0, 1 },
1823 .vdp_src_en = { 0x60058, 4, 4, 0, 1 },
1824 },
1825 }
1826 };
1827
1828 static const struct rockchip_usb2phy_cfg rk3562_phy_cfgs[] = {
1829 {
1830 .reg = 0xff740000,
1831 .num_ports = 2,
1832 .phy_tuning = rk3562_usb2phy_tuning,
1833 .clkout_ctl = { 0x0108, 4, 4, 1, 0 },
1834 .port_cfgs = {
1835 [USB2PHY_PORT_OTG] = {
1836 .phy_sus = { 0x0100, 8, 0, 0, 0x1d1 },
1837 .bvalid_det_en = { 0x0110, 2, 2, 0, 1 },
1838 .bvalid_det_st = { 0x0114, 2, 2, 0, 1 },
1839 .bvalid_det_clr = { 0x0118, 2, 2, 0, 1 },
1840 .iddig_output = { 0x0100, 10, 10, 0, 1 },
1841 .iddig_en = { 0x0100, 9, 9, 0, 1 },
1842 .idfall_det_en = { 0x0110, 5, 5, 0, 1 },
1843 .idfall_det_st = { 0x0114, 5, 5, 0, 1 },
1844 .idfall_det_clr = { 0x0118, 5, 5, 0, 1 },
1845 .idrise_det_en = { 0x0110, 4, 4, 0, 1 },
1846 .idrise_det_st = { 0x0114, 4, 4, 0, 1 },
1847 .idrise_det_clr = { 0x0118, 4, 4, 0, 1 },
1848 .ls_det_en = { 0x0110, 0, 0, 0, 1 },
1849 .ls_det_st = { 0x0114, 0, 0, 0, 1 },
1850 .ls_det_clr = { 0x0118, 0, 0, 0, 1 },
1851 .utmi_avalid = { 0x0120, 10, 10, 0, 1 },
1852 .utmi_bvalid = { 0x0120, 9, 9, 0, 1 },
1853 .utmi_iddig = { 0x0120, 6, 6, 0, 1 },
1854 .utmi_ls = { 0x0120, 5, 4, 0, 1 },
1855 },
1856 [USB2PHY_PORT_HOST] = {
1857 .phy_sus = { 0x0104, 8, 0, 0x1d2, 0x1d1 },
1858 .ls_det_en = { 0x0110, 1, 1, 0, 1 },
1859 .ls_det_st = { 0x0114, 1, 1, 0, 1 },
1860 .ls_det_clr = { 0x0118, 1, 1, 0, 1 },
1861 .utmi_ls = { 0x0120, 17, 16, 0, 1 },
1862 .utmi_hstdet = { 0x0120, 19, 19, 0, 1 }
1863 }
1864 },
1865 .chg_det = {
1866 .opmode = { 0x0100, 3, 0, 5, 1 },
1867 .cp_det = { 0x0120, 24, 24, 0, 1 },
1868 .dcp_det = { 0x0120, 23, 23, 0, 1 },
1869 .dp_det = { 0x0120, 25, 25, 0, 1 },
1870 .idm_sink_en = { 0x0108, 8, 8, 0, 1 },
1871 .idp_sink_en = { 0x0108, 7, 7, 0, 1 },
1872 .idp_src_en = { 0x0108, 9, 9, 0, 1 },
1873 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 },
1874 .vdm_src_en = { 0x0108, 12, 12, 0, 1 },
1875 .vdp_src_en = { 0x0108, 11, 11, 0, 1 },
1876 },
1877 },
1878 { /* sentinel */ }
1879 };
1880
1881 static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] = {
1882 {
1883 .reg = 0xfe8a0000,
1884 .num_ports = 2,
1885 .clkout_ctl = { 0x0008, 4, 4, 1, 0 },
1886 .port_cfgs = {
1887 [USB2PHY_PORT_OTG] = {
1888 .phy_sus = { 0x0000, 8, 0, 0x052, 0x1d1 },
1889 .bvalid_det_en = { 0x0080, 2, 2, 0, 1 },
1890 .bvalid_det_st = { 0x0084, 2, 2, 0, 1 },
1891 .bvalid_det_clr = { 0x0088, 2, 2, 0, 1 },
1892 .iddig_output = { 0x0000, 10, 10, 0, 1 },
1893 .iddig_en = { 0x0000, 9, 9, 0, 1 },
1894 .idfall_det_en = { 0x0080, 5, 5, 0, 1 },
1895 .idfall_det_st = { 0x0084, 5, 5, 0, 1 },
1896 .idfall_det_clr = { 0x0088, 5, 5, 0, 1 },
1897 .idrise_det_en = { 0x0080, 4, 4, 0, 1 },
1898 .idrise_det_st = { 0x0084, 4, 4, 0, 1 },
1899 .idrise_det_clr = { 0x0088, 4, 4, 0, 1 },
1900 .ls_det_en = { 0x0080, 0, 0, 0, 1 },
1901 .ls_det_st = { 0x0084, 0, 0, 0, 1 },
1902 .ls_det_clr = { 0x0088, 0, 0, 0, 1 },
1903 .utmi_avalid = { 0x00c0, 10, 10, 0, 1 },
1904 .utmi_bvalid = { 0x00c0, 9, 9, 0, 1 },
1905 .utmi_iddig = { 0x00c0, 6, 6, 0, 1 },
1906 .utmi_ls = { 0x00c0, 5, 4, 0, 1 },
1907 },
1908 [USB2PHY_PORT_HOST] = {
1909 .phy_sus = { 0x0004, 8, 0, 0x1d2, 0x1d1 },
1910 .ls_det_en = { 0x0080, 1, 1, 0, 1 },
1911 .ls_det_st = { 0x0084, 1, 1, 0, 1 },
1912 .ls_det_clr = { 0x0088, 1, 1, 0, 1 },
1913 .utmi_ls = { 0x00c0, 17, 16, 0, 1 },
1914 .utmi_hstdet = { 0x00c0, 19, 19, 0, 1 }
1915 }
1916 },
1917 .chg_det = {
1918 .opmode = { 0x0000, 3, 0, 5, 1 },
1919 .cp_det = { 0x00c0, 24, 24, 0, 1 },
1920 .dcp_det = { 0x00c0, 23, 23, 0, 1 },
1921 .dp_det = { 0x00c0, 25, 25, 0, 1 },
1922 .idm_sink_en = { 0x0008, 8, 8, 0, 1 },
1923 .idp_sink_en = { 0x0008, 7, 7, 0, 1 },
1924 .idp_src_en = { 0x0008, 9, 9, 0, 1 },
1925 .rdm_pdwn_en = { 0x0008, 10, 10, 0, 1 },
1926 .vdm_src_en = { 0x0008, 12, 12, 0, 1 },
1927 .vdp_src_en = { 0x0008, 11, 11, 0, 1 },
1928 },
1929 },
1930 {
1931 .reg = 0xfe8b0000,
1932 .num_ports = 2,
1933 .clkout_ctl = { 0x0008, 4, 4, 1, 0 },
1934 .port_cfgs = {
1935 [USB2PHY_PORT_OTG] = {
1936 .phy_sus = { 0x0000, 8, 0, 0x1d2, 0x1d1 },
1937 .ls_det_en = { 0x0080, 0, 0, 0, 1 },
1938 .ls_det_st = { 0x0084, 0, 0, 0, 1 },
1939 .ls_det_clr = { 0x0088, 0, 0, 0, 1 },
1940 .utmi_ls = { 0x00c0, 5, 4, 0, 1 },
1941 .utmi_hstdet = { 0x00c0, 7, 7, 0, 1 }
1942 },
1943 [USB2PHY_PORT_HOST] = {
1944 .phy_sus = { 0x0004, 8, 0, 0x1d2, 0x1d1 },
1945 .ls_det_en = { 0x0080, 1, 1, 0, 1 },
1946 .ls_det_st = { 0x0084, 1, 1, 0, 1 },
1947 .ls_det_clr = { 0x0088, 1, 1, 0, 1 },
1948 .utmi_ls = { 0x00c0, 17, 16, 0, 1 },
1949 .utmi_hstdet = { 0x00c0, 19, 19, 0, 1 }
1950 }
1951 },
1952 },
1953 { /* sentinel */ }
1954 };
1955
1956 static const struct rockchip_usb2phy_cfg rk3576_phy_cfgs[] = {
1957 {
1958 .reg = 0x0000,
1959 .num_ports = 1,
1960 .phy_tuning = rk3576_usb2phy_tuning,
1961 .clkout_ctl = { 0x0008, 0, 0, 1, 0 },
1962 .port_cfgs = {
1963 [USB2PHY_PORT_OTG] = {
1964 .phy_sus = { 0x0000, 8, 0, 0, 0x1d1 },
1965 .ls_det_en = { 0x00c0, 0, 0, 0, 1 },
1966 .ls_det_st = { 0x00c4, 0, 0, 0, 1 },
1967 .ls_det_clr = { 0x00c8, 0, 0, 0, 1 },
1968 .utmi_avalid = { 0x0080, 1, 1, 0, 1 },
1969 .utmi_bvalid = { 0x0080, 0, 0, 0, 1 },
1970 .utmi_iddig = { 0x0080, 6, 6, 0, 1 },
1971 .utmi_ls = { 0x0080, 5, 4, 0, 1 },
1972 }
1973 },
1974 .chg_det = {
1975 .opmode = { 0x0000, 8, 0, 0x055, 0x001 },
1976 .cp_det = { 0x0080, 8, 8, 0, 1 },
1977 .dcp_det = { 0x0080, 8, 8, 0, 1 },
1978 .dp_det = { 0x0080, 9, 9, 1, 0 },
1979 .idm_sink_en = { 0x0010, 5, 5, 1, 0 },
1980 .idp_sink_en = { 0x0010, 5, 5, 0, 1 },
1981 .idp_src_en = { 0x0010, 14, 14, 0, 1 },
1982 .rdm_pdwn_en = { 0x0010, 14, 14, 0, 1 },
1983 .vdm_src_en = { 0x0010, 7, 6, 0, 3 },
1984 .vdp_src_en = { 0x0010, 7, 6, 0, 3 },
1985 },
1986 },
1987 {
1988 .reg = 0x2000,
1989 .num_ports = 1,
1990 .phy_tuning = rk3576_usb2phy_tuning,
1991 .clkout_ctl = { 0x2008, 0, 0, 1, 0 },
1992 .port_cfgs = {
1993 [USB2PHY_PORT_OTG] = {
1994 .phy_sus = { 0x2000, 8, 0, 0, 0x1d1 },
1995 .ls_det_en = { 0x20c0, 0, 0, 0, 1 },
1996 .ls_det_st = { 0x20c4, 0, 0, 0, 1 },
1997 .ls_det_clr = { 0x20c8, 0, 0, 0, 1 },
1998 .utmi_avalid = { 0x2080, 1, 1, 0, 1 },
1999 .utmi_bvalid = { 0x2080, 0, 0, 0, 1 },
2000 .utmi_iddig = { 0x2080, 6, 6, 0, 1 },
2001 .utmi_ls = { 0x2080, 5, 4, 0, 1 },
2002 }
2003 },
2004 },
2005 { /* sentinel */ }
2006 };
2007
2008 static const struct rockchip_usb2phy_cfg rk3588_phy_cfgs[] = {
2009 {
2010 .reg = 0x0000,
2011 .num_ports = 1,
2012 .phy_tuning = rk3588_usb2phy_tuning,
2013 .clkout_ctl = { 0x0000, 0, 0, 1, 0 },
2014 .port_cfgs = {
2015 [USB2PHY_PORT_OTG] = {
2016 .phy_sus = { 0x000c, 11, 11, 0, 1 },
2017 .ls_det_en = { 0x0080, 0, 0, 0, 1 },
2018 .ls_det_st = { 0x0084, 0, 0, 0, 1 },
2019 .ls_det_clr = { 0x0088, 0, 0, 0, 1 },
2020 .utmi_avalid = { 0x00c0, 7, 7, 0, 1 },
2021 .utmi_bvalid = { 0x00c0, 6, 6, 0, 1 },
2022 .utmi_iddig = { 0x00c0, 5, 5, 0, 1 },
2023 .utmi_ls = { 0x00c0, 10, 9, 0, 1 },
2024 }
2025 },
2026 .chg_det = {
2027 .opmode = { 0x0008, 2, 2, 1, 0 },
2028 .cp_det = { 0x00c0, 0, 0, 0, 1 },
2029 .dcp_det = { 0x00c0, 0, 0, 0, 1 },
2030 .dp_det = { 0x00c0, 1, 1, 1, 0 },
2031 .idm_sink_en = { 0x0008, 5, 5, 1, 0 },
2032 .idp_sink_en = { 0x0008, 5, 5, 0, 1 },
2033 .idp_src_en = { 0x0008, 14, 14, 0, 1 },
2034 .rdm_pdwn_en = { 0x0008, 14, 14, 0, 1 },
2035 .vdm_src_en = { 0x0008, 7, 6, 0, 3 },
2036 .vdp_src_en = { 0x0008, 7, 6, 0, 3 },
2037 },
2038 },
2039 {
2040 .reg = 0x4000,
2041 .num_ports = 1,
2042 .phy_tuning = rk3588_usb2phy_tuning,
2043 .clkout_ctl = { 0x0000, 0, 0, 1, 0 },
2044 .port_cfgs = {
2045 /* Select suspend control from controller */
2046 [USB2PHY_PORT_OTG] = {
2047 .phy_sus = { 0x000c, 11, 11, 0, 0 },
2048 .ls_det_en = { 0x0080, 0, 0, 0, 1 },
2049 .ls_det_st = { 0x0084, 0, 0, 0, 1 },
2050 .ls_det_clr = { 0x0088, 0, 0, 0, 1 },
2051 .utmi_ls = { 0x00c0, 10, 9, 0, 1 },
2052 }
2053 },
2054 },
2055 {
2056 .reg = 0x8000,
2057 .num_ports = 1,
2058 .phy_tuning = rk3588_usb2phy_tuning,
2059 .clkout_ctl = { 0x0000, 0, 0, 1, 0 },
2060 .port_cfgs = {
2061 [USB2PHY_PORT_HOST] = {
2062 .phy_sus = { 0x0008, 2, 2, 0, 1 },
2063 .ls_det_en = { 0x0080, 0, 0, 0, 1 },
2064 .ls_det_st = { 0x0084, 0, 0, 0, 1 },
2065 .ls_det_clr = { 0x0088, 0, 0, 0, 1 },
2066 .utmi_ls = { 0x00c0, 10, 9, 0, 1 },
2067 }
2068 },
2069 },
2070 {
2071 .reg = 0xc000,
2072 .num_ports = 1,
2073 .phy_tuning = rk3588_usb2phy_tuning,
2074 .clkout_ctl = { 0x0000, 0, 0, 1, 0 },
2075 .port_cfgs = {
2076 [USB2PHY_PORT_HOST] = {
2077 .phy_sus = { 0x0008, 2, 2, 0, 1 },
2078 .ls_det_en = { 0x0080, 0, 0, 0, 1 },
2079 .ls_det_st = { 0x0084, 0, 0, 0, 1 },
2080 .ls_det_clr = { 0x0088, 0, 0, 0, 1 },
2081 .utmi_ls = { 0x00c0, 10, 9, 0, 1 },
2082 }
2083 },
2084 },
2085 { /* sentinel */ }
2086 };
2087
2088 static const struct udevice_id rockchip_usb2phy_ids[] = {
2089 #ifdef CONFIG_ROCKCHIP_PX30
2090 { .compatible = "rockchip,px30-usb2phy", .data = (ulong)&rk3328_phy_cfgs },
2091 #endif
2092 #ifdef CONFIG_ROCKCHIP_RK1808
2093 { .compatible = "rockchip,rk1808-usb2phy", .data = (ulong)&rk1808_phy_cfgs },
2094 #endif
2095 #ifdef CONFIG_ROCKCHIP_RK3036
2096 { .compatible = "rockchip,rk3036-usb2phy", .data = (ulong)&rk3036_phy_cfgs },
2097 #endif
2098 #if defined CONFIG_ROCKCHIP_RK3128 || defined CONFIG_ROCKCHIP_RK3126
2099 { .compatible = "rockchip,rk3128-usb2phy", .data = (ulong)&rk312x_phy_cfgs },
2100 #endif
2101 #ifdef CONFIG_ROCKCHIP_RK322X
2102 { .compatible = "rockchip,rk322x-usb2phy", .data = (ulong)&rk322x_phy_cfgs },
2103 #endif
2104 #ifdef CONFIG_ROCKCHIP_RK3308
2105 { .compatible = "rockchip,rk3308-usb2phy", .data = (ulong)&rk3308_phy_cfgs },
2106 #endif
2107 #ifdef CONFIG_ROCKCHIP_RK3328
2108 { .compatible = "rockchip,rk3328-usb2phy", .data = (ulong)&rk3328_phy_cfgs },
2109 #endif
2110 #ifdef CONFIG_ROCKCHIP_RK3368
2111 { .compatible = "rockchip,rk3368-usb2phy", .data = (ulong)&rk3368_phy_cfgs },
2112 #endif
2113 #ifdef CONFIG_ROCKCHIP_RK3399
2114 { .compatible = "rockchip,rk3399-usb2phy", .data = (ulong)&rk3399_phy_cfgs },
2115 #endif
2116 #ifdef CONFIG_ROCKCHIP_RK3506
2117 { .compatible = "rockchip,rk3506-usb2phy", .data = (ulong)&rk3506_phy_cfgs },
2118 #endif
2119 #ifdef CONFIG_ROCKCHIP_RK3528
2120 { .compatible = "rockchip,rk3528-usb2phy", .data = (ulong)&rk3528_phy_cfgs },
2121 #endif
2122 #ifdef CONFIG_ROCKCHIP_RK3562
2123 { .compatible = "rockchip,rk3562-usb2phy", .data = (ulong)&rk3562_phy_cfgs },
2124 #endif
2125 #ifdef CONFIG_ROCKCHIP_RK3568
2126 { .compatible = "rockchip,rk3568-usb2phy", .data = (ulong)&rk3568_phy_cfgs },
2127 #endif
2128 #ifdef CONFIG_ROCKCHIP_RK3576
2129 { .compatible = "rockchip,rk3576-usb2phy", .data = (ulong)&rk3576_phy_cfgs },
2130 #endif
2131 #ifdef CONFIG_ROCKCHIP_RK3588
2132 { .compatible = "rockchip,rk3588-usb2phy", .data = (ulong)&rk3588_phy_cfgs },
2133 #endif
2134 #ifdef CONFIG_ROCKCHIP_RV1103B
2135 { .compatible = "rockchip,rv1103b-usb2phy", .data = (ulong)&rv1103b_phy_cfgs },
2136 #endif
2137 #ifdef CONFIG_ROCKCHIP_RV1106
2138 { .compatible = "rockchip,rv1106-usb2phy", .data = (ulong)&rv1106_phy_cfgs },
2139 #endif
2140 #ifdef CONFIG_ROCKCHIP_RV1108
2141 { .compatible = "rockchip,rv1108-usb2phy", .data = (ulong)&rv1108_phy_cfgs },
2142 #endif
2143 #ifdef CONFIG_ROCKCHIP_RV1126B
2144 { .compatible = "rockchip,rv1126b-usb2phy", .data = (ulong)&rv1126b_phy_cfgs },
2145 #endif
2146 { }
2147 };
2148
2149 U_BOOT_DRIVER(rockchip_usb2phy_port) = {
2150 .name = "rockchip_usb2phy_port",
2151 .id = UCLASS_PHY,
2152 .ops = &rockchip_usb2phy_ops,
2153 };
2154
2155 U_BOOT_DRIVER(rockchip_usb2phy) = {
2156 .name = "rockchip_usb2phy",
2157 .id = UCLASS_PHY,
2158 .of_match = rockchip_usb2phy_ids,
2159 .probe = rockchip_usb2phy_probe,
2160 .bind = rockchip_usb2phy_bind,
2161 .priv_auto_alloc_size = sizeof(struct rockchip_usb2phy),
2162 };
2163