1 /* 2 * Copyright (C) 2015 Google, Inc 3 * Written by Simon Glass <sjg@chromium.org> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef _PMIC_RK8XX_H_ 9 #define _PMIC_RK8XX_H_ 10 11 enum { 12 REG_SECONDS = 0x00, 13 REG_MINUTES, 14 REG_HOURS, 15 REG_DAYS, 16 REG_MONTHS, 17 REG_YEARS, 18 REG_WEEKS, 19 REG_ALARM_SECONDS, 20 REG_ALARM_MINUTES, 21 REG_ALARM_HOURS, 22 REG_ALARM_DAYS, 23 REG_ALARM_MONTHS, 24 REG_ALARM_YEARS, 25 26 REG_RTC_CTRL = 0x10, 27 REG_RTC_STATUS, 28 REG_RTC_INT, 29 REG_RTC_COMP_LSB, 30 REG_RTC_COMP_MSB, 31 32 ID_MSB = 0x17, 33 ID_LSB, 34 35 REG_CLK32OUT = 0x20, 36 REG_VB_MON, 37 REG_THERMAL, 38 REG_DCDC_EN, 39 REG_LDO_EN, 40 REG_SLEEP_SET_OFF1, 41 REG_SLEEP_SET_OFF2, 42 REG_DCDC_UV_STS, 43 REG_DCDC_UV_ACT, 44 REG_LDO_UV_STS, 45 REG_LDO_UV_ACT, 46 REG_DCDC_PG, 47 REG_LDO_PG, 48 REG_VOUT_MON_TDB, 49 REG_BUCK1_CONFIG, 50 REG_BUCK1_ON_VSEL, 51 REG_BUCK1_SLP_VSEL, 52 REG_BUCK1_DVS_VSEL, 53 REG_BUCK2_CONFIG, 54 REG_BUCK2_ON_VSEL, 55 REG_BUCK2_SLP_VSEL, 56 REG_BUCK2_DVS_VSEL, 57 REG_BUCK3_CONFIG, 58 REG_BUCK4_CONFIG, 59 REG_BUCK4_ON_VSEL, 60 REG_BUCK4_SLP_VSEL, 61 REG_BOOST_CONFIG_REG, 62 REG_LDO1_ON_VSEL, 63 REG_LDO1_SLP_VSEL, 64 REG_LDO2_ON_VSEL, 65 REG_LDO2_SLP_VSEL, 66 REG_LDO3_ON_VSEL, 67 REG_LDO3_SLP_VSEL, 68 REG_LDO4_ON_VSEL, 69 REG_LDO4_SLP_VSEL, 70 REG_LDO5_ON_VSEL, 71 REG_LDO5_SLP_VSEL, 72 REG_LDO6_ON_VSEL, 73 REG_LDO6_SLP_VSEL, 74 REG_LDO7_ON_VSEL, 75 REG_LDO7_SLP_VSEL, 76 REG_LDO8_ON_VSEL, 77 REG_LDO8_SLP_VSEL, 78 REG_DEVCTRL, 79 REG_INT_STS1, 80 REG_INT_STS_MSK1, 81 REG_INT_STS2, 82 REG_INT_STS_MSK2, 83 REG_IO_POL, 84 REG_OTP_VDD_EN, 85 REG_H5V_EN, 86 REG_SLEEP_SET_OFF, 87 REG_BOOST_LDO9_ON_VSEL, 88 REG_BOOST_LDO9_SLP_VSEL, 89 REG_BOOST_CTRL, 90 91 /* Not sure what this does */ 92 REG_DCDC_ILMAX = 0x90, 93 REG_CHRG_COMP = 0x9a, 94 REG_SUP_STS = 0xa0, 95 REG_USB_CTRL, 96 REG1_CHRG_CTRL, 97 REG2_CHRG_CTRL, 98 REG3_CHRG_CTRL, 99 REG_BAT_CTRL, 100 REG_BAT_HTS_TS1, 101 REG_BAT_LTS_TS1, 102 REG_BAT_HTS_TS2, 103 REG_BAT_LTS_TS2, 104 REG_TS_CTRL, 105 REG_ADC_CTRL, 106 REG_ON_SOURCE, 107 REG_OFF_SOURCE, 108 REG_GGCON, 109 REG_GGSTS, 110 REG_FRAME_SMP_INTERV, 111 REG_AUTO_SLP_CUR_THR, 112 REG3_GASCNT_CAL, 113 REG2_GASCNT_CAL, 114 REG1_GASCNT_CAL, 115 REG0_GASCNT_CAL, 116 REG3_GASCNT, 117 REG2_GASCNT, 118 REG1_GASCNT, 119 REG0_GASCNT, 120 REGH_BAT_CUR_AVG, 121 REGL_BAT_CUR_AVG, 122 REGH_TS1_ADC, 123 REGL_TS1_ADC, 124 REGH_TS2_ADC, 125 REGL_TS2_ADC, 126 REGH_BAT_OCV, 127 REGL_BAT_OCV, 128 REGH_BAT_VOL, 129 REGL_BAT_VOL, 130 REGH_RELAX_ENTRY_THRES, 131 REGL_RELAX_ENTRY_THRES, 132 REGH_RELAX_EXIT_THRES, 133 REGL_RELAX_EXIT_THRES, 134 REGH_RELAX_VOL1, 135 REGL_RELAX_VOL1, 136 REGH_RELAX_VOL2, 137 REGL_RELAX_VOL2, 138 REGH_BAT_CUR_R_CALC, 139 REGL_BAT_CUR_R_CALC, 140 REGH_BAT_VOL_R_CALC, 141 REGL_BAT_VOL_R_CALC, 142 REGH_CAL_OFFSET, 143 REGL_CAL_OFFSET, 144 REG_NON_ACT_TIMER_CNT, 145 REGH_VCALIB0, 146 REGL_VCALIB0, 147 REGH_VCALIB1, 148 REGL_VCALIB1, 149 REGH_IOFFSET, 150 REGL_IOFFSET, 151 REG_SOC, 152 REG3_REMAIN_CAP, 153 REG2_REMAIN_CAP, 154 REG1_REMAIN_CAP, 155 REG0_REMAIN_CAP, 156 REG_UPDAT_LEVE, 157 REG3_NEW_FCC, 158 REG2_NEW_FCC, 159 REG1_NEW_FCC, 160 REG0_NEW_FCC, 161 REG_NON_ACT_TIMER_CNT_SAVE, 162 REG_OCV_VOL_VALID, 163 REG_REBOOT_CNT, 164 REG_POFFSET, 165 REG_MISC_MARK, 166 REG_HALT_CNT, 167 REGH_CALC_REST, 168 REGL_CALC_REST, 169 SAVE_DATA19, 170 RK808_NUM_OF_REGS, 171 }; 172 173 enum { 174 RK817_REG_SYS_CFG3 = 0xf4, 175 }; 176 177 enum { 178 RK816_REG_DCDC_EN1 = 0x23, 179 RK816_REG_DCDC_EN2, 180 RK816_REG_DCDC_SLP_EN, 181 RK816_REG_LDO_SLP_EN, 182 RK816_REG_LDO_EN1 = 0x27, 183 RK816_REG_LDO_EN2, 184 }; 185 186 enum { 187 RK805_ID = 0x8050, 188 RK806_ID = 0x8060, 189 RK808_ID = 0x0000, 190 RK809_ID = 0x8090, 191 RK816_ID = 0x8160, 192 RK817_ID = 0x8170, 193 RK818_ID = 0x8180, 194 }; 195 196 enum { 197 RK817_POWER_EN0 = 0xb1, 198 RK817_POWER_EN1, 199 RK817_POWER_EN2, 200 RK817_POWER_EN3, 201 }; 202 203 #define RK8xx_RST_MODE0 0x00 204 #define RK8xx_RST_MODE1 0x01 205 #define RK8xx_RST_MODE2 0x02 206 #define RK8xx_RESET_FUN_CLR 0x3f 207 208 #define RK817_POWER_EN_SAVE0 0x99 209 #define RK817_POWER_EN_SAVE1 0xa4 210 211 #define RK817_ID_MSB 0xed 212 #define RK817_ID_LSB 0xee 213 #define RK8XX_ID_MSK 0xfff0 214 215 #define RK817_PMIC_CHRG_TERM 0xe6 216 #define RK817_PMIC_SYS_CFG1 0xf1 217 #define RK817_PMIC_SYS_CFG3 0xf4 218 #define RK817_GPIO_INT_CFG 0xfe 219 220 #define RK8XX_ON_SOURCE 0xae 221 #define RK8XX_OFF_SOURCE 0xaf 222 #define RK817_BUCK4_CMIN 0xc6 223 #define RK817_ON_SOURCE 0xf5 224 #define RK817_OFF_SOURCE 0xf6 225 #define RK817_NUM_OF_REGS 0xff 226 227 #define RK8XX_DEVCTRL_REG 0x4b 228 #define RK817_PWRON_KEY 0xf7 229 #define RK8XX_LP_ACTION_MSK BIT(6) 230 #define RK8XX_LP_OFF (0 << 6) 231 #define RK8XX_LP_RESTART (1 << 6) 232 #define RK8XX_LP_OFF_MSK BIT(4) | BIT(5) 233 #define RK8XX_LP_TIME_6S (0 << 4) 234 #define RK8XX_LP_TIME_8S (1 << 4) 235 #define RK8XX_LP_TIME_10S (2 << 4) 236 #define RK8XX_LP_TIME_12S (3 << 4) 237 238 /* IRQ definitions */ 239 #define RK8XX_IRQ_PWRON_FALL 0 240 #define RK8XX_IRQ_PWRON_RISE 1 241 #define RK8XX_IRQ_PLUG_OUT 2 242 #define RK8XX_IRQ_PLUG_IN 3 243 #define RK8XX_IRQ_CHG_OK 4 244 #define RK8XX_IRQ_RTC_ALARM 5 245 246 #define RK808_INT_STS_REG1 0x4c 247 #define RK808_INT_MSK_REG1 0x4d 248 #define RK808_IRQ_VOUT_LOW_MSK BIT(0) 249 #define RK808_IRQ_PLUG_OUT_MSK BIT(1) 250 #define RK808_IRQ_RTC_ALARM_MSK BIT(5) 251 #define RK808_IRQ_RTC_PERIOD_MSK BIT(6) 252 253 #define RK805_INT_STS_REG 0x4c 254 #define RK805_INT_MSK_REG 0x4d 255 #define RK805_IRQ_PWRON_FALL_MSK BIT(7) 256 #define RK805_IRQ_PWRON_RISE_MSK BIT(0) 257 #define RK805_IRQ_RTC_ALARM_MSK BIT(5) 258 #define RK805_IRQ_RTC_PERIOD_MSK BIT(6) 259 260 enum rk806_reg_id { 261 RK806_ID_DCDC1 = 0, 262 RK806_ID_DCDC2, 263 RK806_ID_DCDC3, 264 RK806_ID_DCDC4, 265 RK806_ID_DCDC5, 266 RK806_ID_DCDC6, 267 RK806_ID_DCDC7, 268 RK806_ID_DCDC8, 269 RK806_ID_DCDC9, 270 RK806_ID_DCDC10, 271 272 RK806_ID_NLDO1, 273 RK806_ID_NLDO2, 274 RK806_ID_NLDO3, 275 RK806_ID_NLDO4, 276 RK806_ID_NLDO5, 277 278 RK806_ID_PLDO1, 279 RK806_ID_PLDO2, 280 RK806_ID_PLDO3, 281 RK806_ID_PLDO4, 282 RK806_ID_PLDO5, 283 RK806_ID_PLDO6, 284 RK806_ID_END, 285 }; 286 287 #define RK806_CHIP_NAME 0x5A 288 #define RK806_CHIP_VER 0x5B 289 #define RK806_HW_VER 0x21 290 #define HW_DUAL_PMIC 0x28 291 #define HW_SINGLE_PMIC 0xe8 292 293 #define RK806_CMD_READ 0 294 #define RK806_CMD_WRITE BIT(7) 295 #define RK806_CMD_CRC_EN BIT(6) 296 #define RK806_CMD_CRC_DIS 0 297 #define RK806_CMD_LEN_MSK 0x0f 298 #define RK806_REG_H 0x00 299 300 #define RK806_SYS_CFG1 0x5f 301 #define RK806_PWRCTRL_CONFIG0 0x62 302 #define RK806_PWRCTRL_CONFIG1 0x63 303 #define RK806_VSEL_CTR_SEL0 0x64 304 #define RK806_DVS_CTR_SEL4 0x6e 305 #define RK806_PWRCTRL_GPIO 0x71 306 #define RK806_SYS_CFG3 0x72 307 #define RK806_PWRON_KEY 0x76 308 #define RK806_INT_STS0 0x77 309 #define RK806_INT_MSK0 0x78 310 #define RK806_INT_STS1 0x79 311 #define RK806_INT_MSK1 0x7A 312 #define RK806_GPIO_INT_CONFIG 0x7B 313 #define RK806_ON_SOURCE 0x74 314 #define RK806_OFF_SOURCE 0x75 315 #define RK806_BUCK_RSERVE_REG3 0xfd 316 317 #define RK806_SHUTDOWN_SEQ_REG0 0xB2 318 #define RK806_SHUTDOWN_SEQ_REG1 0xB3 319 #define RK806_SHUTDOWN_SEQ_REG2 0xB4 320 #define RK806_SHUTDOWN_SEQ_REG3 0xB5 321 #define RK806_SHUTDOWN_SEQ_REG4 0xB6 322 #define RK806_SHUTDOWN_SEQ_REG5 0xB7 323 #define RK806_SHUTDOWN_SEQ_REG6 0xB8 324 #define RK806_SHUTDOWN_SEQ_REG7 0xB9 325 #define RK806_SHUTDOWN_SEQ_REG8 0xBA 326 #define RK806_SHUTDOWN_SEQ_REG9 0xBB 327 #define RK806_SHUTDOWN_SEQ_REG10 0xBC 328 #define RK806_SHUTDOWN_SEQ_REG11 0xBD 329 #define RK806_SHUTDOWN_SEQ_REG12 0xBE 330 #define RK806_SHUTDOWN_SEQ_REG13 0xBF 331 #define RK806_SHUTDOWN_SEQ_REG14 0xC0 332 #define RK806_SHUTDOWN_SEQ_REG15 0xC1 333 #define RK806_SHUTDOWN_SEQ_REG16 0xC2 334 335 #define RK806_PWRCTRL1 0x01 336 #define RK806_PWRCTRL2 0x02 337 #define RK806_PWRCTRL3 0x03 338 339 #define RK806_PWRCTR_GPIO_FUN 0x05 340 #define RK806_PWRCTR_MSK_FUN 0x07 341 #define RK806_PWRCTR_OUTPUT_MSK 0x11 342 #define RK806_PWRCTR_OUTPUT0 0x01 343 #define RK806_PWRCTR_OUTPUT1 0x11 344 345 #define RK806_INT_POL_HIGH BIT(1) 346 #define RK806_IRQ_PWRON_FALL_MSK BIT(0) 347 #define RK806_IRQ_PWRON_RISE_MSK BIT(1) 348 #define RK806_DEV_OFF BIT(0) 349 #define RK806_RST_MODE1 0x01 350 #define RK806_RST_MODE2 0x02 351 #define RK806_PWRCTRL_FUN_MSK 0x88 352 #define RK806_VSEL_CTRL_MSK 0xcc 353 #define RK806_VSEL_PWRCTRL1 0x11 354 #define RK806_ENABLE_PWRCTRL 0x04 355 #define RK806_VERSION_AB 0x01 356 357 #define RK806_ABNORDET_EN 0x80 358 #define RK806_VERSION_MSK 0x0f 359 #define RK806_RESET_FUN_CLR 0x3f 360 #define RK806_BUCK5_EX_RES_EN 0x10 361 362 /* RK806 buck*/ 363 #define RK806_BUCK_ON_VSEL(n) (0x1a + n - 1) 364 #define RK806_BUCK_SLP_VSEL(n) (0x24 + n - 1) 365 #define RK806_BUCK_CONFIG(n) (0x10 + n - 1) 366 #define RK806_BUCK_VSEL_MASK 0xff 367 368 /* RK806 LDO */ 369 #define RK806_NLDO_ON_VSEL(n) (0x43 + n - 1) 370 #define RK806_NLDO_SLP_VSEL(n) (0x48 + n - 1) 371 #define RK806_NLDO_VSEL_MASK 0xff 372 #define RK806_PLDO_ON_VSEL(n) (0x4e + n - 1) 373 #define RK806_PLDO_SLP_VSEL(n) (0x54 + n - 1) 374 #define RK806_PLDO_VSEL_MASK 0xff 375 376 /* RK806 ENABLE */ 377 #define RK806_POWER_EN(n) (0x00 + n) 378 #define RK806_NLDO_EN(n) (0x03 + n) 379 #define RK806_PLDO_EN(n) (0x04 + n) 380 381 #define RK806_BUCK_SUSPEND_EN 0x06 382 #define RK806_NLDO_SUSPEND_EN 0x07 383 #define RK806_PLDO_SUSPEND_EN 0x08 384 385 #define RK806_RAMP_RATE_MASK1 0xc0 386 #define RK806_RAMP_RATE_REG1(n) (0x10 + n) 387 #define RK806_RAMP_RATE_REG1_8 0xeb 388 #define RK806_RAMP_RATE_REG9_10 0xea 389 390 #define RK806_RAMP_RATE_4LSB_PER_1CLK 0x00/* LDO 100mV/uS buck 50mV/us */ 391 #define RK806_RAMP_RATE_2LSB_PER_1CLK 0x01/* LDO 50mV/uS buck 25mV/us */ 392 #define RK806_RAMP_RATE_1LSB_PER_1CLK 0x02/* LDO 25mV/uS buck 12.5mV/us */ 393 #define RK806_RAMP_RATE_1LSB_PER_2CLK 0x03/* LDO 12.5mV/uS buck 6.25mV/us */ 394 395 #define RK806_RAMP_RATE_1LSB_PER_4CLK 0x04/* LDO 6.28/2mV/uS buck 3.125mV/us */ 396 #define RK806_RAMP_RATE_1LSB_PER_8CLK 0x05/* LDO 3.12mV/uS buck 1.56mV/us */ 397 #define RK806_RAMP_RATE_1LSB_PER_13CLK 0x06/* LDO 1.9mV/uS buck 961mV/us */ 398 #define RK806_RAMP_RATE_1LSB_PER_32CLK 0x07/* LDO 0.78mV/uS buck 0.39mV/us */ 399 400 #define RK806_PLDO0_2_MSK(pldo) (BIT(pldo + 5)) 401 #define RK806_PLDO0_2_SET(pldo) (BIT(pldo + 1) | RK806_PLDO0_2_MSK(pldo)) 402 #define RK806_PLDO0_2_CLR(pldo) RK806_PLDO0_2_MSK(pldo) 403 404 #define RK816_INT_STS_REG1 0x49 405 #define RK816_INT_MSK_REG1 0x4a 406 #define RK816_INT_STS_REG3 0x4e 407 #define RK816_INT_STS_MSK_REG3 0x4f 408 #define RK816_IRQ_PWRON_RISE_MSK BIT(6) 409 #define RK816_IRQ_PWRON_FALL_MSK BIT(5) 410 #define RK816_IRQ_PLUG_OUT_MSK BIT(1) 411 #define RK816_IRQ_CHR_OK_MSK BIT(2) 412 #define RK816_IRQ_RTC_ALARM_MSK BIT(5) 413 #define RK816_IRQ_RTC_PERIOD_MSK BIT(6) 414 415 #define RK818_INT_STS_REG1 0x4c 416 #define RK818_INT_MSK_REG1 0x4d 417 #define RK818_IRQ_PLUG_OUT_MSK BIT(1) 418 #define RK818_IRQ_CHR_OK_MSK BIT(2) 419 #define RK818_IRQ_RTC_ALARM_MSK BIT(5) 420 #define RK818_IRQ_RTC_PERIOD_MSK BIT(6) 421 422 #define RK817_INT_STS_REG0 0xf8 423 #define RK817_INT_MSK_REG0 0xf9 424 #define RK817_IRQ_PWRON_FALL_MSK BIT(0) 425 #define RK817_IRQ_PWRON_RISE_MSK BIT(1) 426 #define RK817_IRQ_PLUG_OUT_MSK BIT(1) 427 #define RK817_IRQ_PLUG_IN_MSK BIT(0) 428 #define RK817_IRQ_RTC_ALARM_MSK BIT(5) 429 #define RK817_IRQ_RTC_PERIOD_MSK BIT(6) 430 431 struct reg_data { 432 u8 reg; 433 u8 val; 434 u8 mask; 435 }; 436 437 struct rk8xx_reg_table { 438 char *name; 439 u8 reg_ctl; 440 u8 reg_vol; 441 }; 442 443 struct rk8xx_priv { 444 struct virq_chip *irq_chip; 445 struct spi_slave *slave; 446 int variant; 447 int irq; 448 int lp_off_time; 449 int lp_action; 450 uint8_t sleep_pin; 451 uint8_t rst_fun; 452 int not_save_power_en; 453 int sys_can_sd; 454 int buck5_feedback_dis; 455 int pwr_ctr[3]; 456 u32 *shutdown_sequence; 457 u32 *vb_shutdown_sequence; 458 int support_shutdown_sequence; 459 int support_vb_sequence; 460 }; 461 462 int rk8xx_spl_configure_buck(struct udevice *pmic, int buck, int uvolt); 463 int rk818_spl_configure_usb_input_current(struct udevice *pmic, int current_ma); 464 int rk818_spl_configure_usb_chrg_shutdown(struct udevice *pmic, int uvolt); 465 466 #endif 467