1 /* Definitions of target machine for GNU compiler, for ARM. 2 Copyright (C) 1991-2020 Free Software Foundation, Inc. 3 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl) 4 and Martin Simmons (@harleqn.co.uk). 5 More major hacks by Richard Earnshaw (rearnsha@arm.com) 6 Minor hacks by Nick Clifton (nickc@cygnus.com) 7 8 This file is part of GCC. 9 10 GCC is free software; you can redistribute it and/or modify it 11 under the terms of the GNU General Public License as published 12 by the Free Software Foundation; either version 3, or (at your 13 option) any later version. 14 15 GCC is distributed in the hope that it will be useful, but WITHOUT 16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 18 License for more details. 19 20 Under Section 7 of GPL version 3, you are granted additional 21 permissions described in the GCC Runtime Library Exception, version 22 3.1, as published by the Free Software Foundation. 23 24 You should have received a copy of the GNU General Public License and 25 a copy of the GCC Runtime Library Exception along with this program; 26 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see 27 <http://www.gnu.org/licenses/>. */ 28 29 #ifndef GCC_ARM_H 30 #define GCC_ARM_H 31 32 /* We can't use machine_mode inside a generator file because it 33 hasn't been created yet; we shouldn't be using any code that 34 needs the real definition though, so this ought to be safe. */ 35 #ifdef GENERATOR_FILE 36 #define MACHMODE int 37 #else 38 #include "insn-modes.h" 39 #define MACHMODE machine_mode 40 #endif 41 42 #include "config/vxworks-dummy.h" 43 44 /* The architecture define. */ 45 extern char arm_arch_name[]; 46 47 /* Target CPU builtins. */ 48 #define TARGET_CPU_CPP_BUILTINS() arm_cpu_cpp_builtins (pfile) 49 50 /* Target CPU versions for D. */ 51 #define TARGET_D_CPU_VERSIONS arm_d_target_versions 52 53 #include "config/arm/arm-opts.h" 54 55 /* The processor for which instructions should be scheduled. */ 56 extern enum processor_type arm_tune; 57 58 typedef enum arm_cond_code 59 { 60 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC, 61 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV 62 } 63 arm_cc; 64 65 extern arm_cc arm_current_cc; 66 67 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1)) 68 69 /* The maximum number of instructions that is beneficial to 70 conditionally execute. */ 71 #undef MAX_CONDITIONAL_EXECUTE 72 #define MAX_CONDITIONAL_EXECUTE arm_max_conditional_execute () 73 74 extern int arm_target_label; 75 extern int arm_ccfsm_state; 76 extern GTY(()) rtx arm_target_insn; 77 /* Callback to output language specific object attributes. */ 78 extern void (*arm_lang_output_object_attributes_hook)(void); 79 80 /* This type is the user-visible __fp16. We need it in a few places in 81 the backend. Defined in arm-builtins.c. */ 82 extern tree arm_fp16_type_node; 83 84 /* This type is the user-visible __bf16. We need it in a few places in 85 the backend. Defined in arm-builtins.c. */ 86 extern tree arm_bf16_type_node; 87 extern tree arm_bf16_ptr_type_node; 88 89 90 #undef CPP_SPEC 91 #define CPP_SPEC "%(subtarget_cpp_spec) \ 92 %{mfloat-abi=soft:%{mfloat-abi=hard: \ 93 %e-mfloat-abi=soft and -mfloat-abi=hard may not be used together}} \ 94 %{mbig-endian:%{mlittle-endian: \ 95 %e-mbig-endian and -mlittle-endian may not be used together}}" 96 97 #ifndef CC1_SPEC 98 #define CC1_SPEC "" 99 #endif 100 101 /* This macro defines names of additional specifications to put in the specs 102 that can be used in various specifications like CC1_SPEC. Its definition 103 is an initializer with a subgrouping for each command option. 104 105 Each subgrouping contains a string constant, that defines the 106 specification name, and a string constant that used by the GCC driver 107 program. 108 109 Do not define this macro if it does not need to do anything. */ 110 #define EXTRA_SPECS \ 111 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \ 112 { "asm_cpu_spec", ASM_CPU_SPEC }, \ 113 SUBTARGET_EXTRA_SPECS 114 115 #ifndef SUBTARGET_EXTRA_SPECS 116 #define SUBTARGET_EXTRA_SPECS 117 #endif 118 119 #ifndef SUBTARGET_CPP_SPEC 120 #define SUBTARGET_CPP_SPEC "" 121 #endif 122 123 /* Tree Target Specification. */ 124 #define TARGET_ARM_P(flags) (!TARGET_THUMB_P (flags)) 125 #define TARGET_THUMB1_P(flags) (TARGET_THUMB_P (flags) && !arm_arch_thumb2) 126 #define TARGET_THUMB2_P(flags) (TARGET_THUMB_P (flags) && arm_arch_thumb2) 127 #define TARGET_32BIT_P(flags) (TARGET_ARM_P (flags) || TARGET_THUMB2_P (flags)) 128 129 /* Run-time Target Specification. */ 130 /* Use hardware floating point instructions. -mgeneral-regs-only prevents 131 the use of floating point instructions and registers but does not prevent 132 emission of floating point pcs attributes. */ 133 #define TARGET_HARD_FLOAT_SUB (arm_float_abi != ARM_FLOAT_ABI_SOFT \ 134 && bitmap_bit_p (arm_active_target.isa, \ 135 isa_bit_vfpv2) \ 136 && TARGET_32BIT) 137 138 #define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_SUB \ 139 && !TARGET_GENERAL_REGS_ONLY) 140 141 #define TARGET_SOFT_FLOAT (!TARGET_HARD_FLOAT_SUB) 142 /* User has permitted use of FP instructions, if they exist for this 143 target. */ 144 #define TARGET_MAYBE_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT) 145 /* Use hardware floating point calling convention. */ 146 #define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD) 147 #define TARGET_IWMMXT (arm_arch_iwmmxt) 148 #define TARGET_IWMMXT2 (arm_arch_iwmmxt2) 149 #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_32BIT \ 150 && !TARGET_GENERAL_REGS_ONLY) 151 #define TARGET_REALLY_IWMMXT2 (TARGET_IWMMXT2 && TARGET_32BIT \ 152 && !TARGET_GENERAL_REGS_ONLY) 153 #define TARGET_IWMMXT_ABI (TARGET_32BIT && arm_abi == ARM_ABI_IWMMXT) 154 #define TARGET_ARM (! TARGET_THUMB) 155 #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */ 156 #define TARGET_BACKTRACE (crtl->is_leaf \ 157 ? TARGET_TPCS_LEAF_FRAME \ 158 : TARGET_TPCS_FRAME) 159 #define TARGET_AAPCS_BASED \ 160 (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS) 161 162 #define TARGET_HARD_TP (target_thread_pointer == TP_CP15) 163 #define TARGET_SOFT_TP (target_thread_pointer == TP_SOFT) 164 #define TARGET_GNU2_TLS (target_tls_dialect == TLS_GNU2) 165 166 /* Only 16-bit thumb code. */ 167 #define TARGET_THUMB1 (TARGET_THUMB && !arm_arch_thumb2) 168 /* Arm or Thumb-2 32-bit code. */ 169 #define TARGET_32BIT (TARGET_ARM || arm_arch_thumb2) 170 /* 32-bit Thumb-2 code. */ 171 #define TARGET_THUMB2 (TARGET_THUMB && arm_arch_thumb2) 172 /* Thumb-1 only. */ 173 #define TARGET_THUMB1_ONLY (TARGET_THUMB1 && !arm_arch_notm) 174 175 #define TARGET_LDRD (arm_arch5te && ARM_DOUBLEWORD_ALIGN \ 176 && !TARGET_THUMB1) 177 178 #define TARGET_CRC32 (arm_arch_crc) 179 180 /* The following two macros concern the ability to execute coprocessor 181 instructions for VFPv3 or NEON. TARGET_VFP3/TARGET_VFPD32 are currently 182 only ever tested when we know we are generating for VFP hardware; we need 183 to be more careful with TARGET_NEON as noted below. */ 184 185 /* FPU is has the full VFPv3/NEON register file of 32 D registers. */ 186 #define TARGET_VFPD32 (bitmap_bit_p (arm_active_target.isa, isa_bit_fp_d32)) 187 188 /* FPU supports VFPv3 instructions. */ 189 #define TARGET_VFP3 (bitmap_bit_p (arm_active_target.isa, isa_bit_vfpv3)) 190 191 /* FPU supports FPv5 instructions. */ 192 #define TARGET_VFP5 (bitmap_bit_p (arm_active_target.isa, isa_bit_fpv5)) 193 194 /* FPU only supports VFP single-precision instructions. */ 195 #define TARGET_VFP_SINGLE (!TARGET_VFP_DOUBLE) 196 197 /* FPU supports VFP double-precision instructions. */ 198 #define TARGET_VFP_DOUBLE (bitmap_bit_p (arm_active_target.isa, isa_bit_fp_dbl)) 199 200 /* FPU supports half-precision floating-point with NEON element load/store. */ 201 #define TARGET_NEON_FP16 \ 202 (bitmap_bit_p (arm_active_target.isa, isa_bit_neon) \ 203 && bitmap_bit_p (arm_active_target.isa, isa_bit_fp16conv)) 204 205 /* FPU supports VFP half-precision floating-point conversions. */ 206 #define TARGET_FP16 (bitmap_bit_p (arm_active_target.isa, isa_bit_fp16conv)) 207 208 /* FPU supports converting between HFmode and DFmode in a single hardware 209 step. */ 210 #define TARGET_FP16_TO_DOUBLE \ 211 (TARGET_HARD_FLOAT && TARGET_FP16 && TARGET_VFP5 && TARGET_VFP_DOUBLE) 212 213 /* FPU supports fused-multiply-add operations. */ 214 #define TARGET_FMA (bitmap_bit_p (arm_active_target.isa, isa_bit_vfpv4)) 215 216 /* FPU supports Crypto extensions. */ 217 #define TARGET_CRYPTO (bitmap_bit_p (arm_active_target.isa, isa_bit_crypto)) 218 219 /* FPU supports Neon instructions. The setting of this macro gets 220 revealed via __ARM_NEON__ so we add extra guards upon TARGET_32BIT 221 and TARGET_HARD_FLOAT to ensure that NEON instructions are 222 available. */ 223 #define TARGET_NEON \ 224 (TARGET_32BIT && TARGET_HARD_FLOAT \ 225 && bitmap_bit_p (arm_active_target.isa, isa_bit_neon)) 226 227 /* FPU supports ARMv8.1 Adv.SIMD extensions. */ 228 #define TARGET_NEON_RDMA (TARGET_NEON && arm_arch8_1) 229 230 /* Supports the Dot Product AdvSIMD extensions. */ 231 #define TARGET_DOTPROD (TARGET_NEON && TARGET_VFP5 \ 232 && bitmap_bit_p (arm_active_target.isa, \ 233 isa_bit_dotprod) \ 234 && arm_arch8_2) 235 236 /* Supports the Armv8.3-a Complex number AdvSIMD extensions. */ 237 #define TARGET_COMPLEX (TARGET_NEON && arm_arch8_3) 238 239 /* FPU supports the floating point FP16 instructions for ARMv8.2-A 240 and later. */ 241 #define TARGET_VFP_FP16INST \ 242 (TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP5 && arm_fp16_inst) 243 244 /* Target supports the floating point FP16 instructions from ARMv8.2-A 245 and later. */ 246 #define TARGET_FP16FML (TARGET_NEON \ 247 && bitmap_bit_p (arm_active_target.isa, \ 248 isa_bit_fp16fml) \ 249 && arm_arch8_2) 250 251 /* FPU supports the AdvSIMD FP16 instructions for ARMv8.2 and later. */ 252 #define TARGET_NEON_FP16INST (TARGET_VFP_FP16INST && TARGET_NEON_RDMA) 253 254 /* FPU supports 8-bit Integer Matrix Multiply (I8MM) AdvSIMD extensions. */ 255 #define TARGET_I8MM (TARGET_NEON && arm_arch8_2 && arm_arch_i8mm) 256 257 /* FPU supports Brain half-precision floating-point (BFloat16) extension. */ 258 #define TARGET_BF16_FP (TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP5 \ 259 && arm_arch8_2 && arm_arch_bf16) 260 #define TARGET_BF16_SIMD (TARGET_NEON && TARGET_VFP5 \ 261 && arm_arch8_2 && arm_arch_bf16) 262 263 /* Q-bit is present. */ 264 #define TARGET_ARM_QBIT \ 265 (TARGET_32BIT && arm_arch5te && (arm_arch_notm || arm_arch7)) 266 /* Saturation operation, e.g. SSAT. */ 267 #define TARGET_ARM_SAT \ 268 (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7)) 269 /* "DSP" multiply instructions, eg. SMULxy. */ 270 #define TARGET_DSP_MULTIPLY \ 271 (TARGET_32BIT && arm_arch5te && (arm_arch_notm || arm_arch7em)) 272 /* Integer SIMD instructions, and extend-accumulate instructions. */ 273 #define TARGET_INT_SIMD \ 274 (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7em)) 275 276 /* Should MOVW/MOVT be used in preference to a constant pool. */ 277 #define TARGET_USE_MOVT \ 278 (TARGET_HAVE_MOVT \ 279 && (arm_disable_literal_pool \ 280 || (!optimize_size && !current_tune->prefer_constant_pool))) 281 282 /* Nonzero if this chip provides the DMB instruction. */ 283 #define TARGET_HAVE_DMB (arm_arch6m || arm_arch7) 284 285 /* Nonzero if this chip implements a memory barrier via CP15. */ 286 #define TARGET_HAVE_DMB_MCR (arm_arch6 && ! TARGET_HAVE_DMB \ 287 && ! TARGET_THUMB1) 288 289 /* Nonzero if this chip implements a memory barrier instruction. */ 290 #define TARGET_HAVE_MEMORY_BARRIER (TARGET_HAVE_DMB || TARGET_HAVE_DMB_MCR) 291 292 /* Nonzero if this chip supports ldrex and strex */ 293 #define TARGET_HAVE_LDREX ((arm_arch6 && TARGET_ARM) \ 294 || arm_arch7 \ 295 || (arm_arch8 && !arm_arch_notm)) 296 297 /* Nonzero if this chip supports LPAE. */ 298 #define TARGET_HAVE_LPAE (arm_arch_lpae) 299 300 /* Nonzero if this chip supports ldrex{bh} and strex{bh}. */ 301 #define TARGET_HAVE_LDREXBH ((arm_arch6k && TARGET_ARM) \ 302 || arm_arch7 \ 303 || (arm_arch8 && !arm_arch_notm)) 304 305 /* Nonzero if this chip supports ldrexd and strexd. */ 306 #define TARGET_HAVE_LDREXD (((arm_arch6k && TARGET_ARM) \ 307 || arm_arch7) && arm_arch_notm) 308 309 /* Nonzero if this chip supports load-acquire and store-release. */ 310 #define TARGET_HAVE_LDACQ (TARGET_ARM_ARCH >= 8) 311 312 /* Nonzero if this chip supports LDAEXD and STLEXD. */ 313 #define TARGET_HAVE_LDACQEXD (TARGET_ARM_ARCH >= 8 \ 314 && TARGET_32BIT \ 315 && arm_arch_notm) 316 317 /* Nonzero if this chip provides the MOVW and MOVT instructions. */ 318 #define TARGET_HAVE_MOVT (arm_arch_thumb2 || arm_arch8) 319 320 /* Nonzero if this chip provides the CBZ and CBNZ instructions. */ 321 #define TARGET_HAVE_CBZ (arm_arch_thumb2 || arm_arch8) 322 323 /* Nonzero if this chip provides Armv8.1-M Mainline Security extensions 324 instructions (most are floating-point related). */ 325 #define TARGET_HAVE_FPCXT_CMSE (arm_arch8_1m_main) 326 327 #define TARGET_HAVE_MVE (arm_float_abi != ARM_FLOAT_ABI_SOFT \ 328 && bitmap_bit_p (arm_active_target.isa, \ 329 isa_bit_mve) \ 330 && !TARGET_GENERAL_REGS_ONLY) 331 332 #define TARGET_HAVE_MVE_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT \ 333 && bitmap_bit_p (arm_active_target.isa, \ 334 isa_bit_mve_float) \ 335 && !TARGET_GENERAL_REGS_ONLY) 336 337 /* MVE have few common instructions as VFP, like VLDM alias VPOP, VLDR, VSTM 338 alia VPUSH, VSTR and VMOV, VMSR and VMRS. In the same manner it updates few 339 registers such as FPCAR, FPCCR, FPDSCR, FPSCR, MVFR0, MVFR1 and MVFR2. All 340 the VFP instructions, RTL patterns and register are guarded by 341 TARGET_HARD_FLOAT. But the common instructions, RTL pattern and registers 342 between MVE and VFP will be guarded by the following macro TARGET_VFP_BASE 343 hereafter. */ 344 345 #define TARGET_VFP_BASE (arm_float_abi != ARM_FLOAT_ABI_SOFT \ 346 && bitmap_bit_p (arm_active_target.isa, \ 347 isa_bit_vfp_base) \ 348 && !TARGET_GENERAL_REGS_ONLY) 349 350 /* Nonzero if integer division instructions supported. */ 351 #define TARGET_IDIV ((TARGET_ARM && arm_arch_arm_hwdiv) \ 352 || (TARGET_THUMB && arm_arch_thumb_hwdiv)) 353 354 /* Nonzero if disallow volatile memory access in IT block. */ 355 #define TARGET_NO_VOLATILE_CE (arm_arch_no_volatile_ce) 356 357 /* Nonzero if chip supports the Custom Datapath Extension. */ 358 #define TARGET_CDE (arm_arch_cde && arm_arch8 && !arm_arch_notm) 359 360 /* Should constant I be slplit for OP. */ 361 #define DONT_EARLY_SPLIT_CONSTANT(i, op) \ 362 ((optimize >= 2) \ 363 && can_create_pseudo_p () \ 364 && !const_ok_for_op (i, op)) 365 366 /* True iff the full BPABI is being used. If TARGET_BPABI is true, 367 then TARGET_AAPCS_BASED must be true -- but the converse does not 368 hold. TARGET_BPABI implies the use of the BPABI runtime library, 369 etc., in addition to just the AAPCS calling conventions. */ 370 #ifndef TARGET_BPABI 371 #define TARGET_BPABI false 372 #endif 373 374 /* Transform lane numbers on big endian targets. This is used to allow for the 375 endianness difference between NEON architectural lane numbers and those 376 used in RTL */ 377 #define NEON_ENDIAN_LANE_N(mode, n) \ 378 (BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) - 1 - n : n) 379 380 /* Support for a compile-time default CPU, et cetera. The rules are: 381 --with-arch is ignored if -march or -mcpu are specified. 382 --with-cpu is ignored if -march or -mcpu are specified, and is overridden 383 by --with-arch. 384 --with-tune is ignored if -mtune or -mcpu are specified (but not affected 385 by -march). 386 --with-float is ignored if -mfloat-abi is specified. 387 --with-fpu is ignored if -mfpu is specified. 388 --with-abi is ignored if -mabi is specified. 389 --with-tls is ignored if -mtls-dialect is specified. */ 390 #define OPTION_DEFAULT_SPECS \ 391 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \ 392 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \ 393 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \ 394 {"float", "%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}" }, \ 395 {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \ 396 {"abi", "%{!mabi=*:-mabi=%(VALUE)}"}, \ 397 {"mode", "%{!marm:%{!mthumb:-m%(VALUE)}}"}, \ 398 {"tls", "%{!mtls-dialect=*:-mtls-dialect=%(VALUE)}"}, 399 400 extern const struct arm_fpu_desc 401 { 402 const char *name; 403 enum isa_feature isa_bits[isa_num_bits]; 404 } all_fpus[]; 405 406 /* Which floating point hardware to schedule for. */ 407 extern int arm_fpu_attr; 408 409 #ifndef TARGET_DEFAULT_FLOAT_ABI 410 #define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT 411 #endif 412 413 #ifndef ARM_DEFAULT_ABI 414 #define ARM_DEFAULT_ABI ARM_ABI_APCS 415 #endif 416 417 /* AAPCS based ABIs use short enums by default. */ 418 #ifndef ARM_DEFAULT_SHORT_ENUMS 419 #define ARM_DEFAULT_SHORT_ENUMS \ 420 (TARGET_AAPCS_BASED && arm_abi != ARM_ABI_AAPCS_LINUX) 421 #endif 422 423 /* Map each of the micro-architecture variants to their corresponding 424 major architecture revision. */ 425 426 enum base_architecture 427 { 428 BASE_ARCH_0 = 0, 429 BASE_ARCH_2 = 2, 430 BASE_ARCH_3 = 3, 431 BASE_ARCH_3M = 3, 432 BASE_ARCH_4 = 4, 433 BASE_ARCH_4T = 4, 434 BASE_ARCH_5T = 5, 435 BASE_ARCH_5TE = 5, 436 BASE_ARCH_5TEJ = 5, 437 BASE_ARCH_6 = 6, 438 BASE_ARCH_6J = 6, 439 BASE_ARCH_6KZ = 6, 440 BASE_ARCH_6K = 6, 441 BASE_ARCH_6T2 = 6, 442 BASE_ARCH_6M = 6, 443 BASE_ARCH_6Z = 6, 444 BASE_ARCH_7 = 7, 445 BASE_ARCH_7A = 7, 446 BASE_ARCH_7R = 7, 447 BASE_ARCH_7M = 7, 448 BASE_ARCH_7EM = 7, 449 BASE_ARCH_8A = 8, 450 BASE_ARCH_8M_BASE = 8, 451 BASE_ARCH_8M_MAIN = 8, 452 BASE_ARCH_8R = 8 453 }; 454 455 /* The major revision number of the ARM Architecture implemented by the target. */ 456 extern enum base_architecture arm_base_arch; 457 458 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */ 459 extern int arm_arch4; 460 461 /* Nonzero if this chip supports the ARM Architecture 4T extensions. */ 462 extern int arm_arch4t; 463 464 /* Nonzero if this chip supports the ARM Architecture 5T extensions. */ 465 extern int arm_arch5t; 466 467 /* Nonzero if this chip supports the ARM Architecture 5TE extensions. */ 468 extern int arm_arch5te; 469 470 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */ 471 extern int arm_arch6; 472 473 /* Nonzero if this chip supports the ARM Architecture 6k extensions. */ 474 extern int arm_arch6k; 475 476 /* Nonzero if instructions present in ARMv6-M can be used. */ 477 extern int arm_arch6m; 478 479 /* Nonzero if this chip supports the ARM Architecture 7 extensions. */ 480 extern int arm_arch7; 481 482 /* Nonzero if instructions not present in the 'M' profile can be used. */ 483 extern int arm_arch_notm; 484 485 /* Nonzero if instructions present in ARMv7E-M can be used. */ 486 extern int arm_arch7em; 487 488 /* Nonzero if this chip supports the ARM Architecture 8 extensions. */ 489 extern int arm_arch8; 490 491 /* Nonzero if this chip supports the ARM Architecture 8.1 extensions. */ 492 extern int arm_arch8_1; 493 494 /* Nonzero if this chip supports the ARM Architecture 8.2 extensions. */ 495 extern int arm_arch8_2; 496 497 /* Nonzero if this chip supports the ARM Architecture 8.3 extensions. */ 498 extern int arm_arch8_3; 499 500 /* Nonzero if this chip supports the ARM Architecture 8.4 extensions. */ 501 extern int arm_arch8_4; 502 503 /* Nonzero if this chip supports the ARM Architecture 8.1-M Mainline 504 extensions. */ 505 extern int arm_arch8_1m_main; 506 507 /* Nonzero if this chip supports the FP16 instructions extension of ARM 508 Architecture 8.2. */ 509 extern int arm_fp16_inst; 510 511 /* Nonzero if this chip can benefit from load scheduling. */ 512 extern int arm_ld_sched; 513 514 /* Nonzero if this chip is a StrongARM. */ 515 extern int arm_tune_strongarm; 516 517 /* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */ 518 extern int arm_arch_iwmmxt; 519 520 /* Nonzero if this chip supports Intel Wireless MMX2 technology. */ 521 extern int arm_arch_iwmmxt2; 522 523 /* Nonzero if this chip is an XScale. */ 524 extern int arm_arch_xscale; 525 526 /* Nonzero if tuning for XScale. */ 527 extern int arm_tune_xscale; 528 529 /* Nonzero if tuning for stores via the write buffer. */ 530 extern int arm_tune_wbuf; 531 532 /* Nonzero if tuning for Cortex-A9. */ 533 extern int arm_tune_cortex_a9; 534 535 /* Nonzero if we should define __THUMB_INTERWORK__ in the 536 preprocessor. 537 XXX This is a bit of a hack, it's intended to help work around 538 problems in GLD which doesn't understand that armv5t code is 539 interworking clean. */ 540 extern int arm_cpp_interwork; 541 542 /* Nonzero if chip supports Thumb 1. */ 543 extern int arm_arch_thumb1; 544 545 /* Nonzero if chip supports Thumb 2. */ 546 extern int arm_arch_thumb2; 547 548 /* Nonzero if chip supports integer division instruction in ARM mode. */ 549 extern int arm_arch_arm_hwdiv; 550 551 /* Nonzero if chip supports integer division instruction in Thumb mode. */ 552 extern int arm_arch_thumb_hwdiv; 553 554 /* Nonzero if chip disallows volatile memory access in IT block. */ 555 extern int arm_arch_no_volatile_ce; 556 557 /* Nonzero if we shouldn't use literal pools. */ 558 #ifndef USED_FOR_TARGET 559 extern bool arm_disable_literal_pool; 560 #endif 561 562 /* Nonzero if chip supports the ARMv8 CRC instructions. */ 563 extern int arm_arch_crc; 564 565 /* Nonzero if chip supports the ARMv8-M Security Extensions. */ 566 extern int arm_arch_cmse; 567 568 /* Nonzero if chip supports the I8MM instructions. */ 569 extern int arm_arch_i8mm; 570 571 /* Nonzero if chip supports the BFloat16 instructions. */ 572 extern int arm_arch_bf16; 573 574 /* Nonzero if chip supports the Custom Datapath Extension. */ 575 extern int arm_arch_cde; 576 extern int arm_arch_cde_coproc; 577 extern const int arm_arch_cde_coproc_bits[]; 578 #define ARM_CDE_CONST_COPROC 7 579 #define ARM_CCDE_CONST_1 ((1 << 13) - 1) 580 #define ARM_CCDE_CONST_2 ((1 << 9 ) - 1) 581 #define ARM_CCDE_CONST_3 ((1 << 6 ) - 1) 582 #define ARM_VCDE_CONST_1 ((1 << 11) - 1) 583 #define ARM_VCDE_CONST_2 ((1 << 6 ) - 1) 584 #define ARM_VCDE_CONST_3 ((1 << 3 ) - 1) 585 #define ARM_MVE_CDE_CONST_1 ((1 << 12) - 1) 586 #define ARM_MVE_CDE_CONST_2 ((1 << 7 ) - 1) 587 #define ARM_MVE_CDE_CONST_3 ((1 << 4 ) - 1) 588 589 #ifndef TARGET_DEFAULT 590 #define TARGET_DEFAULT (MASK_APCS_FRAME) 591 #endif 592 593 /* Nonzero if PIC code requires explicit qualifiers to generate 594 PLT and GOT relocs rather than the assembler doing so implicitly. 595 Subtargets can override these if required. */ 596 #ifndef NEED_GOT_RELOC 597 #define NEED_GOT_RELOC 0 598 #endif 599 #ifndef NEED_PLT_RELOC 600 #define NEED_PLT_RELOC 0 601 #endif 602 603 #ifndef TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE 604 #define TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE 1 605 #endif 606 607 /* Nonzero if we need to refer to the GOT with a PC-relative 608 offset. In other words, generate 609 610 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)] 611 612 rather than 613 614 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8) 615 616 The default is true, which matches NetBSD. Subtargets can 617 override this if required. */ 618 #ifndef GOT_PCREL 619 #define GOT_PCREL 1 620 #endif 621 622 /* Target machine storage Layout. */ 623 624 625 /* Define this macro if it is advisable to hold scalars in registers 626 in a wider mode than that declared by the program. In such cases, 627 the value is constrained to be within the bounds of the declared 628 type, but kept valid in the wider mode. The signedness of the 629 extension may differ from that of the type. */ 630 631 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 632 if (GET_MODE_CLASS (MODE) == MODE_INT \ 633 && GET_MODE_SIZE (MODE) < 4) \ 634 { \ 635 (MODE) = SImode; \ 636 } 637 638 /* Define this if most significant bit is lowest numbered 639 in instructions that operate on numbered bit-fields. */ 640 #define BITS_BIG_ENDIAN 0 641 642 /* Define this if most significant byte of a word is the lowest numbered. 643 Most ARM processors are run in little endian mode, so that is the default. 644 If you want to have it run-time selectable, change the definition in a 645 cover file to be TARGET_BIG_ENDIAN. */ 646 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0) 647 648 /* Define this if most significant word of a multiword number is the lowest 649 numbered. */ 650 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN) 651 652 #define UNITS_PER_WORD 4 653 654 /* True if natural alignment is used for doubleword types. */ 655 #define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED 656 657 #define DOUBLEWORD_ALIGNMENT 64 658 659 #define PARM_BOUNDARY 32 660 661 #define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32) 662 663 #define PREFERRED_STACK_BOUNDARY \ 664 (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY) 665 666 #define FUNCTION_BOUNDARY_P(flags) (TARGET_THUMB_P (flags) ? 16 : 32) 667 #define FUNCTION_BOUNDARY (FUNCTION_BOUNDARY_P (target_flags)) 668 669 /* The lowest bit is used to indicate Thumb-mode functions, so the 670 vbit must go into the delta field of pointers to member 671 functions. */ 672 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta 673 674 #define EMPTY_FIELD_BOUNDARY 32 675 676 #define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32) 677 678 #define MALLOC_ABI_ALIGNMENT BIGGEST_ALIGNMENT 679 680 /* XXX Blah -- this macro is used directly by libobjc. Since it 681 supports no vector modes, cut out the complexity and fall back 682 on BIGGEST_FIELD_ALIGNMENT. */ 683 #ifdef IN_TARGET_LIBS 684 #define BIGGEST_FIELD_ALIGNMENT 64 685 #endif 686 687 /* Align definitions of arrays, unions and structures so that 688 initializations and copies can be made more efficient. This is not 689 ABI-changing, so it only affects places where we can see the 690 definition. Increasing the alignment tends to introduce padding, 691 so don't do this when optimizing for size/conserving stack space. */ 692 #define ARM_EXPAND_ALIGNMENT(COND, EXP, ALIGN) \ 693 (((COND) && ((ALIGN) < BITS_PER_WORD) \ 694 && (TREE_CODE (EXP) == ARRAY_TYPE \ 695 || TREE_CODE (EXP) == UNION_TYPE \ 696 || TREE_CODE (EXP) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN)) 697 698 /* Align global data. */ 699 #define DATA_ALIGNMENT(EXP, ALIGN) \ 700 ARM_EXPAND_ALIGNMENT(!optimize_size, EXP, ALIGN) 701 702 /* Similarly, make sure that objects on the stack are sensibly aligned. */ 703 #define LOCAL_ALIGNMENT(EXP, ALIGN) \ 704 ARM_EXPAND_ALIGNMENT(!flag_conserve_stack, EXP, ALIGN) 705 706 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the 707 value set in previous versions of this toolchain was 8, which produces more 708 compact structures. The command line option -mstructure_size_boundary=<n> 709 can be used to change this value. For compatibility with the ARM SDK 710 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI 711 0020D) page 2-20 says "Structures are aligned on word boundaries". 712 The AAPCS specifies a value of 8. */ 713 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary 714 715 /* This is the value used to initialize arm_structure_size_boundary. If a 716 particular arm target wants to change the default value it should change 717 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h 718 for an example of this. */ 719 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY 720 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32 721 #endif 722 723 /* Nonzero if move instructions will actually fail to work 724 when given unaligned data. */ 725 #define STRICT_ALIGNMENT 1 726 727 /* wchar_t is unsigned under the AAPCS. */ 728 #ifndef WCHAR_TYPE 729 #define WCHAR_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "int") 730 731 #define WCHAR_TYPE_SIZE BITS_PER_WORD 732 #endif 733 734 /* Sized for fixed-point types. */ 735 736 #define SHORT_FRACT_TYPE_SIZE 8 737 #define FRACT_TYPE_SIZE 16 738 #define LONG_FRACT_TYPE_SIZE 32 739 #define LONG_LONG_FRACT_TYPE_SIZE 64 740 741 #define SHORT_ACCUM_TYPE_SIZE 16 742 #define ACCUM_TYPE_SIZE 32 743 #define LONG_ACCUM_TYPE_SIZE 64 744 #define LONG_LONG_ACCUM_TYPE_SIZE 64 745 746 #define MAX_FIXED_MODE_SIZE 64 747 748 #ifndef SIZE_TYPE 749 #define SIZE_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "long unsigned int") 750 #endif 751 752 #ifndef PTRDIFF_TYPE 753 #define PTRDIFF_TYPE (TARGET_AAPCS_BASED ? "int" : "long int") 754 #endif 755 756 /* AAPCS requires that structure alignment is affected by bitfields. */ 757 #ifndef PCC_BITFIELD_TYPE_MATTERS 758 #define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED 759 #endif 760 761 /* The maximum size of the sync library functions supported. */ 762 #ifndef MAX_SYNC_LIBFUNC_SIZE 763 #define MAX_SYNC_LIBFUNC_SIZE (2 * UNITS_PER_WORD) 764 #endif 765 766 767 /* Standard register usage. */ 768 769 /* Register allocation in ARM Procedure Call Standard 770 (S - saved over call, F - Frame-related). 771 772 r0 * argument word/integer result 773 r1-r3 argument word 774 775 r4-r8 S register variable 776 r9 S (rfp) register variable (real frame pointer) 777 778 r10 F S (sl) stack limit (used by -mapcs-stack-check) 779 r11 F S (fp) argument pointer 780 r12 (ip) temp workspace 781 r13 F S (sp) lower end of current stack frame 782 r14 (lr) link address/workspace 783 r15 F (pc) program counter 784 785 cc This is NOT a real register, but is used internally 786 to represent things that use or set the condition 787 codes. 788 sfp This isn't either. It is used during rtl generation 789 since the offset between the frame pointer and the 790 auto's isn't known until after register allocation. 791 afp Nor this, we only need this because of non-local 792 goto. Without it fp appears to be used and the 793 elimination code won't get rid of sfp. It tracks 794 fp exactly at all times. 795 apsrq Nor this, it is used to track operations on the Q bit 796 of APSR by ACLE saturating intrinsics. 797 apsrge Nor this, it is used to track operations on the GE bits 798 of APSR by ACLE SIMD32 intrinsics 799 800 *: See TARGET_CONDITIONAL_REGISTER_USAGE */ 801 802 /* s0-s15 VFP scratch (aka d0-d7). 803 s16-s31 S VFP variable (aka d8-d15). 804 vfpcc Not a real register. Represents the VFP condition 805 code flags. 806 vpr Used to represent MVE VPR predication. */ 807 808 /* The stack backtrace structure is as follows: 809 fp points to here: | save code pointer | [fp] 810 | return link value | [fp, #-4] 811 | return sp value | [fp, #-8] 812 | return fp value | [fp, #-12] 813 [| saved r10 value |] 814 [| saved r9 value |] 815 [| saved r8 value |] 816 [| saved r7 value |] 817 [| saved r6 value |] 818 [| saved r5 value |] 819 [| saved r4 value |] 820 [| saved r3 value |] 821 [| saved r2 value |] 822 [| saved r1 value |] 823 [| saved r0 value |] 824 r0-r3 are not normally saved in a C function. */ 825 826 /* 1 for registers that have pervasive standard uses 827 and are not available for the register allocator. */ 828 #define FIXED_REGISTERS \ 829 { \ 830 /* Core regs. */ \ 831 0,0,0,0,0,0,0,0, \ 832 0,0,0,0,0,1,0,1, \ 833 /* VFP regs. */ \ 834 1,1,1,1,1,1,1,1, \ 835 1,1,1,1,1,1,1,1, \ 836 1,1,1,1,1,1,1,1, \ 837 1,1,1,1,1,1,1,1, \ 838 1,1,1,1,1,1,1,1, \ 839 1,1,1,1,1,1,1,1, \ 840 1,1,1,1,1,1,1,1, \ 841 1,1,1,1,1,1,1,1, \ 842 /* IWMMXT regs. */ \ 843 1,1,1,1,1,1,1,1, \ 844 1,1,1,1,1,1,1,1, \ 845 1,1,1,1, \ 846 /* Specials. */ \ 847 1,1,1,1,1,1,1 \ 848 } 849 850 /* 1 for registers not available across function calls. 851 These must include the FIXED_REGISTERS and also any 852 registers that can be used without being saved. 853 The latter must include the registers where values are returned 854 and the register where structure-value addresses are passed. 855 Aside from that, you can include as many other registers as you like. 856 The CC is not preserved over function calls on the ARM 6, so it is 857 easier to assume this for all. SFP is preserved, since FP is. */ 858 #define CALL_USED_REGISTERS \ 859 { \ 860 /* Core regs. */ \ 861 1,1,1,1,0,0,0,0, \ 862 0,0,0,0,1,1,1,1, \ 863 /* VFP Regs. */ \ 864 1,1,1,1,1,1,1,1, \ 865 1,1,1,1,1,1,1,1, \ 866 1,1,1,1,1,1,1,1, \ 867 1,1,1,1,1,1,1,1, \ 868 1,1,1,1,1,1,1,1, \ 869 1,1,1,1,1,1,1,1, \ 870 1,1,1,1,1,1,1,1, \ 871 1,1,1,1,1,1,1,1, \ 872 /* IWMMXT regs. */ \ 873 1,1,1,1,1,1,1,1, \ 874 1,1,1,1,1,1,1,1, \ 875 1,1,1,1, \ 876 /* Specials. */ \ 877 1,1,1,1,1,1,1 \ 878 } 879 880 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE 881 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE 882 #endif 883 884 /* These are a couple of extensions to the formats accepted 885 by asm_fprintf: 886 %@ prints out ASM_COMMENT_START 887 %r prints out REGISTER_PREFIX reg_names[arg] */ 888 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \ 889 case '@': \ 890 fputs (ASM_COMMENT_START, FILE); \ 891 break; \ 892 \ 893 case 'r': \ 894 fputs (REGISTER_PREFIX, FILE); \ 895 fputs (reg_names [va_arg (ARGS, int)], FILE); \ 896 break; 897 898 /* Round X up to the nearest word. */ 899 #define ROUND_UP_WORD(X) (((X) + 3) & ~3) 900 901 /* Convert fron bytes to ints. */ 902 #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 903 904 /* The number of (integer) registers required to hold a quantity of type MODE. 905 Also used for VFP registers. */ 906 #define ARM_NUM_REGS(MODE) \ 907 ARM_NUM_INTS (GET_MODE_SIZE (MODE)) 908 909 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */ 910 #define ARM_NUM_REGS2(MODE, TYPE) \ 911 ARM_NUM_INTS ((MODE) == BLKmode ? \ 912 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE)) 913 914 /* The number of (integer) argument register available. */ 915 #define NUM_ARG_REGS 4 916 917 /* And similarly for the VFP. */ 918 #define NUM_VFP_ARG_REGS 16 919 920 /* Return the register number of the N'th (integer) argument. */ 921 #define ARG_REGISTER(N) (N - 1) 922 923 /* Specify the registers used for certain standard purposes. 924 The values of these macros are register numbers. */ 925 926 /* The number of the last argument register. */ 927 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS) 928 929 /* The numbers of the Thumb register ranges. */ 930 #define FIRST_LO_REGNUM 0 931 #define LAST_LO_REGNUM 7 932 #define FIRST_HI_REGNUM 8 933 #define LAST_HI_REGNUM 11 934 935 /* Overridden by config/arm/bpabi.h. */ 936 #ifndef ARM_UNWIND_INFO 937 #define ARM_UNWIND_INFO 0 938 #endif 939 940 /* Use r0 and r1 to pass exception handling information. */ 941 #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM) 942 943 /* The register that holds the return address in exception handlers. */ 944 #define ARM_EH_STACKADJ_REGNUM 2 945 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM) 946 947 #ifndef ARM_TARGET2_DWARF_FORMAT 948 #define ARM_TARGET2_DWARF_FORMAT DW_EH_PE_pcrel 949 #endif 950 951 /* ttype entries (the only interesting data references used) 952 use TARGET2 relocations. */ 953 #define ASM_PREFERRED_EH_DATA_FORMAT(code, data) \ 954 (((code) == 0 && (data) == 1 && ARM_UNWIND_INFO) ? ARM_TARGET2_DWARF_FORMAT \ 955 : DW_EH_PE_absptr) 956 957 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain 958 as an invisible last argument (possible since varargs don't exist in 959 Pascal), so the following is not true. */ 960 #define STATIC_CHAIN_REGNUM 12 961 962 /* r9 is the FDPIC register (base register for GOT and FUNCDESC accesses). */ 963 #define FDPIC_REGNUM 9 964 965 /* Define this to be where the real frame pointer is if it is not possible to 966 work out the offset between the frame pointer and the automatic variables 967 until after register allocation has taken place. FRAME_POINTER_REGNUM 968 should point to a special register that we will make sure is eliminated. 969 970 For the Thumb we have another problem. The TPCS defines the frame pointer 971 as r11, and GCC believes that it is always possible to use the frame pointer 972 as base register for addressing purposes. (See comments in 973 find_reloads_address()). But - the Thumb does not allow high registers, 974 including r11, to be used as base address registers. Hence our problem. 975 976 The solution used here, and in the old thumb port is to use r7 instead of 977 r11 as the hard frame pointer and to have special code to generate 978 backtrace structures on the stack (if required to do so via a command line 979 option) using r11. This is the only 'user visible' use of r11 as a frame 980 pointer. */ 981 #define ARM_HARD_FRAME_POINTER_REGNUM 11 982 #define THUMB_HARD_FRAME_POINTER_REGNUM 7 983 984 #define HARD_FRAME_POINTER_REGNUM \ 985 (TARGET_ARM \ 986 ? ARM_HARD_FRAME_POINTER_REGNUM \ 987 : THUMB_HARD_FRAME_POINTER_REGNUM) 988 989 #define HARD_FRAME_POINTER_IS_FRAME_POINTER 0 990 #define HARD_FRAME_POINTER_IS_ARG_POINTER 0 991 992 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM 993 994 /* Register to use for pushing function arguments. */ 995 #define STACK_POINTER_REGNUM SP_REGNUM 996 997 #define FIRST_IWMMXT_REGNUM (LAST_HI_VFP_REGNUM + 1) 998 #define LAST_IWMMXT_REGNUM (FIRST_IWMMXT_REGNUM + 15) 999 1000 /* Need to sync with WCGR in iwmmxt.md. */ 1001 #define FIRST_IWMMXT_GR_REGNUM (LAST_IWMMXT_REGNUM + 1) 1002 #define LAST_IWMMXT_GR_REGNUM (FIRST_IWMMXT_GR_REGNUM + 3) 1003 1004 #define IS_IWMMXT_REGNUM(REGNUM) \ 1005 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM)) 1006 #define IS_IWMMXT_GR_REGNUM(REGNUM) \ 1007 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM)) 1008 1009 /* Base register for access to local variables of the function. */ 1010 #define FRAME_POINTER_REGNUM 102 1011 1012 /* Base register for access to arguments of the function. */ 1013 #define ARG_POINTER_REGNUM 103 1014 1015 #define FIRST_VFP_REGNUM 16 1016 #define D7_VFP_REGNUM (FIRST_VFP_REGNUM + 15) 1017 #define LAST_VFP_REGNUM \ 1018 (TARGET_VFPD32 ? LAST_HI_VFP_REGNUM : LAST_LO_VFP_REGNUM) 1019 1020 #define IS_VFP_REGNUM(REGNUM) \ 1021 (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM)) 1022 1023 /* VFP registers are split into two types: those defined by VFP versions < 3 1024 have D registers overlaid on consecutive pairs of S registers. VFP version 3 1025 defines 16 new D registers (d16-d31) which, for simplicity and correctness 1026 in various parts of the backend, we implement as "fake" single-precision 1027 registers (which would be S32-S63, but cannot be used in that way). The 1028 following macros define these ranges of registers. */ 1029 #define LAST_LO_VFP_REGNUM (FIRST_VFP_REGNUM + 31) 1030 #define FIRST_HI_VFP_REGNUM (LAST_LO_VFP_REGNUM + 1) 1031 #define LAST_HI_VFP_REGNUM (FIRST_HI_VFP_REGNUM + 31) 1032 1033 #define VFP_REGNO_OK_FOR_SINGLE(REGNUM) \ 1034 ((REGNUM) <= LAST_LO_VFP_REGNUM) 1035 1036 /* DFmode values are only valid in even register pairs. */ 1037 #define VFP_REGNO_OK_FOR_DOUBLE(REGNUM) \ 1038 ((((REGNUM) - FIRST_VFP_REGNUM) & 1) == 0) 1039 1040 /* Neon Quad values must start at a multiple of four registers. */ 1041 #define NEON_REGNO_OK_FOR_QUAD(REGNUM) \ 1042 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0) 1043 1044 /* Neon structures of vectors must be in even register pairs and there 1045 must be enough registers available. Because of various patterns 1046 requiring quad registers, we require them to start at a multiple of 1047 four. */ 1048 #define NEON_REGNO_OK_FOR_NREGS(REGNUM, N) \ 1049 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0 \ 1050 && (LAST_VFP_REGNUM - (REGNUM) >= 2 * (N) - 1)) 1051 1052 /* The number of hard registers is 16 ARM + 1 CC + 1 SFP + 1 AFP 1053 + 1 APSRQ + 1 APSRGE + 1 VPR. */ 1054 /* Intel Wireless MMX Technology registers add 16 + 4 more. */ 1055 /* VFP (VFP3) adds 32 (64) + 1 VFPCC. */ 1056 #define FIRST_PSEUDO_REGISTER 107 1057 1058 #define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO) 1059 1060 /* Value should be nonzero if functions must have frame pointers. 1061 Zero means the frame pointer need not be set up (and parms may be accessed 1062 via the stack pointer) in functions that seem suitable. 1063 If we have to have a frame pointer we might as well make use of it. 1064 APCS says that the frame pointer does not need to be pushed in leaf 1065 functions, or simple tail call functions. */ 1066 1067 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED 1068 #define SUBTARGET_FRAME_POINTER_REQUIRED 0 1069 #endif 1070 1071 #define VALID_IWMMXT_REG_MODE(MODE) \ 1072 (arm_vector_mode_supported_p (MODE) || (MODE) == DImode) 1073 1074 /* Modes valid for Neon D registers. */ 1075 #define VALID_NEON_DREG_MODE(MODE) \ 1076 ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \ 1077 || (MODE) == V4HFmode || (MODE) == V2SFmode || (MODE) == DImode \ 1078 || (MODE) == V4BFmode) 1079 1080 /* Modes valid for Neon Q registers. */ 1081 #define VALID_NEON_QREG_MODE(MODE) \ 1082 ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \ 1083 || (MODE) == V8HFmode || (MODE) == V4SFmode || (MODE) == V2DImode \ 1084 || (MODE) == V8BFmode) 1085 1086 #define VALID_MVE_MODE(MODE) \ 1087 ((MODE) == V2DImode ||(MODE) == V4SImode || (MODE) == V8HImode \ 1088 || (MODE) == V16QImode || (MODE) == V8HFmode || (MODE) == V4SFmode \ 1089 || (MODE) == V2DFmode) 1090 1091 #define VALID_MVE_SI_MODE(MODE) \ 1092 ((MODE) == V2DImode ||(MODE) == V4SImode || (MODE) == V8HImode \ 1093 || (MODE) == V16QImode) 1094 1095 #define VALID_MVE_SF_MODE(MODE) \ 1096 ((MODE) == V8HFmode || (MODE) == V4SFmode || (MODE) == V2DFmode) 1097 1098 /* Structure modes valid for Neon registers. */ 1099 #define VALID_NEON_STRUCT_MODE(MODE) \ 1100 ((MODE) == TImode || (MODE) == EImode || (MODE) == OImode \ 1101 || (MODE) == CImode || (MODE) == XImode) 1102 1103 #define VALID_MVE_STRUCT_MODE(MODE) \ 1104 ((MODE) == TImode || (MODE) == OImode || (MODE) == XImode) 1105 1106 /* The register numbers in sequence, for passing to arm_gen_load_multiple. */ 1107 extern int arm_regs_in_sequence[]; 1108 1109 /* The order in which register should be allocated. It is good to use ip 1110 since no saving is required (though calls clobber it) and it never contains 1111 function parameters. It is quite good to use lr since other calls may 1112 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is 1113 least likely to contain a function parameter; in addition results are 1114 returned in r0. 1115 For VFP/VFPv3, allocate D16-D31 first, then caller-saved registers (D0-D7), 1116 then D8-D15. The reason for doing this is to attempt to reduce register 1117 pressure when both single- and double-precision registers are used in a 1118 function. */ 1119 1120 #define VREG(X) (FIRST_VFP_REGNUM + (X)) 1121 #define WREG(X) (FIRST_IWMMXT_REGNUM + (X)) 1122 #define WGREG(X) (FIRST_IWMMXT_GR_REGNUM + (X)) 1123 1124 #define REG_ALLOC_ORDER \ 1125 { \ 1126 /* General registers. */ \ 1127 3, 2, 1, 0, 12, 14, 4, 5, \ 1128 6, 7, 8, 9, 10, 11, \ 1129 /* High VFP registers. */ \ 1130 VREG(32), VREG(33), VREG(34), VREG(35), \ 1131 VREG(36), VREG(37), VREG(38), VREG(39), \ 1132 VREG(40), VREG(41), VREG(42), VREG(43), \ 1133 VREG(44), VREG(45), VREG(46), VREG(47), \ 1134 VREG(48), VREG(49), VREG(50), VREG(51), \ 1135 VREG(52), VREG(53), VREG(54), VREG(55), \ 1136 VREG(56), VREG(57), VREG(58), VREG(59), \ 1137 VREG(60), VREG(61), VREG(62), VREG(63), \ 1138 /* VFP argument registers. */ \ 1139 VREG(15), VREG(14), VREG(13), VREG(12), \ 1140 VREG(11), VREG(10), VREG(9), VREG(8), \ 1141 VREG(7), VREG(6), VREG(5), VREG(4), \ 1142 VREG(3), VREG(2), VREG(1), VREG(0), \ 1143 /* VFP call-saved registers. */ \ 1144 VREG(16), VREG(17), VREG(18), VREG(19), \ 1145 VREG(20), VREG(21), VREG(22), VREG(23), \ 1146 VREG(24), VREG(25), VREG(26), VREG(27), \ 1147 VREG(28), VREG(29), VREG(30), VREG(31), \ 1148 /* IWMMX registers. */ \ 1149 WREG(0), WREG(1), WREG(2), WREG(3), \ 1150 WREG(4), WREG(5), WREG(6), WREG(7), \ 1151 WREG(8), WREG(9), WREG(10), WREG(11), \ 1152 WREG(12), WREG(13), WREG(14), WREG(15), \ 1153 WGREG(0), WGREG(1), WGREG(2), WGREG(3), \ 1154 /* Registers not for general use. */ \ 1155 CC_REGNUM, VFPCC_REGNUM, \ 1156 FRAME_POINTER_REGNUM, ARG_POINTER_REGNUM, \ 1157 SP_REGNUM, PC_REGNUM, APSRQ_REGNUM, \ 1158 APSRGE_REGNUM, VPR_REGNUM \ 1159 } 1160 1161 #define IS_VPR_REGNUM(REGNUM) \ 1162 ((REGNUM) == VPR_REGNUM) 1163 1164 /* Use different register alloc ordering for Thumb. */ 1165 #define ADJUST_REG_ALLOC_ORDER arm_order_regs_for_local_alloc () 1166 1167 /* Tell IRA to use the order we define when optimizing for size. */ 1168 #define HONOR_REG_ALLOC_ORDER optimize_function_for_size_p (cfun) 1169 1170 /* Interrupt functions can only use registers that have already been 1171 saved by the prologue, even if they would normally be 1172 call-clobbered. */ 1173 #define HARD_REGNO_RENAME_OK(SRC, DST) \ 1174 (! IS_INTERRUPT (cfun->machine->func_type) || \ 1175 df_regs_ever_live_p (DST)) 1176 1177 /* Register and constant classes. */ 1178 1179 /* Register classes. */ 1180 enum reg_class 1181 { 1182 NO_REGS, 1183 LO_REGS, 1184 STACK_REG, 1185 BASE_REGS, 1186 HI_REGS, 1187 CALLER_SAVE_REGS, 1188 EVEN_REG, 1189 GENERAL_REGS, 1190 CORE_REGS, 1191 VFP_D0_D7_REGS, 1192 VFP_LO_REGS, 1193 VFP_HI_REGS, 1194 VFP_REGS, 1195 IWMMXT_REGS, 1196 IWMMXT_GR_REGS, 1197 CC_REG, 1198 VFPCC_REG, 1199 SFP_REG, 1200 AFP_REG, 1201 VPR_REG, 1202 ALL_REGS, 1203 LIM_REG_CLASSES 1204 }; 1205 1206 #define N_REG_CLASSES (int) LIM_REG_CLASSES 1207 1208 /* Give names of register classes as strings for dump file. */ 1209 #define REG_CLASS_NAMES \ 1210 { \ 1211 "NO_REGS", \ 1212 "LO_REGS", \ 1213 "STACK_REG", \ 1214 "BASE_REGS", \ 1215 "HI_REGS", \ 1216 "CALLER_SAVE_REGS", \ 1217 "EVEN_REG", \ 1218 "GENERAL_REGS", \ 1219 "CORE_REGS", \ 1220 "VFP_D0_D7_REGS", \ 1221 "VFP_LO_REGS", \ 1222 "VFP_HI_REGS", \ 1223 "VFP_REGS", \ 1224 "IWMMXT_REGS", \ 1225 "IWMMXT_GR_REGS", \ 1226 "CC_REG", \ 1227 "VFPCC_REG", \ 1228 "SFP_REG", \ 1229 "AFP_REG", \ 1230 "VPR_REG", \ 1231 "ALL_REGS" \ 1232 } 1233 1234 /* Define which registers fit in which classes. 1235 This is an initializer for a vector of HARD_REG_SET 1236 of length N_REG_CLASSES. */ 1237 #define REG_CLASS_CONTENTS \ 1238 { \ 1239 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ 1240 { 0x000000FF, 0x00000000, 0x00000000, 0x00000000 }, /* LO_REGS */ \ 1241 { 0x00002000, 0x00000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \ 1242 { 0x000020FF, 0x00000000, 0x00000000, 0x00000000 }, /* BASE_REGS */ \ 1243 { 0x00005F00, 0x00000000, 0x00000000, 0x00000000 }, /* HI_REGS */ \ 1244 { 0x0000100F, 0x00000000, 0x00000000, 0x00000000 }, /* CALLER_SAVE_REGS */ \ 1245 { 0x00005555, 0x00000000, 0x00000000, 0x00000000 }, /* EVEN_REGS. */ \ 1246 { 0x00005FFF, 0x00000000, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \ 1247 { 0x00007FFF, 0x00000000, 0x00000000, 0x00000000 }, /* CORE_REGS */ \ 1248 { 0xFFFF0000, 0x00000000, 0x00000000, 0x00000000 }, /* VFP_D0_D7_REGS */ \ 1249 { 0xFFFF0000, 0x0000FFFF, 0x00000000, 0x00000000 }, /* VFP_LO_REGS */ \ 1250 { 0x00000000, 0xFFFF0000, 0x0000FFFF, 0x00000000 }, /* VFP_HI_REGS */ \ 1251 { 0xFFFF0000, 0xFFFFFFFF, 0x0000FFFF, 0x00000000 }, /* VFP_REGS */ \ 1252 { 0x00000000, 0x00000000, 0xFFFF0000, 0x00000000 }, /* IWMMXT_REGS */ \ 1253 { 0x00000000, 0x00000000, 0x00000000, 0x0000000F }, /* IWMMXT_GR_REGS */ \ 1254 { 0x00000000, 0x00000000, 0x00000000, 0x00000010 }, /* CC_REG */ \ 1255 { 0x00000000, 0x00000000, 0x00000000, 0x00000020 }, /* VFPCC_REG */ \ 1256 { 0x00000000, 0x00000000, 0x00000000, 0x00000040 }, /* SFP_REG */ \ 1257 { 0x00000000, 0x00000000, 0x00000000, 0x00000080 }, /* AFP_REG */ \ 1258 { 0x00000000, 0x00000000, 0x00000000, 0x00000400 }, /* VPR_REG. */ \ 1259 { 0xFFFF7FFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x0000000F } /* ALL_REGS. */ \ 1260 } 1261 1262 #define FP_SYSREGS \ 1263 DEF_FP_SYSREG (FPSCR) \ 1264 DEF_FP_SYSREG (FPSCR_nzcvqc) \ 1265 DEF_FP_SYSREG (VPR) \ 1266 DEF_FP_SYSREG (P0) \ 1267 DEF_FP_SYSREG (FPCXTNS) \ 1268 DEF_FP_SYSREG (FPCXTS) 1269 1270 #define DEF_FP_SYSREG(reg) reg ## _ENUM, 1271 enum vfp_sysregs_encoding { 1272 FP_SYSREGS 1273 NB_FP_SYSREGS 1274 }; 1275 #undef DEF_FP_SYSREG 1276 extern const char *fp_sysreg_names[NB_FP_SYSREGS]; 1277 1278 /* Any of the VFP register classes. */ 1279 #define IS_VFP_CLASS(X) \ 1280 ((X) == VFP_D0_D7_REGS || (X) == VFP_LO_REGS \ 1281 || (X) == VFP_HI_REGS || (X) == VFP_REGS) 1282 1283 /* The same information, inverted: 1284 Return the class number of the smallest class containing 1285 reg number REGNO. This could be a conditional expression 1286 or could index an array. */ 1287 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO) 1288 1289 /* The class value for index registers, and the one for base regs. */ 1290 #define INDEX_REG_CLASS (TARGET_THUMB1 ? LO_REGS : GENERAL_REGS) 1291 #define BASE_REG_CLASS (TARGET_THUMB1 ? LO_REGS : CORE_REGS) 1292 1293 /* For the Thumb the high registers cannot be used as base registers 1294 when addressing quantities in QI or HI mode; if we don't know the 1295 mode, then we must be conservative. For MVE we need to load from 1296 memory to low regs based on given modes i.e [Rn], Rn <= LO_REGS. */ 1297 #define MODE_BASE_REG_CLASS(MODE) \ 1298 (TARGET_HAVE_MVE ? arm_mode_base_reg_class (MODE) \ 1299 :(TARGET_32BIT ? CORE_REGS \ 1300 : GET_MODE_SIZE (MODE) >= 4 ? BASE_REGS \ 1301 : LO_REGS)) 1302 1303 /* For Thumb we cannot support SP+reg addressing, so we return LO_REGS 1304 instead of BASE_REGS. */ 1305 #define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS 1306 1307 /* When this hook returns true for MODE, the compiler allows 1308 registers explicitly used in the rtl to be used as spill registers 1309 but prevents the compiler from extending the lifetime of these 1310 registers. */ 1311 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \ 1312 arm_small_register_classes_for_mode_p 1313 1314 /* Must leave BASE_REGS reloads alone */ 1315 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1316 (lra_in_progress ? NO_REGS \ 1317 : ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \ 1318 ? ((true_regnum (X) == -1 ? LO_REGS \ 1319 : (true_regnum (X) + hard_regno_nregs (0, MODE) > 8) ? LO_REGS \ 1320 : NO_REGS)) \ 1321 : NO_REGS)) 1322 1323 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1324 (lra_in_progress ? NO_REGS \ 1325 : (CLASS) != LO_REGS && (CLASS) != BASE_REGS \ 1326 ? ((true_regnum (X) == -1 ? LO_REGS \ 1327 : (true_regnum (X) + hard_regno_nregs (0, MODE) > 8) ? LO_REGS \ 1328 : NO_REGS)) \ 1329 : NO_REGS) 1330 1331 /* Return the register class of a scratch register needed to copy IN into 1332 or out of a register in CLASS in MODE. If it can be done directly, 1333 NO_REGS is returned. */ 1334 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1335 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \ 1336 ((TARGET_HARD_FLOAT && IS_VFP_CLASS (CLASS)) \ 1337 ? coproc_secondary_reload_class (MODE, X, FALSE) \ 1338 : (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) \ 1339 ? coproc_secondary_reload_class (MODE, X, TRUE) \ 1340 : TARGET_32BIT \ 1341 ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \ 1342 ? GENERAL_REGS : NO_REGS) \ 1343 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X)) 1344 1345 /* If we need to load shorts byte-at-a-time, then we need a scratch. */ 1346 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1347 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \ 1348 ((TARGET_HARD_FLOAT && IS_VFP_CLASS (CLASS)) \ 1349 ? coproc_secondary_reload_class (MODE, X, FALSE) : \ 1350 (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) ? \ 1351 coproc_secondary_reload_class (MODE, X, TRUE) : \ 1352 (TARGET_32BIT ? \ 1353 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \ 1354 && CONSTANT_P (X)) \ 1355 ? GENERAL_REGS : \ 1356 (((MODE) == HImode && ! arm_arch4 \ 1357 && (MEM_P (X) \ 1358 || ((REG_P (X) || GET_CODE (X) == SUBREG) \ 1359 && true_regnum (X) == -1))) \ 1360 ? GENERAL_REGS : NO_REGS) \ 1361 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X))) 1362 1363 /* Return the maximum number of consecutive registers 1364 needed to represent mode MODE in a register of class CLASS. 1365 ARM regs are UNITS_PER_WORD bits. 1366 FIXME: Is this true for iWMMX? */ 1367 #define CLASS_MAX_NREGS(CLASS, MODE) \ 1368 (ARM_NUM_REGS (MODE)) 1369 1370 /* If defined, gives a class of registers that cannot be used as the 1371 operand of a SUBREG that changes the mode of the object illegally. */ 1372 1373 /* Stack layout; function entry, exit and calling. */ 1374 1375 /* Define this if pushing a word on the stack 1376 makes the stack pointer a smaller address. */ 1377 #define STACK_GROWS_DOWNWARD 1 1378 1379 /* Define this to nonzero if the nominal address of the stack frame 1380 is at the high-address end of the local variables; 1381 that is, each additional local variable allocated 1382 goes at a more negative offset in the frame. */ 1383 #define FRAME_GROWS_DOWNWARD 1 1384 1385 /* The amount of scratch space needed by _interwork_{r7,r11}_call_via_rN(). 1386 When present, it is one word in size, and sits at the top of the frame, 1387 between the soft frame pointer and either r7 or r11. 1388 1389 We only need _interwork_rM_call_via_rN() for -mcaller-super-interworking, 1390 and only then if some outgoing arguments are passed on the stack. It would 1391 be tempting to also check whether the stack arguments are passed by indirect 1392 calls, but there seems to be no reason in principle why a post-reload pass 1393 couldn't convert a direct call into an indirect one. */ 1394 #define CALLER_INTERWORKING_SLOT_SIZE \ 1395 (TARGET_CALLER_INTERWORKING \ 1396 && maybe_ne (crtl->outgoing_args_size, 0) \ 1397 ? UNITS_PER_WORD : 0) 1398 1399 /* If we generate an insn to push BYTES bytes, 1400 this says how many the stack pointer really advances by. */ 1401 /* The push insns do not do this rounding implicitly. 1402 So don't define this. */ 1403 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */ 1404 1405 /* Define this if the maximum size of all the outgoing args is to be 1406 accumulated and pushed during the prologue. The amount can be 1407 found in the variable crtl->outgoing_args_size. */ 1408 #define ACCUMULATE_OUTGOING_ARGS 1 1409 1410 /* Offset of first parameter from the argument pointer register value. */ 1411 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0) 1412 1413 /* Amount of memory needed for an untyped call to save all possible return 1414 registers. */ 1415 #define APPLY_RESULT_SIZE arm_apply_result_size() 1416 1417 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return 1418 values must be in memory. On the ARM, they need only do so if larger 1419 than a word, or if they contain elements offset from zero in the struct. */ 1420 #define DEFAULT_PCC_STRUCT_RETURN 0 1421 1422 /* These bits describe the different types of function supported 1423 by the ARM backend. They are exclusive. i.e. a function cannot be both a 1424 normal function and an interworked function, for example. Knowing the 1425 type of a function is important for determining its prologue and 1426 epilogue sequences. 1427 Note value 7 is currently unassigned. Also note that the interrupt 1428 function types all have bit 2 set, so that they can be tested for easily. 1429 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the 1430 machine_function structure is initialized (to zero) func_type will 1431 default to unknown. This will force the first use of arm_current_func_type 1432 to call arm_compute_func_type. */ 1433 #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */ 1434 #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */ 1435 #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */ 1436 #define ARM_FT_ISR 4 /* An interrupt service routine. */ 1437 #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */ 1438 #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */ 1439 1440 #define ARM_FT_TYPE_MASK ((1 << 3) - 1) 1441 1442 /* In addition functions can have several type modifiers, 1443 outlined by these bit masks: */ 1444 #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */ 1445 #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */ 1446 #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */ 1447 #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */ 1448 #define ARM_FT_STACKALIGN (1 << 6) /* Called with misaligned stack. */ 1449 #define ARM_FT_CMSE_ENTRY (1 << 7) /* ARMv8-M non-secure entry function. */ 1450 1451 /* Some macros to test these flags. */ 1452 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK) 1453 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT) 1454 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE) 1455 #define IS_NAKED(t) (t & ARM_FT_NAKED) 1456 #define IS_NESTED(t) (t & ARM_FT_NESTED) 1457 #define IS_STACKALIGN(t) (t & ARM_FT_STACKALIGN) 1458 #define IS_CMSE_ENTRY(t) (t & ARM_FT_CMSE_ENTRY) 1459 1460 1461 /* Structure used to hold the function stack frame layout. Offsets are 1462 relative to the stack pointer on function entry. Positive offsets are 1463 in the direction of stack growth. 1464 Only soft_frame is used in thumb mode. */ 1465 1466 typedef struct GTY(()) arm_stack_offsets 1467 { 1468 int saved_args; /* ARG_POINTER_REGNUM. */ 1469 int frame; /* ARM_HARD_FRAME_POINTER_REGNUM. */ 1470 int saved_regs; 1471 int soft_frame; /* FRAME_POINTER_REGNUM. */ 1472 int locals_base; /* THUMB_HARD_FRAME_POINTER_REGNUM. */ 1473 int outgoing_args; /* STACK_POINTER_REGNUM. */ 1474 unsigned int saved_regs_mask; 1475 } 1476 arm_stack_offsets; 1477 1478 #if !defined(GENERATOR_FILE) && !defined (USED_FOR_TARGET) 1479 /* A C structure for machine-specific, per-function data. 1480 This is added to the cfun structure. */ 1481 typedef struct GTY(()) machine_function 1482 { 1483 /* Additional stack adjustment in __builtin_eh_throw. */ 1484 rtx eh_epilogue_sp_ofs; 1485 /* Records if LR has to be saved for far jumps. */ 1486 int far_jump_used; 1487 /* Records if ARG_POINTER was ever live. */ 1488 int arg_pointer_live; 1489 /* Records if the save of LR has been eliminated. */ 1490 int lr_save_eliminated; 1491 /* The size of the stack frame. Only valid after reload. */ 1492 arm_stack_offsets stack_offsets; 1493 /* Records the type of the current function. */ 1494 unsigned long func_type; 1495 /* Record if the function has a variable argument list. */ 1496 int uses_anonymous_args; 1497 /* Records if sibcalls are blocked because an argument 1498 register is needed to preserve stack alignment. */ 1499 int sibcall_blocked; 1500 /* The PIC register for this function. This might be a pseudo. */ 1501 rtx pic_reg; 1502 /* Labels for per-function Thumb call-via stubs. One per potential calling 1503 register. We can never call via LR or PC. We can call via SP if a 1504 trampoline happens to be on the top of the stack. */ 1505 rtx call_via[14]; 1506 /* Set to 1 when a return insn is output, this means that the epilogue 1507 is not needed. */ 1508 int return_used_this_function; 1509 /* When outputting Thumb-1 code, record the last insn that provides 1510 information about condition codes, and the comparison operands. */ 1511 rtx thumb1_cc_insn; 1512 rtx thumb1_cc_op0; 1513 rtx thumb1_cc_op1; 1514 /* Also record the CC mode that is supported. */ 1515 machine_mode thumb1_cc_mode; 1516 /* Set to 1 after arm_reorg has started. */ 1517 int after_arm_reorg; 1518 /* The number of bytes used to store the static chain register on the 1519 stack, above the stack frame. */ 1520 int static_chain_stack_bytes; 1521 } 1522 machine_function; 1523 #endif 1524 1525 #define ARM_Q_BIT_READ (arm_q_bit_access ()) 1526 #define ARM_GE_BITS_READ (arm_ge_bits_access ()) 1527 1528 /* As in the machine_function, a global set of call-via labels, for code 1529 that is in text_section. */ 1530 extern GTY(()) rtx thumb_call_via_label[14]; 1531 1532 /* The number of potential ways of assigning to a co-processor. */ 1533 #define ARM_NUM_COPROC_SLOTS 1 1534 1535 /* Enumeration of procedure calling standard variants. We don't really 1536 support all of these yet. */ 1537 enum arm_pcs 1538 { 1539 ARM_PCS_AAPCS, /* Base standard AAPCS. */ 1540 ARM_PCS_AAPCS_VFP, /* Use VFP registers for floating point values. */ 1541 ARM_PCS_AAPCS_IWMMXT, /* Use iWMMXT registers for vectors. */ 1542 /* This must be the last AAPCS variant. */ 1543 ARM_PCS_AAPCS_LOCAL, /* Private call within this compilation unit. */ 1544 ARM_PCS_ATPCS, /* ATPCS. */ 1545 ARM_PCS_APCS, /* APCS (legacy Linux etc). */ 1546 ARM_PCS_UNKNOWN 1547 }; 1548 1549 /* Default procedure calling standard of current compilation unit. */ 1550 extern enum arm_pcs arm_pcs_default; 1551 1552 #if !defined (USED_FOR_TARGET) 1553 /* A C type for declaring a variable that is used as the first argument of 1554 `FUNCTION_ARG' and other related values. */ 1555 typedef struct 1556 { 1557 /* This is the number of registers of arguments scanned so far. */ 1558 int nregs; 1559 /* This is the number of iWMMXt register arguments scanned so far. */ 1560 int iwmmxt_nregs; 1561 int named_count; 1562 int nargs; 1563 /* Which procedure call variant to use for this call. */ 1564 enum arm_pcs pcs_variant; 1565 1566 /* AAPCS related state tracking. */ 1567 int aapcs_arg_processed; /* No need to lay out this argument again. */ 1568 int aapcs_cprc_slot; /* Index of co-processor rules to handle 1569 this argument, or -1 if using core 1570 registers. */ 1571 int aapcs_ncrn; 1572 int aapcs_next_ncrn; 1573 rtx aapcs_reg; /* Register assigned to this argument. */ 1574 int aapcs_partial; /* How many bytes are passed in regs (if 1575 split between core regs and stack. 1576 Zero otherwise. */ 1577 int aapcs_cprc_failed[ARM_NUM_COPROC_SLOTS]; 1578 int can_split; /* Argument can be split between core regs 1579 and the stack. */ 1580 /* Private data for tracking VFP register allocation */ 1581 unsigned aapcs_vfp_regs_free; 1582 unsigned aapcs_vfp_reg_alloc; 1583 int aapcs_vfp_rcount; 1584 MACHMODE aapcs_vfp_rmode; 1585 } CUMULATIVE_ARGS; 1586 #endif 1587 1588 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \ 1589 (arm_pad_reg_upward (MODE, TYPE, FIRST) ? PAD_UPWARD : PAD_DOWNWARD) 1590 1591 /* For AAPCS, padding should never be below the argument. For other ABIs, 1592 * mimic the default. */ 1593 #define PAD_VARARGS_DOWN \ 1594 ((TARGET_AAPCS_BASED) ? 0 : BYTES_BIG_ENDIAN) 1595 1596 /* Initialize a variable CUM of type CUMULATIVE_ARGS 1597 for a call to a function whose data type is FNTYPE. 1598 For a library call, FNTYPE is 0. 1599 On the ARM, the offset starts at 0. */ 1600 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ 1601 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL)) 1602 1603 /* 1 if N is a possible register number for function argument passing. 1604 On the ARM, r0-r3 are used to pass args. */ 1605 #define FUNCTION_ARG_REGNO_P(REGNO) \ 1606 (IN_RANGE ((REGNO), 0, 3) \ 1607 || (TARGET_AAPCS_BASED && TARGET_HARD_FLOAT \ 1608 && IN_RANGE ((REGNO), FIRST_VFP_REGNUM, FIRST_VFP_REGNUM + 15)) \ 1609 || (TARGET_IWMMXT_ABI \ 1610 && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9))) 1611 1612 1613 /* If your target environment doesn't prefix user functions with an 1614 underscore, you may wish to re-define this to prevent any conflicts. */ 1615 #ifndef ARM_MCOUNT_NAME 1616 #define ARM_MCOUNT_NAME "*mcount" 1617 #endif 1618 1619 /* Call the function profiler with a given profile label. The Acorn 1620 compiler puts this BEFORE the prolog but gcc puts it afterwards. 1621 On the ARM the full profile code will look like: 1622 .data 1623 LP1 1624 .word 0 1625 .text 1626 mov ip, lr 1627 bl mcount 1628 .word LP1 1629 1630 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER 1631 will output the .text section. 1632 1633 The ``mov ip,lr'' seems like a good idea to stick with cc convention. 1634 ``prof'' doesn't seem to mind about this! 1635 1636 Note - this version of the code is designed to work in both ARM and 1637 Thumb modes. */ 1638 #ifndef ARM_FUNCTION_PROFILER 1639 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \ 1640 { \ 1641 char temp[20]; \ 1642 rtx sym; \ 1643 \ 1644 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \ 1645 IP_REGNUM, LR_REGNUM); \ 1646 assemble_name (STREAM, ARM_MCOUNT_NAME); \ 1647 fputc ('\n', STREAM); \ 1648 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \ 1649 sym = gen_rtx_SYMBOL_REF (Pmode, temp); \ 1650 assemble_aligned_integer (UNITS_PER_WORD, sym); \ 1651 } 1652 #endif 1653 1654 #ifdef THUMB_FUNCTION_PROFILER 1655 #define FUNCTION_PROFILER(STREAM, LABELNO) \ 1656 if (TARGET_ARM) \ 1657 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \ 1658 else \ 1659 THUMB_FUNCTION_PROFILER (STREAM, LABELNO) 1660 #else 1661 #define FUNCTION_PROFILER(STREAM, LABELNO) \ 1662 ARM_FUNCTION_PROFILER (STREAM, LABELNO) 1663 #endif 1664 1665 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1666 the stack pointer does not matter. The value is tested only in 1667 functions that have frame pointers. 1668 No definition is equivalent to always zero. 1669 1670 On the ARM, the function epilogue recovers the stack pointer from the 1671 frame. */ 1672 #define EXIT_IGNORE_STACK 1 1673 1674 #define EPILOGUE_USES(REGNO) (epilogue_completed && (REGNO) == LR_REGNUM) 1675 1676 /* Determine if the epilogue should be output as RTL. 1677 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */ 1678 #define USE_RETURN_INSN(ISCOND) \ 1679 (TARGET_32BIT ? use_return_insn (ISCOND, NULL) : 0) 1680 1681 /* Definitions for register eliminations. 1682 1683 This is an array of structures. Each structure initializes one pair 1684 of eliminable registers. The "from" register number is given first, 1685 followed by "to". Eliminations of the same "from" register are listed 1686 in order of preference. 1687 1688 We have two registers that can be eliminated on the ARM. First, the 1689 arg pointer register can often be eliminated in favor of the stack 1690 pointer register. Secondly, the pseudo frame pointer register can always 1691 be eliminated; it is replaced with either the stack or the real frame 1692 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM 1693 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */ 1694 1695 #define ELIMINABLE_REGS \ 1696 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\ 1697 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\ 1698 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\ 1699 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\ 1700 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\ 1701 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\ 1702 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }} 1703 1704 /* Define the offset between two registers, one to be eliminated, and the 1705 other its replacement, at the start of a routine. */ 1706 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1707 if (TARGET_ARM) \ 1708 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \ 1709 else \ 1710 (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO) 1711 1712 /* Special case handling of the location of arguments passed on the stack. */ 1713 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr) 1714 1715 /* Initialize data used by insn expanders. This is called from insn_emit, 1716 once for every function before code is generated. */ 1717 #define INIT_EXPANDERS arm_init_expanders () 1718 1719 /* Length in units of the trampoline for entering a nested function. */ 1720 #define TRAMPOLINE_SIZE (TARGET_FDPIC ? 32 : (TARGET_32BIT ? 16 : 20)) 1721 1722 /* Alignment required for a trampoline in bits. */ 1723 #define TRAMPOLINE_ALIGNMENT 32 1724 1725 /* Addressing modes, and classification of registers for them. */ 1726 #define HAVE_POST_INCREMENT 1 1727 #define HAVE_PRE_INCREMENT TARGET_32BIT 1728 #define HAVE_POST_DECREMENT TARGET_32BIT 1729 #define HAVE_PRE_DECREMENT TARGET_32BIT 1730 #define HAVE_PRE_MODIFY_DISP TARGET_32BIT 1731 #define HAVE_POST_MODIFY_DISP TARGET_32BIT 1732 #define HAVE_PRE_MODIFY_REG TARGET_32BIT 1733 #define HAVE_POST_MODIFY_REG TARGET_32BIT 1734 1735 enum arm_auto_incmodes 1736 { 1737 ARM_POST_INC, 1738 ARM_PRE_INC, 1739 ARM_POST_DEC, 1740 ARM_PRE_DEC 1741 }; 1742 1743 #define ARM_AUTOINC_VALID_FOR_MODE_P(mode, code) \ 1744 (TARGET_32BIT && arm_autoinc_modes_ok_p (mode, code)) 1745 #define USE_LOAD_POST_INCREMENT(mode) \ 1746 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_POST_INC) 1747 #define USE_LOAD_PRE_INCREMENT(mode) \ 1748 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_PRE_INC) 1749 #define USE_LOAD_POST_DECREMENT(mode) \ 1750 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_POST_DEC) 1751 #define USE_LOAD_PRE_DECREMENT(mode) \ 1752 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_PRE_DEC) 1753 1754 #define USE_STORE_PRE_DECREMENT(mode) USE_LOAD_PRE_DECREMENT(mode) 1755 #define USE_STORE_PRE_INCREMENT(mode) USE_LOAD_PRE_INCREMENT(mode) 1756 #define USE_STORE_POST_DECREMENT(mode) USE_LOAD_POST_DECREMENT(mode) 1757 #define USE_STORE_POST_INCREMENT(mode) USE_LOAD_POST_INCREMENT(mode) 1758 1759 /* Macros to check register numbers against specific register classes. */ 1760 1761 /* These assume that REGNO is a hard or pseudo reg number. 1762 They give nonzero only if REGNO is a hard reg of the suitable class 1763 or a pseudo reg currently allocated to a suitable hard reg. */ 1764 #define TEST_REGNO(R, TEST, VALUE) \ 1765 ((R TEST VALUE) \ 1766 || (reg_renumber && ((unsigned) reg_renumber[R] TEST VALUE))) 1767 1768 /* Don't allow the pc to be used. */ 1769 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \ 1770 (TEST_REGNO (REGNO, <, PC_REGNUM) \ 1771 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \ 1772 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM)) 1773 1774 #define THUMB1_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ 1775 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \ 1776 || (GET_MODE_SIZE (MODE) >= 4 \ 1777 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM))) 1778 1779 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ 1780 (TARGET_THUMB1 \ 1781 ? THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \ 1782 : ARM_REGNO_OK_FOR_BASE_P (REGNO)) 1783 1784 /* Nonzero if X can be the base register in a reg+reg addressing mode. 1785 For Thumb, we cannot use SP + reg, so reject SP. */ 1786 #define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \ 1787 REGNO_MODE_OK_FOR_BASE_P (X, QImode) 1788 1789 /* For ARM code, we don't care about the mode, but for Thumb, the index 1790 must be suitable for use in a QImode load. */ 1791 #define REGNO_OK_FOR_INDEX_P(REGNO) \ 1792 (REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode) \ 1793 && !TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)) 1794 1795 /* Maximum number of registers that can appear in a valid memory address. 1796 Shifts in addresses can't be by a register. */ 1797 #define MAX_REGS_PER_ADDRESS 2 1798 1799 /* Recognize any constant value that is a valid address. */ 1800 /* XXX We can address any constant, eventually... */ 1801 /* ??? Should the TARGET_ARM here also apply to thumb2? */ 1802 #define CONSTANT_ADDRESS_P(X) \ 1803 (GET_CODE (X) == SYMBOL_REF \ 1804 && (CONSTANT_POOL_ADDRESS_P (X) \ 1805 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X)))) 1806 1807 /* True if SYMBOL + OFFSET constants must refer to something within 1808 SYMBOL's section. */ 1809 #define ARM_OFFSETS_MUST_BE_WITHIN_SECTIONS_P 0 1810 1811 /* Nonzero if all target requires all absolute relocations be R_ARM_ABS32. */ 1812 #ifndef TARGET_DEFAULT_WORD_RELOCATIONS 1813 #define TARGET_DEFAULT_WORD_RELOCATIONS 0 1814 #endif 1815 1816 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS 1817 #define SUBTARGET_NAME_ENCODING_LENGTHS 1818 #endif 1819 1820 /* This is a C fragment for the inside of a switch statement. 1821 Each case label should return the number of characters to 1822 be stripped from the start of a function's name, if that 1823 name starts with the indicated character. */ 1824 #define ARM_NAME_ENCODING_LENGTHS \ 1825 case '*': return 1; \ 1826 SUBTARGET_NAME_ENCODING_LENGTHS 1827 1828 /* This is how to output a reference to a user-level label named NAME. 1829 `assemble_name' uses this. */ 1830 #undef ASM_OUTPUT_LABELREF 1831 #define ASM_OUTPUT_LABELREF(FILE, NAME) \ 1832 arm_asm_output_labelref (FILE, NAME) 1833 1834 /* Output IT instructions for conditionally executed Thumb-2 instructions. */ 1835 #define ASM_OUTPUT_OPCODE(STREAM, PTR) \ 1836 if (TARGET_THUMB2) \ 1837 thumb2_asm_output_opcode (STREAM); 1838 1839 /* The EABI specifies that constructors should go in .init_array. 1840 Other targets use .ctors for compatibility. */ 1841 #ifndef ARM_EABI_CTORS_SECTION_OP 1842 #define ARM_EABI_CTORS_SECTION_OP \ 1843 "\t.section\t.init_array,\"aw\",%init_array" 1844 #endif 1845 #ifndef ARM_EABI_DTORS_SECTION_OP 1846 #define ARM_EABI_DTORS_SECTION_OP \ 1847 "\t.section\t.fini_array,\"aw\",%fini_array" 1848 #endif 1849 #define ARM_CTORS_SECTION_OP \ 1850 "\t.section\t.ctors,\"aw\",%progbits" 1851 #define ARM_DTORS_SECTION_OP \ 1852 "\t.section\t.dtors,\"aw\",%progbits" 1853 1854 /* Define CTORS_SECTION_ASM_OP. */ 1855 #undef CTORS_SECTION_ASM_OP 1856 #undef DTORS_SECTION_ASM_OP 1857 #ifndef IN_LIBGCC2 1858 # define CTORS_SECTION_ASM_OP \ 1859 (TARGET_AAPCS_BASED ? ARM_EABI_CTORS_SECTION_OP : ARM_CTORS_SECTION_OP) 1860 # define DTORS_SECTION_ASM_OP \ 1861 (TARGET_AAPCS_BASED ? ARM_EABI_DTORS_SECTION_OP : ARM_DTORS_SECTION_OP) 1862 #else /* !defined (IN_LIBGCC2) */ 1863 /* In libgcc, CTORS_SECTION_ASM_OP must be a compile-time constant, 1864 so we cannot use the definition above. */ 1865 # ifdef __ARM_EABI__ 1866 /* The .ctors section is not part of the EABI, so we do not define 1867 CTORS_SECTION_ASM_OP when in libgcc; that prevents crtstuff 1868 from trying to use it. We do define it when doing normal 1869 compilation, as .init_array can be used instead of .ctors. */ 1870 /* There is no need to emit begin or end markers when using 1871 init_array; the dynamic linker will compute the size of the 1872 array itself based on special symbols created by the static 1873 linker. However, we do need to arrange to set up 1874 exception-handling here. */ 1875 # define CTOR_LIST_BEGIN asm (ARM_EABI_CTORS_SECTION_OP) 1876 # define CTOR_LIST_END /* empty */ 1877 # define DTOR_LIST_BEGIN asm (ARM_EABI_DTORS_SECTION_OP) 1878 # define DTOR_LIST_END /* empty */ 1879 # else /* !defined (__ARM_EABI__) */ 1880 # define CTORS_SECTION_ASM_OP ARM_CTORS_SECTION_OP 1881 # define DTORS_SECTION_ASM_OP ARM_DTORS_SECTION_OP 1882 # endif /* !defined (__ARM_EABI__) */ 1883 #endif /* !defined (IN_LIBCC2) */ 1884 1885 /* True if the operating system can merge entities with vague linkage 1886 (e.g., symbols in COMDAT group) during dynamic linking. */ 1887 #ifndef TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P 1888 #define TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P true 1889 #endif 1890 1891 #define ARM_OUTPUT_FN_UNWIND(F, PROLOGUE) arm_output_fn_unwind (F, PROLOGUE) 1892 1893 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 1894 and check its validity for a certain class. 1895 We have two alternate definitions for each of them. 1896 The usual definition accepts all pseudo regs; the other rejects 1897 them unless they have been allocated suitable hard regs. 1898 The symbol REG_OK_STRICT causes the latter definition to be used. 1899 Thumb-2 has the same restrictions as arm. */ 1900 #ifndef REG_OK_STRICT 1901 1902 #define ARM_REG_OK_FOR_BASE_P(X) \ 1903 (REGNO (X) <= LAST_ARM_REGNUM \ 1904 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ 1905 || REGNO (X) == FRAME_POINTER_REGNUM \ 1906 || REGNO (X) == ARG_POINTER_REGNUM) 1907 1908 #define ARM_REG_OK_FOR_INDEX_P(X) \ 1909 ((REGNO (X) <= LAST_ARM_REGNUM \ 1910 && REGNO (X) != STACK_POINTER_REGNUM) \ 1911 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ 1912 || REGNO (X) == FRAME_POINTER_REGNUM \ 1913 || REGNO (X) == ARG_POINTER_REGNUM) 1914 1915 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \ 1916 (REGNO (X) <= LAST_LO_REGNUM \ 1917 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ 1918 || (GET_MODE_SIZE (MODE) >= 4 \ 1919 && (REGNO (X) == STACK_POINTER_REGNUM \ 1920 || (X) == hard_frame_pointer_rtx \ 1921 || (X) == arg_pointer_rtx))) 1922 1923 #define REG_STRICT_P 0 1924 1925 #else /* REG_OK_STRICT */ 1926 1927 #define ARM_REG_OK_FOR_BASE_P(X) \ 1928 ARM_REGNO_OK_FOR_BASE_P (REGNO (X)) 1929 1930 #define ARM_REG_OK_FOR_INDEX_P(X) \ 1931 ARM_REGNO_OK_FOR_INDEX_P (REGNO (X)) 1932 1933 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \ 1934 THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE) 1935 1936 #define REG_STRICT_P 1 1937 1938 #endif /* REG_OK_STRICT */ 1939 1940 /* Now define some helpers in terms of the above. */ 1941 1942 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \ 1943 (TARGET_THUMB1 \ 1944 ? THUMB1_REG_MODE_OK_FOR_BASE_P (X, MODE) \ 1945 : ARM_REG_OK_FOR_BASE_P (X)) 1946 1947 /* For 16-bit Thumb, a valid index register is anything that can be used in 1948 a byte load instruction. */ 1949 #define THUMB1_REG_OK_FOR_INDEX_P(X) \ 1950 THUMB1_REG_MODE_OK_FOR_BASE_P (X, QImode) 1951 1952 /* Nonzero if X is a hard reg that can be used as an index 1953 or if it is a pseudo reg. On the Thumb, the stack pointer 1954 is not suitable. */ 1955 #define REG_OK_FOR_INDEX_P(X) \ 1956 (TARGET_THUMB1 \ 1957 ? THUMB1_REG_OK_FOR_INDEX_P (X) \ 1958 : ARM_REG_OK_FOR_INDEX_P (X)) 1959 1960 /* Nonzero if X can be the base register in a reg+reg addressing mode. 1961 For Thumb, we cannot use SP + reg, so reject SP. */ 1962 #define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \ 1963 REG_OK_FOR_INDEX_P (X) 1964 1965 #define ARM_BASE_REGISTER_RTX_P(X) \ 1966 (REG_P (X) && ARM_REG_OK_FOR_BASE_P (X)) 1967 1968 #define ARM_INDEX_REGISTER_RTX_P(X) \ 1969 (REG_P (X) && ARM_REG_OK_FOR_INDEX_P (X)) 1970 1971 /* Specify the machine mode that this machine uses 1972 for the index in the tablejump instruction. */ 1973 #define CASE_VECTOR_MODE Pmode 1974 1975 #define CASE_VECTOR_PC_RELATIVE ((TARGET_THUMB2 \ 1976 || (TARGET_THUMB1 \ 1977 && (optimize_size || flag_pic))) \ 1978 && (!target_pure_code)) 1979 1980 1981 #define CASE_VECTOR_SHORTEN_MODE(min, max, body) \ 1982 (TARGET_THUMB1 \ 1983 ? (min >= 0 && max < 512 \ 1984 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, QImode) \ 1985 : min >= -256 && max < 256 \ 1986 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, QImode) \ 1987 : min >= 0 && max < 8192 \ 1988 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, HImode) \ 1989 : min >= -4096 && max < 4096 \ 1990 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, HImode) \ 1991 : SImode) \ 1992 : ((min < 0 || max >= 0x20000 || !TARGET_THUMB2) ? SImode \ 1993 : (max >= 0x200) ? HImode \ 1994 : QImode)) 1995 1996 /* signed 'char' is most compatible, but RISC OS wants it unsigned. 1997 unsigned is probably best, but may break some code. */ 1998 #ifndef DEFAULT_SIGNED_CHAR 1999 #define DEFAULT_SIGNED_CHAR 0 2000 #endif 2001 2002 /* Max number of bytes we can move from memory to memory 2003 in one reasonably fast instruction. */ 2004 #define MOVE_MAX 4 2005 2006 #undef MOVE_RATIO 2007 #define MOVE_RATIO(speed) (arm_tune_xscale ? 4 : 2) 2008 2009 /* Define if operations between registers always perform the operation 2010 on the full register even if a narrower mode is specified. */ 2011 #define WORD_REGISTER_OPERATIONS 1 2012 2013 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD 2014 will either zero-extend or sign-extend. The value of this macro should 2015 be the code that says which one of the two operations is implicitly 2016 done, UNKNOWN if none. */ 2017 #define LOAD_EXTEND_OP(MODE) \ 2018 (TARGET_THUMB ? ZERO_EXTEND : \ 2019 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \ 2020 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN))) 2021 2022 /* Nonzero if access to memory by bytes is slow and undesirable. */ 2023 #define SLOW_BYTE_ACCESS 0 2024 2025 /* Immediate shift counts are truncated by the output routines (or was it 2026 the assembler?). Shift counts in a register are truncated by ARM. Note 2027 that the native compiler puts too large (> 32) immediate shift counts 2028 into a register and shifts by the register, letting the ARM decide what 2029 to do instead of doing that itself. */ 2030 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that 2031 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y). 2032 On the arm, Y in a register is used modulo 256 for the shift. Only for 2033 rotates is modulo 32 used. */ 2034 /* #define SHIFT_COUNT_TRUNCATED 1 */ 2035 2036 /* Calling from registers is a massive pain. */ 2037 #define NO_FUNCTION_CSE 1 2038 2039 /* The machine modes of pointers and functions */ 2040 #define Pmode SImode 2041 #define FUNCTION_MODE Pmode 2042 2043 #define ARM_FRAME_RTX(X) \ 2044 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \ 2045 || (X) == arg_pointer_rtx) 2046 2047 /* Try to generate sequences that don't involve branches, we can then use 2048 conditional instructions. */ 2049 #define BRANCH_COST(speed_p, predictable_p) \ 2050 ((arm_branch_cost != -1) ? arm_branch_cost : \ 2051 (current_tune->branch_cost (speed_p, predictable_p))) 2052 2053 /* False if short circuit operation is preferred. */ 2054 #define LOGICAL_OP_NON_SHORT_CIRCUIT \ 2055 ((optimize_size) \ 2056 ? (TARGET_THUMB ? false : true) \ 2057 : TARGET_THUMB ? static_cast<bool> (current_tune->logical_op_non_short_circuit_thumb) \ 2058 : static_cast<bool> (current_tune->logical_op_non_short_circuit_arm)) 2059 2060 2061 /* Position Independent Code. */ 2062 /* We decide which register to use based on the compilation options and 2063 the assembler in use; this is more general than the APCS restriction of 2064 using sb (r9) all the time. */ 2065 extern unsigned arm_pic_register; 2066 2067 /* The register number of the register used to address a table of static 2068 data addresses in memory. */ 2069 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register 2070 2071 /* For FDPIC, the FDPIC register is call-clobbered (otherwise PLT 2072 entries would need to handle saving and restoring it). */ 2073 #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED TARGET_FDPIC 2074 2075 /* We can't directly access anything that contains a symbol, 2076 nor can we indirect via the constant pool. One exception is 2077 UNSPEC_TLS, which is always PIC. */ 2078 #define LEGITIMATE_PIC_OPERAND_P(X) \ 2079 (!(symbol_mentioned_p (X) \ 2080 || label_mentioned_p (X) \ 2081 || (GET_CODE (X) == SYMBOL_REF \ 2082 && CONSTANT_POOL_ADDRESS_P (X) \ 2083 && (symbol_mentioned_p (get_pool_constant (X)) \ 2084 || label_mentioned_p (get_pool_constant (X))))) \ 2085 || tls_mentioned_p (X)) 2086 2087 /* We may want to save the PIC register if it is a dedicated one. */ 2088 #define PIC_REGISTER_MAY_NEED_SAVING \ 2089 (flag_pic \ 2090 && !TARGET_SINGLE_PIC_BASE \ 2091 && !TARGET_FDPIC \ 2092 && arm_pic_register != INVALID_REGNUM) 2093 2094 /* We need to know when we are making a constant pool; this determines 2095 whether data needs to be in the GOT or can be referenced via a GOT 2096 offset. */ 2097 extern int making_const_table; 2098 2099 /* Handle pragmas for compatibility with Intel's compilers. */ 2100 /* Also abuse this to register additional C specific EABI attributes. */ 2101 #define REGISTER_TARGET_PRAGMAS() do { \ 2102 c_register_pragma (0, "long_calls", arm_pr_long_calls); \ 2103 c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \ 2104 c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \ 2105 arm_lang_object_attributes_init(); \ 2106 arm_register_target_pragmas(); \ 2107 } while (0) 2108 2109 /* Condition code information. */ 2110 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 2111 return the mode to be used for the comparison. */ 2112 2113 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y) 2114 2115 #define REVERSIBLE_CC_MODE(MODE) 1 2116 2117 #define REVERSE_CONDITION(CODE,MODE) \ 2118 (((MODE) == CCFPmode || (MODE) == CCFPEmode) \ 2119 ? reverse_condition_maybe_unordered (code) \ 2120 : reverse_condition (code)) 2121 2122 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 2123 ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2) 2124 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 2125 ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2) 2126 2127 #define CC_STATUS_INIT \ 2128 do { cfun->machine->thumb1_cc_insn = NULL_RTX; } while (0) 2129 2130 #undef ASM_APP_ON 2131 #define ASM_APP_ON (inline_asm_unified ? "\t.syntax unified\n" : \ 2132 "\t.syntax divided\n") 2133 2134 #undef ASM_APP_OFF 2135 #define ASM_APP_OFF (TARGET_ARM ? "\t.arm\n\t.syntax unified\n" : \ 2136 "\t.thumb\n\t.syntax unified\n") 2137 2138 /* Output a push or a pop instruction (only used when profiling). 2139 We can't push STATIC_CHAIN_REGNUM (r12) directly with Thumb-1. We know 2140 that ASM_OUTPUT_REG_PUSH will be matched with ASM_OUTPUT_REG_POP, and 2141 that r7 isn't used by the function profiler, so we can use it as a 2142 scratch reg. WARNING: This isn't safe in the general case! It may be 2143 sensitive to future changes in final.c:profile_function. */ 2144 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \ 2145 do \ 2146 { \ 2147 if (TARGET_THUMB1 \ 2148 && (REGNO) == STATIC_CHAIN_REGNUM) \ 2149 { \ 2150 asm_fprintf (STREAM, "\tpush\t{r7}\n"); \ 2151 asm_fprintf (STREAM, "\tmov\tr7, %r\n", REGNO);\ 2152 asm_fprintf (STREAM, "\tpush\t{r7}\n"); \ 2153 } \ 2154 else \ 2155 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \ 2156 } while (0) 2157 2158 2159 /* See comment for ASM_OUTPUT_REG_PUSH concerning Thumb-1 issue. */ 2160 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \ 2161 do \ 2162 { \ 2163 if (TARGET_THUMB1 \ 2164 && (REGNO) == STATIC_CHAIN_REGNUM) \ 2165 { \ 2166 asm_fprintf (STREAM, "\tpop\t{r7}\n"); \ 2167 asm_fprintf (STREAM, "\tmov\t%r, r7\n", REGNO);\ 2168 asm_fprintf (STREAM, "\tpop\t{r7}\n"); \ 2169 } \ 2170 else \ 2171 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \ 2172 } while (0) 2173 2174 #define ADDR_VEC_ALIGN(JUMPTABLE) \ 2175 ((TARGET_THUMB && GET_MODE (PATTERN (JUMPTABLE)) == SImode) ? 2 : 0) 2176 2177 /* Alignment for case labels comes from ADDR_VEC_ALIGN; avoid the 2178 default alignment from elfos.h. */ 2179 #undef ASM_OUTPUT_BEFORE_CASE_LABEL 2180 #define ASM_OUTPUT_BEFORE_CASE_LABEL(FILE, PREFIX, NUM, TABLE) /* Empty. */ 2181 2182 #define LABEL_ALIGN_AFTER_BARRIER(LABEL) \ 2183 (GET_CODE (PATTERN (prev_active_insn (LABEL))) == ADDR_DIFF_VEC \ 2184 ? 1 : 0) 2185 2186 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \ 2187 arm_declare_function_name ((STREAM), (NAME), (DECL)); 2188 2189 /* For aliases of functions we use .thumb_set instead. */ 2190 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \ 2191 do \ 2192 { \ 2193 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \ 2194 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \ 2195 \ 2196 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \ 2197 { \ 2198 fprintf (FILE, "\t.thumb_set "); \ 2199 assemble_name (FILE, LABEL1); \ 2200 fprintf (FILE, ","); \ 2201 assemble_name (FILE, LABEL2); \ 2202 fprintf (FILE, "\n"); \ 2203 } \ 2204 else \ 2205 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \ 2206 } \ 2207 while (0) 2208 2209 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN 2210 /* To support -falign-* switches we need to use .p2align so 2211 that alignment directives in code sections will be padded 2212 with no-op instructions, rather than zeroes. */ 2213 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \ 2214 if ((LOG) != 0) \ 2215 { \ 2216 if ((MAX_SKIP) == 0) \ 2217 fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \ 2218 else \ 2219 fprintf ((FILE), "\t.p2align %d,,%d\n", \ 2220 (int) (LOG), (int) (MAX_SKIP)); \ 2221 } 2222 #endif 2223 2224 /* Add two bytes to the length of conditionally executed Thumb-2 2225 instructions for the IT instruction. */ 2226 #define ADJUST_INSN_LENGTH(insn, length) \ 2227 if (TARGET_THUMB2 && GET_CODE (PATTERN (insn)) == COND_EXEC) \ 2228 length += 2; 2229 2230 /* Only perform branch elimination (by making instructions conditional) if 2231 we're optimizing. For Thumb-2 check if any IT instructions need 2232 outputting. */ 2233 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ 2234 if (TARGET_ARM && optimize) \ 2235 arm_final_prescan_insn (INSN); \ 2236 else if (TARGET_THUMB2) \ 2237 thumb2_final_prescan_insn (INSN); \ 2238 else if (TARGET_THUMB1) \ 2239 thumb1_final_prescan_insn (INSN) 2240 2241 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \ 2242 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \ 2243 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\ 2244 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \ 2245 ? ((~ (unsigned HOST_WIDE_INT) 0) \ 2246 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \ 2247 : 0)))) 2248 2249 /* A C expression whose value is RTL representing the value of the return 2250 address for the frame COUNT steps up from the current frame. */ 2251 2252 #define RETURN_ADDR_RTX(COUNT, FRAME) \ 2253 arm_return_addr (COUNT, FRAME) 2254 2255 /* Mask of the bits in the PC that contain the real return address 2256 when running in 26-bit mode. */ 2257 #define RETURN_ADDR_MASK26 (0x03fffffc) 2258 2259 /* Pick up the return address upon entry to a procedure. Used for 2260 dwarf2 unwind information. This also enables the table driven 2261 mechanism. */ 2262 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM) 2263 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM) 2264 2265 /* Used to mask out junk bits from the return address, such as 2266 processor state, interrupt status, condition codes and the like. */ 2267 #define MASK_RETURN_ADDR \ 2268 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \ 2269 in 26 bit mode, the condition codes must be masked out of the \ 2270 return address. This does not apply to ARM6 and later processors \ 2271 when running in 32 bit mode. */ \ 2272 ((arm_arch4 || TARGET_THUMB) \ 2273 ? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \ 2274 : arm_gen_return_addr_mask ()) 2275 2276 2277 /* Do not emit .note.GNU-stack by default. */ 2278 #ifndef NEED_INDICATE_EXEC_STACK 2279 #define NEED_INDICATE_EXEC_STACK 0 2280 #endif 2281 2282 #define TARGET_ARM_ARCH \ 2283 (arm_base_arch) \ 2284 2285 /* The highest Thumb instruction set version supported by the chip. */ 2286 #define TARGET_ARM_ARCH_ISA_THUMB \ 2287 (arm_arch_thumb2 ? 2 : (arm_arch_thumb1 ? 1 : 0)) 2288 2289 /* Expands to an upper-case char of the target's architectural 2290 profile. */ 2291 #define TARGET_ARM_ARCH_PROFILE \ 2292 (arm_active_target.profile) 2293 2294 /* Bit-field indicating what size LDREX/STREX loads/stores are available. 2295 Bit 0 for bytes, up to bit 3 for double-words. */ 2296 #define TARGET_ARM_FEATURE_LDREX \ 2297 ((TARGET_HAVE_LDREX ? 4 : 0) \ 2298 | (TARGET_HAVE_LDREXBH ? 3 : 0) \ 2299 | (TARGET_HAVE_LDREXD ? 8 : 0)) 2300 2301 /* Set as a bit mask indicating the available widths of hardware floating 2302 point types. Where bit 1 indicates 16-bit support, bit 2 indicates 2303 32-bit support, bit 3 indicates 64-bit support. */ 2304 #define TARGET_ARM_FP \ 2305 (!TARGET_SOFT_FLOAT ? (TARGET_VFP_SINGLE ? 4 \ 2306 : (TARGET_VFP_DOUBLE ? (TARGET_FP16 ? 14 : 12) : 0)) \ 2307 : 0) 2308 2309 2310 /* Set as a bit mask indicating the available widths of floating point 2311 types for hardware NEON floating point. This is the same as 2312 TARGET_ARM_FP without the 64-bit bit set. */ 2313 #define TARGET_NEON_FP \ 2314 (TARGET_NEON ? (TARGET_ARM_FP & (0xff ^ 0x08)) \ 2315 : 0) 2316 2317 /* Name of the automatic fpu-selection option. */ 2318 #define FPUTYPE_AUTO "auto" 2319 2320 /* The maximum number of parallel loads or stores we support in an ldm/stm 2321 instruction. */ 2322 #define MAX_LDM_STM_OPS 4 2323 2324 extern const char *arm_rewrite_mcpu (int argc, const char **argv); 2325 extern const char *arm_rewrite_march (int argc, const char **argv); 2326 extern const char *arm_asm_auto_mfpu (int argc, const char **argv); 2327 #define ASM_CPU_SPEC_FUNCTIONS \ 2328 { "rewrite_mcpu", arm_rewrite_mcpu }, \ 2329 { "rewrite_march", arm_rewrite_march }, \ 2330 { "asm_auto_mfpu", arm_asm_auto_mfpu }, 2331 2332 #define ASM_CPU_SPEC \ 2333 " %{mfpu=auto:%<mfpu=auto %:asm_auto_mfpu(%{march=*: arch %*})}" \ 2334 " %{mcpu=generic-*:-march=%:rewrite_march(%{mcpu=generic-*:%*});" \ 2335 " march=*:-march=%:rewrite_march(%{march=*:%*});" \ 2336 " mcpu=*:-mcpu=%:rewrite_mcpu(%{mcpu=*:%*})" \ 2337 " }" 2338 2339 extern const char *arm_target_thumb_only (int argc, const char **argv); 2340 #define TARGET_MODE_SPEC_FUNCTIONS \ 2341 { "target_mode_check", arm_target_thumb_only }, 2342 2343 /* -mcpu=native handling only makes sense with compiler running on 2344 an ARM chip. */ 2345 #if defined(__arm__) 2346 extern const char *host_detect_local_cpu (int argc, const char **argv); 2347 #define HAVE_LOCAL_CPU_DETECT 2348 # define MCPU_MTUNE_NATIVE_FUNCTIONS \ 2349 { "local_cpu_detect", host_detect_local_cpu }, 2350 # define MCPU_MTUNE_NATIVE_SPECS \ 2351 " %{march=native:%<march=native %:local_cpu_detect(arch)}" \ 2352 " %{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)}" \ 2353 " %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}" 2354 #else 2355 # define MCPU_MTUNE_NATIVE_FUNCTIONS 2356 # define MCPU_MTUNE_NATIVE_SPECS "" 2357 #endif 2358 2359 const char *arm_canon_arch_option (int argc, const char **argv); 2360 const char *arm_canon_arch_multilib_option (int argc, const char **argv); 2361 2362 #define CANON_ARCH_SPEC_FUNCTION \ 2363 { "canon_arch", arm_canon_arch_option }, 2364 2365 #define CANON_ARCH_MULTILIB_SPEC_FUNCTION \ 2366 { "canon_arch_multilib", arm_canon_arch_multilib_option }, 2367 2368 const char *arm_be8_option (int argc, const char **argv); 2369 #define BE8_SPEC_FUNCTION \ 2370 { "be8_linkopt", arm_be8_option }, 2371 2372 # define EXTRA_SPEC_FUNCTIONS \ 2373 MCPU_MTUNE_NATIVE_FUNCTIONS \ 2374 ASM_CPU_SPEC_FUNCTIONS \ 2375 CANON_ARCH_SPEC_FUNCTION \ 2376 CANON_ARCH_MULTILIB_SPEC_FUNCTION \ 2377 TARGET_MODE_SPEC_FUNCTIONS \ 2378 BE8_SPEC_FUNCTION 2379 2380 /* Automatically add -mthumb for Thumb-only targets if mode isn't specified 2381 via the configuration option --with-mode or via the command line. The 2382 function target_mode_check is called to do the check with either: 2383 - an array of -march values if any is given; 2384 - an array of -mcpu values if any is given; 2385 - an empty array. */ 2386 #define TARGET_MODE_SPECS \ 2387 " %{!marm:%{!mthumb:%:target_mode_check(%{march=*:arch %*;mcpu=*:cpu %*;:})}}" 2388 2389 /* Generate a canonical string to represent the architecture selected. */ 2390 #define ARCH_CANONICAL_SPECS \ 2391 " -march=%:canon_arch(%{mcpu=*: cpu %*} " \ 2392 " %{march=*: arch %*} " \ 2393 " %{mfpu=*: fpu %*} " \ 2394 " %{mfloat-abi=*: abi %*}" \ 2395 " %<march=*) " 2396 2397 /* Generate a canonical string to represent the architecture selected ignoring 2398 the options not required for multilib linking. */ 2399 #define MULTILIB_ARCH_CANONICAL_SPECS \ 2400 "-mlibarch=%:canon_arch_multilib(%{mcpu=*: cpu %*} " \ 2401 " %{march=*: arch %*} " \ 2402 " %{mfpu=*: fpu %*} " \ 2403 " %{mfloat-abi=*: abi %*}" \ 2404 " %<mlibarch=*) " 2405 2406 /* Complete set of specs for the driver. Commas separate the 2407 individual rules so that any option suppression (%<opt...)is 2408 completed before starting subsequent rules. */ 2409 #define DRIVER_SELF_SPECS \ 2410 MCPU_MTUNE_NATIVE_SPECS, \ 2411 TARGET_MODE_SPECS, \ 2412 MULTILIB_ARCH_CANONICAL_SPECS, \ 2413 ARCH_CANONICAL_SPECS 2414 2415 #define TARGET_SUPPORTS_WIDE_INT 1 2416 2417 /* For switching between functions with different target attributes. */ 2418 #define SWITCHABLE_TARGET 1 2419 2420 /* Define SECTION_ARM_PURECODE as the ARM specific section attribute 2421 representation for SHF_ARM_PURECODE in GCC. */ 2422 #define SECTION_ARM_PURECODE SECTION_MACH_DEP 2423 2424 #endif /* ! GCC_ARM_H */ 2425