1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) Freescale Semiconductor, Inc. 2006.
4 * Author: Jason Jin<Jason.jin@freescale.com>
5 * Zhang Wei<wei.zhang@freescale.com>
6 *
7 * with the reference on libata and ahci drvier in kernel
8 *
9 * This driver provides a SCSI interface to SATA.
10 */
11 #include <common.h>
12 #include <blk.h>
13 #include <log.h>
14 #include <linux/bitops.h>
15 #include <linux/delay.h>
16
17 #include <command.h>
18 #include <dm.h>
19 #include <pci.h>
20 #include <asm/processor.h>
21 #include <linux/errno.h>
22 #include <asm/io.h>
23 #include <malloc.h>
24 #include <memalign.h>
25 #include <pci.h>
26 #include <scsi.h>
27 #include <libata.h>
28 #include <linux/ctype.h>
29 #include <ahci.h>
30 #include <dm/device-internal.h>
31 #include <dm/lists.h>
32
33 static int ata_io_flush(struct ahci_uc_priv *uc_priv, u8 port);
34
35 #ifndef CONFIG_DM_SCSI
36 struct ahci_uc_priv *probe_ent = NULL;
37 #endif
38
39 #define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0)
40
41 /*
42 * Some controllers limit number of blocks they can read/write at once.
43 * Contemporary SSD devices work much faster if the read/write size is aligned
44 * to a power of 2. Let's set default to 128 and allowing to be overwritten if
45 * needed.
46 */
47 #ifndef MAX_SATA_BLOCKS_READ_WRITE
48 #define MAX_SATA_BLOCKS_READ_WRITE 0x80
49 #endif
50
51 /* Maximum timeouts for each event */
52 #define WAIT_MS_SPINUP 20000
53 #define WAIT_MS_DATAIO 10000
54 #define WAIT_MS_FLUSH 5000
55 #define WAIT_MS_LINKUP 200
56
57 #define AHCI_CAP_S64A BIT(31)
58
ahci_port_base(void __iomem * base,u32 port)59 __weak void __iomem *ahci_port_base(void __iomem *base, u32 port)
60 {
61 return base + 0x100 + (port * 0x80);
62 }
63
64 #define msleep(a) udelay(a * 1000)
65
ahci_dcache_flush_range(unsigned long begin,unsigned long len)66 static void ahci_dcache_flush_range(unsigned long begin, unsigned long len)
67 {
68 const unsigned long start = begin;
69 const unsigned long end = start + len;
70
71 debug("%s: flush dcache: [%#lx, %#lx)\n", __func__, start, end);
72 flush_dcache_range(start, end);
73 }
74
75 /*
76 * SATA controller DMAs to physical RAM. Ensure data from the
77 * controller is invalidated from dcache; next access comes from
78 * physical RAM.
79 */
ahci_dcache_invalidate_range(unsigned long begin,unsigned long len)80 static void ahci_dcache_invalidate_range(unsigned long begin, unsigned long len)
81 {
82 const unsigned long start = begin;
83 const unsigned long end = start + len;
84
85 debug("%s: invalidate dcache: [%#lx, %#lx)\n", __func__, start, end);
86 invalidate_dcache_range(start, end);
87 }
88
89 /*
90 * Ensure data for SATA controller is flushed out of dcache and
91 * written to physical memory.
92 */
ahci_dcache_flush_sata_cmd(struct ahci_ioports * pp)93 static void ahci_dcache_flush_sata_cmd(struct ahci_ioports *pp)
94 {
95 ahci_dcache_flush_range((unsigned long)pp->cmd_slot,
96 AHCI_PORT_PRIV_DMA_SZ);
97 }
98
waiting_for_cmd_completed(void __iomem * offset,int timeout_msec,u32 sign)99 static int waiting_for_cmd_completed(void __iomem *offset,
100 int timeout_msec,
101 u32 sign)
102 {
103 int i;
104 u32 status;
105
106 for (i = 0; ((status = readl(offset)) & sign) && i < timeout_msec; i++)
107 msleep(1);
108
109 return (i < timeout_msec) ? 0 : -1;
110 }
111
ahci_link_up(struct ahci_uc_priv * uc_priv,u8 port)112 int __weak ahci_link_up(struct ahci_uc_priv *uc_priv, u8 port)
113 {
114 u32 tmp;
115 int j = 0;
116 void __iomem *port_mmio = uc_priv->port[port].port_mmio;
117
118 /*
119 * Add port reset before link up to fix some device link up
120 * fail.
121 */
122 writel(0x4, port_mmio + PORT_SCR_CTL);
123 udelay(10000);
124 writel(0x1, port_mmio + PORT_SCR_CTL);
125 udelay(10000);
126 writel(0x0, port_mmio + PORT_SCR_CTL);
127 udelay(10000);
128
129 writel(0x301, port_mmio + PORT_SCR_CTL);
130 udelay(10000);
131 writel(0x300, port_mmio + PORT_SCR_CTL);
132 udelay(1000);
133
134 /*
135 * Bring up SATA link.
136 * SATA link bringup time is usually less than 1 ms; only very
137 * rarely has it taken between 1-2 ms. Never seen it above 2 ms.
138 */
139 while (j < WAIT_MS_LINKUP) {
140 tmp = readl(port_mmio + PORT_SCR_STAT);
141 tmp &= PORT_SCR_STAT_DET_MASK;
142 if (tmp == PORT_SCR_STAT_DET_PHYRDY)
143 return 0;
144 udelay(1000);
145 j++;
146 }
147 return 1;
148 }
149
150 #ifdef CONFIG_SUNXI_AHCI
151 /* The sunxi AHCI controller requires this undocumented setup */
sunxi_dma_init(void __iomem * port_mmio)152 static void sunxi_dma_init(void __iomem *port_mmio)
153 {
154 clrsetbits_le32(port_mmio + PORT_P0DMACR, 0x0000ff00, 0x00004400);
155 }
156 #endif
157
ahci_reset(void __iomem * base)158 int ahci_reset(void __iomem *base)
159 {
160 int i = 1000;
161 u32 __iomem *host_ctl_reg = base + HOST_CTL;
162 u32 tmp = readl(host_ctl_reg); /* global controller reset */
163
164 if ((tmp & HOST_RESET) == 0)
165 writel_with_flush(tmp | HOST_RESET, host_ctl_reg);
166
167 /*
168 * reset must complete within 1 second, or
169 * the hardware should be considered fried.
170 */
171 do {
172 udelay(1000);
173 tmp = readl(host_ctl_reg);
174 i--;
175 } while ((i > 0) && (tmp & HOST_RESET));
176
177 if (i == 0) {
178 printf("controller reset failed (0x%x)\n", tmp);
179 return -1;
180 }
181
182 return 0;
183 }
184
ahci_host_init(struct ahci_uc_priv * uc_priv)185 static int ahci_host_init(struct ahci_uc_priv *uc_priv)
186 {
187 #if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI)
188 # ifdef CONFIG_DM_PCI
189 struct udevice *dev = uc_priv->dev;
190 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
191 # else
192 pci_dev_t pdev = uc_priv->dev;
193 unsigned short vendor;
194 # endif
195 u16 tmp16;
196 #endif
197 void __iomem *mmio = uc_priv->mmio_base;
198 u32 tmp, cap_save, cmd;
199 int i, j, ret;
200 void __iomem *port_mmio;
201 u32 port_map;
202
203 debug("ahci_host_init: start\n");
204
205 cap_save = readl(mmio + HOST_CAP);
206 cap_save &= ((1 << 28) | (1 << 17));
207 cap_save |= (1 << 27); /* Staggered Spin-up. Not needed. */
208
209 ret = ahci_reset(uc_priv->mmio_base);
210 if (ret)
211 return ret;
212
213 writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL);
214 writel(cap_save, mmio + HOST_CAP);
215 writel_with_flush(0xf, mmio + HOST_PORTS_IMPL);
216
217 #if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI)
218 # ifdef CONFIG_DM_PCI
219 if (pplat->vendor == PCI_VENDOR_ID_INTEL) {
220 u16 tmp16;
221
222 dm_pci_read_config16(dev, 0x92, &tmp16);
223 dm_pci_write_config16(dev, 0x92, tmp16 | 0xf);
224 }
225 # else
226 pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
227
228 if (vendor == PCI_VENDOR_ID_INTEL) {
229 u16 tmp16;
230 pci_read_config_word(pdev, 0x92, &tmp16);
231 tmp16 |= 0xf;
232 pci_write_config_word(pdev, 0x92, tmp16);
233 }
234 # endif
235 #endif
236 uc_priv->cap = readl(mmio + HOST_CAP);
237 uc_priv->port_map = readl(mmio + HOST_PORTS_IMPL);
238 port_map = uc_priv->port_map;
239 uc_priv->n_ports = (uc_priv->cap & 0x1f) + 1;
240
241 debug("cap 0x%x port_map 0x%x n_ports %d\n",
242 uc_priv->cap, uc_priv->port_map, uc_priv->n_ports);
243
244 #if !defined(CONFIG_DM_SCSI)
245 if (uc_priv->n_ports > CONFIG_SYS_SCSI_MAX_SCSI_ID)
246 uc_priv->n_ports = CONFIG_SYS_SCSI_MAX_SCSI_ID;
247 #endif
248
249 for (i = 0; i < uc_priv->n_ports; i++) {
250 uc_priv->port[i].port_mmio = ahci_port_base(mmio, i);
251 if (!(port_map & (1 << i)))
252 continue;
253 port_mmio = (u8 *)uc_priv->port[i].port_mmio;
254
255 /* make sure port is not active */
256 tmp = readl(port_mmio + PORT_CMD);
257 if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
258 PORT_CMD_FIS_RX | PORT_CMD_START)) {
259 debug("Port %d is active. Deactivating.\n", i);
260 tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
261 PORT_CMD_FIS_RX | PORT_CMD_START);
262 writel_with_flush(tmp, port_mmio + PORT_CMD);
263
264 /* spec says 500 msecs for each bit, so
265 * this is slightly incorrect.
266 */
267 msleep(500);
268 }
269
270 #ifdef CONFIG_SUNXI_AHCI
271 sunxi_dma_init(port_mmio);
272 #endif
273
274 /* Add the spinup command to whatever mode bits may
275 * already be on in the command register.
276 */
277 cmd = readl(port_mmio + PORT_CMD);
278 cmd |= PORT_CMD_SPIN_UP;
279 writel_with_flush(cmd, port_mmio + PORT_CMD);
280
281 /* Bring up SATA link. */
282 ret = ahci_link_up(uc_priv, i);
283 if (ret) {
284 printf("SATA link %d timeout.\n", i);
285 continue;
286 } else {
287 debug("SATA link ok.\n");
288 }
289
290 /* Clear error status */
291 tmp = readl(port_mmio + PORT_SCR_ERR);
292 if (tmp)
293 writel(tmp, port_mmio + PORT_SCR_ERR);
294
295 debug("Spinning up device on SATA port %d... ", i);
296
297 j = 0;
298 while (j < WAIT_MS_SPINUP) {
299 tmp = readl(port_mmio + PORT_TFDATA);
300 if (!(tmp & (ATA_BUSY | ATA_DRQ)))
301 break;
302 udelay(1000);
303 tmp = readl(port_mmio + PORT_SCR_STAT);
304 tmp &= PORT_SCR_STAT_DET_MASK;
305 if (tmp == PORT_SCR_STAT_DET_PHYRDY)
306 break;
307 j++;
308 }
309
310 tmp = readl(port_mmio + PORT_SCR_STAT) & PORT_SCR_STAT_DET_MASK;
311 if (tmp == PORT_SCR_STAT_DET_COMINIT) {
312 debug("SATA link %d down (COMINIT received), retrying...\n", i);
313 i--;
314 continue;
315 }
316
317 printf("Target spinup took %d ms.\n", j);
318 if (j == WAIT_MS_SPINUP)
319 debug("timeout.\n");
320 else
321 debug("ok.\n");
322
323 tmp = readl(port_mmio + PORT_SCR_ERR);
324 debug("PORT_SCR_ERR 0x%x\n", tmp);
325 writel(tmp, port_mmio + PORT_SCR_ERR);
326
327 /* ack any pending irq events for this port */
328 tmp = readl(port_mmio + PORT_IRQ_STAT);
329 debug("PORT_IRQ_STAT 0x%x\n", tmp);
330 if (tmp)
331 writel(tmp, port_mmio + PORT_IRQ_STAT);
332
333 writel(1 << i, mmio + HOST_IRQ_STAT);
334
335 /* register linkup ports */
336 tmp = readl(port_mmio + PORT_SCR_STAT);
337 debug("SATA port %d status: 0x%x\n", i, tmp);
338 if ((tmp & PORT_SCR_STAT_DET_MASK) == PORT_SCR_STAT_DET_PHYRDY)
339 uc_priv->link_port_map |= (0x01 << i);
340 }
341
342 tmp = readl(mmio + HOST_CTL);
343 debug("HOST_CTL 0x%x\n", tmp);
344 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
345 tmp = readl(mmio + HOST_CTL);
346 debug("HOST_CTL 0x%x\n", tmp);
347 #if !defined(CONFIG_DM_SCSI)
348 #ifndef CONFIG_SCSI_AHCI_PLAT
349 # ifdef CONFIG_DM_PCI
350 dm_pci_read_config16(dev, PCI_COMMAND, &tmp16);
351 tmp |= PCI_COMMAND_MASTER;
352 dm_pci_write_config16(dev, PCI_COMMAND, tmp16);
353 # else
354 pci_read_config_word(pdev, PCI_COMMAND, &tmp16);
355 tmp |= PCI_COMMAND_MASTER;
356 pci_write_config_word(pdev, PCI_COMMAND, tmp16);
357 # endif
358 #endif
359 #endif
360 return 0;
361 }
362
363
ahci_print_info(struct ahci_uc_priv * uc_priv)364 static void ahci_print_info(struct ahci_uc_priv *uc_priv)
365 {
366 #if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI)
367 # if defined(CONFIG_DM_PCI)
368 struct udevice *dev = uc_priv->dev;
369 # else
370 pci_dev_t pdev = uc_priv->dev;
371 # endif
372 u16 cc;
373 #endif
374 void __iomem *mmio = uc_priv->mmio_base;
375 u32 vers, cap, cap2, impl, speed;
376 const char *speed_s;
377 const char *scc_s;
378
379 vers = readl(mmio + HOST_VERSION);
380 cap = uc_priv->cap;
381 cap2 = readl(mmio + HOST_CAP2);
382 impl = uc_priv->port_map;
383
384 speed = (cap >> 20) & 0xf;
385 if (speed == 1)
386 speed_s = "1.5";
387 else if (speed == 2)
388 speed_s = "3";
389 else if (speed == 3)
390 speed_s = "6";
391 else
392 speed_s = "?";
393
394 #if defined(CONFIG_SCSI_AHCI_PLAT) || defined(CONFIG_DM_SCSI)
395 scc_s = "SATA";
396 #else
397 # ifdef CONFIG_DM_PCI
398 dm_pci_read_config16(dev, 0x0a, &cc);
399 # else
400 pci_read_config_word(pdev, 0x0a, &cc);
401 # endif
402 if (cc == 0x0101)
403 scc_s = "IDE";
404 else if (cc == 0x0106)
405 scc_s = "SATA";
406 else if (cc == 0x0104)
407 scc_s = "RAID";
408 else
409 scc_s = "unknown";
410 #endif
411 printf("AHCI %02x%02x.%02x%02x "
412 "%u slots %u ports %s Gbps 0x%x impl %s mode\n",
413 (vers >> 24) & 0xff,
414 (vers >> 16) & 0xff,
415 (vers >> 8) & 0xff,
416 vers & 0xff,
417 ((cap >> 8) & 0x1f) + 1, (cap & 0x1f) + 1, speed_s, impl, scc_s);
418
419 printf("flags: "
420 "%s%s%s%s%s%s%s"
421 "%s%s%s%s%s%s%s"
422 "%s%s%s%s%s%s\n",
423 cap & (1 << 31) ? "64bit " : "",
424 cap & (1 << 30) ? "ncq " : "",
425 cap & (1 << 28) ? "ilck " : "",
426 cap & (1 << 27) ? "stag " : "",
427 cap & (1 << 26) ? "pm " : "",
428 cap & (1 << 25) ? "led " : "",
429 cap & (1 << 24) ? "clo " : "",
430 cap & (1 << 19) ? "nz " : "",
431 cap & (1 << 18) ? "only " : "",
432 cap & (1 << 17) ? "pmp " : "",
433 cap & (1 << 16) ? "fbss " : "",
434 cap & (1 << 15) ? "pio " : "",
435 cap & (1 << 14) ? "slum " : "",
436 cap & (1 << 13) ? "part " : "",
437 cap & (1 << 7) ? "ccc " : "",
438 cap & (1 << 6) ? "ems " : "",
439 cap & (1 << 5) ? "sxs " : "",
440 cap2 & (1 << 2) ? "apst " : "",
441 cap2 & (1 << 1) ? "nvmp " : "",
442 cap2 & (1 << 0) ? "boh " : "");
443 }
444
445 #if defined(CONFIG_DM_SCSI) || !defined(CONFIG_SCSI_AHCI_PLAT)
446 # if defined(CONFIG_DM_PCI) || defined(CONFIG_DM_SCSI)
ahci_init_one(struct ahci_uc_priv * uc_priv,struct udevice * dev)447 static int ahci_init_one(struct ahci_uc_priv *uc_priv, struct udevice *dev)
448 # else
449 static int ahci_init_one(struct ahci_uc_priv *uc_priv, pci_dev_t dev)
450 # endif
451 {
452 #if !defined(CONFIG_DM_SCSI)
453 u16 vendor;
454 #endif
455 int rc;
456
457 uc_priv->dev = dev;
458
459 uc_priv->host_flags = ATA_FLAG_SATA
460 | ATA_FLAG_NO_LEGACY
461 | ATA_FLAG_MMIO
462 | ATA_FLAG_PIO_DMA
463 | ATA_FLAG_NO_ATAPI;
464 uc_priv->pio_mask = 0x1f;
465 uc_priv->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
466
467 #if !defined(CONFIG_DM_SCSI)
468 #ifdef CONFIG_DM_PCI
469 uc_priv->mmio_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_5,
470 PCI_REGION_MEM);
471
472 /* Take from kernel:
473 * JMicron-specific fixup:
474 * make sure we're in AHCI mode
475 */
476 dm_pci_read_config16(dev, PCI_VENDOR_ID, &vendor);
477 if (vendor == 0x197b)
478 dm_pci_write_config8(dev, 0x41, 0xa1);
479 #else
480 uc_priv->mmio_base = pci_map_bar(dev, PCI_BASE_ADDRESS_5,
481 PCI_REGION_MEM);
482
483 /* Take from kernel:
484 * JMicron-specific fixup:
485 * make sure we're in AHCI mode
486 */
487 pci_read_config_word(dev, PCI_VENDOR_ID, &vendor);
488 if (vendor == 0x197b)
489 pci_write_config_byte(dev, 0x41, 0xa1);
490 #endif
491 #else
492 struct scsi_platdata *plat = dev_get_uclass_platdata(dev);
493 uc_priv->mmio_base = (void *)plat->base;
494 #endif
495
496 debug("ahci mmio_base=0x%p\n", uc_priv->mmio_base);
497 /* initialize adapter */
498 rc = ahci_host_init(uc_priv);
499 if (rc)
500 goto err_out;
501
502 ahci_print_info(uc_priv);
503
504 return 0;
505
506 err_out:
507 return rc;
508 }
509 #endif
510
511 #define MAX_DATA_BYTE_COUNT (4*1024*1024)
512
ahci_fill_sg(struct ahci_uc_priv * uc_priv,u8 port,unsigned char * buf,int buf_len)513 static int ahci_fill_sg(struct ahci_uc_priv *uc_priv, u8 port,
514 unsigned char *buf, int buf_len)
515 {
516 struct ahci_ioports *pp = &(uc_priv->port[port]);
517 struct ahci_sg *ahci_sg = pp->cmd_tbl_sg;
518 u32 sg_count;
519 int i;
520
521 sg_count = ((buf_len - 1) / MAX_DATA_BYTE_COUNT) + 1;
522 if (sg_count > AHCI_MAX_SG) {
523 printf("Error:Too much sg!\n");
524 return -1;
525 }
526
527 for (i = 0; i < sg_count; i++) {
528 /* We assume virt=phys */
529 phys_addr_t pa = (unsigned long)buf + i * MAX_DATA_BYTE_COUNT;
530
531 ahci_sg->addr = cpu_to_le32(lower_32_bits(pa));
532 ahci_sg->addr_hi = cpu_to_le32(upper_32_bits(pa));
533 if (ahci_sg->addr_hi && !(uc_priv->cap & AHCI_CAP_S64A)) {
534 printf("Error: DMA address too high\n");
535 return -1;
536 }
537 ahci_sg->flags_size = cpu_to_le32(0x3fffff &
538 (buf_len < MAX_DATA_BYTE_COUNT
539 ? (buf_len - 1)
540 : (MAX_DATA_BYTE_COUNT - 1)));
541 ahci_sg++;
542 buf_len -= MAX_DATA_BYTE_COUNT;
543 }
544
545 return sg_count;
546 }
547
548
ahci_fill_cmd_slot(struct ahci_ioports * pp,u32 opts)549 static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts)
550 {
551 pp->cmd_slot->opts = cpu_to_le32(opts);
552 pp->cmd_slot->status = 0;
553 pp->cmd_slot->tbl_addr = cpu_to_le32((u32)pp->cmd_tbl & 0xffffffff);
554 #ifdef CONFIG_PHYS_64BIT
555 pp->cmd_slot->tbl_addr_hi =
556 cpu_to_le32((u32)(((pp->cmd_tbl) >> 16) >> 16));
557 #endif
558 }
559
wait_spinup(void __iomem * port_mmio)560 static int wait_spinup(void __iomem *port_mmio)
561 {
562 ulong start;
563 u32 tf_data;
564
565 start = get_timer(0);
566 do {
567 tf_data = readl(port_mmio + PORT_TFDATA);
568 if (!(tf_data & ATA_BUSY))
569 return 0;
570 } while (get_timer(start) < WAIT_MS_SPINUP);
571
572 return -ETIMEDOUT;
573 }
574
ahci_port_start(struct ahci_uc_priv * uc_priv,u8 port)575 static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 port)
576 {
577 struct ahci_ioports *pp = &(uc_priv->port[port]);
578 void __iomem *port_mmio = pp->port_mmio;
579 u64 dma_addr;
580 u32 port_status;
581 void __iomem *mem;
582
583 debug("Enter start port: %d\n", port);
584 port_status = readl(port_mmio + PORT_SCR_STAT);
585 debug("Port %d status: %x\n", port, port_status);
586 if ((port_status & 0xf) != 0x03) {
587 printf("No Link on this port!\n");
588 return -1;
589 }
590
591 mem = memalign(2048, AHCI_PORT_PRIV_DMA_SZ);
592 if (!mem) {
593 free(pp);
594 printf("%s: No mem for table!\n", __func__);
595 return -ENOMEM;
596 }
597 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
598
599 /*
600 * First item in chunk of DMA memory: 32-slot command table,
601 * 32 bytes each in size
602 */
603 pp->cmd_slot =
604 (struct ahci_cmd_hdr *)(uintptr_t)virt_to_phys((void *)mem);
605 debug("cmd_slot = %p\n", pp->cmd_slot);
606 mem += (AHCI_CMD_SLOT_SZ + 224);
607
608 /*
609 * Second item: Received-FIS area
610 */
611 pp->rx_fis = virt_to_phys((void *)mem);
612 mem += AHCI_RX_FIS_SZ;
613
614 /*
615 * Third item: data area for storing a single command
616 * and its scatter-gather table
617 */
618 pp->cmd_tbl = virt_to_phys((void *)mem);
619 debug("cmd_tbl_dma = %lx\n", pp->cmd_tbl);
620
621 mem += AHCI_CMD_TBL_HDR;
622 pp->cmd_tbl_sg =
623 (struct ahci_sg *)(uintptr_t)virt_to_phys((void *)mem);
624
625 dma_addr = (ulong)pp->cmd_slot;
626 writel_with_flush(dma_addr, port_mmio + PORT_LST_ADDR);
627 writel_with_flush(dma_addr >> 32, port_mmio + PORT_LST_ADDR_HI);
628 dma_addr = (ulong)pp->rx_fis;
629 writel_with_flush(dma_addr, port_mmio + PORT_FIS_ADDR);
630 writel_with_flush(dma_addr >> 32, port_mmio + PORT_FIS_ADDR_HI);
631
632 #ifdef CONFIG_SUNXI_AHCI
633 sunxi_dma_init(port_mmio);
634 #endif
635
636 writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
637 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
638 PORT_CMD_START, port_mmio + PORT_CMD);
639
640 debug("Exit start port %d\n", port);
641
642 /*
643 * Make sure interface is not busy based on error and status
644 * information from task file data register before proceeding
645 */
646 return wait_spinup(port_mmio);
647 }
648
649
ahci_device_data_io(struct ahci_uc_priv * uc_priv,u8 port,u8 * fis,int fis_len,u8 * buf,int buf_len,u8 is_write)650 static int ahci_device_data_io(struct ahci_uc_priv *uc_priv, u8 port, u8 *fis,
651 int fis_len, u8 *buf, int buf_len, u8 is_write)
652 {
653
654 struct ahci_ioports *pp = &(uc_priv->port[port]);
655 void __iomem *port_mmio = pp->port_mmio;
656 u32 opts;
657 u32 port_status;
658 int sg_count;
659
660 debug("Enter %s: for port %d\n", __func__, port);
661
662 if (port > uc_priv->n_ports) {
663 printf("Invalid port number %d\n", port);
664 return -1;
665 }
666
667 port_status = readl(port_mmio + PORT_SCR_STAT);
668 if ((port_status & 0xf) != 0x03) {
669 debug("No Link on port %d!\n", port);
670 return -1;
671 }
672
673 memcpy((unsigned char *)pp->cmd_tbl, fis, fis_len);
674
675 sg_count = ahci_fill_sg(uc_priv, port, buf, buf_len);
676 opts = (fis_len >> 2) | (sg_count << 16) | (is_write << 6);
677 ahci_fill_cmd_slot(pp, opts);
678
679 ahci_dcache_flush_sata_cmd(pp);
680 ahci_dcache_flush_range((unsigned long)buf, (unsigned long)buf_len);
681
682 writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
683
684 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
685 WAIT_MS_DATAIO, 0x1)) {
686 printf("timeout exit!\n");
687 return -1;
688 }
689
690 ahci_dcache_invalidate_range((unsigned long)buf,
691 (unsigned long)buf_len);
692 debug("%s: %d byte transferred.\n", __func__, pp->cmd_slot->status);
693
694 return 0;
695 }
696
697
ata_id_strcpy(u16 * target,u16 * src,int len)698 static char *ata_id_strcpy(u16 *target, u16 *src, int len)
699 {
700 int i;
701 for (i = 0; i < len / 2; i++)
702 target[i] = swab16(src[i]);
703 return (char *)target;
704 }
705
706 /*
707 * SCSI INQUIRY command operation.
708 */
ata_scsiop_inquiry(struct ahci_uc_priv * uc_priv,struct scsi_cmd * pccb)709 static int ata_scsiop_inquiry(struct ahci_uc_priv *uc_priv,
710 struct scsi_cmd *pccb)
711 {
712 static const u8 hdr[] = {
713 0,
714 0,
715 0x5, /* claim SPC-3 version compatibility */
716 2,
717 95 - 4,
718 };
719 u8 fis[20];
720 u16 *idbuf;
721 ALLOC_CACHE_ALIGN_BUFFER(u16, tmpid, ATA_ID_WORDS);
722 u8 port;
723
724 /* Clean ccb data buffer */
725 memset(pccb->pdata, 0, pccb->datalen);
726
727 memcpy(pccb->pdata, hdr, sizeof(hdr));
728
729 if (pccb->datalen <= 35)
730 return 0;
731
732 memset(fis, 0, sizeof(fis));
733 /* Construct the FIS */
734 fis[0] = 0x27; /* Host to device FIS. */
735 fis[1] = 1 << 7; /* Command FIS. */
736 fis[2] = ATA_CMD_ID_ATA; /* Command byte. */
737
738 /* Read id from sata */
739 port = pccb->target;
740
741 if (ahci_device_data_io(uc_priv, port, (u8 *)&fis, sizeof(fis),
742 (u8 *)tmpid, ATA_ID_WORDS * 2, 0)) {
743 debug("scsi_ahci: SCSI inquiry command failure.\n");
744 return -EIO;
745 }
746
747 if (!uc_priv->ataid[port]) {
748 uc_priv->ataid[port] = malloc(ATA_ID_WORDS * 2);
749 if (!uc_priv->ataid[port]) {
750 printf("%s: No memory for ataid[port]\n", __func__);
751 return -ENOMEM;
752 }
753 }
754
755 idbuf = uc_priv->ataid[port];
756
757 memcpy(idbuf, tmpid, ATA_ID_WORDS * 2);
758 ata_swap_buf_le16(idbuf, ATA_ID_WORDS);
759
760 memcpy(&pccb->pdata[8], "ATA ", 8);
761 ata_id_strcpy((u16 *)&pccb->pdata[16], &idbuf[ATA_ID_PROD], 16);
762 ata_id_strcpy((u16 *)&pccb->pdata[32], &idbuf[ATA_ID_FW_REV], 4);
763
764 #ifdef DEBUG
765 ata_dump_id(idbuf);
766 #endif
767 return 0;
768 }
769
770
771 /*
772 * SCSI READ10/WRITE10 command operation.
773 */
ata_scsiop_read_write(struct ahci_uc_priv * uc_priv,struct scsi_cmd * pccb,u8 is_write)774 static int ata_scsiop_read_write(struct ahci_uc_priv *uc_priv,
775 struct scsi_cmd *pccb, u8 is_write)
776 {
777 lbaint_t lba = 0;
778 u16 blocks = 0;
779 u8 fis[20];
780 u8 *user_buffer = pccb->pdata;
781 u32 user_buffer_size = pccb->datalen;
782
783 /* Retrieve the base LBA number from the ccb structure. */
784 if (pccb->cmd[0] == SCSI_READ16) {
785 memcpy(&lba, pccb->cmd + 2, 8);
786 lba = be64_to_cpu(lba);
787 } else {
788 u32 temp;
789 memcpy(&temp, pccb->cmd + 2, 4);
790 lba = be32_to_cpu(temp);
791 }
792
793 /*
794 * Retrieve the base LBA number and the block count from
795 * the ccb structure.
796 *
797 * For 10-byte and 16-byte SCSI R/W commands, transfer
798 * length 0 means transfer 0 block of data.
799 * However, for ATA R/W commands, sector count 0 means
800 * 256 or 65536 sectors, not 0 sectors as in SCSI.
801 *
802 * WARNING: one or two older ATA drives treat 0 as 0...
803 */
804 if (pccb->cmd[0] == SCSI_READ16)
805 blocks = (((u16)pccb->cmd[13]) << 8) | ((u16) pccb->cmd[14]);
806 else
807 blocks = (((u16)pccb->cmd[7]) << 8) | ((u16) pccb->cmd[8]);
808
809 debug("scsi_ahci: %s %u blocks starting from lba 0x" LBAFU "\n",
810 is_write ? "write" : "read", blocks, lba);
811
812 /* Preset the FIS */
813 memset(fis, 0, sizeof(fis));
814 fis[0] = 0x27; /* Host to device FIS. */
815 fis[1] = 1 << 7; /* Command FIS. */
816 /* Command byte (read/write). */
817 fis[2] = is_write ? ATA_CMD_WRITE_EXT : ATA_CMD_READ_EXT;
818
819 while (blocks) {
820 u16 now_blocks; /* number of blocks per iteration */
821 u32 transfer_size; /* number of bytes per iteration */
822
823 now_blocks = min((u16)MAX_SATA_BLOCKS_READ_WRITE, blocks);
824
825 transfer_size = ATA_SECT_SIZE * now_blocks;
826 if (transfer_size > user_buffer_size) {
827 printf("scsi_ahci: Error: buffer too small.\n");
828 return -EIO;
829 }
830
831 /*
832 * LBA48 SATA command but only use 32bit address range within
833 * that (unless we've enabled 64bit LBA support). The next
834 * smaller command range (28bit) is too small.
835 */
836 fis[4] = (lba >> 0) & 0xff;
837 fis[5] = (lba >> 8) & 0xff;
838 fis[6] = (lba >> 16) & 0xff;
839 fis[7] = 1 << 6; /* device reg: set LBA mode */
840 fis[8] = ((lba >> 24) & 0xff);
841 #ifdef CONFIG_SYS_64BIT_LBA
842 if (pccb->cmd[0] == SCSI_READ16) {
843 fis[9] = ((lba >> 32) & 0xff);
844 fis[10] = ((lba >> 40) & 0xff);
845 }
846 #endif
847
848 fis[3] = 0xe0; /* features */
849
850 /* Block (sector) count */
851 fis[12] = (now_blocks >> 0) & 0xff;
852 fis[13] = (now_blocks >> 8) & 0xff;
853
854 /* Read/Write from ahci */
855 if (ahci_device_data_io(uc_priv, pccb->target, (u8 *)&fis,
856 sizeof(fis), user_buffer, transfer_size,
857 is_write)) {
858 debug("scsi_ahci: SCSI %s10 command failure.\n",
859 is_write ? "WRITE" : "READ");
860 return -EIO;
861 }
862
863 /* If this transaction is a write, do a following flush.
864 * Writes in u-boot are so rare, and the logic to know when is
865 * the last write and do a flush only there is sufficiently
866 * difficult. Just do a flush after every write. This incurs,
867 * usually, one extra flush when the rare writes do happen.
868 */
869 if (is_write) {
870 if (-EIO == ata_io_flush(uc_priv, pccb->target))
871 return -EIO;
872 }
873 user_buffer += transfer_size;
874 user_buffer_size -= transfer_size;
875 blocks -= now_blocks;
876 lba += now_blocks;
877 }
878
879 return 0;
880 }
881
882
883 /*
884 * SCSI READ CAPACITY10 command operation.
885 */
ata_scsiop_read_capacity10(struct ahci_uc_priv * uc_priv,struct scsi_cmd * pccb)886 static int ata_scsiop_read_capacity10(struct ahci_uc_priv *uc_priv,
887 struct scsi_cmd *pccb)
888 {
889 u32 cap;
890 u64 cap64;
891 u32 block_size;
892
893 if (!uc_priv->ataid[pccb->target]) {
894 printf("scsi_ahci: SCSI READ CAPACITY10 command failure. "
895 "\tNo ATA info!\n"
896 "\tPlease run SCSI command INQUIRY first!\n");
897 return -EPERM;
898 }
899
900 cap64 = ata_id_n_sectors(uc_priv->ataid[pccb->target]);
901 if (cap64 > 0x100000000ULL)
902 cap64 = 0xffffffff;
903
904 cap = cpu_to_be32(cap64);
905 memcpy(pccb->pdata, &cap, sizeof(cap));
906
907 block_size = cpu_to_be32((u32)512);
908 memcpy(&pccb->pdata[4], &block_size, 4);
909
910 return 0;
911 }
912
913
914 /*
915 * SCSI READ CAPACITY16 command operation.
916 */
ata_scsiop_read_capacity16(struct ahci_uc_priv * uc_priv,struct scsi_cmd * pccb)917 static int ata_scsiop_read_capacity16(struct ahci_uc_priv *uc_priv,
918 struct scsi_cmd *pccb)
919 {
920 u64 cap;
921 u64 block_size;
922
923 if (!uc_priv->ataid[pccb->target]) {
924 printf("scsi_ahci: SCSI READ CAPACITY16 command failure. "
925 "\tNo ATA info!\n"
926 "\tPlease run SCSI command INQUIRY first!\n");
927 return -EPERM;
928 }
929
930 cap = ata_id_n_sectors(uc_priv->ataid[pccb->target]);
931 cap = cpu_to_be64(cap);
932 memcpy(pccb->pdata, &cap, sizeof(cap));
933
934 block_size = cpu_to_be64((u64)512);
935 memcpy(&pccb->pdata[8], &block_size, 8);
936
937 return 0;
938 }
939
940
941 /*
942 * SCSI TEST UNIT READY command operation.
943 */
ata_scsiop_test_unit_ready(struct ahci_uc_priv * uc_priv,struct scsi_cmd * pccb)944 static int ata_scsiop_test_unit_ready(struct ahci_uc_priv *uc_priv,
945 struct scsi_cmd *pccb)
946 {
947 return (uc_priv->ataid[pccb->target]) ? 0 : -EPERM;
948 }
949
950
ahci_scsi_exec(struct udevice * dev,struct scsi_cmd * pccb)951 static int ahci_scsi_exec(struct udevice *dev, struct scsi_cmd *pccb)
952 {
953 struct ahci_uc_priv *uc_priv;
954 #ifdef CONFIG_DM_SCSI
955 uc_priv = dev_get_uclass_priv(dev->parent);
956 #else
957 uc_priv = probe_ent;
958 #endif
959 int ret;
960
961 switch (pccb->cmd[0]) {
962 case SCSI_READ16:
963 case SCSI_READ10:
964 ret = ata_scsiop_read_write(uc_priv, pccb, 0);
965 break;
966 case SCSI_WRITE10:
967 ret = ata_scsiop_read_write(uc_priv, pccb, 1);
968 break;
969 case SCSI_RD_CAPAC10:
970 ret = ata_scsiop_read_capacity10(uc_priv, pccb);
971 break;
972 case SCSI_RD_CAPAC16:
973 ret = ata_scsiop_read_capacity16(uc_priv, pccb);
974 break;
975 case SCSI_TST_U_RDY:
976 ret = ata_scsiop_test_unit_ready(uc_priv, pccb);
977 break;
978 case SCSI_INQUIRY:
979 ret = ata_scsiop_inquiry(uc_priv, pccb);
980 break;
981 default:
982 printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]);
983 return -ENOTSUPP;
984 }
985
986 if (ret) {
987 debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0], ret);
988 return ret;
989 }
990 return 0;
991
992 }
993
ahci_start_ports(struct ahci_uc_priv * uc_priv)994 static int ahci_start_ports(struct ahci_uc_priv *uc_priv)
995 {
996 u32 linkmap;
997 int i;
998
999 linkmap = uc_priv->link_port_map;
1000
1001 for (i = 0; i < uc_priv->n_ports; i++) {
1002 if (((linkmap >> i) & 0x01)) {
1003 if (ahci_port_start(uc_priv, (u8) i)) {
1004 printf("Can not start port %d\n", i);
1005 continue;
1006 }
1007 }
1008 }
1009
1010 return 0;
1011 }
1012
1013 #ifndef CONFIG_DM_SCSI
scsi_low_level_init(int busdevfunc)1014 void scsi_low_level_init(int busdevfunc)
1015 {
1016 struct ahci_uc_priv *uc_priv;
1017
1018 #ifndef CONFIG_SCSI_AHCI_PLAT
1019 probe_ent = calloc(1, sizeof(struct ahci_uc_priv));
1020 if (!probe_ent) {
1021 printf("%s: No memory for uc_priv\n", __func__);
1022 return;
1023 }
1024 uc_priv = probe_ent;
1025 # if defined(CONFIG_DM_PCI)
1026 struct udevice *dev;
1027 int ret;
1028
1029 ret = dm_pci_bus_find_bdf(busdevfunc, &dev);
1030 if (ret)
1031 return;
1032 ahci_init_one(uc_priv, dev);
1033 # else
1034 ahci_init_one(uc_priv, busdevfunc);
1035 # endif
1036 #else
1037 uc_priv = probe_ent;
1038 #endif
1039
1040 ahci_start_ports(uc_priv);
1041 }
1042 #endif
1043
1044 #ifndef CONFIG_SCSI_AHCI_PLAT
1045 # if defined(CONFIG_DM_PCI) || defined(CONFIG_DM_SCSI)
achi_init_one_dm(struct udevice * dev)1046 int achi_init_one_dm(struct udevice *dev)
1047 {
1048 struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
1049
1050 return ahci_init_one(uc_priv, dev);
1051 }
1052 #endif
1053 #endif
1054
achi_start_ports_dm(struct udevice * dev)1055 int achi_start_ports_dm(struct udevice *dev)
1056 {
1057 struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
1058
1059 return ahci_start_ports(uc_priv);
1060 }
1061
1062 #ifdef CONFIG_SCSI_AHCI_PLAT
ahci_init_common(struct ahci_uc_priv * uc_priv,void __iomem * base)1063 static int ahci_init_common(struct ahci_uc_priv *uc_priv, void __iomem *base)
1064 {
1065 int rc;
1066
1067 uc_priv->host_flags = ATA_FLAG_SATA
1068 | ATA_FLAG_NO_LEGACY
1069 | ATA_FLAG_MMIO
1070 | ATA_FLAG_PIO_DMA
1071 | ATA_FLAG_NO_ATAPI;
1072 uc_priv->pio_mask = 0x1f;
1073 uc_priv->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
1074
1075 uc_priv->mmio_base = base;
1076
1077 /* initialize adapter */
1078 rc = ahci_host_init(uc_priv);
1079 if (rc)
1080 goto err_out;
1081
1082 ahci_print_info(uc_priv);
1083
1084 rc = ahci_start_ports(uc_priv);
1085
1086 err_out:
1087 return rc;
1088 }
1089
1090 #ifndef CONFIG_DM_SCSI
ahci_init(void __iomem * base)1091 int ahci_init(void __iomem *base)
1092 {
1093 struct ahci_uc_priv *uc_priv;
1094
1095 probe_ent = malloc(sizeof(struct ahci_uc_priv));
1096 if (!probe_ent) {
1097 printf("%s: No memory for uc_priv\n", __func__);
1098 return -ENOMEM;
1099 }
1100
1101 uc_priv = probe_ent;
1102 memset(uc_priv, 0, sizeof(struct ahci_uc_priv));
1103
1104 return ahci_init_common(uc_priv, base);
1105 }
1106 #endif
1107
ahci_init_dm(struct udevice * dev,void __iomem * base)1108 int ahci_init_dm(struct udevice *dev, void __iomem *base)
1109 {
1110 struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
1111
1112 return ahci_init_common(uc_priv, base);
1113 }
1114
scsi_init(void)1115 void __weak scsi_init(void)
1116 {
1117 }
1118
1119 #endif /* CONFIG_SCSI_AHCI_PLAT */
1120
1121 /*
1122 * In the general case of generic rotating media it makes sense to have a
1123 * flush capability. It probably even makes sense in the case of SSDs because
1124 * one cannot always know for sure what kind of internal cache/flush mechanism
1125 * is embodied therein. At first it was planned to invoke this after the last
1126 * write to disk and before rebooting. In practice, knowing, a priori, which
1127 * is the last write is difficult. Because writing to the disk in u-boot is
1128 * very rare, this flush command will be invoked after every block write.
1129 */
ata_io_flush(struct ahci_uc_priv * uc_priv,u8 port)1130 static int ata_io_flush(struct ahci_uc_priv *uc_priv, u8 port)
1131 {
1132 u8 fis[20];
1133 struct ahci_ioports *pp = &(uc_priv->port[port]);
1134 void __iomem *port_mmio = pp->port_mmio;
1135 u32 cmd_fis_len = 5; /* five dwords */
1136
1137 /* Preset the FIS */
1138 memset(fis, 0, 20);
1139 fis[0] = 0x27; /* Host to device FIS. */
1140 fis[1] = 1 << 7; /* Command FIS. */
1141 fis[2] = ATA_CMD_FLUSH_EXT;
1142
1143 memcpy((unsigned char *)pp->cmd_tbl, fis, 20);
1144 ahci_fill_cmd_slot(pp, cmd_fis_len);
1145 ahci_dcache_flush_sata_cmd(pp);
1146 writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
1147
1148 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
1149 WAIT_MS_FLUSH, 0x1)) {
1150 debug("scsi_ahci: flush command timeout on port %d.\n", port);
1151 return -EIO;
1152 }
1153
1154 return 0;
1155 }
1156
ahci_scsi_bus_reset(struct udevice * dev)1157 static int ahci_scsi_bus_reset(struct udevice *dev)
1158 {
1159 /* Not implemented */
1160
1161 return 0;
1162 }
1163
1164 #ifdef CONFIG_DM_SCSI
ahci_bind_scsi(struct udevice * ahci_dev,struct udevice ** devp)1165 int ahci_bind_scsi(struct udevice *ahci_dev, struct udevice **devp)
1166 {
1167 struct udevice *dev;
1168 int ret;
1169
1170 ret = device_bind_driver(ahci_dev, "ahci_scsi", "ahci_scsi", &dev);
1171 if (ret)
1172 return ret;
1173 *devp = dev;
1174
1175 return 0;
1176 }
1177
ahci_probe_scsi(struct udevice * ahci_dev,ulong base)1178 int ahci_probe_scsi(struct udevice *ahci_dev, ulong base)
1179 {
1180 struct ahci_uc_priv *uc_priv;
1181 struct scsi_platdata *uc_plat;
1182 struct udevice *dev;
1183 int ret;
1184
1185 device_find_first_child(ahci_dev, &dev);
1186 if (!dev)
1187 return -ENODEV;
1188 uc_plat = dev_get_uclass_platdata(dev);
1189 uc_plat->base = base;
1190 uc_plat->max_lun = 1;
1191 uc_plat->max_id = 2;
1192
1193 uc_priv = dev_get_uclass_priv(ahci_dev);
1194 ret = ahci_init_one(uc_priv, dev);
1195 if (ret)
1196 return ret;
1197 ret = ahci_start_ports(uc_priv);
1198 if (ret)
1199 return ret;
1200
1201 /*
1202 * scsi_scan_dev() scans devices up-to the number of max_id.
1203 * Update max_id if the number of detected ports exceeds max_id.
1204 * This allows SCSI to scan all detected ports.
1205 */
1206 uc_plat->max_id = max_t(unsigned long, uc_priv->n_ports,
1207 uc_plat->max_id);
1208 /* If port count is less than max_id, update max_id */
1209 if (uc_priv->n_ports < uc_plat->max_id)
1210 uc_plat->max_id = uc_priv->n_ports;
1211
1212 return 0;
1213 }
1214
1215 #ifdef CONFIG_DM_PCI
ahci_probe_scsi_pci(struct udevice * ahci_dev)1216 int ahci_probe_scsi_pci(struct udevice *ahci_dev)
1217 {
1218 ulong base;
1219
1220 base = (ulong)dm_pci_map_bar(ahci_dev, PCI_BASE_ADDRESS_5,
1221 PCI_REGION_MEM);
1222
1223 return ahci_probe_scsi(ahci_dev, base);
1224 }
1225 #endif
1226
1227 struct scsi_ops scsi_ops = {
1228 .exec = ahci_scsi_exec,
1229 .bus_reset = ahci_scsi_bus_reset,
1230 };
1231
1232 U_BOOT_DRIVER(ahci_scsi) = {
1233 .name = "ahci_scsi",
1234 .id = UCLASS_SCSI,
1235 .ops = &scsi_ops,
1236 };
1237 #else
scsi_exec(struct udevice * dev,struct scsi_cmd * pccb)1238 int scsi_exec(struct udevice *dev, struct scsi_cmd *pccb)
1239 {
1240 return ahci_scsi_exec(dev, pccb);
1241 }
1242
scsi_bus_reset(struct udevice * dev)1243 __weak int scsi_bus_reset(struct udevice *dev)
1244 {
1245 return ahci_scsi_bus_reset(dev);
1246
1247 return 0;
1248 }
1249 #endif
1250