1 ////////////////////////////////////////////////////////////////////////////////
2 //
3 // Copyright (c) 2011-2013 MStar Semiconductor, Inc.
4 // All rights reserved.
5 //
6 // Unless otherwise stipulated in writing, any and all information contained
7 // herein regardless in any format shall remain the sole proprietary of
8 // MStar Semiconductor Inc. and be kept in strict confidence
9 // ("MStar Confidential Information") by the recipient.
10 // Any unauthorized act including without limitation unauthorized disclosure,
11 // copying, use, reproduction, sale, distribution, modification, disassembling,
12 // reverse engineering and compiling of the contents of MStar Confidential
13 // Information is unlawful and strictly prohibited. MStar hereby reserves the
14 // rights to any and all damages, losses, costs and expenses resulting therefrom.
15 //
16 ////////////////////////////////////////////////////////////////////////////////
17
18 ////////////////////////////////////////////////////////////////////////////////////////////////////
19 // file halPVR_IframeLUT.c
20 // @brief Secure PVR Iframe LUT HAL
21 // @author MStar Semiconductor,Inc.
22 ////////////////////////////////////////////////////////////////////////////////////////////////////
23 #include "MsCommon.h"
24 #include "drvSYS.h"
25 #include "regPVR_IframeLUT.h"
26 #include "halPVR_IframeLUT.h"
27
28 #define K6LITEU01 (MDrv_SYS_GetChipRev() < 0x1)
29
30 //--------------------------------------------------------------------------------------------------
31 // Driver Compiler Option
32 //--------------------------------------------------------------------------------------------------
33
34 //--------------------------------------------------------------------------------------------------
35 // TSP Hardware Abstraction Layer
36 //--------------------------------------------------------------------------------------------------
37
38 static REG_Ctrl0* _RegCtrl0 = NULL; // PVR_IframeLUT LUT
39 static REG_Ctrl1* _RegCtrl1[4] = {NULL}; // PVR_IframeLUT FSC
40
41
42 //-------------------------------------------------------------------------------------------------
43 // Local Functions
44 //-------------------------------------------------------------------------------------------------
45 #define MIU_BUS (4)
46
47 //-------------------------------------------------------------------------------------------------
48 // Debug Message
49 //-------------------------------------------------------------------------------------------------
50 typedef enum
51 {
52 E_HAL_PVR_IframeLUT_DBG_LEVEL_NONE, // no debug message shown
53 E_HAL_PVR_IframeLUT_DBG_LEVEL_ERR, // only shows error message that can't be recover
54 E_HAL_PVR_IframeLUT_DBG_LEVEL_WARN, // error case can be recover, like retry
55 E_HAL_PVR_IframeLUT_DBG_LEVEL_EVENT, // event that is okay but better known, ex: timestamp ring, file circular, etc.
56 E_HAL_PVR_IframeLUT_DBG_LEVEL_INFO, // information for internal parameter
57 E_HAL_PVR_IframeLUT_DBG_LEVEL_FUNC, // Function trace and input parameter trace
58 E_HAL_PVR_IframeLUT_DBG_LEVEL_TRACE, // debug trace
59 } EN_HAL_PVR_IframeLUT_DBGMSG_LEVEL;
60
61 typedef enum
62 {
63 E_HAL_PVR_IframeLUT_DBG_MODEL_NONE, // @temporarily , need to refine
64 E_HAL_PVR_IframeLUT_DBG_MODEL_ALL,
65 } EN_HAL_PVR_IframeLUT_DBGMSG_MODEL;
66
67 //#define HAL_PVR_IframeLUT_DBGMSG(_level,_model,_f) do {if(_u32PVR_IframeLUTDbgLevel >= (_level)&&((_u32PVR_IframeLUTDbgModel&_model)!=0)) (_f);} while(0)
68 //static MS_U32 _u32PVR_IframeLUTDbgLevel = E_HAL_PVR_IframeLUT_DBG_LEVEL_ERR;
69 //static MS_U32 _u32PVR_IframeLUTDbgModel = E_HAL_PVR_IframeLUT_DBG_MODEL_ALL;
70
71
72 //[NOTE] Jerry
73 // Some register has write order, for example, writing PCR_L will disable PCR counter
74 // writing PCR_M trigger nothing, writing PCR_H will enable PCR counter
75 #define _HAL_REG32_PVR_IframeLUT_W(reg, value) do { (reg)->low = ((value) & 0x0000FFFF); \
76 (reg)->high = ((value) >> 16); } while(0)
77
78 #define _HAL_REG16_PVR_IframeLUT_W(reg, value) { (reg)->data = (MS_U16)((value) & 0xFFFF); }
79
80 //--------------------------------------------------------------------------------------------------
81 // Macro of bit operations
82 //--------------------------------------------------------------------------------------------------
83 #define HAS_FLAG(flag, bit) ((flag) & (bit))
84 #define SET_FLAG(flag, bit) ((flag) |= (bit))
85 #define RESET_FLAG(flag, bit) ((flag) &= (~(bit)))
86 #define SET_FLAG1(flag, bit) ((flag) | (bit))
87 #define RESET_FLAG1(flag, bit) ((flag) & (~(bit)))
88
89
90 #define _REG16_SET_PVR_IframeLUT(reg, value); _HAL_REG16_PVR_IframeLUT_W(reg, SET_FLAG1(_HAL_REG16_PVR_IframeLUT_R(reg), value));
91 //#define _REG32_SET_PVR_IframeLUT(reg, value); _HAL_REG32_PVR_IframeLUT_W(reg, SET_FLAG1(_HAL_REG32_PVR_IframeLUT_R(reg), value));
92 #define _REG16_CLR_PVR_IframeLUT(reg, value); _HAL_REG16_PVR_IframeLUT_W(reg, RESET_FLAG1(_HAL_REG16_PVR_IframeLUT_R(reg), value));
93 //#define _REG32_CLR_PVR_IframeLUT(reg, value); _HAL_REG32_PVR_IframeLUT_W(reg, RESET_FLAG1(_HAL_REG32_PVR_IframeLUT_R(reg), value));
94
95
96 //--------------------------------------------------------------------------------------------------
97 // Implementation
98 //--------------------------------------------------------------------------------------------------
99 MS_VIRT _u32LutRegBase = 0;
100
101 #define PVR_IframeLUT_WRITE_POINTER_GET(reg) *((volatile MS_U32*)(_u32LutRegBase + ((0x50480UL + reg)<< 2)))
102 #define REG_LUT_WP_PVR1 0x78
103 #define REG_LUT_WP_PVR2 0x79
104 #define REG_LUT_WP_PVR3 0x7A
105 #define REG_LUT_WP_PVR4 0x7B
106
107 #if 0
108 static MS_U32 _HAL_REG32_PVR_IframeLUT_R(REG32PVR_IframeLUT *reg)
109 {
110 MS_U32 value = 0;
111 value = (reg)->high << 16;
112 value |= (reg)->low;
113 return value;
114 }
115 #endif
116
_HAL_REG16_PVR_IframeLUT_R(REG16PVR_IframeLUT * reg)117 static MS_U16 _HAL_REG16_PVR_IframeLUT_R(REG16PVR_IframeLUT *reg)
118 {
119 MS_U16 value = 0;
120 value = (reg)->data;
121 return value;
122 }
123
_HAL_PVR_IframeLUT_SetBank(MS_VIRT u32BankAddr)124 static void _HAL_PVR_IframeLUT_SetBank(MS_VIRT u32BankAddr)
125 {
126 _u32LutRegBase = u32BankAddr;
127
128 _RegCtrl0 = (REG_Ctrl0*)(u32BankAddr + 0xE6C00UL); // PVR_IframeLUT LUT 0x1736
129 _RegCtrl1[0] = (REG_Ctrl1*)(u32BankAddr + 0xE6E00UL); // PVR_IframeLUT FSC 0x1737
130 _RegCtrl1[1] = (REG_Ctrl1*)(u32BankAddr + 0xE6E80UL); // PVR_IframeLUT FSC 0x1737
131 _RegCtrl1[2] = (REG_Ctrl1*)(u32BankAddr + 0xE6F00UL); // PVR_IframeLUT FSC 0x1737
132 _RegCtrl1[3] = (REG_Ctrl1*)(u32BankAddr + 0xE6F80UL); // PVR_IframeLUT FSC 0x1737
133 }
134
_HAL_PVR_IframeLUT_SetBuf(MS_U32 u32PVREng,MS_U32 u32StartAddr0,MS_U32 u32BufSize0)135 static MS_BOOL _HAL_PVR_IframeLUT_SetBuf(MS_U32 u32PVREng , MS_U32 u32StartAddr0, MS_U32 u32BufSize0)
136 {
137 MS_U32 u32EndAddr0 = u32StartAddr0 + u32BufSize0;
138 switch(u32PVREng)
139 {
140 case 0:
141 //head1
142 _HAL_REG32_PVR_IframeLUT_W(&_RegCtrl0->CFG0_10_11, u32StartAddr0 >> MIU_BUS);
143 //end1
144 _HAL_REG32_PVR_IframeLUT_W(&(_RegCtrl0->CFG0_14_15), u32EndAddr0 >> MIU_BUS);
145 //mid1
146 _HAL_REG32_PVR_IframeLUT_W(&(_RegCtrl0->CFG0_12_13), u32EndAddr0 >> (MIU_BUS + 1));
147 break;
148 case 1:
149 //head1
150 _HAL_REG32_PVR_IframeLUT_W(&_RegCtrl0->CFG0_16_17, u32StartAddr0 >> MIU_BUS);
151 //end1
152 _HAL_REG32_PVR_IframeLUT_W(&_RegCtrl0->CFG0_1A_1B, u32EndAddr0 >> MIU_BUS);
153 //mid1
154 _HAL_REG32_PVR_IframeLUT_W(&(_RegCtrl0->CFG0_18_19), u32EndAddr0 >> (MIU_BUS + 1));
155 break;
156
157 case 2:
158 //head1
159 _HAL_REG32_PVR_IframeLUT_W(&(_RegCtrl0->CFG0_1C_1D), u32StartAddr0 >> MIU_BUS);
160 //end1
161 _HAL_REG32_PVR_IframeLUT_W(&(_RegCtrl0->CFG0_20_21), u32EndAddr0 >> MIU_BUS);
162 //mid1
163 _HAL_REG32_PVR_IframeLUT_W(&(_RegCtrl0->CFG0_1E_1F), u32EndAddr0 >> (MIU_BUS + 1));
164 break;
165
166 case 3:
167 //head1
168 _HAL_REG32_PVR_IframeLUT_W(&(_RegCtrl0->CFG0_22_23), u32StartAddr0 >> MIU_BUS);
169 //end1
170 _HAL_REG32_PVR_IframeLUT_W(&(_RegCtrl0->CFG0_26_27), u32EndAddr0 >> MIU_BUS);
171 //mid1
172 _HAL_REG32_PVR_IframeLUT_W(&(_RegCtrl0->CFG0_24_25), u32EndAddr0 >> (MIU_BUS + 1));
173 break;
174
175 default:
176 return FALSE;
177 }
178
179 // set the addr to LUT
180 _REG16_SET_PVR_IframeLUT(&_RegCtrl0->CFG0_00, CFG0_00_REG_TABLE_ID_AUTO_SET);
181 _REG16_CLR_PVR_IframeLUT(&_RegCtrl0->CFG0_00, CFG0_00_REG_TABLE_ID_AUTO_SET);
182 return TRUE;
183 }
184
185 //
186 // General API
187 //
188
HAL_PVR_IframeLUT_Init(MS_VIRT u32BankAddr)189 MS_BOOL HAL_PVR_IframeLUT_Init(MS_VIRT u32BankAddr)
190 {/*
191 if(K6LITEU01)
192 {
193 printf("HAL_PVR_IframeLUT_Init fail: Not Support in K6LITEU01\n");
194 return FALSE;
195 }*/
196
197 // check if DSCMB inited
198 MS_U8 u8RegReceiveBufSDrc = *((volatile MS_U8*)(u32BankAddr + 0xE0400UL + 4 * 0x11)); // TSP3 0x1702, offset 0x11
199 // check reg_receive_buf0_src ~ reg_receive_buf3_src = 0b10 Dscrmb
200 // 0b1010,1010 = 0xAA
201 if(0xAA != u8RegReceiveBufSDrc)
202 {
203 printf("HAL_PVR_IframeLUT_Init fail!\n");
204 return FALSE;
205 }
206
207 _HAL_PVR_IframeLUT_SetBank(u32BankAddr);
208
209 // solve endian problem
210 // from 32-bytes big-endian
211 // to 16-bytes little-endian | 16-bytes little-endian
212 _REG16_SET_PVR_IframeLUT(&_RegCtrl0->CFG0_0B, CFG0_0B_REG_LUT2MI_DSWAP_BT_ORDER);
213
214 return TRUE;
215 }
216
HAL_PVR_IframeLUT_Open(MS_U32 u32PVREng,MS_U32 u32StartAddr0,MS_U32 u32BufSize0,HAL_PVR_IframeLUT_VDEC_TYPE eVdec,MS_U32 u32TSCEPath)217 MS_BOOL HAL_PVR_IframeLUT_Open(MS_U32 u32PVREng, MS_U32 u32StartAddr0, MS_U32 u32BufSize0, HAL_PVR_IframeLUT_VDEC_TYPE eVdec, MS_U32 u32TSCEPath)
218 {
219 if(!_HAL_PVR_IframeLUT_SetBuf(u32PVREng, u32StartAddr0, u32BufSize0))
220 {
221 printf("_HAL_PVR_IframeLUT_SetBuf fail\n");
222 return FALSE;
223 }
224 if(!HAL_PVR_IframeLUT_SetVdecType(u32PVREng, eVdec))
225 {
226 printf("HAL_PVR_IframeLUT_SetVdec fail\n");
227 return FALSE;
228 }
229
230 switch(u32TSCEPath)
231 {
232 case 0:
233 _REG16_SET_PVR_IframeLUT(&_RegCtrl0->CFG0_0B, CFG0_0B_REG_LUT2MI_EN0); // upper path
234 break;
235 case 1:
236 _REG16_SET_PVR_IframeLUT(&_RegCtrl0->CFG0_0B, CFG0_0B_REG_LUT2MI_EN1); // lower path
237 break;
238 case 2:
239 _REG16_SET_PVR_IframeLUT(&_RegCtrl0->CFG0_0B, CFG0_0B_REG_LUT2MI_EN2); // mid path
240 break;
241 default:
242 return FALSE;
243 }
244
245 switch(u32PVREng)
246 {
247 case 0:
248 // enable LUT for PVR eng 0
249 _REG16_SET_PVR_IframeLUT(&(_RegCtrl0->CFG0_00), CFG0_00_REG_CHANNEL_EN0);
250 break;
251 case 1:
252 // enable LUT for PVR eng 1
253 _REG16_SET_PVR_IframeLUT(&(_RegCtrl0->CFG0_00), CFG0_00_REG_CHANNEL_EN1);
254 break;
255 case 2:
256 // enable LUT for PVR eng 2
257 _REG16_SET_PVR_IframeLUT(&(_RegCtrl0->CFG0_00), CFG0_00_REG_CHANNEL_EN2);
258 break;
259 case 3:
260 // enable LUT for PVR eng 3
261 _REG16_SET_PVR_IframeLUT(&(_RegCtrl0->CFG0_00), CFG0_00_REG_CHANNEL_EN3);
262 break;
263 default:
264 return FALSE;
265 }
266
267 _REG16_SET_PVR_IframeLUT(&_RegCtrl1[u32PVREng]->CFG1_01, 0x0FE0);
268 return TRUE;
269 }
270
HAL_PVR_IframeLUT_Close(MS_U32 u32PVREng)271 MS_BOOL HAL_PVR_IframeLUT_Close(MS_U32 u32PVREng)
272 {
273 switch(u32PVREng)
274 {
275 case 0:
276 // disable LUT for PVR eng 0
277 _REG16_CLR_PVR_IframeLUT(&(_RegCtrl0->CFG0_00), CFG0_00_REG_CHANNEL_EN0);
278 break;
279 case 1:
280 // disable LUT for PVR eng 1
281 _REG16_CLR_PVR_IframeLUT(&(_RegCtrl0->CFG0_00), CFG0_00_REG_CHANNEL_EN1);
282 break;
283 case 2:
284 // disable LUT for PVR eng 2
285 _REG16_CLR_PVR_IframeLUT(&(_RegCtrl0->CFG0_00), CFG0_00_REG_CHANNEL_EN2);
286 break;
287 case 3:
288 // disable LUT for PVR eng 3
289 _REG16_CLR_PVR_IframeLUT(&(_RegCtrl0->CFG0_00), CFG0_00_REG_CHANNEL_EN3);
290 break;
291 default:
292 return FALSE;
293 }
294
295 _REG16_SET_PVR_IframeLUT(&_RegCtrl1[u32PVREng]->CFG1_01, 0x0FE0);
296
297 //_REG16_SET_PVR_IframeLUT(&_RegCtrl0->CFG0_00, CFG0_00_REG_SW_RSTB);
298 //_REG16_CLR_PVR_IframeLUT(&_RegCtrl0->CFG0_00, CFG0_00_REG_SW_RSTB);
299 return TRUE;
300 }
301
HAL_PVR_IframeLUT_SetVdecType(MS_U32 u32PVREng,HAL_PVR_IframeLUT_VDEC_TYPE eVdec)302 MS_BOOL HAL_PVR_IframeLUT_SetVdecType(MS_U32 u32PVREng , HAL_PVR_IframeLUT_VDEC_TYPE eVdec)
303 {
304 switch(eVdec)
305 {
306 case E_HAL_PVR_IframeLUT_MPEG:
307 _HAL_REG16_PVR_IframeLUT_W(&_RegCtrl1[u32PVREng]->CFG1_03, CFG1_03_REG_PVR_CODEC_MPGE);
308 break;
309 case E_HAL_PVR_IframeLUT_H264:
310 _HAL_REG16_PVR_IframeLUT_W(&_RegCtrl1[u32PVREng]->CFG1_03, CFG1_03_REG_PVR_CODEC_H264);
311 break;
312 case E_HAL_PVR_IframeLUT_HEVC:
313 _HAL_REG16_PVR_IframeLUT_W(&_RegCtrl1[u32PVREng]->CFG1_03, CFG1_03_REG_PVR_CODEC_HEVC);
314 break;
315 case E_HAL_PVR_IframeLUT_AVS:
316 _HAL_REG16_PVR_IframeLUT_W(&_RegCtrl1[u32PVREng]->CFG1_03, CFG1_03_REG_PVR_CODEC_AVS );
317 break;
318 default:
319 return FALSE;
320 }
321 return TRUE;
322 }
323
HAL_PVR_IframeLUT_GetWritePtr(MS_U32 u32PVREng)324 MS_U32 HAL_PVR_IframeLUT_GetWritePtr(MS_U32 u32PVREng)
325 {
326 switch(u32PVREng)
327 {
328 case 0:
329 return (PVR_IframeLUT_WRITE_POINTER_GET(REG_LUT_WP_PVR1) << MIU_BUS);
330 case 1:
331 return (PVR_IframeLUT_WRITE_POINTER_GET(REG_LUT_WP_PVR2) << MIU_BUS);
332 case 2:
333 return (PVR_IframeLUT_WRITE_POINTER_GET(REG_LUT_WP_PVR3) << MIU_BUS);
334 case 3:
335 return (PVR_IframeLUT_WRITE_POINTER_GET(REG_LUT_WP_PVR4) << MIU_BUS);
336 default:
337 return 0;
338 }
339 }
340
HAL_PVR_IframeLUT_Exit(void)341 MS_BOOL HAL_PVR_IframeLUT_Exit(void)
342 {
343 // disable TSCE path
344 _REG16_CLR_PVR_IframeLUT(&_RegCtrl0->CFG0_0B, CFG0_0B_REG_LUT2MI_EN0); // upper path
345 _REG16_CLR_PVR_IframeLUT(&_RegCtrl0->CFG0_0B, CFG0_0B_REG_LUT2MI_EN1); // lower path
346 _REG16_CLR_PVR_IframeLUT(&_RegCtrl0->CFG0_0B, CFG0_0B_REG_LUT2MI_EN2); // mid path
347
348 // disable channel
349 _REG16_CLR_PVR_IframeLUT(&(_RegCtrl0->CFG0_00), CFG0_00_REG_CHANNEL_EN0);
350 _REG16_CLR_PVR_IframeLUT(&(_RegCtrl0->CFG0_00), CFG0_00_REG_CHANNEL_EN1);
351 _REG16_CLR_PVR_IframeLUT(&(_RegCtrl0->CFG0_00), CFG0_00_REG_CHANNEL_EN2);
352 _REG16_CLR_PVR_IframeLUT(&(_RegCtrl0->CFG0_00), CFG0_00_REG_CHANNEL_EN3);
353
354 _REG16_SET_PVR_IframeLUT(&_RegCtrl0->CFG0_00, CFG0_00_REG_SW_RSTB);
355 _REG16_CLR_PVR_IframeLUT(&_RegCtrl0->CFG0_00, CFG0_00_REG_SW_RSTB);
356
357 return TRUE;
358 }
359