1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * techpoint lib
4 *
5 * Copyright (C) 2023 Rockchip Electronics Co., Ltd.
6 */
7
8 #include "techpoint_tp2855.h"
9 #include "techpoint_dev.h"
10
11 static __maybe_unused const struct regval common_setting_297M_720p_regs[] = {
12 { 0x40, 0x08 },
13 { 0x01, 0xf0 },
14 { 0x02, 0x01 },
15 { 0x08, 0x0f },
16 { 0x20, 0x44 },
17 { 0x34, 0xe4 },
18 { 0x14, 0x44 },
19 { 0x15, 0x0d },
20 { 0x25, 0x04 },
21 { 0x26, 0x03 },
22 { 0x27, 0x09 },
23 { 0x29, 0x02 },
24 { 0x33, 0x07 },
25 { 0x33, 0x00 },
26 { 0x14, 0xc4 },
27 { 0x14, 0x44 },
28 // {0x23, 0x02}, //vi test ok
29 // {0x23, 0x00},
30 };
31
32 static __maybe_unused const struct regval common_setting_594M_1080p_regs[] = {
33 { 0x40, 0x08 },
34 { 0x01, 0xf0 },
35 { 0x02, 0x01 },
36 { 0x08, 0x0f },
37 { 0x20, 0x44 },
38 { 0x34, 0xe4 },
39 { 0x15, 0x0C },
40 { 0x25, 0x08 },
41 { 0x26, 0x06 },
42 { 0x27, 0x11 },
43 { 0x29, 0x0a },
44 { 0x33, 0x07 },
45 { 0x33, 0x00 },
46 { 0x14, 0x33 },
47 { 0x14, 0xb3 },
48 { 0x14, 0x33 },
49
50 // {0x23, 0x02}, //vi test ok
51 // {0x23, 0x00},
52 };
53
54 static __maybe_unused const struct regval common_setting_594M_720p_1chn_2lane_regs[] = {
55 {0x40, 0x08},
56 {0x01, 0xf0},
57 {0x02, 0x01},
58 {0x08, 0x0f},
59 {0x20, 0x12},
60 {0x34, 0x10}, //output vin1&vin2
61 {0x15, 0x0c},
62 {0x25, 0x08},
63 {0x26, 0x06},
64 {0x27, 0x11},
65 {0x29, 0x0a},
66 {0x33, 0x07},
67 {0x33, 0x00},
68 {0x14, 0x43},
69 {0x14, 0xc3},
70 {0x14, 0x43},
71
72 {0x23, 0x02}, //vi test ok
73 {0x23, 0x00},
74 };
75
76 static __maybe_unused const struct regval common_setting_594M_4ch_2lane_720p_25fps_regs[] = {
77 { 0x40, 0x08 },
78 { 0x01, 0xf0 },
79 { 0x02, 0x01 },
80 { 0x08, 0x0f },
81 {0x20, 0x42},
82 {0x34, 0xe4}, //output vin1&vin2
83 {0x15, 0x0c},
84 {0x25, 0x08},
85 {0x26, 0x06},
86 {0x27, 0x11},
87 {0x29, 0x0a},
88 {0x33, 0x07},
89 {0x33, 0x00},
90 {0x14, 0x43},
91 {0x14, 0xc3},
92 {0x14, 0x43},
93
94 {0x23, 0x02},
95 {0x23, 0x00},
96 };
97
98 static struct techpoint_video_modes supported_modes[] = {
99 {// 4CH 2lane 720p
100 .bus_fmt = MEDIA_BUS_FMT_UYVY8_2X8,
101 .width = 1280,
102 .height = 720,
103 .max_fps = {
104 .numerator = 10000,
105 .denominator = 250000,
106 },
107 .link_freq_value = TP2855_LINK_FREQ_594M,
108 .common_reg_list = common_setting_594M_4ch_2lane_720p_25fps_regs,
109 .common_reg_size = ARRAY_SIZE(common_setting_594M_4ch_2lane_720p_25fps_regs),
110 .bpp = 8,
111 .lane = 2,
112 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
113 .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_1,
114 .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_2,
115 .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_3,
116 },
117 {//1 chn 2 lane 720p
118 .bus_fmt = MEDIA_BUS_FMT_UYVY8_2X8,
119 .width = 1280,
120 .height = 720,
121 .max_fps = {
122 .numerator = 10000,
123 .denominator = 300000,
124 },
125 .link_freq_value = TP2855_LINK_FREQ_594M,
126 .common_reg_list = common_setting_594M_720p_1chn_2lane_regs,
127 .common_reg_size = ARRAY_SIZE(common_setting_594M_720p_1chn_2lane_regs),
128 .bpp = 8,
129 .lane = 2,
130 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
131 },
132 {//4 chn 4 lane 1080p
133 .bus_fmt = MEDIA_BUS_FMT_UYVY8_2X8,
134 .width = 1920,
135 .height = 1080,
136 .max_fps = {
137 .numerator = 10000,
138 .denominator = 250000,
139 },
140 .link_freq_value = TP2855_LINK_FREQ_594M,
141 .common_reg_list = common_setting_594M_1080p_regs,
142 .common_reg_size = ARRAY_SIZE(common_setting_594M_1080p_regs),
143 .bpp = 8,
144 .lane = 4,
145 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
146 .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_1,
147 .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_2,
148 .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_3,
149 },
150 {//4 chn 4 lane 720p
151 .bus_fmt = MEDIA_BUS_FMT_UYVY8_2X8,
152 .width = 1280,
153 .height = 720,
154 .max_fps = {
155 .numerator = 10000,
156 .denominator = 250000,
157 },
158 .link_freq_value = TP2855_LINK_FREQ_297M,
159 .common_reg_list = common_setting_297M_720p_regs,
160 .common_reg_size = ARRAY_SIZE(common_setting_297M_720p_regs),
161 .bpp = 8,
162 .lane = 4,
163 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
164 .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_1,
165 .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_2,
166 .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_3,
167 },
168 {//4 chn 4 lane 576p
169 .bus_fmt = MEDIA_BUS_FMT_UYVY8_2X8,
170 .width = 720,
171 .height = 576,
172 .max_fps = {
173 .numerator = 10000,
174 .denominator = 250000,
175 },
176 .link_freq_value = TP2855_LINK_FREQ_297M,
177 .common_reg_list = common_setting_297M_720p_regs,
178 .common_reg_size = ARRAY_SIZE(common_setting_297M_720p_regs),
179 .bpp = 8,
180 .lane = 4,
181 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
182 .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_1,
183 .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_2,
184 .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_3,
185 },
186 };
187
tp2855_initialize(struct techpoint * techpoint)188 int tp2855_initialize(struct techpoint *techpoint)
189 {
190 int array_size = 0;
191 struct i2c_client *client = techpoint->client;
192 struct device *dev = &client->dev;
193
194 techpoint->video_modes_num = ARRAY_SIZE(supported_modes);
195 array_size =
196 sizeof(struct techpoint_video_modes) * techpoint->video_modes_num;
197 techpoint->video_modes = devm_kzalloc(dev, array_size, GFP_KERNEL);
198 memcpy(techpoint->video_modes, supported_modes, array_size);
199
200 techpoint->cur_video_mode = &techpoint->video_modes[0];
201
202 return 0;
203 }
204
tp2855_get_channel_input_status(struct techpoint * techpoint,u8 ch)205 int tp2855_get_channel_input_status(struct techpoint *techpoint, u8 ch)
206 {
207 struct i2c_client *client = techpoint->client;
208 u8 val = 0;
209
210 mutex_lock(&techpoint->mutex);
211 techpoint_write_reg(client, PAGE_REG, ch);
212 techpoint_read_reg(client, INPUT_STATUS_REG, &val);
213 mutex_unlock(&techpoint->mutex);
214 dev_dbg(&client->dev, "input_status ch %d : %x\n", ch, val);
215
216 return (val & INPUT_STATUS_MASK) ? 0 : 1;
217 }
218
tp2855_get_all_input_status(struct techpoint * techpoint,u8 * detect_status)219 int tp2855_get_all_input_status(struct techpoint *techpoint, u8 *detect_status)
220 {
221 struct i2c_client *client = techpoint->client;
222 u8 val = 0, i;
223
224 for (i = 0; i < PAD_MAX; i++) {
225 techpoint_write_reg(client, PAGE_REG, i);
226 techpoint_read_reg(client, INPUT_STATUS_REG, &val);
227 detect_status[i] = tp2855_get_channel_input_status(techpoint, i);
228 }
229
230 return 0;
231 }
232
tp2855_set_channel_reso(struct i2c_client * client,int ch,enum techpoint_support_reso reso)233 int tp2855_set_channel_reso(struct i2c_client *client, int ch,
234 enum techpoint_support_reso reso)
235 {
236 int val = reso;
237 u8 tmp;
238 const unsigned char SYS_MODE[5] = { 0x01, 0x02, 0x04, 0x08, 0x0f };
239
240 techpoint_write_reg(client, 0x40, ch);
241
242 switch (val) {
243 case TECHPOINT_S_RESO_1080P_30:
244 dev_info(&client->dev, "set channel %d 1080P_30, TBD\n", ch);
245 techpoint_read_reg(client, 0xf5, &tmp);
246 tmp &= ~SYS_MODE[ch];
247 techpoint_write_reg(client, 0xf5, tmp);
248 techpoint_write_reg(client, 0x02, 0x40);
249 techpoint_write_reg(client, 0x07, 0xc0);
250 techpoint_write_reg(client, 0x0b, 0xc0);
251 techpoint_write_reg(client, 0x0c, 0x03);
252 techpoint_write_reg(client, 0x0d, 0x50);
253 techpoint_write_reg(client, 0x15, 0x03);
254 techpoint_write_reg(client, 0x16, 0xd2);
255 techpoint_write_reg(client, 0x17, 0x80);
256 techpoint_write_reg(client, 0x18, 0x29);
257 techpoint_write_reg(client, 0x19, 0x38);
258 techpoint_write_reg(client, 0x1a, 0x47);
259 techpoint_write_reg(client, 0x1c, 0x08);
260 techpoint_write_reg(client, 0x1d, 0x98);
261 techpoint_write_reg(client, 0x20, 0x30);
262 techpoint_write_reg(client, 0x21, 0x84);
263 techpoint_write_reg(client, 0x22, 0x36);
264 techpoint_write_reg(client, 0x23, 0x3c);
265 techpoint_write_reg(client, 0x2b, 0x60);
266 techpoint_write_reg(client, 0x2c, 0x0a);
267 techpoint_write_reg(client, 0x2d, 0x30);
268 techpoint_write_reg(client, 0x2e, 0x70);
269 techpoint_write_reg(client, 0x30, 0x48);
270 techpoint_write_reg(client, 0x31, 0xbb);
271 techpoint_write_reg(client, 0x32, 0x2e);
272 techpoint_write_reg(client, 0x33, 0x90);
273 techpoint_write_reg(client, 0x35, 0x05);
274 techpoint_write_reg(client, 0x38, 0x00);
275 techpoint_write_reg(client, 0x39, 0x1C);
276 //def ahd config
277 techpoint_write_reg(client, 0x02, 0x44);
278 techpoint_write_reg(client, 0x0d, 0x72);
279 techpoint_write_reg(client, 0x15, 0x01);
280 techpoint_write_reg(client, 0x16, 0xf0);
281 techpoint_write_reg(client, 0x20, 0x38);
282 techpoint_write_reg(client, 0x21, 0x46);
283 techpoint_write_reg(client, 0x25, 0xfe);
284 techpoint_write_reg(client, 0x26, 0x0d);
285 techpoint_write_reg(client, 0x2c, 0x3a);
286 techpoint_write_reg(client, 0x2d, 0x54);
287 techpoint_write_reg(client, 0x2e, 0x40);
288 techpoint_write_reg(client, 0x30, 0xa5);
289 techpoint_write_reg(client, 0x31, 0x95);
290 techpoint_write_reg(client, 0x32, 0xe0);
291 techpoint_write_reg(client, 0x33, 0x60);
292 break;
293 case TECHPOINT_S_RESO_1080P_25:
294 dev_info(&client->dev, "set channel %d 1080P_25\n", ch);
295 techpoint_read_reg(client, 0xf5, &tmp);
296 tmp &= ~SYS_MODE[ch];
297 techpoint_write_reg(client, 0xf5, tmp);
298 techpoint_write_reg(client, 0x02, 0x40);
299 techpoint_write_reg(client, 0x07, 0xc0);
300 techpoint_write_reg(client, 0x0b, 0xc0);
301 techpoint_write_reg(client, 0x0c, 0x03);
302 techpoint_write_reg(client, 0x0d, 0x50);
303 techpoint_write_reg(client, 0x15, 0x03);
304 techpoint_write_reg(client, 0x16, 0xd2);
305 techpoint_write_reg(client, 0x17, 0x80);
306 techpoint_write_reg(client, 0x18, 0x29);
307 techpoint_write_reg(client, 0x19, 0x38);
308 techpoint_write_reg(client, 0x1a, 0x47);
309 techpoint_write_reg(client, 0x1c, 0x0a);
310 techpoint_write_reg(client, 0x1d, 0x50);
311 techpoint_write_reg(client, 0x20, 0x30);
312 techpoint_write_reg(client, 0x21, 0x84);
313 techpoint_write_reg(client, 0x22, 0x36);
314 techpoint_write_reg(client, 0x23, 0x3c);
315 techpoint_write_reg(client, 0x2b, 0x60);
316 techpoint_write_reg(client, 0x2c, 0x0a);
317 techpoint_write_reg(client, 0x2d, 0x30);
318 techpoint_write_reg(client, 0x2e, 0x70);
319 techpoint_write_reg(client, 0x30, 0x48);
320 techpoint_write_reg(client, 0x31, 0xbb);
321 techpoint_write_reg(client, 0x32, 0x2e);
322 techpoint_write_reg(client, 0x33, 0x90);
323 techpoint_write_reg(client, 0x35, 0x05);
324 techpoint_write_reg(client, 0x38, 0x00);
325 techpoint_write_reg(client, 0x39, 0x1C);
326 //def ahd config
327 techpoint_write_reg(client, 0x02, 0x44);
328 techpoint_write_reg(client, 0x0d, 0x73);
329 techpoint_write_reg(client, 0x15, 0x01);
330 techpoint_write_reg(client, 0x16, 0xf0);
331 techpoint_write_reg(client, 0x20, 0x3c);
332 techpoint_write_reg(client, 0x21, 0x46);
333 techpoint_write_reg(client, 0x25, 0xfe);
334 techpoint_write_reg(client, 0x26, 0x0d);
335 techpoint_write_reg(client, 0x2c, 0x3a);
336 techpoint_write_reg(client, 0x2d, 0x54);
337 techpoint_write_reg(client, 0x2e, 0x40);
338 techpoint_write_reg(client, 0x30, 0xa5);
339 techpoint_write_reg(client, 0x31, 0x86);
340 techpoint_write_reg(client, 0x32, 0xfb);
341 techpoint_write_reg(client, 0x33, 0x60);
342 break;
343 case TECHPOINT_S_RESO_720P_30:
344 dev_info(&client->dev, "set channel %d 720P_30\n", ch);
345 techpoint_read_reg(client, 0xf5, &tmp);
346 tmp |= SYS_MODE[ch];
347 techpoint_write_reg(client, 0xf5, tmp);
348 techpoint_write_reg(client, 0x02, 0x42);
349 techpoint_write_reg(client, 0x07, 0xc0);
350 techpoint_write_reg(client, 0x0b, 0xc0);
351 techpoint_write_reg(client, 0x0c, 0x13);
352 techpoint_write_reg(client, 0x0d, 0x50);
353 techpoint_write_reg(client, 0x15, 0x13);
354 techpoint_write_reg(client, 0x16, 0x15);
355 techpoint_write_reg(client, 0x17, 0x00);
356 techpoint_write_reg(client, 0x18, 0x19);
357 techpoint_write_reg(client, 0x19, 0xd0);
358 techpoint_write_reg(client, 0x1a, 0x25);
359 techpoint_write_reg(client, 0x1c, 0x06);
360 techpoint_write_reg(client, 0x1d, 0x72);
361 techpoint_write_reg(client, 0x20, 0x30);
362 techpoint_write_reg(client, 0x21, 0x84);
363 techpoint_write_reg(client, 0x22, 0x36);
364 techpoint_write_reg(client, 0x23, 0x3c);
365 techpoint_write_reg(client, 0x2b, 0x60);
366 techpoint_write_reg(client, 0x2c, 0x0a);
367 techpoint_write_reg(client, 0x2d, 0x30);
368 techpoint_write_reg(client, 0x2e, 0x70);
369 techpoint_write_reg(client, 0x30, 0x48);
370 techpoint_write_reg(client, 0x31, 0xbb);
371 techpoint_write_reg(client, 0x32, 0x2e);
372 techpoint_write_reg(client, 0x33, 0x90);
373 techpoint_write_reg(client, 0x35, 0x25);
374 techpoint_write_reg(client, 0x38, 0x00);
375 techpoint_write_reg(client, 0x39, 0x18);
376 //def ahd config
377 techpoint_write_reg(client, 0x02, 0x46);
378 techpoint_write_reg(client, 0x0d, 0x70);
379 techpoint_write_reg(client, 0x20, 0x40);
380 techpoint_write_reg(client, 0x21, 0x46);
381 techpoint_write_reg(client, 0x25, 0xfe);
382 techpoint_write_reg(client, 0x26, 0x01);
383 techpoint_write_reg(client, 0x2c, 0x3a);
384 techpoint_write_reg(client, 0x2d, 0x5a);
385 techpoint_write_reg(client, 0x2e, 0x40);
386 techpoint_write_reg(client, 0x30, 0x9d);
387 techpoint_write_reg(client, 0x31, 0xca);
388 techpoint_write_reg(client, 0x32, 0x01);
389 techpoint_write_reg(client, 0x33, 0xd0);
390 break;
391 case TECHPOINT_S_RESO_720P_25:
392 dev_info(&client->dev, "set channel %d 720P_25\n", ch);
393 techpoint_read_reg(client, 0xf5, &tmp);
394 tmp |= SYS_MODE[ch];
395 techpoint_write_reg(client, 0xf5, tmp);
396 techpoint_write_reg(client, 0x02, 0x42);
397 techpoint_write_reg(client, 0x07, 0xc0);
398 techpoint_write_reg(client, 0x0b, 0xc0);
399 techpoint_write_reg(client, 0x0c, 0x13);
400 techpoint_write_reg(client, 0x0d, 0x50);
401 techpoint_write_reg(client, 0x15, 0x13);
402 techpoint_write_reg(client, 0x16, 0x15);
403 techpoint_write_reg(client, 0x17, 0x00);
404 techpoint_write_reg(client, 0x18, 0x19);
405 techpoint_write_reg(client, 0x19, 0xd0);
406 techpoint_write_reg(client, 0x1a, 0x25);
407 techpoint_write_reg(client, 0x1c, 0x07);
408 techpoint_write_reg(client, 0x1d, 0xbc);
409 techpoint_write_reg(client, 0x20, 0x30);
410 techpoint_write_reg(client, 0x21, 0x84);
411 techpoint_write_reg(client, 0x22, 0x36);
412 techpoint_write_reg(client, 0x23, 0x3c);
413 techpoint_write_reg(client, 0x2b, 0x60);
414 techpoint_write_reg(client, 0x2c, 0x0a);
415 techpoint_write_reg(client, 0x2d, 0x30);
416 techpoint_write_reg(client, 0x2e, 0x70);
417 techpoint_write_reg(client, 0x30, 0x48);
418 techpoint_write_reg(client, 0x31, 0xbb);
419 techpoint_write_reg(client, 0x32, 0x2e);
420 techpoint_write_reg(client, 0x33, 0x90);
421 techpoint_write_reg(client, 0x35, 0x25);
422 techpoint_write_reg(client, 0x38, 0x00);
423 techpoint_write_reg(client, 0x39, 0x18);
424 //def ahd config
425 techpoint_write_reg(client, 0x02, 0x46);
426 techpoint_write_reg(client, 0x0d, 0x71);
427 techpoint_write_reg(client, 0x20, 0x40);
428 techpoint_write_reg(client, 0x21, 0x46);
429 techpoint_write_reg(client, 0x25, 0xfe);
430 techpoint_write_reg(client, 0x26, 0x01);
431 techpoint_write_reg(client, 0x2c, 0x3a);
432 techpoint_write_reg(client, 0x2d, 0x5a);
433 techpoint_write_reg(client, 0x2e, 0x40);
434 techpoint_write_reg(client, 0x30, 0x9e);
435 techpoint_write_reg(client, 0x31, 0x20);
436 techpoint_write_reg(client, 0x32, 0x10);
437 techpoint_write_reg(client, 0x33, 0x90);
438 break;
439 case TECHPOINT_S_RESO_SD:
440 dev_info(&client->dev, "set channel %d SD\n", ch);
441 techpoint_read_reg(client, 0xf5, &tmp);
442 tmp |= SYS_MODE[ch];
443 techpoint_write_reg(client, 0xf5, tmp);
444 techpoint_write_reg(client, 0x06, 0x32);
445 techpoint_write_reg(client, 0x02, 0x47);
446 techpoint_write_reg(client, 0x07, 0x80);
447 techpoint_write_reg(client, 0x0b, 0x80);
448 techpoint_write_reg(client, 0x0c, 0x13);
449 techpoint_write_reg(client, 0x0d, 0x51);
450 techpoint_write_reg(client, 0x15, 0x13);
451 techpoint_write_reg(client, 0x16, 0x18);
452 techpoint_write_reg(client, 0x17, 0xa0);
453 techpoint_write_reg(client, 0x18, 0x17);
454 techpoint_write_reg(client, 0x19, 0x20);
455 techpoint_write_reg(client, 0x1a, 0x15);
456 techpoint_write_reg(client, 0x1c, 0x06);
457 techpoint_write_reg(client, 0x1d, 0xf0);
458 techpoint_write_reg(client, 0x20, 0x48);
459 techpoint_write_reg(client, 0x21, 0x84);
460 techpoint_write_reg(client, 0x22, 0x37);
461 techpoint_write_reg(client, 0x23, 0x3f);
462 techpoint_write_reg(client, 0x2b, 0x70);
463 techpoint_write_reg(client, 0x2c, 0x2a);
464 techpoint_write_reg(client, 0x2d, 0x4b);
465 techpoint_write_reg(client, 0x2e, 0x56);
466 techpoint_write_reg(client, 0x30, 0x7a);
467 techpoint_write_reg(client, 0x31, 0x4a);
468 techpoint_write_reg(client, 0x32, 0x4d);
469 techpoint_write_reg(client, 0x33, 0xfb);
470 techpoint_write_reg(client, 0x35, 0x65);
471 techpoint_write_reg(client, 0x38, 0x00);
472 techpoint_write_reg(client, 0x39, 0x04);
473 break;
474 default:
475 dev_info(&client->dev,
476 "set channel %d is not supported, default 1080P_25\n", ch);
477 techpoint_read_reg(client, 0xf5, &tmp);
478 tmp &= ~SYS_MODE[ch];
479 techpoint_write_reg(client, 0xf5, tmp);
480 techpoint_write_reg(client, 0x02, 0x40);
481 techpoint_write_reg(client, 0x07, 0xc0);
482 techpoint_write_reg(client, 0x0b, 0xc0);
483 techpoint_write_reg(client, 0x0c, 0x03);
484 techpoint_write_reg(client, 0x0d, 0x50);
485 techpoint_write_reg(client, 0x15, 0x03);
486 techpoint_write_reg(client, 0x16, 0xd2);
487 techpoint_write_reg(client, 0x17, 0x80);
488 techpoint_write_reg(client, 0x18, 0x29);
489 techpoint_write_reg(client, 0x19, 0x38);
490 techpoint_write_reg(client, 0x1a, 0x47);
491 techpoint_write_reg(client, 0x1c, 0x0a);
492 techpoint_write_reg(client, 0x1d, 0x50);
493 techpoint_write_reg(client, 0x20, 0x30);
494 techpoint_write_reg(client, 0x21, 0x84);
495 techpoint_write_reg(client, 0x22, 0x36);
496 techpoint_write_reg(client, 0x23, 0x3c);
497 techpoint_write_reg(client, 0x2b, 0x60);
498 techpoint_write_reg(client, 0x2c, 0x0a);
499 techpoint_write_reg(client, 0x2d, 0x30);
500 techpoint_write_reg(client, 0x2e, 0x70);
501 techpoint_write_reg(client, 0x30, 0x48);
502 techpoint_write_reg(client, 0x31, 0xbb);
503 techpoint_write_reg(client, 0x32, 0x2e);
504 techpoint_write_reg(client, 0x33, 0x90);
505 techpoint_write_reg(client, 0x35, 0x05);
506 techpoint_write_reg(client, 0x38, 0x00);
507 techpoint_write_reg(client, 0x39, 0x1C);
508 //def ahd config
509 techpoint_write_reg(client, 0x02, 0x44);
510 techpoint_write_reg(client, 0x0d, 0x73);
511 techpoint_write_reg(client, 0x15, 0x01);
512 techpoint_write_reg(client, 0x16, 0xf0);
513 techpoint_write_reg(client, 0x20, 0x3c);
514 techpoint_write_reg(client, 0x21, 0x46);
515 techpoint_write_reg(client, 0x25, 0xfe);
516 techpoint_write_reg(client, 0x26, 0x0d);
517 techpoint_write_reg(client, 0x2c, 0x3a);
518 techpoint_write_reg(client, 0x2d, 0x54);
519 techpoint_write_reg(client, 0x2e, 0x40);
520 techpoint_write_reg(client, 0x30, 0xa5);
521 techpoint_write_reg(client, 0x31, 0x86);
522 techpoint_write_reg(client, 0x32, 0xfb);
523 techpoint_write_reg(client, 0x33, 0x60);
524 break;
525 }
526
527 #if TECHPOINT_TEST_PATTERN
528 techpoint_write_reg(client, 0x2a, 0x3c);
529 #endif
530
531 return 0;
532 }
533
tp2855_get_channel_reso(struct i2c_client * client,int ch)534 int tp2855_get_channel_reso(struct i2c_client *client, int ch)
535 {
536 u8 detect_fmt = 0xff;
537 u8 reso = 0xff;
538
539 techpoint_write_reg(client, 0x40, ch);
540 techpoint_read_reg(client, 0x03, &detect_fmt);
541 reso = detect_fmt & 0x7;
542
543 switch (reso) {
544 case TP2855_CVSTD_1080P_30:
545 dev_err(&client->dev, "detect channel %d 1080P_30\n", ch);
546 return TECHPOINT_S_RESO_1080P_30;
547 case TP2855_CVSTD_1080P_25:
548 dev_err(&client->dev, "detect channel %d 1080P_25\n", ch);
549 return TECHPOINT_S_RESO_1080P_25;
550 case TP2855_CVSTD_720P_30:
551 dev_err(&client->dev, "detect channel %d 720P_30\n", ch);
552 return TECHPOINT_S_RESO_720P_30;
553 case TP2855_CVSTD_720P_25:
554 dev_err(&client->dev, "detect channel %d 720P_25\n", ch);
555 return TECHPOINT_S_RESO_720P_25;
556 case TP2855_CVSTD_SD:
557 dev_err(&client->dev, "detect channel %d SD\n", ch);
558 return TECHPOINT_S_RESO_SD;
559 default:
560 dev_err(&client->dev,
561 "detect channel %d is not supported, default 1080P_25\n", ch);
562 return TECHPOINT_S_RESO_1080P_25;
563 }
564
565 return reso;
566 }
567
tp2855_set_decoder_mode(struct i2c_client * client,int ch,int status)568 int tp2855_set_decoder_mode(struct i2c_client *client, int ch, int status)
569 {
570 u8 val = 0;
571
572 techpoint_write_reg(client, PAGE_REG, ch);
573 techpoint_read_reg(client, 0x26, &val);
574 if (status)
575 val |= 0x1;
576 else
577 val &= ~0x1;
578 techpoint_write_reg(client, 0x26, val);
579
580 return 0;
581 }
582
tp2855_set_quick_stream(struct techpoint * techpoint,u32 stream)583 int tp2855_set_quick_stream(struct techpoint *techpoint, u32 stream)
584 {
585 struct i2c_client *client = techpoint->client;
586
587 mutex_lock(&techpoint->mutex);
588 if (stream) {
589 techpoint_write_reg(client, 0x40, 0x8);
590 techpoint_write_reg(client, 0x23, 0x0);
591 } else {
592 techpoint_write_reg(client, 0x40, 0x8);
593 techpoint_write_reg(client, 0x23, 0x2);
594 usleep_range(40 * 1000, 50 * 1000);
595 }
596 mutex_unlock(&techpoint->mutex);
597
598 return 0;
599 }
600