1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _RGA_DRIVER_H_ 3 #define _RGA_DRIVER_H_ 4 5 #include <linux/mutex.h> 6 #include <linux/scatterlist.h> 7 8 9 #define RGA_BLIT_SYNC 0x5017 10 #define RGA_BLIT_ASYNC 0x5018 11 #define RGA_FLUSH 0x5019 12 #define RGA_GET_RESULT 0x501a 13 #define RGA_GET_VERSION 0x501b 14 15 16 #define RGA_REG_CTRL_LEN 0x8 /* 8 */ 17 #define RGA_REG_CMD_LEN 0x20 /* 32 */ 18 #define RGA_CMD_BUF_SIZE 0x700 /* 16*28*4 */ 19 20 #define RGA_OUT_OF_RESOURCES -10 21 #define RGA_MALLOC_ERROR -11 22 23 #define RGA_BUF_GEM_TYPE_MASK 0xC0 24 25 #define rgaIS_ERROR(status) (status < 0) 26 #define rgaNO_ERROR(status) (status >= 0) 27 #define rgaIS_SUCCESS(status) (status == 0) 28 29 #define RGA_DEBUGFS 1 30 31 /* RGA process mode enum */ 32 enum 33 { 34 bitblt_mode = 0x0, 35 color_palette_mode = 0x1, 36 color_fill_mode = 0x2, 37 line_point_drawing_mode = 0x3, 38 blur_sharp_filter_mode = 0x4, 39 pre_scaling_mode = 0x5, 40 update_palette_table_mode = 0x6, 41 update_patten_buff_mode = 0x7, 42 }; 43 44 45 enum 46 { 47 rop_enable_mask = 0x2, 48 dither_enable_mask = 0x8, 49 fading_enable_mask = 0x10, 50 PD_enbale_mask = 0x20, 51 }; 52 53 enum 54 { 55 yuv2rgb_mode0 = 0x0, /* BT.601 MPEG */ 56 yuv2rgb_mode1 = 0x1, /* BT.601 JPEG */ 57 yuv2rgb_mode2 = 0x2, /* BT.709 */ 58 }; 59 60 61 /* RGA rotate mode */ 62 enum 63 { 64 rotate_mode0 = 0x0, /* no rotate */ 65 rotate_mode1 = 0x1, /* rotate */ 66 rotate_mode2 = 0x2, /* x_mirror */ 67 rotate_mode3 = 0x3, /* y_mirror */ 68 }; 69 70 enum 71 { 72 color_palette_mode0 = 0x0, /* 1K */ 73 color_palette_mode1 = 0x1, /* 2K */ 74 color_palette_mode2 = 0x2, /* 4K */ 75 color_palette_mode3 = 0x3, /* 8K */ 76 }; 77 78 79 80 /* 81 // Alpha Red Green Blue 82 { 4, 32, {{32,24, 8, 0, 16, 8, 24,16 }}, GGL_RGBA }, // RK_FORMAT_RGBA_8888 83 { 4, 24, {{ 0, 0, 8, 0, 16, 8, 24,16 }}, GGL_RGB }, // RK_FORMAT_RGBX_8888 84 { 3, 24, {{ 0, 0, 8, 0, 16, 8, 24,16 }}, GGL_RGB }, // RK_FORMAT_RGB_888 85 { 4, 32, {{32,24, 24,16, 16, 8, 8, 0 }}, GGL_BGRA }, // RK_FORMAT_BGRA_8888 86 { 2, 16, {{ 0, 0, 16,11, 11, 5, 5, 0 }}, GGL_RGB }, // RK_FORMAT_RGB_565 87 { 2, 16, {{ 1, 0, 16,11, 11, 6, 6, 1 }}, GGL_RGBA }, // RK_FORMAT_RGBA_5551 88 { 2, 16, {{ 4, 0, 16,12, 12, 8, 8, 4 }}, GGL_RGBA }, // RK_FORMAT_RGBA_4444 89 { 3, 24, {{ 0, 0, 24,16, 16, 8, 8, 0 }}, GGL_BGR }, // RK_FORMAT_BGB_888 90 91 */ 92 enum 93 { 94 RK_FORMAT_RGBA_8888 = 0x0, 95 RK_FORMAT_RGBX_8888 = 0x1, 96 RK_FORMAT_RGB_888 = 0x2, 97 RK_FORMAT_BGRA_8888 = 0x3, 98 RK_FORMAT_RGB_565 = 0x4, 99 RK_FORMAT_RGBA_5551 = 0x5, 100 RK_FORMAT_RGBA_4444 = 0x6, 101 RK_FORMAT_BGR_888 = 0x7, 102 103 RK_FORMAT_YCbCr_422_SP = 0x8, 104 RK_FORMAT_YCbCr_422_P = 0x9, 105 RK_FORMAT_YCbCr_420_SP = 0xa, 106 RK_FORMAT_YCbCr_420_P = 0xb, 107 108 RK_FORMAT_YCrCb_422_SP = 0xc, 109 RK_FORMAT_YCrCb_422_P = 0xd, 110 RK_FORMAT_YCrCb_420_SP = 0xe, 111 RK_FORMAT_YCrCb_420_P = 0xf, 112 113 RK_FORMAT_BPP1 = 0x10, 114 RK_FORMAT_BPP2 = 0x11, 115 RK_FORMAT_BPP4 = 0x12, 116 RK_FORMAT_BPP8 = 0x13, 117 RK_FORMAT_YCbCr_420_SP_10B = 0x20, 118 RK_FORMAT_YCrCb_420_SP_10B = 0x21, 119 }; 120 121 122 typedef struct rga_img_info_t 123 { 124 unsigned long yrgb_addr; /* yrgb mem addr */ 125 unsigned long uv_addr; /* cb/cr mem addr */ 126 unsigned long v_addr; /* cr mem addr */ 127 unsigned int format; //definition by RK_FORMAT 128 129 unsigned short act_w; 130 unsigned short act_h; 131 unsigned short x_offset; 132 unsigned short y_offset; 133 134 unsigned short vir_w; 135 unsigned short vir_h; 136 137 unsigned short endian_mode; //for BPP 138 unsigned short alpha_swap; 139 } 140 rga_img_info_t; 141 142 143 typedef struct mdp_img_act 144 { 145 unsigned short w; // width 146 unsigned short h; // height 147 short x_off; // x offset for the vir 148 short y_off; // y offset for the vir 149 } 150 mdp_img_act; 151 152 153 154 typedef struct RANGE 155 { 156 unsigned short min; 157 unsigned short max; 158 } 159 RANGE; 160 161 typedef struct POINT 162 { 163 unsigned short x; 164 unsigned short y; 165 } 166 POINT; 167 168 typedef struct RECT 169 { 170 unsigned short xmin; 171 unsigned short xmax; // width - 1 172 unsigned short ymin; 173 unsigned short ymax; // height - 1 174 } RECT; 175 176 typedef struct RGB 177 { 178 unsigned char r; 179 unsigned char g; 180 unsigned char b; 181 unsigned char res; 182 }RGB; 183 184 185 typedef struct MMU 186 { 187 unsigned char mmu_en; 188 unsigned long base_addr; 189 uint32_t mmu_flag; 190 } MMU; 191 192 193 194 195 typedef struct COLOR_FILL 196 { 197 short gr_x_a; 198 short gr_y_a; 199 short gr_x_b; 200 short gr_y_b; 201 short gr_x_g; 202 short gr_y_g; 203 short gr_x_r; 204 short gr_y_r; 205 206 //u8 cp_gr_saturation; 207 } 208 COLOR_FILL; 209 210 typedef struct FADING 211 { 212 uint8_t b; 213 uint8_t g; 214 uint8_t r; 215 uint8_t res; 216 } 217 FADING; 218 219 220 typedef struct line_draw_t 221 { 222 POINT start_point; /* LineDraw_start_point */ 223 POINT end_point; /* LineDraw_end_point */ 224 uint32_t color; /* LineDraw_color */ 225 uint32_t flag; /* (enum) LineDrawing mode sel */ 226 uint32_t line_width; /* range 1~16 */ 227 } 228 line_draw_t; 229 230 231 232 struct rga_req { 233 uint8_t render_mode; /* (enum) process mode sel */ 234 235 rga_img_info_t src; /* src image info */ 236 rga_img_info_t dst; /* dst image info */ 237 rga_img_info_t pat; /* patten image info */ 238 239 unsigned long rop_mask_addr; /* rop4 mask addr */ 240 unsigned long LUT_addr; /* LUT addr */ 241 242 RECT clip; /* dst clip window default value is dst_vir */ 243 /* value from [0, w-1] / [0, h-1]*/ 244 245 int32_t sina; /* dst angle default value 0 16.16 scan from table */ 246 int32_t cosa; /* dst angle default value 0 16.16 scan from table */ 247 248 uint16_t alpha_rop_flag; /* alpha rop process flag */ 249 /* ([0] = 1 alpha_rop_enable) */ 250 /* ([1] = 1 rop enable) */ 251 /* ([2] = 1 fading_enable) */ 252 /* ([3] = 1 PD_enable) */ 253 /* ([4] = 1 alpha cal_mode_sel) */ 254 /* ([5] = 1 dither_enable) */ 255 /* ([6] = 1 gradient fill mode sel) */ 256 /* ([7] = 1 AA_enable) */ 257 258 uint8_t scale_mode; /* 0 nearst / 1 bilnear / 2 bicubic */ 259 260 uint32_t color_key_max; /* color key max */ 261 uint32_t color_key_min; /* color key min */ 262 263 uint32_t fg_color; /* foreground color */ 264 uint32_t bg_color; /* background color */ 265 266 COLOR_FILL gr_color; /* color fill use gradient */ 267 268 line_draw_t line_draw_info; 269 270 FADING fading; 271 272 uint8_t PD_mode; /* porter duff alpha mode sel */ 273 274 uint8_t alpha_global_value; /* global alpha value */ 275 276 uint16_t rop_code; /* rop2/3/4 code scan from rop code table*/ 277 278 uint8_t bsfilter_flag; /* [2] 0 blur 1 sharp / [1:0] filter_type*/ 279 280 uint8_t palette_mode; /* (enum) color palatte 0/1bpp, 1/2bpp 2/4bpp 3/8bpp*/ 281 282 uint8_t yuv2rgb_mode; /* (enum) BT.601 MPEG / BT.601 JPEG / BT.709 */ 283 284 uint8_t endian_mode; /* 0/big endian 1/little endian*/ 285 286 uint8_t rotate_mode; /* (enum) rotate mode */ 287 /* 0x0, no rotate */ 288 /* 0x1, rotate */ 289 /* 0x2, x_mirror */ 290 /* 0x3, y_mirror */ 291 292 uint8_t color_fill_mode; /* 0 solid color / 1 patten color */ 293 294 MMU mmu_info; /* mmu information */ 295 296 uint8_t alpha_rop_mode; /* ([0~1] alpha mode) */ 297 /* ([2~3] rop mode) */ 298 /* ([4] zero mode en) */ 299 /* ([5] dst alpha mode) */ 300 301 uint8_t src_trans_mode; 302 303 struct sg_table *sg_src; 304 struct sg_table *sg_dst; 305 struct dma_buf_attachment *attach_src; 306 struct dma_buf_attachment *attach_dst; 307 }; 308 309 310 typedef struct TILE_INFO 311 { 312 int64_t matrix[4]; 313 314 uint16_t tile_x_num; /* x axis tile num / tile size is 8x8 pixel */ 315 uint16_t tile_y_num; /* y axis tile num */ 316 317 int16_t dst_x_tmp; /* dst pos x = (xstart - xoff) default value 0 */ 318 int16_t dst_y_tmp; /* dst pos y = (ystart - yoff) default value 0 */ 319 320 uint16_t tile_w; 321 uint16_t tile_h; 322 int16_t tile_start_x_coor; 323 int16_t tile_start_y_coor; 324 int32_t tile_xoff; 325 int32_t tile_yoff; 326 327 int32_t tile_temp_xstart; 328 int32_t tile_temp_ystart; 329 330 /* src tile incr */ 331 int32_t x_dx; 332 int32_t x_dy; 333 int32_t y_dx; 334 int32_t y_dy; 335 336 mdp_img_act dst_ctrl; 337 338 } 339 TILE_INFO; 340 341 struct rga_mmu_buf_t { 342 int32_t front; 343 int32_t back; 344 int32_t size; 345 int32_t curr; 346 unsigned int *buf; 347 unsigned int *buf_virtual; 348 349 struct page **pages; 350 }; 351 352 /** 353 * struct for process session which connect to rga 354 * 355 * @author ZhangShengqin (2012-2-15) 356 */ 357 typedef struct rga_session { 358 /* a linked list of data so we can access them for debugging */ 359 struct list_head list_session; 360 /* a linked list of register data waiting for process */ 361 struct list_head waiting; 362 /* a linked list of register data in processing */ 363 struct list_head running; 364 /* all coommand this thread done */ 365 atomic_t done; 366 wait_queue_head_t wait; 367 pid_t pid; 368 atomic_t task_running; 369 atomic_t num_done; 370 } rga_session; 371 372 struct rga_reg { 373 rga_session *session; 374 struct list_head session_link; /* link to rga service session */ 375 struct list_head status_link; /* link to register set list */ 376 uint32_t sys_reg[RGA_REG_CTRL_LEN]; 377 uint32_t cmd_reg[RGA_REG_CMD_LEN]; 378 379 uint32_t *MMU_base; 380 uint32_t MMU_len; 381 //atomic_t int_enable; 382 383 //struct rga_req req; 384 385 struct sg_table *sg_src; 386 struct sg_table *sg_dst; 387 388 struct dma_buf_attachment *attach_src; 389 struct dma_buf_attachment *attach_dst; 390 }; 391 392 393 394 typedef struct rga_service_info { 395 struct mutex lock; 396 struct timer_list timer; /* timer for power off */ 397 struct list_head waiting; /* link to link_reg in struct vpu_reg */ 398 struct list_head running; /* link to link_reg in struct vpu_reg */ 399 struct list_head done; /* link to link_reg in struct vpu_reg */ 400 struct list_head session; /* link to list_session in struct vpu_session */ 401 atomic_t total_running; 402 403 struct rga_reg *reg; 404 405 uint32_t cmd_buff[28*8];/* cmd_buff for rga */ 406 uint32_t *pre_scale_buf; 407 atomic_t int_disable; /* 0 int enable 1 int disable */ 408 atomic_t cmd_num; 409 atomic_t src_format_swt; 410 int last_prc_src_format; 411 atomic_t rga_working; 412 bool enable; 413 u32 dev_mode; 414 415 //struct rga_req req[10]; 416 417 struct mutex mutex; // mutex 418 } rga_service_info; 419 420 421 422 #if defined(CONFIG_ARCH_RK2928) || defined(CONFIG_ARCH_RK3026) || defined(CONFIG_ARCH_RK312x) 423 #define RGA_BASE 0x1010c000 424 #elif defined(CONFIG_ARCH_RK30) 425 #define RGA_BASE 0x10114000 426 #endif 427 428 //General Registers 429 #define RGA_SYS_CTRL 0x000 430 #define RGA_CMD_CTRL 0x004 431 #define RGA_CMD_ADDR 0x008 432 #define RGA_STATUS 0x00c 433 #define RGA_INT 0x010 434 #define RGA_AXI_ID 0x014 435 #define RGA_MMU_STA_CTRL 0x018 436 #define RGA_MMU_STA 0x01c 437 #define RGA_VERSION 0x028 438 439 //Command code start 440 #define RGA_MODE_CTRL 0x100 441 442 //Source Image Registers 443 #define RGA_SRC_Y_MST 0x104 444 #define RGA_SRC_CB_MST 0x108 445 #define RGA_MASK_READ_MST 0x108 //repeat 446 #define RGA_SRC_CR_MST 0x10c 447 #define RGA_SRC_VIR_INFO 0x110 448 #define RGA_SRC_ACT_INFO 0x114 449 #define RGA_SRC_X_PARA 0x118 450 #define RGA_SRC_Y_PARA 0x11c 451 #define RGA_SRC_TILE_XINFO 0x120 452 #define RGA_SRC_TILE_YINFO 0x124 453 #define RGA_SRC_TILE_H_INCR 0x128 454 #define RGA_SRC_TILE_V_INCR 0x12c 455 #define RGA_SRC_TILE_OFFSETX 0x130 456 #define RGA_SRC_TILE_OFFSETY 0x134 457 #define RGA_SRC_BG_COLOR 0x138 458 #define RGA_SRC_FG_COLOR 0x13c 459 #define RGA_LINE_DRAWING_COLOR 0x13c //repeat 460 #define RGA_SRC_TR_COLOR0 0x140 461 #define RGA_CP_GR_A 0x140 //repeat 462 #define RGA_SRC_TR_COLOR1 0x144 463 #define RGA_CP_GR_B 0x144 //repeat 464 465 #define RGA_LINE_DRAW 0x148 466 #define RGA_PAT_START_POINT 0x148 //repeat 467 468 //Destination Image Registers 469 #define RGA_DST_MST 0x14c 470 #define RGA_LUT_MST 0x14c //repeat 471 #define RGA_PAT_MST 0x14c //repeat 472 #define RGA_LINE_DRAWING_MST 0x14c //repeat 473 474 #define RGA_DST_VIR_INFO 0x150 475 476 #define RGA_DST_CTR_INFO 0x154 477 #define RGA_LINE_DRAW_XY_INFO 0x154 //repeat 478 479 //Alpha/ROP Registers 480 #define RGA_ALPHA_CON 0x158 481 482 #define RGA_PAT_CON 0x15c 483 #define RGA_DST_VIR_WIDTH_PIX 0x15c //repeat 484 485 #define RGA_ROP_CON0 0x160 486 #define RGA_CP_GR_G 0x160 //repeat 487 #define RGA_PRESCL_CB_MST 0x160 //repeat 488 489 #define RGA_ROP_CON1 0x164 490 #define RGA_CP_GR_R 0x164 //repeat 491 #define RGA_PRESCL_CR_MST 0x164 //repeat 492 493 //MMU Register 494 #define RGA_FADING_CON 0x168 495 #define RGA_MMU_CTRL 0x168 //repeat 496 497 #define RGA_MMU_TBL 0x16c //repeat 498 499 #define RGA_YUV_OUT_CFG 0x170 500 #define RGA_DST_UV_MST 0x174 501 502 503 #define RGA_BLIT_COMPLETE_EVENT 1 504 505 long rga_ioctl_kernel(struct rga_req *req); 506 507 #endif /*_RK29_IPP_DRIVER_H_*/ 508