1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Rockchip CIF Driver
4 *
5 * Copyright (C) 2018 Rockchip Electronics Co., Ltd.
6 */
7
8 #include <linux/delay.h>
9 #include <linux/pm_runtime.h>
10 #include <linux/reset.h>
11 #include <linux/iommu.h>
12 #include <media/v4l2-common.h>
13 #include <media/v4l2-event.h>
14 #include <media/v4l2-fh.h>
15 #include <media/v4l2-fwnode.h>
16 #include <media/v4l2-ioctl.h>
17 #include <media/v4l2-subdev.h>
18 #include <media/videobuf2-dma-contig.h>
19 #include <media/videobuf2-dma-sg.h>
20 #include <soc/rockchip/rockchip-system-status.h>
21 #include <dt-bindings/soc/rockchip-system-status.h>
22 #include <soc/rockchip/rockchip_iommu.h>
23
24 #include "dev.h"
25 #include "mipi-csi2.h"
26 #include "common.h"
27 #include "rkcif-externel.h"
28
29 #define CIF_REQ_BUFS_MIN 1
30 #define CIF_MIN_WIDTH 64
31 #define CIF_MIN_HEIGHT 64
32 #define CIF_MAX_WIDTH 8192
33 #define CIF_MAX_HEIGHT 8192
34
35 #define OUTPUT_STEP_WISE 8
36
37 #define RKCIF_PLANE_Y 0
38 #define RKCIF_PLANE_CBCR 1
39 #define RKCIF_MAX_PLANE 3
40
41 #define STREAM_PAD_SINK 0
42 #define STREAM_PAD_SOURCE 1
43
44 #define CIF_TIMEOUT_FRAME_NUM (2)
45
46 #define CIF_DVP_PCLK_DUAL_EDGE (V4L2_MBUS_PCLK_SAMPLE_RISING |\
47 V4L2_MBUS_PCLK_SAMPLE_FALLING)
48
49 /*
50 * Round up height when allocate memory so that Rockchip encoder can
51 * use DMA buffer directly, though this may waste a bit of memory.
52 */
53 #define MEMORY_ALIGN_ROUND_UP_HEIGHT 16
54
55 /* Get xsubs and ysubs for fourcc formats
56 *
57 * @xsubs: horizontal color samples in a 4*4 matrix, for yuv
58 * @ysubs: vertical color samples in a 4*4 matrix, for yuv
59 */
fcc_xysubs(u32 fcc,u32 * xsubs,u32 * ysubs)60 static int fcc_xysubs(u32 fcc, u32 *xsubs, u32 *ysubs)
61 {
62 switch (fcc) {
63 case V4L2_PIX_FMT_NV16:
64 case V4L2_PIX_FMT_NV61:
65 case V4L2_PIX_FMT_UYVY:
66 case V4L2_PIX_FMT_VYUY:
67 case V4L2_PIX_FMT_YUYV:
68 case V4L2_PIX_FMT_YVYU:
69 *xsubs = 2;
70 *ysubs = 1;
71 break;
72 case V4L2_PIX_FMT_NV21:
73 case V4L2_PIX_FMT_NV12:
74 *xsubs = 2;
75 *ysubs = 2;
76 break;
77 default:
78 return -EINVAL;
79 }
80
81 return 0;
82 }
83
84 static const struct cif_output_fmt out_fmts[] = {
85 {
86 .fourcc = V4L2_PIX_FMT_NV16,
87 .cplanes = 2,
88 .mplanes = 1,
89 .fmt_val = YUV_OUTPUT_422 | UV_STORAGE_ORDER_UVUV,
90 .bpp = { 8, 16 },
91 .csi_fmt_val = CSI_WRDDR_TYPE_YUV422,
92 .fmt_type = CIF_FMT_TYPE_YUV,
93 }, {
94 .fourcc = V4L2_PIX_FMT_NV61,
95 .fmt_val = YUV_OUTPUT_422 | UV_STORAGE_ORDER_VUVU,
96 .cplanes = 2,
97 .mplanes = 1,
98 .bpp = { 8, 16 },
99 .csi_fmt_val = CSI_WRDDR_TYPE_YUV422,
100 .fmt_type = CIF_FMT_TYPE_YUV,
101 }, {
102 .fourcc = V4L2_PIX_FMT_NV12,
103 .fmt_val = YUV_OUTPUT_420 | UV_STORAGE_ORDER_UVUV,
104 .cplanes = 2,
105 .mplanes = 1,
106 .bpp = { 8, 16 },
107 .csi_fmt_val = CSI_WRDDR_TYPE_YUV420SP,
108 .fmt_type = CIF_FMT_TYPE_YUV,
109 }, {
110 .fourcc = V4L2_PIX_FMT_NV21,
111 .fmt_val = YUV_OUTPUT_420 | UV_STORAGE_ORDER_VUVU,
112 .cplanes = 2,
113 .mplanes = 1,
114 .bpp = { 8, 16 },
115 .csi_fmt_val = CSI_WRDDR_TYPE_YUV420SP,
116 .fmt_type = CIF_FMT_TYPE_YUV,
117 }, {
118 .fourcc = V4L2_PIX_FMT_YUYV,
119 .cplanes = 2,
120 .mplanes = 1,
121 .bpp = { 8, 16 },
122 .csi_fmt_val = CSI_WRDDR_TYPE_RAW8,
123 .fmt_type = CIF_FMT_TYPE_YUV,
124 }, {
125 .fourcc = V4L2_PIX_FMT_YVYU,
126 .cplanes = 2,
127 .mplanes = 1,
128 .bpp = { 8, 16 },
129 .csi_fmt_val = CSI_WRDDR_TYPE_RAW8,
130 .fmt_type = CIF_FMT_TYPE_YUV,
131 }, {
132 .fourcc = V4L2_PIX_FMT_UYVY,
133 .cplanes = 2,
134 .mplanes = 1,
135 .bpp = { 8, 16 },
136 .csi_fmt_val = CSI_WRDDR_TYPE_RAW8,
137 .fmt_type = CIF_FMT_TYPE_YUV,
138 }, {
139 .fourcc = V4L2_PIX_FMT_VYUY,
140 .cplanes = 2,
141 .mplanes = 1,
142 .bpp = { 8, 16 },
143 .csi_fmt_val = CSI_WRDDR_TYPE_RAW8,
144 .fmt_type = CIF_FMT_TYPE_YUV,
145 }, {
146 .fourcc = V4L2_PIX_FMT_RGB24,
147 .cplanes = 1,
148 .mplanes = 1,
149 .bpp = { 24 },
150 .csi_fmt_val = CSI_WRDDR_TYPE_RGB888,
151 .fmt_type = CIF_FMT_TYPE_RAW,
152 }, {
153 .fourcc = V4L2_PIX_FMT_BGR24,
154 .cplanes = 1,
155 .mplanes = 1,
156 .bpp = { 24 },
157 .csi_fmt_val = CSI_WRDDR_TYPE_RGB888,
158 .fmt_type = CIF_FMT_TYPE_RAW,
159 }, {
160 .fourcc = V4L2_PIX_FMT_RGB565,
161 .cplanes = 1,
162 .mplanes = 1,
163 .bpp = { 16 },
164 .csi_fmt_val = CSI_WRDDR_TYPE_RGB565,
165 .fmt_type = CIF_FMT_TYPE_RAW,
166 }, {
167 .fourcc = V4L2_PIX_FMT_BGR666,
168 .cplanes = 1,
169 .mplanes = 1,
170 .bpp = { 18 },
171 .fmt_type = CIF_FMT_TYPE_RAW,
172 }, {
173 .fourcc = V4L2_PIX_FMT_SRGGB8,
174 .cplanes = 1,
175 .mplanes = 1,
176 .bpp = { 8 },
177 .raw_bpp = 8,
178 .csi_fmt_val = CSI_WRDDR_TYPE_RAW8,
179 .fmt_type = CIF_FMT_TYPE_RAW,
180 }, {
181 .fourcc = V4L2_PIX_FMT_SGRBG8,
182 .cplanes = 1,
183 .mplanes = 1,
184 .bpp = { 8 },
185 .raw_bpp = 8,
186 .csi_fmt_val = CSI_WRDDR_TYPE_RAW8,
187 .fmt_type = CIF_FMT_TYPE_RAW,
188 }, {
189 .fourcc = V4L2_PIX_FMT_SGBRG8,
190 .cplanes = 1,
191 .mplanes = 1,
192 .bpp = { 8 },
193 .raw_bpp = 8,
194 .csi_fmt_val = CSI_WRDDR_TYPE_RAW8,
195 .fmt_type = CIF_FMT_TYPE_RAW,
196 }, {
197 .fourcc = V4L2_PIX_FMT_SBGGR8,
198 .cplanes = 1,
199 .mplanes = 1,
200 .bpp = { 8 },
201 .raw_bpp = 8,
202 .csi_fmt_val = CSI_WRDDR_TYPE_RAW8,
203 .fmt_type = CIF_FMT_TYPE_RAW,
204 }, {
205 .fourcc = V4L2_PIX_FMT_SRGGB10,
206 .cplanes = 1,
207 .mplanes = 1,
208 .bpp = { 16 },
209 .raw_bpp = 10,
210 .csi_fmt_val = CSI_WRDDR_TYPE_RAW10,
211 .fmt_type = CIF_FMT_TYPE_RAW,
212 }, {
213 .fourcc = V4L2_PIX_FMT_SGRBG10,
214 .cplanes = 1,
215 .mplanes = 1,
216 .bpp = { 16 },
217 .raw_bpp = 10,
218 .csi_fmt_val = CSI_WRDDR_TYPE_RAW10,
219 .fmt_type = CIF_FMT_TYPE_RAW,
220 }, {
221 .fourcc = V4L2_PIX_FMT_SGBRG10,
222 .cplanes = 1,
223 .mplanes = 1,
224 .bpp = { 16 },
225 .raw_bpp = 10,
226 .csi_fmt_val = CSI_WRDDR_TYPE_RAW10,
227 .fmt_type = CIF_FMT_TYPE_RAW,
228 }, {
229 .fourcc = V4L2_PIX_FMT_SBGGR10,
230 .cplanes = 1,
231 .mplanes = 1,
232 .bpp = { 16 },
233 .raw_bpp = 10,
234 .csi_fmt_val = CSI_WRDDR_TYPE_RAW10,
235 .fmt_type = CIF_FMT_TYPE_RAW,
236 }, {
237 .fourcc = V4L2_PIX_FMT_SRGGB12,
238 .cplanes = 1,
239 .mplanes = 1,
240 .bpp = { 16 },
241 .raw_bpp = 12,
242 .csi_fmt_val = CSI_WRDDR_TYPE_RAW12,
243 .fmt_type = CIF_FMT_TYPE_RAW,
244 }, {
245 .fourcc = V4L2_PIX_FMT_SGRBG12,
246 .cplanes = 1,
247 .mplanes = 1,
248 .bpp = { 16 },
249 .raw_bpp = 12,
250 .csi_fmt_val = CSI_WRDDR_TYPE_RAW12,
251 .fmt_type = CIF_FMT_TYPE_RAW,
252 }, {
253 .fourcc = V4L2_PIX_FMT_SGBRG12,
254 .cplanes = 1,
255 .mplanes = 1,
256 .bpp = { 16 },
257 .raw_bpp = 12,
258 .csi_fmt_val = CSI_WRDDR_TYPE_RAW12,
259 .fmt_type = CIF_FMT_TYPE_RAW,
260 }, {
261 .fourcc = V4L2_PIX_FMT_SBGGR12,
262 .cplanes = 1,
263 .mplanes = 1,
264 .bpp = { 16 },
265 .raw_bpp = 12,
266 .csi_fmt_val = CSI_WRDDR_TYPE_RAW12,
267 .fmt_type = CIF_FMT_TYPE_RAW,
268 }, {
269 .fourcc = V4L2_PIX_FMT_SBGGR16,
270 .cplanes = 1,
271 .mplanes = 1,
272 .bpp = { 16 },
273 .raw_bpp = 16,
274 .csi_fmt_val = CSI_WRDDR_TYPE_RAW8,
275 .fmt_type = CIF_FMT_TYPE_RAW,
276 }, {
277 .fourcc = V4L2_PIX_FMT_SGBRG16,
278 .cplanes = 1,
279 .mplanes = 1,
280 .bpp = { 16 },
281 .raw_bpp = 16,
282 .csi_fmt_val = CSI_WRDDR_TYPE_RAW8,
283 .fmt_type = CIF_FMT_TYPE_RAW,
284 }, {
285 .fourcc = V4L2_PIX_FMT_SGRBG16,
286 .cplanes = 1,
287 .mplanes = 1,
288 .bpp = { 16 },
289 .raw_bpp = 16,
290 .csi_fmt_val = CSI_WRDDR_TYPE_RAW8,
291 .fmt_type = CIF_FMT_TYPE_RAW,
292 }, {
293 .fourcc = V4L2_PIX_FMT_SRGGB16,
294 .cplanes = 1,
295 .mplanes = 1,
296 .bpp = { 16 },
297 .raw_bpp = 16,
298 .csi_fmt_val = CSI_WRDDR_TYPE_RAW8,
299 .fmt_type = CIF_FMT_TYPE_RAW,
300 }, {
301 .fourcc = V4L2_PIX_FMT_Y16,
302 .cplanes = 1,
303 .mplanes = 1,
304 .bpp = { 16 },
305 .raw_bpp = 16,
306 .csi_fmt_val = CSI_WRDDR_TYPE_RAW8,
307 .fmt_type = CIF_FMT_TYPE_RAW,
308 }, {
309 .fourcc = V4L2_PIX_FMT_GREY,
310 .cplanes = 1,
311 .mplanes = 1,
312 .bpp = {8},
313 .raw_bpp = 8,
314 .csi_fmt_val = CSI_WRDDR_TYPE_RAW8,
315 .fmt_type = CIF_FMT_TYPE_RAW,
316 }, {
317 .fourcc = V4l2_PIX_FMT_EBD8,
318 .cplanes = 1,
319 .mplanes = 1,
320 .bpp = {8},
321 .raw_bpp = 8,
322 .csi_fmt_val = CSI_WRDDR_TYPE_RAW8,
323 .fmt_type = CIF_FMT_TYPE_RAW,
324 }, {
325 .fourcc = V4l2_PIX_FMT_SPD16,
326 .cplanes = 1,
327 .mplanes = 1,
328 .bpp = {16},
329 .raw_bpp = 16,
330 .csi_fmt_val = CSI_WRDDR_TYPE_RAW8,
331 .fmt_type = CIF_FMT_TYPE_RAW,
332 }, {
333 .fourcc = V4L2_PIX_FMT_Y12,
334 .cplanes = 1,
335 .mplanes = 1,
336 .bpp = { 16 },
337 .raw_bpp = 12,
338 .csi_fmt_val = CSI_WRDDR_TYPE_RAW12,
339 .fmt_type = CIF_FMT_TYPE_RAW,
340 }, {
341 .fourcc = V4L2_PIX_FMT_Y10,
342 .cplanes = 1,
343 .mplanes = 1,
344 .bpp = { 16 },
345 .raw_bpp = 10,
346 .csi_fmt_val = CSI_WRDDR_TYPE_RAW10,
347 .fmt_type = CIF_FMT_TYPE_RAW,
348 }, {
349 .fourcc = V4L2_PIX_FMT_SRGGB16,
350 .cplanes = 1,
351 .mplanes = 1,
352 .bpp = { 16 },
353 .raw_bpp = 16,
354 .fmt_type = CIF_FMT_TYPE_RAW,
355 }, {
356 .fourcc = V4L2_PIX_FMT_SGRBG16,
357 .cplanes = 1,
358 .mplanes = 1,
359 .bpp = { 16 },
360 .raw_bpp = 16,
361 .fmt_type = CIF_FMT_TYPE_RAW,
362 }, {
363 .fourcc = V4L2_PIX_FMT_SGBRG16,
364 .cplanes = 1,
365 .mplanes = 1,
366 .bpp = { 16 },
367 .raw_bpp = 16,
368 .fmt_type = CIF_FMT_TYPE_RAW,
369 }, {
370 .fourcc = V4L2_PIX_FMT_SBGGR16,
371 .cplanes = 1,
372 .mplanes = 1,
373 .bpp = { 16 },
374 .raw_bpp = 16,
375 .fmt_type = CIF_FMT_TYPE_RAW,
376 }
377 /* TODO: We can support NV12M/NV21M/NV16M/NV61M too */
378 };
379
380 static const struct cif_input_fmt in_fmts[] = {
381 {
382 .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8,
383 .dvp_fmt_val = YUV_INPUT_422 | YUV_INPUT_ORDER_YUYV,
384 .csi_fmt_val = CSI_WRDDR_TYPE_YUV422,
385 .csi_yuv_order = CSI_YUV_INPUT_ORDER_YUYV,
386 .fmt_type = CIF_FMT_TYPE_YUV,
387 .field = V4L2_FIELD_NONE,
388 }, {
389 .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8,
390 .dvp_fmt_val = YUV_INPUT_422 | YUV_INPUT_ORDER_YUYV,
391 .csi_fmt_val = CSI_WRDDR_TYPE_YUV422,
392 .csi_yuv_order = CSI_YUV_INPUT_ORDER_YUYV,
393 .fmt_type = CIF_FMT_TYPE_YUV,
394 .field = V4L2_FIELD_INTERLACED,
395 }, {
396 .mbus_code = MEDIA_BUS_FMT_YVYU8_2X8,
397 .dvp_fmt_val = YUV_INPUT_422 | YUV_INPUT_ORDER_YVYU,
398 .csi_fmt_val = CSI_WRDDR_TYPE_YUV422,
399 .csi_yuv_order = CSI_YUV_INPUT_ORDER_YVYU,
400 .fmt_type = CIF_FMT_TYPE_YUV,
401 .field = V4L2_FIELD_NONE,
402 }, {
403 .mbus_code = MEDIA_BUS_FMT_YVYU8_2X8,
404 .dvp_fmt_val = YUV_INPUT_422 | YUV_INPUT_ORDER_YVYU,
405 .csi_fmt_val = CSI_WRDDR_TYPE_YUV422,
406 .csi_yuv_order = CSI_YUV_INPUT_ORDER_YVYU,
407 .fmt_type = CIF_FMT_TYPE_YUV,
408 .field = V4L2_FIELD_INTERLACED,
409 }, {
410 .mbus_code = MEDIA_BUS_FMT_UYVY8_2X8,
411 .dvp_fmt_val = YUV_INPUT_422 | YUV_INPUT_ORDER_UYVY,
412 .csi_fmt_val = CSI_WRDDR_TYPE_YUV422,
413 .csi_yuv_order = CSI_YUV_INPUT_ORDER_UYVY,
414 .fmt_type = CIF_FMT_TYPE_YUV,
415 .field = V4L2_FIELD_NONE,
416 }, {
417 .mbus_code = MEDIA_BUS_FMT_UYVY8_2X8,
418 .dvp_fmt_val = YUV_INPUT_422 | YUV_INPUT_ORDER_UYVY,
419 .csi_fmt_val = CSI_WRDDR_TYPE_YUV422,
420 .csi_yuv_order = CSI_YUV_INPUT_ORDER_UYVY,
421 .fmt_type = CIF_FMT_TYPE_YUV,
422 .field = V4L2_FIELD_INTERLACED,
423 }, {
424 .mbus_code = MEDIA_BUS_FMT_VYUY8_2X8,
425 .dvp_fmt_val = YUV_INPUT_422 | YUV_INPUT_ORDER_VYUY,
426 .csi_fmt_val = CSI_WRDDR_TYPE_YUV422,
427 .csi_yuv_order = CSI_YUV_INPUT_ORDER_VYUY,
428 .fmt_type = CIF_FMT_TYPE_YUV,
429 .field = V4L2_FIELD_NONE,
430 }, {
431 .mbus_code = MEDIA_BUS_FMT_VYUY8_2X8,
432 .dvp_fmt_val = YUV_INPUT_422 | YUV_INPUT_ORDER_VYUY,
433 .csi_fmt_val = CSI_WRDDR_TYPE_YUV422,
434 .csi_yuv_order = CSI_YUV_INPUT_ORDER_VYUY,
435 .fmt_type = CIF_FMT_TYPE_YUV,
436 .field = V4L2_FIELD_INTERLACED,
437 }, {
438 .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8,
439 .dvp_fmt_val = INPUT_MODE_RAW | RAW_DATA_WIDTH_8,
440 .csi_fmt_val = CSI_WRDDR_TYPE_RAW8,
441 .fmt_type = CIF_FMT_TYPE_RAW,
442 .field = V4L2_FIELD_NONE,
443 }, {
444 .mbus_code = MEDIA_BUS_FMT_SGBRG8_1X8,
445 .dvp_fmt_val = INPUT_MODE_RAW | RAW_DATA_WIDTH_8,
446 .csi_fmt_val = CSI_WRDDR_TYPE_RAW8,
447 .fmt_type = CIF_FMT_TYPE_RAW,
448 .field = V4L2_FIELD_NONE,
449 }, {
450 .mbus_code = MEDIA_BUS_FMT_SGRBG8_1X8,
451 .dvp_fmt_val = INPUT_MODE_RAW | RAW_DATA_WIDTH_8,
452 .csi_fmt_val = CSI_WRDDR_TYPE_RAW8,
453 .fmt_type = CIF_FMT_TYPE_RAW,
454 .field = V4L2_FIELD_NONE,
455 }, {
456 .mbus_code = MEDIA_BUS_FMT_SRGGB8_1X8,
457 .dvp_fmt_val = INPUT_MODE_RAW | RAW_DATA_WIDTH_8,
458 .csi_fmt_val = CSI_WRDDR_TYPE_RAW8,
459 .fmt_type = CIF_FMT_TYPE_RAW,
460 .field = V4L2_FIELD_NONE,
461 }, {
462 .mbus_code = MEDIA_BUS_FMT_SBGGR10_1X10,
463 .dvp_fmt_val = INPUT_MODE_RAW | RAW_DATA_WIDTH_10,
464 .csi_fmt_val = CSI_WRDDR_TYPE_RAW10,
465 .fmt_type = CIF_FMT_TYPE_RAW,
466 .field = V4L2_FIELD_NONE,
467 }, {
468 .mbus_code = MEDIA_BUS_FMT_SGBRG10_1X10,
469 .dvp_fmt_val = INPUT_MODE_RAW | RAW_DATA_WIDTH_10,
470 .csi_fmt_val = CSI_WRDDR_TYPE_RAW10,
471 .fmt_type = CIF_FMT_TYPE_RAW,
472 .field = V4L2_FIELD_NONE,
473 }, {
474 .mbus_code = MEDIA_BUS_FMT_SGRBG10_1X10,
475 .dvp_fmt_val = INPUT_MODE_RAW | RAW_DATA_WIDTH_10,
476 .csi_fmt_val = CSI_WRDDR_TYPE_RAW10,
477 .fmt_type = CIF_FMT_TYPE_RAW,
478 .field = V4L2_FIELD_NONE,
479 }, {
480 .mbus_code = MEDIA_BUS_FMT_SRGGB10_1X10,
481 .dvp_fmt_val = INPUT_MODE_RAW | RAW_DATA_WIDTH_10,
482 .csi_fmt_val = CSI_WRDDR_TYPE_RAW10,
483 .fmt_type = CIF_FMT_TYPE_RAW,
484 .field = V4L2_FIELD_NONE,
485 }, {
486 .mbus_code = MEDIA_BUS_FMT_SBGGR12_1X12,
487 .dvp_fmt_val = INPUT_MODE_RAW | RAW_DATA_WIDTH_12,
488 .csi_fmt_val = CSI_WRDDR_TYPE_RAW12,
489 .fmt_type = CIF_FMT_TYPE_RAW,
490 .field = V4L2_FIELD_NONE,
491 }, {
492 .mbus_code = MEDIA_BUS_FMT_SGBRG12_1X12,
493 .dvp_fmt_val = INPUT_MODE_RAW | RAW_DATA_WIDTH_12,
494 .csi_fmt_val = CSI_WRDDR_TYPE_RAW12,
495 .fmt_type = CIF_FMT_TYPE_RAW,
496 .field = V4L2_FIELD_NONE,
497 }, {
498 .mbus_code = MEDIA_BUS_FMT_SGRBG12_1X12,
499 .dvp_fmt_val = INPUT_MODE_RAW | RAW_DATA_WIDTH_12,
500 .csi_fmt_val = CSI_WRDDR_TYPE_RAW12,
501 .fmt_type = CIF_FMT_TYPE_RAW,
502 .field = V4L2_FIELD_NONE,
503 }, {
504 .mbus_code = MEDIA_BUS_FMT_SRGGB12_1X12,
505 .dvp_fmt_val = INPUT_MODE_RAW | RAW_DATA_WIDTH_12,
506 .csi_fmt_val = CSI_WRDDR_TYPE_RAW12,
507 .fmt_type = CIF_FMT_TYPE_RAW,
508 .field = V4L2_FIELD_NONE,
509 }, {
510 .mbus_code = MEDIA_BUS_FMT_RGB888_1X24,
511 .csi_fmt_val = CSI_WRDDR_TYPE_RGB888,
512 .field = V4L2_FIELD_NONE,
513 }, {
514 .mbus_code = MEDIA_BUS_FMT_BGR888_1X24,
515 .csi_fmt_val = CSI_WRDDR_TYPE_RGB888,
516 .field = V4L2_FIELD_NONE,
517 }, {
518 .mbus_code = MEDIA_BUS_FMT_RGB565_1X16,
519 .csi_fmt_val = CSI_WRDDR_TYPE_RGB565,
520 .field = V4L2_FIELD_NONE,
521 }, {
522 .mbus_code = MEDIA_BUS_FMT_Y8_1X8,
523 .dvp_fmt_val = INPUT_MODE_RAW | RAW_DATA_WIDTH_8,
524 .csi_fmt_val = CSI_WRDDR_TYPE_RAW8,
525 .fmt_type = CIF_FMT_TYPE_RAW,
526 .field = V4L2_FIELD_NONE,
527 }, {
528 .mbus_code = MEDIA_BUS_FMT_Y10_1X10,
529 .dvp_fmt_val = INPUT_MODE_RAW | RAW_DATA_WIDTH_10,
530 .csi_fmt_val = CSI_WRDDR_TYPE_RAW10,
531 .fmt_type = CIF_FMT_TYPE_RAW,
532 .field = V4L2_FIELD_NONE,
533 }, {
534 .mbus_code = MEDIA_BUS_FMT_Y12_1X12,
535 .dvp_fmt_val = INPUT_MODE_RAW | RAW_DATA_WIDTH_12,
536 .csi_fmt_val = CSI_WRDDR_TYPE_RAW12,
537 .fmt_type = CIF_FMT_TYPE_RAW,
538 .field = V4L2_FIELD_NONE,
539 }, {
540 .mbus_code = MEDIA_BUS_FMT_EBD_1X8,
541 .dvp_fmt_val = INPUT_MODE_RAW | RAW_DATA_WIDTH_8,
542 .csi_fmt_val = CSI_WRDDR_TYPE_RAW8,
543 .fmt_type = CIF_FMT_TYPE_RAW,
544 .field = V4L2_FIELD_NONE,
545 }, {
546 .mbus_code = MEDIA_BUS_FMT_SPD_2X8,
547 .dvp_fmt_val = INPUT_MODE_RAW | RAW_DATA_WIDTH_12,
548 .csi_fmt_val = CSI_WRDDR_TYPE_RAW12,
549 .fmt_type = CIF_FMT_TYPE_RAW,
550 .field = V4L2_FIELD_NONE,
551 }
552 };
553
rkcif_output_fmt_check(struct rkcif_stream * stream,const struct cif_output_fmt * output_fmt)554 static int rkcif_output_fmt_check(struct rkcif_stream *stream,
555 const struct cif_output_fmt *output_fmt)
556 {
557 const struct cif_input_fmt *input_fmt = stream->cif_fmt_in;
558 struct csi_channel_info *channel = &stream->cifdev->channels[stream->id];
559 int ret = -EINVAL;
560
561 switch (input_fmt->mbus_code) {
562 case MEDIA_BUS_FMT_YUYV8_2X8:
563 case MEDIA_BUS_FMT_YVYU8_2X8:
564 case MEDIA_BUS_FMT_UYVY8_2X8:
565 case MEDIA_BUS_FMT_VYUY8_2X8:
566 if (output_fmt->fourcc == V4L2_PIX_FMT_NV16 ||
567 output_fmt->fourcc == V4L2_PIX_FMT_NV61 ||
568 output_fmt->fourcc == V4L2_PIX_FMT_NV12 ||
569 output_fmt->fourcc == V4L2_PIX_FMT_NV21 ||
570 output_fmt->fourcc == V4L2_PIX_FMT_YUYV ||
571 output_fmt->fourcc == V4L2_PIX_FMT_YVYU ||
572 output_fmt->fourcc == V4L2_PIX_FMT_UYVY ||
573 output_fmt->fourcc == V4L2_PIX_FMT_VYUY)
574 ret = 0;
575 break;
576 case MEDIA_BUS_FMT_SBGGR8_1X8:
577 case MEDIA_BUS_FMT_SGBRG8_1X8:
578 case MEDIA_BUS_FMT_SGRBG8_1X8:
579 case MEDIA_BUS_FMT_SRGGB8_1X8:
580 case MEDIA_BUS_FMT_Y8_1X8:
581 if (output_fmt->fourcc == V4L2_PIX_FMT_SRGGB8 ||
582 output_fmt->fourcc == V4L2_PIX_FMT_SGRBG8 ||
583 output_fmt->fourcc == V4L2_PIX_FMT_SGBRG8 ||
584 output_fmt->fourcc == V4L2_PIX_FMT_SBGGR8 ||
585 output_fmt->fourcc == V4L2_PIX_FMT_GREY)
586 ret = 0;
587 break;
588 case MEDIA_BUS_FMT_SBGGR10_1X10:
589 case MEDIA_BUS_FMT_SGBRG10_1X10:
590 case MEDIA_BUS_FMT_SGRBG10_1X10:
591 case MEDIA_BUS_FMT_SRGGB10_1X10:
592 case MEDIA_BUS_FMT_Y10_1X10:
593 if (output_fmt->fourcc == V4L2_PIX_FMT_SRGGB10 ||
594 output_fmt->fourcc == V4L2_PIX_FMT_SGRBG10 ||
595 output_fmt->fourcc == V4L2_PIX_FMT_SGBRG10 ||
596 output_fmt->fourcc == V4L2_PIX_FMT_SBGGR10 ||
597 output_fmt->fourcc == V4L2_PIX_FMT_Y10)
598 ret = 0;
599 break;
600 case MEDIA_BUS_FMT_SBGGR12_1X12:
601 case MEDIA_BUS_FMT_SGBRG12_1X12:
602 case MEDIA_BUS_FMT_SGRBG12_1X12:
603 case MEDIA_BUS_FMT_SRGGB12_1X12:
604 case MEDIA_BUS_FMT_Y12_1X12:
605 if (output_fmt->fourcc == V4L2_PIX_FMT_SRGGB12 ||
606 output_fmt->fourcc == V4L2_PIX_FMT_SGRBG12 ||
607 output_fmt->fourcc == V4L2_PIX_FMT_SGBRG12 ||
608 output_fmt->fourcc == V4L2_PIX_FMT_SBGGR12 ||
609 output_fmt->fourcc == V4L2_PIX_FMT_Y12)
610 ret = 0;
611 break;
612 case MEDIA_BUS_FMT_RGB888_1X24:
613 case MEDIA_BUS_FMT_BGR888_1X24:
614 if (output_fmt->fourcc == V4L2_PIX_FMT_RGB24 ||
615 output_fmt->fourcc == V4L2_PIX_FMT_BGR24)
616 ret = 0;
617 break;
618 case MEDIA_BUS_FMT_RGB565_1X16:
619 if (output_fmt->fourcc == V4L2_PIX_FMT_RGB565)
620 ret = 0;
621 break;
622 case MEDIA_BUS_FMT_EBD_1X8:
623 if (output_fmt->fourcc == V4l2_PIX_FMT_EBD8 ||
624 (channel->data_bit == 8 &&
625 (output_fmt->fourcc == V4L2_PIX_FMT_SRGGB8 ||
626 output_fmt->fourcc == V4L2_PIX_FMT_SGRBG8 ||
627 output_fmt->fourcc == V4L2_PIX_FMT_SGBRG8 ||
628 output_fmt->fourcc == V4L2_PIX_FMT_SBGGR8)) ||
629 (channel->data_bit == 10 &&
630 (output_fmt->fourcc == V4L2_PIX_FMT_SRGGB10 ||
631 output_fmt->fourcc == V4L2_PIX_FMT_SGRBG10 ||
632 output_fmt->fourcc == V4L2_PIX_FMT_SGBRG10 ||
633 output_fmt->fourcc == V4L2_PIX_FMT_SBGGR10)) ||
634 (channel->data_bit == 12 &&
635 (output_fmt->fourcc == V4L2_PIX_FMT_SRGGB12 ||
636 output_fmt->fourcc == V4L2_PIX_FMT_SGRBG12 ||
637 output_fmt->fourcc == V4L2_PIX_FMT_SGBRG12 ||
638 output_fmt->fourcc == V4L2_PIX_FMT_SBGGR12)) ||
639 (channel->data_bit == 16 &&
640 (output_fmt->fourcc == V4L2_PIX_FMT_SRGGB16 ||
641 output_fmt->fourcc == V4L2_PIX_FMT_SGRBG16 ||
642 output_fmt->fourcc == V4L2_PIX_FMT_SGBRG16 ||
643 output_fmt->fourcc == V4L2_PIX_FMT_SBGGR16)))
644 ret = 0;
645 break;
646 case MEDIA_BUS_FMT_SPD_2X8:
647 if (output_fmt->fourcc == V4l2_PIX_FMT_SPD16 ||
648 (channel->data_bit == 8 &&
649 (output_fmt->fourcc == V4L2_PIX_FMT_SRGGB8 ||
650 output_fmt->fourcc == V4L2_PIX_FMT_SGRBG8 ||
651 output_fmt->fourcc == V4L2_PIX_FMT_SGBRG8 ||
652 output_fmt->fourcc == V4L2_PIX_FMT_SBGGR8)) ||
653 (channel->data_bit == 10 &&
654 (output_fmt->fourcc == V4L2_PIX_FMT_SRGGB10 ||
655 output_fmt->fourcc == V4L2_PIX_FMT_SGRBG10 ||
656 output_fmt->fourcc == V4L2_PIX_FMT_SGBRG10 ||
657 output_fmt->fourcc == V4L2_PIX_FMT_SBGGR10)) ||
658 (channel->data_bit == 12 &&
659 (output_fmt->fourcc == V4L2_PIX_FMT_SRGGB12 ||
660 output_fmt->fourcc == V4L2_PIX_FMT_SGRBG12 ||
661 output_fmt->fourcc == V4L2_PIX_FMT_SGBRG12 ||
662 output_fmt->fourcc == V4L2_PIX_FMT_SBGGR12)) ||
663 (channel->data_bit == 16 &&
664 (output_fmt->fourcc == V4L2_PIX_FMT_SRGGB16 ||
665 output_fmt->fourcc == V4L2_PIX_FMT_SGRBG16 ||
666 output_fmt->fourcc == V4L2_PIX_FMT_SGBRG16 ||
667 output_fmt->fourcc == V4L2_PIX_FMT_SBGGR16)))
668 ret = 0;
669 break;
670 default:
671 break;
672 }
673 if (ret)
674 v4l2_err(&stream->cifdev->v4l2_dev,
675 "input mbus_code 0x%x, can't transform to %c%c%c%c\n",
676 input_fmt->mbus_code,
677 output_fmt->fourcc & 0xff,
678 (output_fmt->fourcc >> 8) & 0xff,
679 (output_fmt->fourcc >> 16) & 0xff,
680 (output_fmt->fourcc >> 24) & 0xff);
681 return ret;
682 }
683
684 static int rkcif_stop_dma_capture(struct rkcif_stream *stream);
685
to_cif_rx_buf(struct rkisp_rx_buf * dbufs)686 struct rkcif_rx_buffer *to_cif_rx_buf(struct rkisp_rx_buf *dbufs)
687 {
688 return container_of(dbufs, struct rkcif_rx_buffer, dbufs);
689 }
690
get_remote_sensor(struct rkcif_stream * stream,u16 * index)691 static struct v4l2_subdev *get_remote_sensor(struct rkcif_stream *stream, u16 *index)
692 {
693 struct media_pad *local, *remote;
694 struct media_entity *sensor_me;
695 struct v4l2_subdev *sub = NULL;
696
697 local = &stream->vnode.vdev.entity.pads[0];
698 if (!local) {
699 v4l2_err(&stream->cifdev->v4l2_dev,
700 "%s: video pad[0] is null\n", __func__);
701 return NULL;
702 }
703
704 remote = media_entity_remote_pad(local);
705 if (!remote) {
706 v4l2_err(&stream->cifdev->v4l2_dev,
707 "%s: remote pad is null\n", __func__);
708 return NULL;
709 }
710
711 if (index)
712 *index = remote->index;
713
714 sensor_me = remote->entity;
715
716 sub = media_entity_to_v4l2_subdev(sensor_me);
717
718 return sub;
719
720 }
721
get_remote_terminal_sensor(struct rkcif_stream * stream,struct v4l2_subdev ** sensor_sd)722 static void get_remote_terminal_sensor(struct rkcif_stream *stream,
723 struct v4l2_subdev **sensor_sd)
724 {
725 struct media_graph graph;
726 struct media_entity *entity = &stream->vnode.vdev.entity;
727 struct media_device *mdev = entity->graph_obj.mdev;
728 int ret;
729
730 /* Walk the graph to locate sensor nodes. */
731 mutex_lock(&mdev->graph_mutex);
732 ret = media_graph_walk_init(&graph, mdev);
733 if (ret) {
734 mutex_unlock(&mdev->graph_mutex);
735 *sensor_sd = NULL;
736 return;
737 }
738
739 media_graph_walk_start(&graph, entity);
740 while ((entity = media_graph_walk_next(&graph))) {
741 if (entity->function == MEDIA_ENT_F_CAM_SENSOR)
742 break;
743 }
744 mutex_unlock(&mdev->graph_mutex);
745 media_graph_walk_cleanup(&graph);
746
747 if (entity)
748 *sensor_sd = media_entity_to_v4l2_subdev(entity);
749 else
750 *sensor_sd = NULL;
751 }
752
sd_to_sensor(struct rkcif_device * dev,struct v4l2_subdev * sd)753 static struct rkcif_sensor_info *sd_to_sensor(struct rkcif_device *dev,
754 struct v4l2_subdev *sd)
755 {
756 u32 i;
757
758 for (i = 0; i < dev->num_sensors; ++i)
759 if (dev->sensors[i].sd == sd)
760 return &dev->sensors[i];
761
762 if (i == dev->num_sensors) {
763 for (i = 0; i < dev->num_sensors; ++i) {
764 if (dev->sensors[i].mbus.type == V4L2_MBUS_CCP2)
765 return &dev->lvds_subdev.sensor_self;
766 }
767 }
768
769 return NULL;
770 }
771
get_data_type(u32 pixelformat,u8 cmd_mode_en,u8 dsi_input)772 static unsigned char get_data_type(u32 pixelformat, u8 cmd_mode_en, u8 dsi_input)
773 {
774 switch (pixelformat) {
775 /* csi raw8 */
776 case MEDIA_BUS_FMT_SBGGR8_1X8:
777 case MEDIA_BUS_FMT_SGBRG8_1X8:
778 case MEDIA_BUS_FMT_SGRBG8_1X8:
779 case MEDIA_BUS_FMT_SRGGB8_1X8:
780 case MEDIA_BUS_FMT_Y8_1X8:
781 return 0x2a;
782 /* csi raw10 */
783 case MEDIA_BUS_FMT_SBGGR10_1X10:
784 case MEDIA_BUS_FMT_SGBRG10_1X10:
785 case MEDIA_BUS_FMT_SGRBG10_1X10:
786 case MEDIA_BUS_FMT_SRGGB10_1X10:
787 case MEDIA_BUS_FMT_Y10_1X10:
788 return 0x2b;
789 /* csi raw12 */
790 case MEDIA_BUS_FMT_SBGGR12_1X12:
791 case MEDIA_BUS_FMT_SGBRG12_1X12:
792 case MEDIA_BUS_FMT_SGRBG12_1X12:
793 case MEDIA_BUS_FMT_SRGGB12_1X12:
794 case MEDIA_BUS_FMT_Y12_1X12:
795 return 0x2c;
796 /* csi uyvy 422 */
797 case MEDIA_BUS_FMT_UYVY8_2X8:
798 case MEDIA_BUS_FMT_VYUY8_2X8:
799 case MEDIA_BUS_FMT_YUYV8_2X8:
800 case MEDIA_BUS_FMT_YVYU8_2X8:
801 return 0x1e;
802 case MEDIA_BUS_FMT_RGB888_1X24:
803 case MEDIA_BUS_FMT_BGR888_1X24:
804 if (dsi_input) {
805 if (cmd_mode_en) /* dsi command mode*/
806 return 0x39;
807 else /* dsi video mode */
808 return 0x3e;
809 } else {
810 return 0x24;
811 }
812 case MEDIA_BUS_FMT_RGB565_1X16:
813 if (dsi_input) {
814 if (cmd_mode_en) /* dsi command mode*/
815 return 0x39;
816 else /* dsi video mode */
817 return 0x0e;
818 } else {
819 return 0x22;
820 }
821 case MEDIA_BUS_FMT_EBD_1X8:
822 return 0x12;
823 case MEDIA_BUS_FMT_SPD_2X8:
824 return 0x2f;
825
826 default:
827 return 0x2b;
828 }
829 }
830
get_csi_crop_align(const struct cif_input_fmt * fmt_in)831 static int get_csi_crop_align(const struct cif_input_fmt *fmt_in)
832 {
833 switch (fmt_in->csi_fmt_val) {
834 case CSI_WRDDR_TYPE_RGB888:
835 return 24;
836 case CSI_WRDDR_TYPE_RGB565:
837 return 16;
838 case CSI_WRDDR_TYPE_RAW10:
839 case CSI_WRDDR_TYPE_RAW12:
840 return 4;
841 case CSI_WRDDR_TYPE_RAW8:
842 case CSI_WRDDR_TYPE_YUV422:
843 return 8;
844 default:
845 return -1;
846 }
847 }
848
849 const struct
rkcif_get_input_fmt(struct rkcif_device * dev,struct v4l2_rect * rect,u32 pad_id,struct csi_channel_info * csi_info)850 cif_input_fmt *rkcif_get_input_fmt(struct rkcif_device *dev, struct v4l2_rect *rect,
851 u32 pad_id, struct csi_channel_info *csi_info)
852 {
853 struct v4l2_subdev_format fmt;
854 struct v4l2_subdev *sd = dev->terminal_sensor.sd;
855 struct rkmodule_channel_info ch_info = {0};
856 struct rkmodule_capture_info capture_info;
857 int ret;
858 u32 i;
859
860 fmt.pad = 0;
861 fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
862 fmt.reserved[0] = 0;
863 fmt.format.field = V4L2_FIELD_NONE;
864 ret = v4l2_subdev_call(sd, pad, get_fmt, NULL, &fmt);
865 if (ret < 0) {
866 v4l2_warn(sd->v4l2_dev,
867 "sensor fmt invalid, set to default size\n");
868 goto set_default;
869 }
870 ch_info.index = pad_id;
871 ret = v4l2_subdev_call(sd,
872 core, ioctl,
873 RKMODULE_GET_CHANNEL_INFO,
874 &ch_info);
875 if (!ret) {
876 fmt.format.width = ch_info.width;
877 fmt.format.height = ch_info.height;
878 fmt.format.code = ch_info.bus_fmt;
879 switch (ch_info.vc) {
880 case V4L2_MBUS_CSI2_CHANNEL_3:
881 csi_info->vc = 3;
882 break;
883 case V4L2_MBUS_CSI2_CHANNEL_2:
884 csi_info->vc = 2;
885 break;
886 case V4L2_MBUS_CSI2_CHANNEL_1:
887 csi_info->vc = 1;
888 break;
889 case V4L2_MBUS_CSI2_CHANNEL_0:
890 csi_info->vc = 0;
891 break;
892 default:
893 csi_info->vc = 0xff;
894 }
895 if (ch_info.bus_fmt == MEDIA_BUS_FMT_SPD_2X8 ||
896 ch_info.bus_fmt == MEDIA_BUS_FMT_EBD_1X8) {
897 if (ch_info.data_type > 0)
898 csi_info->data_type = ch_info.data_type;
899 if (ch_info.data_bit > 0)
900 csi_info->data_bit = ch_info.data_bit;
901 }
902 } else {
903 csi_info->vc = 0xff;
904 }
905
906 v4l2_dbg(1, rkcif_debug, sd->v4l2_dev,
907 "remote fmt: mbus code:0x%x, size:%dx%d, field: %d\n",
908 fmt.format.code, fmt.format.width,
909 fmt.format.height, fmt.format.field);
910 rect->left = 0;
911 rect->top = 0;
912 rect->width = fmt.format.width;
913 rect->height = fmt.format.height;
914 ret = v4l2_subdev_call(sd,
915 core, ioctl,
916 RKMODULE_GET_CAPTURE_MODE,
917 &capture_info);
918 if (!ret) {
919 if (capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE &&
920 dev->hw_dev->is_rk3588s2) {
921 for (i = 0; i < capture_info.multi_dev.dev_num; i++) {
922 if (capture_info.multi_dev.dev_idx[i] == 0)
923 capture_info.multi_dev.dev_idx[i] = 2;
924 else if (capture_info.multi_dev.dev_idx[i] == 2)
925 capture_info.multi_dev.dev_idx[i] = 4;
926 else if (capture_info.multi_dev.dev_idx[i] == 3)
927 capture_info.multi_dev.dev_idx[i] = 5;
928 }
929 }
930 csi_info->capture_info = capture_info;
931 } else {
932 csi_info->capture_info.mode = RKMODULE_CAPTURE_MODE_NONE;
933 }
934 for (i = 0; i < ARRAY_SIZE(in_fmts); i++)
935 if (fmt.format.code == in_fmts[i].mbus_code &&
936 fmt.format.field == in_fmts[i].field)
937 return &in_fmts[i];
938
939 v4l2_err(sd->v4l2_dev, "remote sensor mbus code not supported\n");
940
941 set_default:
942 rect->left = 0;
943 rect->top = 0;
944 rect->width = RKCIF_DEFAULT_WIDTH;
945 rect->height = RKCIF_DEFAULT_HEIGHT;
946
947 return NULL;
948 }
949
950 const struct
rkcif_find_output_fmt(struct rkcif_stream * stream,u32 pixelfmt)951 cif_output_fmt *rkcif_find_output_fmt(struct rkcif_stream *stream, u32 pixelfmt)
952 {
953 const struct cif_output_fmt *fmt;
954 u32 i;
955
956 for (i = 0; i < ARRAY_SIZE(out_fmts); i++) {
957 fmt = &out_fmts[i];
958 if (fmt->fourcc == pixelfmt)
959 return fmt;
960 }
961
962 return NULL;
963 }
964
get_reg_index_of_id_ctrl0(int channel_id)965 static enum cif_reg_index get_reg_index_of_id_ctrl0(int channel_id)
966 {
967 enum cif_reg_index index;
968
969 switch (channel_id) {
970 case 0:
971 index = CIF_REG_MIPI_LVDS_ID0_CTRL0;
972 break;
973 case 1:
974 index = CIF_REG_MIPI_LVDS_ID1_CTRL0;
975 break;
976 case 2:
977 index = CIF_REG_MIPI_LVDS_ID2_CTRL0;
978 break;
979 case 3:
980 index = CIF_REG_MIPI_LVDS_ID3_CTRL0;
981 break;
982 default:
983 index = CIF_REG_MIPI_LVDS_ID0_CTRL0;
984 break;
985 }
986
987 return index;
988 }
989
get_reg_index_of_lvds_id_ctrl0(int channel_id)990 static enum cif_reg_index get_reg_index_of_lvds_id_ctrl0(int channel_id)
991 {
992 enum cif_reg_index index;
993
994 switch (channel_id) {
995 case 0:
996 index = CIF_REG_LVDS_ID0_CTRL0;
997 break;
998 case 1:
999 index = CIF_REG_LVDS_ID1_CTRL0;
1000 break;
1001 case 2:
1002 index = CIF_REG_LVDS_ID2_CTRL0;
1003 break;
1004 case 3:
1005 index = CIF_REG_LVDS_ID3_CTRL0;
1006 break;
1007 default:
1008 index = CIF_REG_LVDS_ID0_CTRL0;
1009 break;
1010 }
1011
1012 return index;
1013 }
1014
get_reg_index_of_id_ctrl1(int channel_id)1015 static enum cif_reg_index get_reg_index_of_id_ctrl1(int channel_id)
1016 {
1017 enum cif_reg_index index;
1018
1019 switch (channel_id) {
1020 case 0:
1021 index = CIF_REG_MIPI_LVDS_ID0_CTRL1;
1022 break;
1023 case 1:
1024 index = CIF_REG_MIPI_LVDS_ID1_CTRL1;
1025 break;
1026 case 2:
1027 index = CIF_REG_MIPI_LVDS_ID2_CTRL1;
1028 break;
1029 case 3:
1030 index = CIF_REG_MIPI_LVDS_ID3_CTRL1;
1031 break;
1032 default:
1033 index = CIF_REG_MIPI_LVDS_ID0_CTRL1;
1034 break;
1035 }
1036
1037 return index;
1038 }
1039
get_reg_index_of_frm0_y_addr(int channel_id)1040 static enum cif_reg_index get_reg_index_of_frm0_y_addr(int channel_id)
1041 {
1042 enum cif_reg_index index;
1043
1044 switch (channel_id) {
1045 case 0:
1046 index = CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID0;
1047 break;
1048 case 1:
1049 index = CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID1;
1050 break;
1051 case 2:
1052 index = CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID2;
1053 break;
1054 case 3:
1055 index = CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID3;
1056 break;
1057 default:
1058 index = CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID0;
1059 break;
1060 }
1061
1062 return index;
1063 }
1064
get_reg_index_of_frm1_y_addr(int channel_id)1065 static enum cif_reg_index get_reg_index_of_frm1_y_addr(int channel_id)
1066 {
1067 enum cif_reg_index index;
1068
1069 switch (channel_id) {
1070 case 0:
1071 index = CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID0;
1072 break;
1073 case 1:
1074 index = CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID1;
1075 break;
1076 case 2:
1077 index = CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID2;
1078 break;
1079 case 3:
1080 index = CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID3;
1081 break;
1082 default:
1083 index = CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID0;
1084 break;
1085 }
1086
1087 return index;
1088 }
1089
get_reg_index_of_frm0_uv_addr(int channel_id)1090 static enum cif_reg_index get_reg_index_of_frm0_uv_addr(int channel_id)
1091 {
1092 enum cif_reg_index index;
1093
1094 switch (channel_id) {
1095 case 0:
1096 index = CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID0;
1097 break;
1098 case 1:
1099 index = CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID1;
1100 break;
1101 case 2:
1102 index = CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID2;
1103 break;
1104 case 3:
1105 index = CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID3;
1106 break;
1107 default:
1108 index = CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID0;
1109 break;
1110 }
1111
1112 return index;
1113 }
1114
get_reg_index_of_frm1_uv_addr(int channel_id)1115 static enum cif_reg_index get_reg_index_of_frm1_uv_addr(int channel_id)
1116 {
1117 enum cif_reg_index index;
1118
1119 switch (channel_id) {
1120 case 0:
1121 index = CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID0;
1122 break;
1123 case 1:
1124 index = CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID1;
1125 break;
1126 case 2:
1127 index = CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID2;
1128 break;
1129 case 3:
1130 index = CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID3;
1131 break;
1132 default:
1133 index = CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID0;
1134 break;
1135 }
1136
1137 return index;
1138 }
1139
get_reg_index_of_frm0_y_vlw(int channel_id)1140 static enum cif_reg_index get_reg_index_of_frm0_y_vlw(int channel_id)
1141 {
1142 enum cif_reg_index index;
1143
1144 switch (channel_id) {
1145 case 0:
1146 index = CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID0;
1147 break;
1148 case 1:
1149 index = CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID1;
1150 break;
1151 case 2:
1152 index = CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID2;
1153 break;
1154 case 3:
1155 index = CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID3;
1156 break;
1157 default:
1158 index = CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID0;
1159 break;
1160 }
1161
1162 return index;
1163 }
1164
get_reg_index_of_frm1_y_vlw(int channel_id)1165 static enum cif_reg_index get_reg_index_of_frm1_y_vlw(int channel_id)
1166 {
1167 enum cif_reg_index index;
1168
1169 switch (channel_id) {
1170 case 0:
1171 index = CIF_REG_MIPI_LVDS_FRAME1_VLW_Y_ID0;
1172 break;
1173 case 1:
1174 index = CIF_REG_MIPI_LVDS_FRAME1_VLW_Y_ID1;
1175 break;
1176 case 2:
1177 index = CIF_REG_MIPI_LVDS_FRAME1_VLW_Y_ID2;
1178 break;
1179 case 3:
1180 index = CIF_REG_MIPI_LVDS_FRAME1_VLW_Y_ID3;
1181 break;
1182 default:
1183 index = CIF_REG_MIPI_LVDS_FRAME1_VLW_Y_ID0;
1184 break;
1185 }
1186
1187 return index;
1188 }
1189
get_reg_index_of_frm0_uv_vlw(int channel_id)1190 static enum cif_reg_index get_reg_index_of_frm0_uv_vlw(int channel_id)
1191 {
1192 enum cif_reg_index index;
1193
1194 switch (channel_id) {
1195 case 0:
1196 index = CIF_REG_MIPI_LVDS_FRAME0_VLW_UV_ID0;
1197 break;
1198 case 1:
1199 index = CIF_REG_MIPI_LVDS_FRAME0_VLW_UV_ID1;
1200 break;
1201 case 2:
1202 index = CIF_REG_MIPI_LVDS_FRAME0_VLW_UV_ID2;
1203 break;
1204 case 3:
1205 index = CIF_REG_MIPI_LVDS_FRAME0_VLW_UV_ID3;
1206 break;
1207 default:
1208 index = CIF_REG_MIPI_LVDS_FRAME0_VLW_UV_ID0;
1209 break;
1210 }
1211
1212 return index;
1213 }
1214
get_reg_index_of_frm1_uv_vlw(int channel_id)1215 static enum cif_reg_index get_reg_index_of_frm1_uv_vlw(int channel_id)
1216 {
1217 enum cif_reg_index index;
1218
1219 switch (channel_id) {
1220 case 0:
1221 index = CIF_REG_MIPI_LVDS_FRAME1_VLW_UV_ID0;
1222 break;
1223 case 1:
1224 index = CIF_REG_MIPI_LVDS_FRAME1_VLW_UV_ID1;
1225 break;
1226 case 2:
1227 index = CIF_REG_MIPI_LVDS_FRAME1_VLW_UV_ID2;
1228 break;
1229 case 3:
1230 index = CIF_REG_MIPI_LVDS_FRAME1_VLW_UV_ID3;
1231 break;
1232 default:
1233 index = CIF_REG_MIPI_LVDS_FRAME1_VLW_UV_ID0;
1234 break;
1235 }
1236
1237 return index;
1238 }
1239
get_reg_index_of_id_crop_start(int channel_id)1240 static enum cif_reg_index get_reg_index_of_id_crop_start(int channel_id)
1241 {
1242 enum cif_reg_index index;
1243
1244 switch (channel_id) {
1245 case 0:
1246 index = CIF_REG_MIPI_LVDS_ID0_CROP_START;
1247 break;
1248 case 1:
1249 index = CIF_REG_MIPI_LVDS_ID1_CROP_START;
1250 break;
1251 case 2:
1252 index = CIF_REG_MIPI_LVDS_ID2_CROP_START;
1253 break;
1254 case 3:
1255 index = CIF_REG_MIPI_LVDS_ID3_CROP_START;
1256 break;
1257 default:
1258 index = CIF_REG_MIPI_LVDS_ID0_CROP_START;
1259 break;
1260 }
1261
1262 return index;
1263 }
1264
get_reg_index_of_lvds_sav_eav_act0(int channel_id)1265 static enum cif_reg_index get_reg_index_of_lvds_sav_eav_act0(int channel_id)
1266 {
1267 enum cif_reg_index index;
1268
1269 switch (channel_id) {
1270 case 0:
1271 index = CIF_REG_LVDS_SAV_EAV_ACT0_ID0;
1272 break;
1273 case 1:
1274 index = CIF_REG_LVDS_SAV_EAV_ACT0_ID1;
1275 break;
1276 case 2:
1277 index = CIF_REG_LVDS_SAV_EAV_ACT0_ID2;
1278 break;
1279 case 3:
1280 index = CIF_REG_LVDS_SAV_EAV_ACT0_ID3;
1281 break;
1282 default:
1283 index = CIF_REG_LVDS_SAV_EAV_ACT0_ID0;
1284 break;
1285 }
1286
1287 return index;
1288 }
1289
get_reg_index_of_lvds_sav_eav_act1(int channel_id)1290 static enum cif_reg_index get_reg_index_of_lvds_sav_eav_act1(int channel_id)
1291 {
1292 enum cif_reg_index index;
1293
1294 switch (channel_id) {
1295 case 0:
1296 index = CIF_REG_LVDS_SAV_EAV_ACT1_ID0;
1297 break;
1298 case 1:
1299 index = CIF_REG_LVDS_SAV_EAV_ACT1_ID1;
1300 break;
1301 case 2:
1302 index = CIF_REG_LVDS_SAV_EAV_ACT1_ID2;
1303 break;
1304 case 3:
1305 index = CIF_REG_LVDS_SAV_EAV_ACT1_ID3;
1306 break;
1307 default:
1308 index = CIF_REG_LVDS_SAV_EAV_ACT1_ID0;
1309 break;
1310 }
1311
1312 return index;
1313 }
1314
get_reg_index_of_lvds_sav_eav_blk0(int channel_id)1315 static enum cif_reg_index get_reg_index_of_lvds_sav_eav_blk0(int channel_id)
1316 {
1317 enum cif_reg_index index;
1318
1319 switch (channel_id) {
1320 case 0:
1321 index = CIF_REG_LVDS_SAV_EAV_BLK0_ID0;
1322 break;
1323 case 1:
1324 index = CIF_REG_LVDS_SAV_EAV_BLK0_ID1;
1325 break;
1326 case 2:
1327 index = CIF_REG_LVDS_SAV_EAV_BLK0_ID2;
1328 break;
1329 case 3:
1330 index = CIF_REG_LVDS_SAV_EAV_BLK0_ID3;
1331 break;
1332 default:
1333 index = CIF_REG_LVDS_SAV_EAV_BLK0_ID0;
1334 break;
1335 }
1336
1337 return index;
1338 }
1339
get_reg_index_of_lvds_sav_eav_blk1(int channel_id)1340 static enum cif_reg_index get_reg_index_of_lvds_sav_eav_blk1(int channel_id)
1341 {
1342 enum cif_reg_index index;
1343
1344 switch (channel_id) {
1345 case 0:
1346 index = CIF_REG_LVDS_SAV_EAV_BLK1_ID0;
1347 break;
1348 case 1:
1349 index = CIF_REG_LVDS_SAV_EAV_BLK1_ID1;
1350 break;
1351 case 2:
1352 index = CIF_REG_LVDS_SAV_EAV_BLK1_ID2;
1353 break;
1354 case 3:
1355 index = CIF_REG_LVDS_SAV_EAV_BLK1_ID3;
1356 break;
1357 default:
1358 index = CIF_REG_LVDS_SAV_EAV_BLK1_ID0;
1359 break;
1360 }
1361
1362 return index;
1363 }
1364
get_dvp_reg_index_of_frm0_y_addr(int channel_id)1365 static enum cif_reg_index get_dvp_reg_index_of_frm0_y_addr(int channel_id)
1366 {
1367 enum cif_reg_index index;
1368
1369 switch (channel_id) {
1370 case 0:
1371 index = CIF_REG_DVP_FRM0_ADDR_Y;
1372 break;
1373 case 1:
1374 index = CIF_REG_DVP_FRM0_ADDR_Y_ID1;
1375 break;
1376 case 2:
1377 index = CIF_REG_DVP_FRM0_ADDR_Y_ID2;
1378 break;
1379 case 3:
1380 index = CIF_REG_DVP_FRM0_ADDR_Y_ID3;
1381 break;
1382 default:
1383 index = CIF_REG_DVP_FRM0_ADDR_Y;
1384 break;
1385 }
1386
1387 return index;
1388 }
1389
get_dvp_reg_index_of_frm1_y_addr(int channel_id)1390 static enum cif_reg_index get_dvp_reg_index_of_frm1_y_addr(int channel_id)
1391 {
1392 enum cif_reg_index index;
1393
1394 switch (channel_id) {
1395 case 0:
1396 index = CIF_REG_DVP_FRM1_ADDR_Y;
1397 break;
1398 case 1:
1399 index = CIF_REG_DVP_FRM1_ADDR_Y_ID1;
1400 break;
1401 case 2:
1402 index = CIF_REG_DVP_FRM1_ADDR_Y_ID2;
1403 break;
1404 case 3:
1405 index = CIF_REG_DVP_FRM1_ADDR_Y_ID3;
1406 break;
1407 default:
1408 index = CIF_REG_DVP_FRM0_ADDR_Y;
1409 break;
1410 }
1411
1412 return index;
1413 }
1414
get_dvp_reg_index_of_frm0_uv_addr(int channel_id)1415 static enum cif_reg_index get_dvp_reg_index_of_frm0_uv_addr(int channel_id)
1416 {
1417 enum cif_reg_index index;
1418
1419 switch (channel_id) {
1420 case 0:
1421 index = CIF_REG_DVP_FRM0_ADDR_UV;
1422 break;
1423 case 1:
1424 index = CIF_REG_DVP_FRM0_ADDR_UV_ID1;
1425 break;
1426 case 2:
1427 index = CIF_REG_DVP_FRM0_ADDR_UV_ID2;
1428 break;
1429 case 3:
1430 index = CIF_REG_DVP_FRM0_ADDR_UV_ID3;
1431 break;
1432 default:
1433 index = CIF_REG_DVP_FRM0_ADDR_UV;
1434 break;
1435 }
1436
1437 return index;
1438 }
1439
get_dvp_reg_index_of_frm1_uv_addr(int channel_id)1440 static enum cif_reg_index get_dvp_reg_index_of_frm1_uv_addr(int channel_id)
1441 {
1442 enum cif_reg_index index;
1443
1444 switch (channel_id) {
1445 case 0:
1446 index = CIF_REG_DVP_FRM1_ADDR_UV;
1447 break;
1448 case 1:
1449 index = CIF_REG_DVP_FRM1_ADDR_UV_ID1;
1450 break;
1451 case 2:
1452 index = CIF_REG_DVP_FRM1_ADDR_UV_ID2;
1453 break;
1454 case 3:
1455 index = CIF_REG_DVP_FRM1_ADDR_UV_ID3;
1456 break;
1457 default:
1458 index = CIF_REG_DVP_FRM1_ADDR_UV;
1459 break;
1460 }
1461
1462 return index;
1463 }
1464
rkcif_get_linetime(struct rkcif_stream * stream)1465 int rkcif_get_linetime(struct rkcif_stream *stream)
1466 {
1467 struct rkcif_device *cif_dev = stream->cifdev;
1468 struct rkcif_sensor_info *sensor = &cif_dev->terminal_sensor;
1469 u32 numerator, denominator;
1470 u32 def_fps = 0;
1471 int line_time = 0;
1472 int vblank_def = 0;
1473 int vblank_curr = 0;
1474
1475 numerator = sensor->fi.interval.numerator;
1476 denominator = sensor->fi.interval.denominator;
1477 if (!numerator || !denominator) {
1478 v4l2_err(&cif_dev->v4l2_dev,
1479 "get frame interval fail, numerator %d, denominator %d\n",
1480 numerator, denominator);
1481 return -EINVAL;
1482 }
1483 def_fps = denominator / numerator;
1484 if (!def_fps) {
1485 v4l2_err(&cif_dev->v4l2_dev,
1486 "get fps fail, numerator %d, denominator %d\n",
1487 numerator, denominator);
1488 return -EINVAL;
1489 }
1490 vblank_def = rkcif_get_sensor_vblank_def(cif_dev);
1491 vblank_curr = rkcif_get_sensor_vblank(cif_dev);
1492 if (!vblank_def || !vblank_curr) {
1493 v4l2_err(&cif_dev->v4l2_dev,
1494 "get vblank fail, vblank_def %d, vblank_curr %d\n",
1495 vblank_def, vblank_curr);
1496 return -EINVAL;
1497 }
1498 line_time = div_u64(1000000000, def_fps);
1499 line_time = div_u64(line_time, vblank_def + sensor->raw_rect.height);
1500 return line_time;
1501 }
1502
1503 /***************************** stream operations ******************************/
rkcif_assign_new_buffer_oneframe(struct rkcif_stream * stream,enum rkcif_yuvaddr_state stat)1504 static int rkcif_assign_new_buffer_oneframe(struct rkcif_stream *stream,
1505 enum rkcif_yuvaddr_state stat)
1506 {
1507 struct rkcif_device *dev = stream->cifdev;
1508 struct rkcif_dummy_buffer *dummy_buf = &dev->hw_dev->dummy_buf;
1509 struct rkcif_buffer *buffer = NULL;
1510 u32 frm_addr_y = CIF_REG_DVP_FRM0_ADDR_Y;
1511 u32 frm_addr_uv = CIF_REG_DVP_FRM0_ADDR_UV;
1512 unsigned long flags;
1513 int ret = 0;
1514
1515 spin_lock_irqsave(&stream->vbq_lock, flags);
1516 if (stat == RKCIF_YUV_ADDR_STATE_INIT) {
1517 if (!stream->curr_buf) {
1518 if (!list_empty(&stream->buf_head)) {
1519 stream->curr_buf = list_first_entry(&stream->buf_head,
1520 struct rkcif_buffer,
1521 queue);
1522 list_del(&stream->curr_buf->queue);
1523 }
1524 }
1525
1526 if (stream->curr_buf) {
1527 rkcif_write_register(dev, CIF_REG_DVP_FRM0_ADDR_Y,
1528 stream->curr_buf->buff_addr[RKCIF_PLANE_Y]);
1529 rkcif_write_register(dev, CIF_REG_DVP_FRM0_ADDR_UV,
1530 stream->curr_buf->buff_addr[RKCIF_PLANE_CBCR]);
1531 } else {
1532 if (dummy_buf->vaddr) {
1533 rkcif_write_register(dev, CIF_REG_DVP_FRM0_ADDR_Y,
1534 dummy_buf->dma_addr);
1535 rkcif_write_register(dev, CIF_REG_DVP_FRM0_ADDR_UV,
1536 dummy_buf->dma_addr);
1537 }
1538 }
1539
1540 if (!stream->next_buf) {
1541 if (!list_empty(&stream->buf_head)) {
1542 stream->next_buf = list_first_entry(&stream->buf_head,
1543 struct rkcif_buffer, queue);
1544 list_del(&stream->next_buf->queue);
1545 }
1546 }
1547
1548 if (stream->next_buf) {
1549 rkcif_write_register(dev, CIF_REG_DVP_FRM1_ADDR_Y,
1550 stream->next_buf->buff_addr[RKCIF_PLANE_Y]);
1551 rkcif_write_register(dev, CIF_REG_DVP_FRM1_ADDR_UV,
1552 stream->next_buf->buff_addr[RKCIF_PLANE_CBCR]);
1553 } else {
1554 if (dummy_buf->vaddr) {
1555 rkcif_write_register(dev, CIF_REG_DVP_FRM1_ADDR_Y,
1556 dummy_buf->dma_addr);
1557 rkcif_write_register(dev, CIF_REG_DVP_FRM1_ADDR_UV,
1558 dummy_buf->dma_addr);
1559 }
1560 }
1561 } else if (stat == RKCIF_YUV_ADDR_STATE_UPDATE) {
1562 if (!list_empty(&stream->buf_head)) {
1563 if (stream->frame_phase == CIF_CSI_FRAME0_READY) {
1564 stream->curr_buf = list_first_entry(&stream->buf_head,
1565 struct rkcif_buffer, queue);
1566 list_del(&stream->curr_buf->queue);
1567 buffer = stream->curr_buf;
1568 } else if (stream->frame_phase == CIF_CSI_FRAME1_READY) {
1569 stream->next_buf = list_first_entry(&stream->buf_head,
1570 struct rkcif_buffer, queue);
1571 list_del(&stream->next_buf->queue);
1572 buffer = stream->next_buf;
1573 }
1574 } else {
1575 if (dummy_buf->vaddr && stream->frame_phase == CIF_CSI_FRAME0_READY)
1576 stream->curr_buf = NULL;
1577 if (dummy_buf->vaddr && stream->frame_phase == CIF_CSI_FRAME1_READY)
1578 stream->next_buf = NULL;
1579 buffer = NULL;
1580 }
1581 if (stream->frame_phase == CIF_CSI_FRAME0_READY) {
1582 frm_addr_y = CIF_REG_DVP_FRM0_ADDR_Y;
1583 frm_addr_uv = CIF_REG_DVP_FRM0_ADDR_UV;
1584 } else if (stream->frame_phase == CIF_CSI_FRAME1_READY) {
1585 frm_addr_y = CIF_REG_DVP_FRM1_ADDR_Y;
1586 frm_addr_uv = CIF_REG_DVP_FRM1_ADDR_UV;
1587 }
1588
1589 if (buffer) {
1590 rkcif_write_register(dev, frm_addr_y,
1591 buffer->buff_addr[RKCIF_PLANE_Y]);
1592 rkcif_write_register(dev, frm_addr_uv,
1593 buffer->buff_addr[RKCIF_PLANE_CBCR]);
1594 } else {
1595 if (dummy_buf->vaddr) {
1596 rkcif_write_register(dev, frm_addr_y,
1597 dummy_buf->dma_addr);
1598 rkcif_write_register(dev, frm_addr_uv,
1599 dummy_buf->dma_addr);
1600 } else {
1601 ret = -EINVAL;
1602 }
1603 dev->err_state |= (RKCIF_ERR_ID0_NOT_BUF << stream->id);
1604 dev->irq_stats.not_active_buf_cnt[stream->id]++;
1605 }
1606 }
1607 spin_unlock_irqrestore(&stream->vbq_lock, flags);
1608 return ret;
1609 }
1610
rkcif_rx_buffer_free(struct rkcif_stream * stream)1611 static void rkcif_rx_buffer_free(struct rkcif_stream *stream)
1612 {
1613 struct media_pad *pad = NULL;
1614 struct v4l2_subdev *sd;
1615 struct rkisp_rx_buf *dbufs;
1616 struct rkcif_device *dev = stream->cifdev;
1617
1618 if (dev->sditf[0] && dev->sditf[0]->num_sensors != 0) {
1619 if (dev->sditf[0]->is_combine_mode)
1620 pad = media_entity_remote_pad(&dev->sditf[0]->pads[1]);
1621 else
1622 pad = media_entity_remote_pad(&dev->sditf[0]->pads[0]);
1623 } else {
1624 return;
1625 }
1626
1627 if (pad)
1628 sd = media_entity_to_v4l2_subdev(pad->entity);
1629 else
1630 return;
1631
1632 while (!list_empty(&stream->rx_buf_head_vicap)) {
1633 dbufs = list_first_entry(&stream->rx_buf_head_vicap, struct rkisp_rx_buf, list);
1634 if (dbufs->is_init)
1635 v4l2_subdev_call(sd, core, ioctl,
1636 RKISP_VICAP_CMD_RX_BUFFER_FREE, dbufs);
1637 dma_buf_put(dbufs->dbuf);
1638 list_del(&dbufs->list);
1639 kfree(dbufs);
1640 }
1641 }
1642
rkcif_s_rx_buffer(struct rkcif_device * dev,struct rkisp_rx_buf * dbufs)1643 static void rkcif_s_rx_buffer(struct rkcif_device *dev, struct rkisp_rx_buf *dbufs)
1644 {
1645 struct media_pad *pad = NULL;
1646 struct v4l2_subdev *sd;
1647 struct rkcif_rx_buffer *rx_buf = NULL;
1648
1649 if (dev->sditf[0]) {
1650 if (dev->sditf[0]->is_combine_mode)
1651 pad = media_entity_remote_pad(&dev->sditf[0]->pads[1]);
1652 else
1653 pad = media_entity_remote_pad(&dev->sditf[0]->pads[0]);
1654 } else {
1655 return;
1656 }
1657 if (pad)
1658 sd = media_entity_to_v4l2_subdev(pad->entity);
1659 else
1660 return;
1661 if (dev->rdbk_debug &&
1662 dbufs->sequence < 15) {
1663 rx_buf = to_cif_rx_buf(dbufs);
1664 v4l2_info(&dev->v4l2_dev,
1665 "s_buf seq %d type %d, dma addr %x, %lld\n",
1666 dbufs->sequence, dbufs->type, (u32)rx_buf->dummy.dma_addr,
1667 ktime_get_ns());
1668 }
1669 v4l2_subdev_call(sd, video, s_rx_buffer, dbufs, NULL);
1670 }
1671
rkcif_enable_skip_frame(struct rkcif_stream * stream,int cap_m,int skip_n)1672 static void rkcif_enable_skip_frame(struct rkcif_stream *stream, int cap_m, int skip_n)
1673 {
1674 struct rkcif_device *dev = stream->cifdev;
1675 u32 val = 0;
1676
1677 val = rkcif_read_register(dev, CIF_REG_MIPI_LVDS_CTRL);
1678 val &= 0xc00fffff;
1679 val |= cap_m << RKCIF_CAP_SHIFT | skip_n << RKCIF_SKIP_SHIFT | RKCIF_SKIP_EN(stream->id);
1680 rkcif_write_register(dev, CIF_REG_MIPI_LVDS_CTRL, val);
1681 stream->skip_info.skip_en = true;
1682 }
1683
rkcif_disable_skip_frame(struct rkcif_stream * stream)1684 static void rkcif_disable_skip_frame(struct rkcif_stream *stream)
1685 { struct rkcif_device *dev = stream->cifdev;
1686 u32 val = 0;
1687
1688 val = rkcif_read_register(dev, CIF_REG_MIPI_LVDS_CTRL);
1689 val &= ~(RKCIF_SKIP_EN(stream->id));
1690 rkcif_write_register(dev, CIF_REG_MIPI_LVDS_CTRL, val);
1691 stream->skip_info.skip_en = false;
1692 }
1693
rkcif_rdbk_with_tools(struct rkcif_stream * stream,struct rkcif_rx_buffer * active_buf)1694 static void rkcif_rdbk_with_tools(struct rkcif_stream *stream,
1695 struct rkcif_rx_buffer *active_buf)
1696 {
1697 unsigned long flags;
1698
1699 spin_lock_irqsave(&stream->tools_vdev->vbq_lock, flags);
1700 if (stream->tools_vdev->state == RKCIF_STATE_STREAMING) {
1701 list_add_tail(&active_buf->list, &stream->tools_vdev->buf_done_head);
1702 if (!work_busy(&stream->tools_vdev->work))
1703 schedule_work(&stream->tools_vdev->work);
1704 }
1705 spin_unlock_irqrestore(&stream->tools_vdev->vbq_lock, flags);
1706 }
1707
rkcif_rdbk_frame_end_toisp(struct rkcif_stream * stream,struct rkcif_rx_buffer * buffer)1708 static void rkcif_rdbk_frame_end_toisp(struct rkcif_stream *stream,
1709 struct rkcif_rx_buffer *buffer)
1710 {
1711 struct rkcif_device *dev = stream->cifdev;
1712 struct rkcif_sensor_info *sensor = &stream->cifdev->terminal_sensor;
1713 u32 denominator, numerator;
1714 u64 l_ts, m_ts, s_ts, time = 30000000LL;
1715 int ret, fps = -1;
1716 unsigned long flags;
1717
1718 spin_lock_irqsave(&dev->hdr_lock, flags);
1719 if (dev->rdbk_rx_buf[stream->id]) {
1720 list_add_tail(&dev->rdbk_rx_buf[stream->id]->list, &stream->rx_buf_head);
1721 dev->rdbk_rx_buf[stream->id] = buffer;
1722 } else {
1723 dev->rdbk_rx_buf[stream->id] = buffer;
1724 }
1725
1726 numerator = sensor->fi.interval.numerator;
1727 denominator = sensor->fi.interval.denominator;
1728 if (denominator && numerator)
1729 time = numerator * 1000 / denominator * 1000 * 1000;
1730
1731 if (dev->hdr.hdr_mode == HDR_X3 &&
1732 dev->rdbk_rx_buf[RDBK_L] &&
1733 dev->rdbk_rx_buf[RDBK_M] &&
1734 dev->rdbk_rx_buf[RDBK_S]) {
1735 l_ts = dev->rdbk_rx_buf[RDBK_L]->fe_timestamp;
1736 m_ts = dev->rdbk_rx_buf[RDBK_M]->fe_timestamp;
1737 s_ts = dev->rdbk_rx_buf[RDBK_S]->fe_timestamp;
1738
1739 if (m_ts < l_ts || s_ts < m_ts) {
1740 v4l2_err(&dev->v4l2_dev,
1741 "s/m/l frame err, timestamp s:%lld m:%lld l:%lld\n",
1742 s_ts, m_ts, l_ts);
1743 goto RDBK_TOISP_UNMATCH;
1744 }
1745
1746 if ((m_ts - l_ts) > time || (s_ts - m_ts) > time) {
1747 ret = v4l2_subdev_call(sensor->sd,
1748 video,
1749 g_frame_interval,
1750 &sensor->fi);
1751 if (!ret) {
1752 denominator = sensor->fi.interval.denominator;
1753 numerator = sensor->fi.interval.numerator;
1754 if (denominator && numerator) {
1755 time = numerator * 1000 / denominator * 1000 * 1000;
1756 fps = denominator / numerator;
1757 }
1758 }
1759
1760 if ((m_ts - l_ts) > time || (s_ts - m_ts) > time) {
1761 v4l2_err(&dev->v4l2_dev,
1762 "timestamp no match, s:%lld m:%lld l:%lld, fps:%d\n",
1763 s_ts, m_ts, l_ts, fps);
1764 goto RDBK_TOISP_UNMATCH;
1765 }
1766 }
1767 dev->rdbk_rx_buf[RDBK_M]->dbufs.sequence = dev->rdbk_rx_buf[RDBK_L]->dbufs.sequence;
1768 dev->rdbk_rx_buf[RDBK_S]->dbufs.sequence = dev->rdbk_rx_buf[RDBK_L]->dbufs.sequence;
1769 rkcif_s_rx_buffer(dev, &dev->rdbk_rx_buf[RDBK_L]->dbufs);
1770 rkcif_s_rx_buffer(dev, &dev->rdbk_rx_buf[RDBK_M]->dbufs);
1771 rkcif_s_rx_buffer(dev, &dev->rdbk_rx_buf[RDBK_S]->dbufs);
1772 rkcif_rdbk_with_tools(&dev->stream[RDBK_L], dev->rdbk_rx_buf[RDBK_L]);
1773 rkcif_rdbk_with_tools(&dev->stream[RDBK_M], dev->rdbk_rx_buf[RDBK_M]);
1774 rkcif_rdbk_with_tools(&dev->stream[RDBK_S], dev->rdbk_rx_buf[RDBK_S]);
1775 atomic_dec(&dev->stream[RDBK_L].buf_cnt);
1776 atomic_dec(&dev->stream[RDBK_M].buf_cnt);
1777 atomic_dec(&dev->stream[RDBK_S].buf_cnt);
1778 dev->rdbk_rx_buf[RDBK_L] = NULL;
1779 dev->rdbk_rx_buf[RDBK_M] = NULL;
1780 dev->rdbk_rx_buf[RDBK_S] = NULL;
1781 } else if (dev->hdr.hdr_mode == HDR_X2 &&
1782 dev->rdbk_rx_buf[RDBK_L] && dev->rdbk_rx_buf[RDBK_M]) {
1783 l_ts = dev->rdbk_rx_buf[RDBK_L]->fe_timestamp;
1784 s_ts = dev->rdbk_rx_buf[RDBK_M]->fe_timestamp;
1785
1786 if (s_ts < l_ts) {
1787 v4l2_err(&dev->v4l2_dev,
1788 "s/l frame err, timestamp s:%lld l:%lld\n",
1789 s_ts, l_ts);
1790 goto RDBK_TOISP_UNMATCH;
1791 }
1792
1793 if ((s_ts - l_ts) > time) {
1794 ret = v4l2_subdev_call(sensor->sd,
1795 video,
1796 g_frame_interval,
1797 &sensor->fi);
1798 if (!ret) {
1799 denominator = sensor->fi.interval.denominator;
1800 numerator = sensor->fi.interval.numerator;
1801 if (denominator && numerator) {
1802 time = numerator * 1000 / denominator * 1000 * 1000;
1803 fps = denominator / numerator;
1804 }
1805 }
1806 if ((s_ts - l_ts) > time) {
1807 v4l2_err(&dev->v4l2_dev,
1808 "timestamp no match, s:%lld l:%lld, fps:%d\n",
1809 s_ts, l_ts, fps);
1810 goto RDBK_TOISP_UNMATCH;
1811 }
1812 }
1813 dev->rdbk_rx_buf[RDBK_M]->dbufs.sequence = dev->rdbk_rx_buf[RDBK_L]->dbufs.sequence;
1814 rkcif_s_rx_buffer(dev, &dev->rdbk_rx_buf[RDBK_L]->dbufs);
1815 rkcif_s_rx_buffer(dev, &dev->rdbk_rx_buf[RDBK_M]->dbufs);
1816 rkcif_rdbk_with_tools(&dev->stream[RDBK_L], dev->rdbk_rx_buf[RDBK_L]);
1817 rkcif_rdbk_with_tools(&dev->stream[RDBK_M], dev->rdbk_rx_buf[RDBK_M]);
1818 atomic_dec(&dev->stream[RDBK_L].buf_cnt);
1819 atomic_dec(&dev->stream[RDBK_M].buf_cnt);
1820 dev->rdbk_rx_buf[RDBK_L] = NULL;
1821 dev->rdbk_rx_buf[RDBK_M] = NULL;
1822 }
1823
1824 spin_unlock_irqrestore(&dev->hdr_lock, flags);
1825 return;
1826
1827 RDBK_TOISP_UNMATCH:
1828 spin_unlock_irqrestore(&dev->hdr_lock, flags);
1829 }
1830
rkcif_write_buff_addr_multi_dev_combine(struct rkcif_stream * stream,u32 frm_addr_y,u32 frm_addr_uv,u32 buff_addr_y,u32 buff_addr_cbcr,bool is_dummy_buf)1831 static void rkcif_write_buff_addr_multi_dev_combine(struct rkcif_stream *stream,
1832 u32 frm_addr_y, u32 frm_addr_uv,
1833 u32 buff_addr_y, u32 buff_addr_cbcr,
1834 bool is_dummy_buf)
1835 {
1836 struct rkcif_device *dev = stream->cifdev;
1837 struct rkmodule_capture_info *capture_info = &dev->channels[stream->id].capture_info;
1838 u32 addr_y, addr_cbcr;
1839 int addr_offset = 0;
1840 int i = 0;
1841 int tmp_host_index = dev->csi_host_idx;
1842
1843 for (i = 0; i < capture_info->multi_dev.dev_num; i++) {
1844 if (is_dummy_buf) {
1845 addr_y = buff_addr_y;
1846 } else {
1847 addr_offset = dev->channels[stream->id].left_virtual_width;
1848 addr_y = buff_addr_y + addr_offset * i;
1849 }
1850 dev->csi_host_idx = capture_info->multi_dev.dev_idx[i];
1851 rkcif_write_register(dev, frm_addr_y, addr_y);
1852 if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW &&
1853 frm_addr_uv && buff_addr_cbcr) {
1854 if (is_dummy_buf) {
1855 addr_cbcr = buff_addr_cbcr;
1856 } else {
1857 addr_offset = dev->channels[stream->id].left_virtual_width;
1858 addr_cbcr = buff_addr_cbcr + addr_offset * i;
1859 }
1860 rkcif_write_register(dev, frm_addr_uv, addr_cbcr);
1861 }
1862 }
1863 dev->csi_host_idx = tmp_host_index;
1864 }
1865
rkcif_assign_new_buffer_init_toisp(struct rkcif_stream * stream,int channel_id)1866 static void rkcif_assign_new_buffer_init_toisp(struct rkcif_stream *stream,
1867 int channel_id)
1868 {
1869 struct rkcif_device *dev = stream->cifdev;
1870 struct rkcif_rx_buffer *rx_buf;
1871 struct v4l2_mbus_config *mbus_cfg = &dev->active_sensor->mbus;
1872 struct rkmodule_capture_info *capture_info = &dev->channels[channel_id].capture_info;
1873 u32 frm0_addr_y;
1874 u32 frm1_addr_y;
1875 u32 buff_addr_y;
1876 unsigned long flags;
1877
1878 if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY ||
1879 mbus_cfg->type == V4L2_MBUS_CSI2_CPHY ||
1880 mbus_cfg->type == V4L2_MBUS_CCP2) {
1881 frm0_addr_y = get_reg_index_of_frm0_y_addr(channel_id);
1882 frm1_addr_y = get_reg_index_of_frm1_y_addr(channel_id);
1883 } else {
1884 frm0_addr_y = get_dvp_reg_index_of_frm0_y_addr(channel_id);
1885 frm1_addr_y = get_dvp_reg_index_of_frm1_y_addr(channel_id);
1886 }
1887
1888 spin_lock_irqsave(&stream->vbq_lock, flags);
1889
1890 if (!stream->curr_buf_toisp) {
1891 if (!list_empty(&stream->rx_buf_head)) {
1892 rx_buf = list_first_entry(&stream->rx_buf_head,
1893 struct rkcif_rx_buffer,
1894 list);
1895 if (rx_buf) {
1896 list_del(&rx_buf->list);
1897 stream->curr_buf_toisp = rx_buf;
1898 }
1899 }
1900 }
1901
1902 if (stream->curr_buf_toisp) {
1903 buff_addr_y = stream->curr_buf_toisp->dummy.dma_addr;
1904 if (capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
1905 rkcif_write_buff_addr_multi_dev_combine(stream, frm0_addr_y, 0,
1906 buff_addr_y, 0, false);
1907 } else {
1908 rkcif_write_register(dev, frm0_addr_y, buff_addr_y);
1909 }
1910 }
1911
1912 if (!stream->next_buf_toisp) {
1913 if (!list_empty(&stream->rx_buf_head)) {
1914 rx_buf = list_first_entry(&stream->rx_buf_head,
1915 struct rkcif_rx_buffer, list);
1916 if (rx_buf) {
1917 list_del(&rx_buf->list);
1918 stream->next_buf_toisp = rx_buf;
1919 } else {
1920 stream->next_buf_toisp = stream->curr_buf_toisp;
1921 }
1922 } else {
1923 stream->next_buf_toisp = stream->curr_buf_toisp;
1924 }
1925 }
1926
1927 if (stream->next_buf_toisp) {
1928 buff_addr_y = stream->next_buf_toisp->dummy.dma_addr;
1929 if (capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
1930 rkcif_write_buff_addr_multi_dev_combine(stream, frm1_addr_y, 0,
1931 buff_addr_y, 0, false);
1932 } else {
1933 rkcif_write_register(dev, frm1_addr_y, buff_addr_y);
1934 }
1935 }
1936
1937 spin_unlock_irqrestore(&stream->vbq_lock, flags);
1938 stream->buf_owner = RKCIF_DMAEN_BY_ISP;
1939 }
1940
rkcif_assign_new_buffer_update_toisp(struct rkcif_stream * stream,int channel_id)1941 static int rkcif_assign_new_buffer_update_toisp(struct rkcif_stream *stream,
1942 int channel_id)
1943 {
1944 struct rkcif_device *dev = stream->cifdev;
1945 struct v4l2_mbus_config *mbus_cfg = &dev->active_sensor->mbus;
1946 struct rkmodule_capture_info *capture_info = &dev->channels[channel_id].capture_info;
1947 struct rkcif_rx_buffer *buffer = NULL;
1948 struct rkcif_rx_buffer *active_buf = NULL;
1949 struct sditf_priv *priv = dev->sditf[0];
1950 u32 frm_addr_y, buff_addr_y;
1951 unsigned long flags;
1952
1953 if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY ||
1954 mbus_cfg->type == V4L2_MBUS_CSI2_CPHY ||
1955 mbus_cfg->type == V4L2_MBUS_CCP2) {
1956 frm_addr_y = stream->frame_phase & CIF_CSI_FRAME0_READY ?
1957 get_reg_index_of_frm0_y_addr(channel_id) :
1958 get_reg_index_of_frm1_y_addr(channel_id);
1959 } else {
1960 frm_addr_y = stream->frame_phase & CIF_CSI_FRAME0_READY ?
1961 get_dvp_reg_index_of_frm0_y_addr(channel_id) :
1962 get_dvp_reg_index_of_frm1_y_addr(channel_id);
1963 }
1964 spin_lock_irqsave(&stream->vbq_lock, flags);
1965 if (!list_empty(&stream->rx_buf_head)) {
1966 if (stream->frame_phase == CIF_CSI_FRAME0_READY) {
1967 if (stream->curr_buf_toisp == stream->next_buf_toisp)
1968 active_buf = NULL;
1969 else
1970 active_buf = stream->curr_buf_toisp;
1971
1972 buffer = list_first_entry(&stream->rx_buf_head,
1973 struct rkcif_rx_buffer, list);
1974 if (buffer) {
1975 list_del(&buffer->list);
1976 stream->curr_buf_toisp = buffer;
1977 }
1978 if (priv && priv->mode.rdbk_mode == RKISP_VICAP_RDBK_AUTO) {
1979 if (!active_buf)
1980 goto out_get_buf;
1981 if (stream->frame_idx == 1)
1982 active_buf->dbufs.is_first = true;
1983 active_buf->dbufs.sequence = stream->frame_idx - 1;
1984 active_buf->dbufs.timestamp = stream->readout.fs_timestamp;
1985 active_buf->fe_timestamp = ktime_get_ns();
1986 stream->last_frame_idx = stream->frame_idx;
1987 if (dev->hdr.hdr_mode == NO_HDR) {
1988 rkcif_s_rx_buffer(dev, &active_buf->dbufs);
1989 if (dev->is_support_tools && stream->tools_vdev)
1990 rkcif_rdbk_with_tools(stream, active_buf);
1991 atomic_dec(&stream->buf_cnt);
1992 } else {
1993 rkcif_rdbk_frame_end_toisp(stream, active_buf);
1994 }
1995 } else {
1996 rkcif_s_rx_buffer(dev, &active_buf->dbufs);
1997 if (dev->is_support_tools && stream->tools_vdev)
1998 rkcif_rdbk_with_tools(stream, active_buf);
1999 }
2000 } else if (stream->frame_phase == CIF_CSI_FRAME1_READY) {
2001 if (stream->curr_buf_toisp == stream->next_buf_toisp)
2002 active_buf = NULL;
2003 else
2004 active_buf = stream->next_buf_toisp;
2005 buffer = list_first_entry(&stream->rx_buf_head,
2006 struct rkcif_rx_buffer, list);
2007 if (buffer) {
2008 list_del(&buffer->list);
2009 stream->next_buf_toisp = buffer;
2010 }
2011 if (priv && priv->mode.rdbk_mode == RKISP_VICAP_RDBK_AUTO) {
2012 if (!active_buf)
2013 goto out_get_buf;
2014 if (stream->frame_idx == 1)
2015 active_buf->dbufs.is_first = true;
2016 active_buf->dbufs.sequence = stream->frame_idx - 1;
2017 active_buf->dbufs.timestamp = stream->readout.fs_timestamp;
2018 active_buf->fe_timestamp = ktime_get_ns();
2019 stream->last_frame_idx = stream->frame_idx;
2020 if (dev->hdr.hdr_mode == NO_HDR) {
2021 rkcif_s_rx_buffer(dev, &active_buf->dbufs);
2022 if (dev->is_support_tools && stream->tools_vdev)
2023 rkcif_rdbk_with_tools(stream, active_buf);
2024 atomic_dec(&stream->buf_cnt);
2025 } else {
2026 rkcif_rdbk_frame_end_toisp(stream, active_buf);
2027 }
2028 } else {
2029 rkcif_s_rx_buffer(dev, &active_buf->dbufs);
2030 if (dev->is_support_tools && stream->tools_vdev)
2031 rkcif_rdbk_with_tools(stream, active_buf);
2032 }
2033 }
2034 if (stream->lack_buf_cnt)
2035 stream->lack_buf_cnt--;
2036 } else {
2037 if (priv->mode.rdbk_mode == RKISP_VICAP_ONLINE)
2038 goto out_get_buf;
2039 if (stream->lack_buf_cnt < 2)
2040 stream->lack_buf_cnt++;
2041 if (dev->hw_dev->dummy_buf.vaddr) {
2042 if (stream->frame_phase == CIF_CSI_FRAME0_READY) {
2043 active_buf = stream->curr_buf_toisp;
2044 stream->curr_buf_toisp = NULL;
2045 } else {
2046 active_buf = stream->next_buf_toisp;
2047 stream->next_buf_toisp = NULL;
2048 }
2049 } else if (stream->curr_buf_toisp && stream->next_buf_toisp &&
2050 stream->curr_buf_toisp != stream->next_buf_toisp) {
2051 if (stream->frame_phase == CIF_CSI_FRAME0_READY) {
2052 active_buf = stream->curr_buf_toisp;
2053 stream->curr_buf_toisp = stream->next_buf_toisp;
2054 buffer = stream->next_buf_toisp;
2055 } else if (stream->frame_phase == CIF_CSI_FRAME1_READY) {
2056 active_buf = stream->next_buf_toisp;
2057 stream->next_buf_toisp = stream->curr_buf_toisp;
2058 buffer = stream->curr_buf_toisp;
2059 }
2060 if (stream->cifdev->rdbk_debug)
2061 v4l2_info(&stream->cifdev->v4l2_dev,
2062 "stream[%d] hold buf %x\n",
2063 stream->id,
2064 (u32)stream->next_buf_toisp->dummy.dma_addr);
2065 }
2066 if (active_buf) {
2067 if (stream->frame_idx == 1)
2068 active_buf->dbufs.is_first = true;
2069 active_buf->dbufs.sequence = stream->frame_idx - 1;
2070 active_buf->dbufs.timestamp = stream->readout.fs_timestamp;
2071 active_buf->fe_timestamp = ktime_get_ns();
2072 stream->last_frame_idx = stream->frame_idx;
2073 if (dev->hdr.hdr_mode == NO_HDR) {
2074 rkcif_s_rx_buffer(dev, &active_buf->dbufs);
2075 if (dev->is_support_tools && stream->tools_vdev)
2076 rkcif_rdbk_with_tools(stream, active_buf);
2077 atomic_dec(&stream->buf_cnt);
2078 } else {
2079 rkcif_rdbk_frame_end_toisp(stream, active_buf);
2080 }
2081 } else {
2082 if (stream->cifdev->rdbk_debug && dev->hw_dev->dummy_buf.vaddr)
2083 v4l2_info(&stream->cifdev->v4l2_dev,
2084 "stream[%d] loss frame %d\n",
2085 stream->id,
2086 stream->frame_idx - 1);
2087 }
2088 if (dev->is_support_tools && stream->tools_vdev && stream->curr_buf_toisp)
2089 rkcif_rdbk_with_tools(stream, stream->curr_buf_toisp);
2090 }
2091
2092 out_get_buf:
2093 stream->frame_phase_cache = stream->frame_phase;
2094 if (buffer) {
2095 buff_addr_y = buffer->dummy.dma_addr;
2096 if (capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
2097 rkcif_write_buff_addr_multi_dev_combine(stream, frm_addr_y, 0,
2098 buff_addr_y, 0, false);
2099 } else {
2100 rkcif_write_register(dev, frm_addr_y, buff_addr_y);
2101 }
2102 if (dev->rdbk_debug > 1 &&
2103 stream->frame_idx < 15)
2104 v4l2_info(&dev->v4l2_dev,
2105 "stream[%d] update, seq %d, reg %x, buf %x\n",
2106 stream->id,
2107 stream->frame_idx - 1,
2108 frm_addr_y, (u32)buffer->dummy.dma_addr);
2109 } else if (dev->hw_dev->dummy_buf.vaddr && priv &&
2110 priv->mode.rdbk_mode == RKISP_VICAP_RDBK_AUTO) {
2111 buff_addr_y = dev->hw_dev->dummy_buf.dma_addr;
2112 if (capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
2113 rkcif_write_buff_addr_multi_dev_combine(stream, frm_addr_y, 0,
2114 buff_addr_y, 0, true);
2115 } else {
2116 rkcif_write_register(dev, frm_addr_y, buff_addr_y);
2117 }
2118 }
2119 spin_unlock_irqrestore(&stream->vbq_lock, flags);
2120 return 0;
2121 }
2122
rkcif_assign_new_buffer_pingpong_toisp(struct rkcif_stream * stream,int init,int channel_id)2123 static int rkcif_assign_new_buffer_pingpong_toisp(struct rkcif_stream *stream,
2124 int init, int channel_id)
2125 {
2126 int ret = 0;
2127
2128 if (init)
2129 rkcif_assign_new_buffer_init_toisp(stream, channel_id);
2130 else
2131 ret = rkcif_assign_new_buffer_update_toisp(stream, channel_id);
2132 return ret;
2133 }
2134
rkcif_assign_check_buffer_update_toisp(struct rkcif_stream * stream)2135 void rkcif_assign_check_buffer_update_toisp(struct rkcif_stream *stream)
2136 {
2137 struct rkcif_device *dev = stream->cifdev;
2138 struct v4l2_mbus_config *mbus_cfg = &dev->active_sensor->mbus;
2139 struct rkcif_rx_buffer *buffer = NULL;
2140 struct rkmodule_capture_info *capture_info = &dev->channels[stream->id].capture_info;
2141 struct rkcif_rx_buffer *active_buf = NULL;
2142 u32 frm_addr_y, buff_addr_y;
2143 u32 vblank = 0;
2144 u32 vblank_ns = 0;
2145 u64 cur_time = 0;
2146 int frame_phase = 0;
2147 int frame_phase_next = 0;
2148 bool is_early_update = false;
2149
2150 if (stream->curr_buf_toisp != stream->next_buf_toisp) {
2151 if (dev->rdbk_debug > 2 &&
2152 stream->frame_idx < 15)
2153 v4l2_info(&dev->v4l2_dev,
2154 "stream[%d] addr check not equal 0x%x 0x%x\n",
2155 stream->id,
2156 (u32)stream->curr_buf_toisp->dummy.dma_addr,
2157 (u32)stream->next_buf_toisp->dummy.dma_addr);
2158 return;
2159 }
2160 if (!dev->sensor_linetime)
2161 dev->sensor_linetime = rkcif_get_linetime(stream);
2162 vblank = rkcif_get_sensor_vblank(dev);
2163 vblank_ns = vblank * dev->sensor_linetime;
2164 cur_time = ktime_get_ns();
2165
2166 if (dev->chip_id > CHIP_RK3568_CIF &&
2167 dev->hdr.hdr_mode == NO_HDR &&
2168 cur_time - stream->readout.fe_timestamp < (vblank_ns - 500000) &&
2169 stream->lack_buf_cnt == 2 &&
2170 stream->frame_idx > stream->last_frame_idx) {
2171 is_early_update = true;
2172 frame_phase = stream->frame_phase & CIF_CSI_FRAME0_READY ?
2173 CIF_CSI_FRAME1_READY : CIF_CSI_FRAME0_READY;
2174 frame_phase_next = stream->frame_phase & CIF_CSI_FRAME0_READY ?
2175 CIF_CSI_FRAME0_READY : CIF_CSI_FRAME1_READY;
2176 } else {
2177 frame_phase = stream->frame_phase;
2178 }
2179 if (dev->rdbk_debug > 2 &&
2180 stream->frame_idx < 15)
2181 v4l2_info(&dev->v4l2_dev,
2182 "stream[%d] check update, cur %lld, fe %lld, vb %u lack_buf %d\n",
2183 stream->id,
2184 cur_time, stream->readout.fe_timestamp,
2185 vblank_ns, stream->lack_buf_cnt);
2186 if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY ||
2187 mbus_cfg->type == V4L2_MBUS_CSI2_CPHY ||
2188 mbus_cfg->type == V4L2_MBUS_CCP2) {
2189 frm_addr_y = frame_phase & CIF_CSI_FRAME0_READY ?
2190 get_reg_index_of_frm0_y_addr(stream->id) :
2191 get_reg_index_of_frm1_y_addr(stream->id);
2192 } else {
2193 frm_addr_y = frame_phase & CIF_CSI_FRAME0_READY ?
2194 get_dvp_reg_index_of_frm0_y_addr(stream->id) :
2195 get_dvp_reg_index_of_frm1_y_addr(stream->id);
2196 }
2197 if (!list_empty(&stream->rx_buf_head)) {
2198 if (frame_phase == CIF_CSI_FRAME0_READY) {
2199 active_buf = stream->curr_buf_toisp;
2200 buffer = list_first_entry(&stream->rx_buf_head,
2201 struct rkcif_rx_buffer, list);
2202 if (buffer) {
2203 list_del(&buffer->list);
2204 stream->curr_buf_toisp = buffer;
2205 buff_addr_y = stream->curr_buf_toisp->dummy.dma_addr;
2206 if (capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
2207 rkcif_write_buff_addr_multi_dev_combine(stream,
2208 frm_addr_y, 0,
2209 buff_addr_y, 0,
2210 false);
2211 } else {
2212 rkcif_write_register(dev, frm_addr_y, buff_addr_y);
2213 }
2214 if (dev->rdbk_debug > 1 &&
2215 stream->frame_idx < 15)
2216 v4l2_info(&dev->v4l2_dev,
2217 "stream[%d] check update, seq %d, addr 0x%x, buf 0x%x\n",
2218 stream->id,
2219 stream->frame_idx - 1, frm_addr_y,
2220 (u32)stream->curr_buf_toisp->dummy.dma_addr);
2221 }
2222 } else if (frame_phase == CIF_CSI_FRAME1_READY) {
2223 active_buf = stream->next_buf_toisp;
2224 buffer = list_first_entry(&stream->rx_buf_head,
2225 struct rkcif_rx_buffer, list);
2226 if (buffer) {
2227 list_del(&buffer->list);
2228 stream->next_buf_toisp = buffer;
2229 buff_addr_y = stream->next_buf_toisp->dummy.dma_addr;
2230 if (capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
2231 rkcif_write_buff_addr_multi_dev_combine(stream,
2232 frm_addr_y, 0,
2233 buff_addr_y, 0,
2234 false);
2235 } else {
2236 rkcif_write_register(dev, frm_addr_y, buff_addr_y);
2237 }
2238 if (dev->rdbk_debug > 1 &&
2239 stream->frame_idx < 15)
2240 v4l2_info(&dev->v4l2_dev,
2241 "stream[%d] check update, seq %d, addr 0x%x, buf 0x%x\n",
2242 stream->id,
2243 stream->frame_idx - 1, frm_addr_y,
2244 (u32)stream->next_buf_toisp->dummy.dma_addr);
2245 }
2246 }
2247 if (stream->lack_buf_cnt)
2248 stream->lack_buf_cnt--;
2249 }
2250 if (is_early_update) {
2251 if (dev->rdbk_debug > 1 &&
2252 stream->frame_idx < 15)
2253 v4l2_info(&dev->v4l2_dev,
2254 "stream[%d] early update, seq %d\n",
2255 stream->id,
2256 stream->frame_idx - 1);
2257 if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY ||
2258 mbus_cfg->type == V4L2_MBUS_CSI2_CPHY)
2259 rkcif_write_register_or(dev, CIF_REG_MIPI_LVDS_CTRL, 0x00010000);
2260 else
2261 rkcif_write_register_or(dev, CIF_REG_DVP_CTRL, 0x00010000);
2262 if (active_buf) {
2263 active_buf->dbufs.sequence = stream->frame_idx - 1;
2264 active_buf->dbufs.timestamp = stream->readout.fs_timestamp;
2265 stream->last_frame_idx = stream->frame_idx;
2266 rkcif_s_rx_buffer(dev, &active_buf->dbufs);
2267 }
2268 if (dev->hw_dev->dummy_buf.vaddr)
2269 return;
2270 if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY ||
2271 mbus_cfg->type == V4L2_MBUS_CSI2_CPHY ||
2272 mbus_cfg->type == V4L2_MBUS_CCP2) {
2273 frm_addr_y = frame_phase_next & CIF_CSI_FRAME0_READY ?
2274 get_reg_index_of_frm0_y_addr(stream->id) :
2275 get_reg_index_of_frm1_y_addr(stream->id);
2276 } else {
2277 frm_addr_y = frame_phase_next & CIF_CSI_FRAME0_READY ?
2278 get_dvp_reg_index_of_frm0_y_addr(stream->id) :
2279 get_dvp_reg_index_of_frm1_y_addr(stream->id);
2280 }
2281 if (frame_phase == CIF_CSI_FRAME0_READY)
2282 stream->next_buf_toisp = stream->curr_buf_toisp;
2283 else
2284 stream->curr_buf_toisp = stream->next_buf_toisp;
2285 buff_addr_y = stream->curr_buf_toisp->dummy.dma_addr;
2286 if (capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
2287 rkcif_write_buff_addr_multi_dev_combine(stream, frm_addr_y, 0,
2288 buff_addr_y, 0, false);
2289 } else {
2290 rkcif_write_register(dev, frm_addr_y, buff_addr_y);
2291 }
2292 }
2293 }
2294
rkcif_assign_new_buffer_init(struct rkcif_stream * stream,int channel_id)2295 static void rkcif_assign_new_buffer_init(struct rkcif_stream *stream,
2296 int channel_id)
2297 {
2298 struct rkcif_device *dev = stream->cifdev;
2299 struct v4l2_mbus_config *mbus_cfg = &dev->active_sensor->mbus;
2300 u32 frm0_addr_y, frm0_addr_uv;
2301 u32 frm1_addr_y, frm1_addr_uv;
2302 u32 buff_addr_y, buff_addr_cbcr;
2303 unsigned long flags;
2304 struct rkcif_dummy_buffer *dummy_buf = &dev->hw_dev->dummy_buf;
2305 struct csi_channel_info *channel = &dev->channels[channel_id];
2306
2307 if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY ||
2308 mbus_cfg->type == V4L2_MBUS_CSI2_CPHY ||
2309 mbus_cfg->type == V4L2_MBUS_CCP2) {
2310 frm0_addr_y = get_reg_index_of_frm0_y_addr(channel_id);
2311 frm0_addr_uv = get_reg_index_of_frm0_uv_addr(channel_id);
2312 frm1_addr_y = get_reg_index_of_frm1_y_addr(channel_id);
2313 frm1_addr_uv = get_reg_index_of_frm1_uv_addr(channel_id);
2314 } else {
2315 frm0_addr_y = get_dvp_reg_index_of_frm0_y_addr(channel_id);
2316 frm0_addr_uv = get_dvp_reg_index_of_frm0_uv_addr(channel_id);
2317 frm1_addr_y = get_dvp_reg_index_of_frm1_y_addr(channel_id);
2318 frm1_addr_uv = get_dvp_reg_index_of_frm1_uv_addr(channel_id);
2319 }
2320
2321 spin_lock_irqsave(&stream->vbq_lock, flags);
2322
2323 if (!stream->curr_buf) {
2324 if (!list_empty(&stream->buf_head)) {
2325 stream->curr_buf = list_first_entry(&stream->buf_head,
2326 struct rkcif_buffer,
2327 queue);
2328 list_del(&stream->curr_buf->queue);
2329 }
2330 }
2331
2332 if (stream->curr_buf) {
2333 buff_addr_y = stream->curr_buf->buff_addr[RKCIF_PLANE_Y];
2334 buff_addr_cbcr = stream->curr_buf->buff_addr[RKCIF_PLANE_CBCR];
2335 if (channel->capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
2336 rkcif_write_buff_addr_multi_dev_combine(stream,
2337 frm0_addr_y,
2338 frm0_addr_uv,
2339 buff_addr_y,
2340 buff_addr_cbcr,
2341 false);
2342 } else {
2343 rkcif_write_register(dev, frm0_addr_y,
2344 stream->curr_buf->buff_addr[RKCIF_PLANE_Y]);
2345 if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
2346 rkcif_write_register(dev, frm0_addr_uv,
2347 stream->curr_buf->buff_addr[RKCIF_PLANE_CBCR]);
2348 }
2349 } else {
2350 if (dummy_buf->vaddr) {
2351 buff_addr_y = dummy_buf->dma_addr;
2352 buff_addr_cbcr = dummy_buf->dma_addr;
2353 if (channel->capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
2354 rkcif_write_buff_addr_multi_dev_combine(stream,
2355 frm0_addr_y,
2356 frm0_addr_uv,
2357 buff_addr_y,
2358 buff_addr_cbcr,
2359 true);
2360 } else {
2361 rkcif_write_register(dev, frm0_addr_y, buff_addr_y);
2362 if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
2363 rkcif_write_register(dev, frm0_addr_uv, buff_addr_cbcr);
2364 }
2365 } else {
2366 if (stream->lack_buf_cnt < 2)
2367 stream->lack_buf_cnt++;
2368 }
2369 }
2370
2371 if (stream->cif_fmt_in->field == V4L2_FIELD_INTERLACED) {
2372 stream->next_buf = stream->curr_buf;
2373 if (stream->next_buf) {
2374 buff_addr_y = stream->next_buf->buff_addr[RKCIF_PLANE_Y];
2375 buff_addr_cbcr = stream->next_buf->buff_addr[RKCIF_PLANE_CBCR];
2376 if (channel->capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
2377 rkcif_write_buff_addr_multi_dev_combine(stream,
2378 frm1_addr_y,
2379 frm1_addr_uv,
2380 buff_addr_y,
2381 buff_addr_cbcr,
2382 false);
2383 } else {
2384 rkcif_write_register(dev, frm1_addr_y,
2385 buff_addr_y + (channel->virtual_width / 2));
2386 if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
2387 rkcif_write_register(dev, frm1_addr_uv,
2388 buff_addr_cbcr + (channel->virtual_width / 2));
2389 }
2390 }
2391 } else {
2392 if (!stream->next_buf) {
2393 if (!list_empty(&stream->buf_head)) {
2394 stream->next_buf = list_first_entry(&stream->buf_head,
2395 struct rkcif_buffer, queue);
2396 list_del(&stream->next_buf->queue);
2397 }
2398 }
2399
2400 if (!stream->next_buf && dummy_buf->vaddr) {
2401 buff_addr_y = dummy_buf->dma_addr;
2402 buff_addr_cbcr = dummy_buf->dma_addr;
2403 if (channel->capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
2404 rkcif_write_buff_addr_multi_dev_combine(stream,
2405 frm1_addr_y,
2406 frm1_addr_uv,
2407 buff_addr_y,
2408 buff_addr_cbcr,
2409 true);
2410 } else {
2411 rkcif_write_register(dev, frm1_addr_y, dummy_buf->dma_addr);
2412 if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
2413 rkcif_write_register(dev, frm1_addr_uv, dummy_buf->dma_addr);
2414 }
2415
2416 } else if (!stream->next_buf && stream->curr_buf) {
2417 stream->next_buf = stream->curr_buf;
2418 if (stream->lack_buf_cnt < 2)
2419 stream->lack_buf_cnt++;
2420 }
2421 if (stream->next_buf) {
2422 buff_addr_y = stream->next_buf->buff_addr[RKCIF_PLANE_Y];
2423 buff_addr_cbcr = stream->next_buf->buff_addr[RKCIF_PLANE_CBCR];
2424 if (channel->capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
2425 rkcif_write_buff_addr_multi_dev_combine(stream,
2426 frm1_addr_y,
2427 frm1_addr_uv,
2428 buff_addr_y,
2429 buff_addr_cbcr,
2430 false);
2431 } else {
2432 rkcif_write_register(dev, frm1_addr_y, buff_addr_y);
2433 if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
2434 rkcif_write_register(dev, frm1_addr_uv, buff_addr_cbcr);
2435 }
2436 }
2437 }
2438 spin_unlock_irqrestore(&stream->vbq_lock, flags);
2439
2440 stream->is_dvp_yuv_addr_init = true;
2441
2442 /* for BT.656/BT.1120 multi channels function,
2443 * yuv addr of unused channel must be set
2444 */
2445 if (mbus_cfg->type == V4L2_MBUS_BT656) {
2446 int ch_id;
2447
2448 for (ch_id = 0; ch_id < RKCIF_MAX_STREAM_DVP; ch_id++) {
2449 if (dev->stream[ch_id].is_dvp_yuv_addr_init)
2450 continue;
2451 if (dummy_buf->dma_addr) {
2452 rkcif_write_register(dev,
2453 get_dvp_reg_index_of_frm0_y_addr(ch_id),
2454 dummy_buf->dma_addr);
2455 rkcif_write_register(dev,
2456 get_dvp_reg_index_of_frm0_uv_addr(ch_id),
2457 dummy_buf->dma_addr);
2458 rkcif_write_register(dev,
2459 get_dvp_reg_index_of_frm1_y_addr(ch_id),
2460 dummy_buf->dma_addr);
2461 rkcif_write_register(dev,
2462 get_dvp_reg_index_of_frm1_uv_addr(ch_id),
2463 dummy_buf->dma_addr);
2464 }
2465 }
2466 }
2467 stream->buf_owner = RKCIF_DMAEN_BY_VICAP;
2468 }
2469
rkcif_assign_new_buffer_update(struct rkcif_stream * stream,int channel_id)2470 static int rkcif_assign_new_buffer_update(struct rkcif_stream *stream,
2471 int channel_id)
2472 {
2473 struct rkcif_device *dev = stream->cifdev;
2474 struct rkcif_dummy_buffer *dummy_buf = &dev->hw_dev->dummy_buf;
2475 struct v4l2_mbus_config *mbus_cfg = &dev->active_sensor->mbus;
2476 struct rkcif_buffer *buffer = NULL;
2477 u32 frm_addr_y, frm_addr_uv;
2478 struct csi_channel_info *channel = &dev->channels[channel_id];
2479 struct rkisp_rx_buf *dbufs = NULL;
2480 struct dma_buf *dbuf = NULL;
2481 int ret = 0;
2482 u32 buff_addr_y, buff_addr_cbcr;
2483 unsigned long flags;
2484
2485 if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY ||
2486 mbus_cfg->type == V4L2_MBUS_CSI2_CPHY ||
2487 mbus_cfg->type == V4L2_MBUS_CCP2) {
2488 frm_addr_y = stream->frame_phase & CIF_CSI_FRAME0_READY ?
2489 get_reg_index_of_frm0_y_addr(channel_id) :
2490 get_reg_index_of_frm1_y_addr(channel_id);
2491 frm_addr_uv = stream->frame_phase & CIF_CSI_FRAME0_READY ?
2492 get_reg_index_of_frm0_uv_addr(channel_id) :
2493 get_reg_index_of_frm1_uv_addr(channel_id);
2494 } else {
2495 frm_addr_y = stream->frame_phase & CIF_CSI_FRAME0_READY ?
2496 get_dvp_reg_index_of_frm0_y_addr(channel_id) :
2497 get_dvp_reg_index_of_frm1_y_addr(channel_id);
2498 frm_addr_uv = stream->frame_phase & CIF_CSI_FRAME0_READY ?
2499 get_dvp_reg_index_of_frm0_uv_addr(channel_id) :
2500 get_dvp_reg_index_of_frm1_uv_addr(channel_id);
2501 }
2502
2503 if (dev->hdr.hdr_mode != NO_HDR && stream->id != 0 && (!dev->rdbk_buf[RDBK_L])) {
2504 v4l2_dbg(3, rkcif_debug, &dev->v4l2_dev, "%s %d\n", __func__, __LINE__);
2505 return -EINVAL;
2506 }
2507
2508 if (stream->to_stop_dma) {
2509 if (stream->dma_en & RKCIF_DMAEN_BY_ISP) {
2510 v4l2_dbg(3, rkcif_debug, &dev->v4l2_dev, "%s %d\n", __func__, __LINE__);
2511 goto stop_dma;
2512 } else {
2513 v4l2_dbg(3, rkcif_debug, &dev->v4l2_dev, "%s %d\n", __func__, __LINE__);
2514 return -EINVAL;
2515 }
2516 }
2517
2518 spin_lock_irqsave(&stream->vbq_lock, flags);
2519 if (!list_empty(&stream->buf_head)) {
2520
2521 if (!dummy_buf->vaddr &&
2522 stream->curr_buf == stream->next_buf &&
2523 stream->cif_fmt_in->field != V4L2_FIELD_INTERLACED)
2524 ret = -EINVAL;
2525
2526 if (stream->frame_phase == CIF_CSI_FRAME0_READY) {
2527 if (!stream->curr_buf)
2528 ret = -EINVAL;
2529 stream->curr_buf = list_first_entry(&stream->buf_head,
2530 struct rkcif_buffer, queue);
2531 if (stream->curr_buf) {
2532 list_del(&stream->curr_buf->queue);
2533 buffer = stream->curr_buf;
2534 v4l2_dbg(3, rkcif_debug, &dev->v4l2_dev,
2535 "stream[%d] update curr_buf 0x%x\n",
2536 stream->id, buffer->buff_addr[0]);
2537 }
2538 } else if (stream->frame_phase == CIF_CSI_FRAME1_READY) {
2539 if (!stream->next_buf)
2540 ret = -EINVAL;
2541 if (stream->cif_fmt_in->field == V4L2_FIELD_INTERLACED) {
2542 if (stream->next_buf != stream->curr_buf) {
2543 stream->next_buf = stream->curr_buf;
2544 buffer = stream->next_buf;
2545 } else {
2546 buffer = NULL;
2547 }
2548
2549 } else {
2550 stream->next_buf = list_first_entry(&stream->buf_head,
2551 struct rkcif_buffer, queue);
2552 if (stream->next_buf) {
2553 list_del(&stream->next_buf->queue);
2554 buffer = stream->next_buf;
2555 v4l2_dbg(3, rkcif_debug, &dev->v4l2_dev,
2556 "stream[%d] update next_buf 0x%x\n",
2557 stream->id, buffer->buff_addr[0]);
2558 }
2559 }
2560 }
2561 } else if (!(stream->dma_en & RKCIF_DMAEN_BY_ISP)) {
2562 buffer = NULL;
2563 if (dummy_buf->vaddr) {
2564 if (stream->frame_phase == CIF_CSI_FRAME0_READY) {
2565 stream->curr_buf = NULL;
2566 } else if (stream->frame_phase == CIF_CSI_FRAME1_READY) {
2567 if (stream->cif_fmt_in->field == V4L2_FIELD_INTERLACED) {
2568 stream->next_buf = stream->curr_buf;
2569 buffer = stream->next_buf;
2570 } else {
2571 stream->next_buf = NULL;
2572 }
2573 }
2574 } else if (stream->curr_buf && stream->next_buf &&
2575 stream->curr_buf != stream->next_buf) {
2576 if (stream->frame_phase == CIF_CSI_FRAME0_READY) {
2577 stream->curr_buf = stream->next_buf;
2578 buffer = stream->next_buf;
2579 } else if (stream->frame_phase == CIF_CSI_FRAME1_READY) {
2580 stream->next_buf = stream->curr_buf;
2581 buffer = stream->curr_buf;
2582 }
2583 if (stream->lack_buf_cnt < 2)
2584 stream->lack_buf_cnt++;
2585 } else {
2586 stream->curr_buf = NULL;
2587 stream->next_buf = NULL;
2588 if (stream->lack_buf_cnt < 2)
2589 stream->lack_buf_cnt++;
2590 }
2591 }
2592 stream->frame_phase_cache = stream->frame_phase;
2593
2594 if (buffer) {
2595 buff_addr_y = buffer->buff_addr[RKCIF_PLANE_Y];
2596 buff_addr_cbcr = buffer->buff_addr[RKCIF_PLANE_CBCR];
2597 if (stream->cif_fmt_in->field == V4L2_FIELD_INTERLACED &&
2598 stream->frame_phase == CIF_CSI_FRAME1_READY) {
2599 if (channel->capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
2600 rkcif_write_buff_addr_multi_dev_combine(stream,
2601 frm_addr_y,
2602 frm_addr_uv,
2603 buff_addr_y,
2604 buff_addr_cbcr,
2605 false);
2606 } else {
2607 rkcif_write_register(dev, frm_addr_y,
2608 buff_addr_y + (channel->virtual_width / 2));
2609 if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
2610 rkcif_write_register(dev, frm_addr_uv,
2611 buff_addr_cbcr + (channel->virtual_width / 2));
2612 }
2613 } else {
2614 if (channel->capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
2615 rkcif_write_buff_addr_multi_dev_combine(stream,
2616 frm_addr_y,
2617 frm_addr_uv,
2618 buff_addr_y,
2619 buff_addr_cbcr,
2620 false);
2621 } else {
2622 rkcif_write_register(dev, frm_addr_y, buff_addr_y);
2623 if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
2624 rkcif_write_register(dev, frm_addr_uv, buff_addr_cbcr);
2625 }
2626 }
2627 if (stream->dma_en & RKCIF_DMAEN_BY_ISP) {
2628 if (stream->buf_replace_cnt < 2)
2629 stream->buf_replace_cnt++;
2630 if (stream->frame_phase == CIF_CSI_FRAME0_READY &&
2631 stream->next_buf)
2632 dbuf = stream->next_buf->dbuf;
2633 else if (stream->frame_phase == CIF_CSI_FRAME1_READY &&
2634 stream->curr_buf)
2635 dbuf = stream->curr_buf->dbuf;
2636
2637 if (dbuf) {
2638 list_for_each_entry(dbufs, &stream->rx_buf_head_vicap, list) {
2639 if (dbufs->dbuf == dbuf)
2640 break;
2641 }
2642 }
2643 if (dbufs)
2644 rkcif_s_rx_buffer(dev, dbufs);
2645 }
2646 } else {
2647 if (stream->dma_en & RKCIF_DMAEN_BY_ISP) {
2648 buff_addr_y = stream->curr_buf_toisp->dummy.dma_addr;
2649 if (channel->capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE)
2650 rkcif_write_buff_addr_multi_dev_combine(stream,
2651 frm_addr_y, 0,
2652 buff_addr_y, 0, false);
2653 else
2654 rkcif_write_register(dev, frm_addr_y, buff_addr_y);
2655 if (stream->frame_phase == CIF_CSI_FRAME0_READY &&
2656 stream->next_buf)
2657 dbuf = stream->next_buf->dbuf;
2658 else if (stream->frame_phase == CIF_CSI_FRAME1_READY &&
2659 stream->curr_buf)
2660 dbuf = stream->curr_buf->dbuf;
2661
2662 if (dbuf) {
2663 list_for_each_entry(dbufs, &stream->rx_buf_head_vicap, list)
2664 if (dbufs->dbuf == dbuf)
2665 break;
2666 } else {
2667 dbufs = &stream->curr_buf_toisp->dbufs;
2668 }
2669 rkcif_s_rx_buffer(dev, dbufs);
2670 if (stream->curr_buf && stream->frame_phase == CIF_CSI_FRAME0_READY) {
2671 stream->curr_buf = NULL;
2672 if (stream->buf_replace_cnt)
2673 stream->buf_replace_cnt--;
2674 } else if (stream->next_buf && stream->frame_phase == CIF_CSI_FRAME1_READY) {
2675 stream->next_buf = NULL;
2676 if (stream->buf_replace_cnt)
2677 stream->buf_replace_cnt--;
2678 }
2679 } else if (dummy_buf->vaddr) {
2680
2681 if (channel->capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
2682 buff_addr_y = dummy_buf->dma_addr;
2683 buff_addr_cbcr = dummy_buf->dma_addr;
2684 rkcif_write_buff_addr_multi_dev_combine(stream,
2685 frm_addr_y,
2686 frm_addr_uv,
2687 buff_addr_y,
2688 buff_addr_cbcr,
2689 true);
2690 } else {
2691 rkcif_write_register(dev, frm_addr_y, dummy_buf->dma_addr);
2692 if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
2693 rkcif_write_register(dev, frm_addr_uv, dummy_buf->dma_addr);
2694 }
2695 dev->err_state |= (RKCIF_ERR_ID0_NOT_BUF << stream->id);
2696 dev->irq_stats.not_active_buf_cnt[stream->id]++;
2697
2698 } else {
2699 ret = -EINVAL;
2700 stream->curr_buf = NULL;
2701 stream->next_buf = NULL;
2702 dev->err_state |= (RKCIF_ERR_ID0_NOT_BUF << stream->id);
2703 dev->irq_stats.not_active_buf_cnt[stream->id]++;
2704 }
2705 }
2706 spin_unlock_irqrestore(&stream->vbq_lock, flags);
2707 return ret;
2708 stop_dma:
2709 if (stream->buf_replace_cnt) {
2710 spin_lock_irqsave(&stream->vbq_lock, flags);
2711 buff_addr_y = stream->curr_buf_toisp->dummy.dma_addr;
2712 if (channel->capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE)
2713 rkcif_write_buff_addr_multi_dev_combine(stream,
2714 frm_addr_y, 0,
2715 buff_addr_y, 0, false);
2716 else
2717 rkcif_write_register(dev, frm_addr_y, buff_addr_y);
2718 if (stream->frame_phase == CIF_CSI_FRAME0_READY &&
2719 stream->next_buf)
2720 dbuf = stream->next_buf->dbuf;
2721 else if (stream->frame_phase == CIF_CSI_FRAME1_READY &&
2722 stream->curr_buf)
2723 dbuf = stream->curr_buf->dbuf;
2724
2725 if (dbuf) {
2726 list_for_each_entry(dbufs, &stream->rx_buf_head_vicap, list)
2727 if (dbufs->dbuf == dbuf)
2728 break;
2729 } else {
2730 dbufs = &stream->curr_buf_toisp->dbufs;
2731 }
2732 if (dbufs)
2733 rkcif_s_rx_buffer(dev, dbufs);
2734
2735 if (stream->frame_phase == CIF_CSI_FRAME0_READY &&
2736 stream->curr_buf) {
2737 list_add_tail(&stream->curr_buf->queue, &stream->buf_head);
2738 stream->curr_buf = NULL;
2739 } else if (stream->frame_phase == CIF_CSI_FRAME1_READY &&
2740 stream->next_buf) {
2741 list_add_tail(&stream->next_buf->queue, &stream->buf_head);
2742 stream->next_buf = NULL;
2743 }
2744 stream->buf_replace_cnt--;
2745 spin_unlock_irqrestore(&stream->vbq_lock, flags);
2746 }
2747 return -EINVAL;
2748 }
2749
rkcif_get_new_buffer_wake_up_mode(struct rkcif_stream * stream)2750 static int rkcif_get_new_buffer_wake_up_mode(struct rkcif_stream *stream)
2751 {
2752 struct rkcif_device *dev = stream->cifdev;
2753 struct rkcif_dummy_buffer *dummy_buf = &dev->hw_dev->dummy_buf;
2754 int ret = 0;
2755 unsigned long flags;
2756
2757 spin_lock_irqsave(&stream->vbq_lock, flags);
2758 if (!list_empty(&stream->buf_head)) {
2759 if (!dummy_buf->vaddr &&
2760 stream->curr_buf == stream->next_buf)
2761 ret = -EINVAL;
2762 if (stream->line_int_cnt % 2) {
2763 stream->curr_buf = list_first_entry(&stream->buf_head,
2764 struct rkcif_buffer, queue);
2765 if (stream->curr_buf)
2766 list_del(&stream->curr_buf->queue);
2767 } else {
2768 stream->next_buf = list_first_entry(&stream->buf_head,
2769 struct rkcif_buffer, queue);
2770 if (stream->next_buf)
2771 list_del(&stream->next_buf->queue);
2772 }
2773 stream->is_buf_active = true;
2774 if (stream->lack_buf_cnt)
2775 stream->lack_buf_cnt--;
2776 } else {
2777 stream->is_buf_active = false;
2778 if (dummy_buf->vaddr) {
2779 if (stream->line_int_cnt % 2)
2780 stream->curr_buf = NULL;
2781 else
2782 stream->next_buf = NULL;
2783 } else if (stream->curr_buf != stream->next_buf) {
2784 if (stream->line_int_cnt % 2) {
2785 stream->curr_buf = stream->next_buf;
2786 stream->frame_phase_cache = CIF_CSI_FRAME0_READY;
2787 } else {
2788 stream->next_buf = stream->curr_buf;
2789 stream->frame_phase_cache = CIF_CSI_FRAME1_READY;
2790 }
2791 stream->is_buf_active = true;
2792 if (stream->lack_buf_cnt < 2)
2793 stream->lack_buf_cnt++;
2794 } else {
2795 if (dev->chip_id < CHIP_RK3588_CIF)
2796 ret = -EINVAL;
2797 else
2798 ret = 0;
2799 if (stream->lack_buf_cnt < 2)
2800 stream->lack_buf_cnt++;
2801 }
2802 }
2803 spin_unlock_irqrestore(&stream->vbq_lock, flags);
2804
2805 return ret;
2806 }
2807
rkcif_update_new_buffer_wake_up_mode(struct rkcif_stream * stream)2808 static int rkcif_update_new_buffer_wake_up_mode(struct rkcif_stream *stream)
2809 {
2810 struct rkcif_device *dev = stream->cifdev;
2811 struct rkcif_dummy_buffer *dummy_buf = &dev->hw_dev->dummy_buf;
2812 struct v4l2_mbus_config *mbus_cfg = &dev->active_sensor->mbus;
2813 struct rkmodule_capture_info *capture_info = &dev->channels[stream->id].capture_info;
2814 struct rkcif_buffer *buffer = NULL;
2815 u32 frm_addr_y, frm_addr_uv;
2816 u32 buff_addr_y, buff_addr_cbcr;
2817 int channel_id = stream->id;
2818 int ret = 0;
2819 unsigned long flags;
2820
2821 if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY ||
2822 mbus_cfg->type == V4L2_MBUS_CSI2_CPHY ||
2823 mbus_cfg->type == V4L2_MBUS_CCP2) {
2824 frm_addr_y = stream->frame_phase & CIF_CSI_FRAME0_READY ?
2825 get_reg_index_of_frm0_y_addr(channel_id) :
2826 get_reg_index_of_frm1_y_addr(channel_id);
2827 frm_addr_uv = stream->frame_phase & CIF_CSI_FRAME0_READY ?
2828 get_reg_index_of_frm0_uv_addr(channel_id) :
2829 get_reg_index_of_frm1_uv_addr(channel_id);
2830 } else {
2831 frm_addr_y = stream->frame_phase & CIF_CSI_FRAME0_READY ?
2832 get_dvp_reg_index_of_frm0_y_addr(channel_id) :
2833 get_dvp_reg_index_of_frm1_y_addr(channel_id);
2834 frm_addr_uv = stream->frame_phase & CIF_CSI_FRAME0_READY ?
2835 get_dvp_reg_index_of_frm0_uv_addr(channel_id) :
2836 get_dvp_reg_index_of_frm1_uv_addr(channel_id);
2837 }
2838 spin_lock_irqsave(&stream->vbq_lock, flags);
2839 if (stream->is_buf_active) {
2840 if (stream->frame_phase == CIF_CSI_FRAME0_READY)
2841 buffer = stream->curr_buf;
2842 else if (stream->frame_phase == CIF_CSI_FRAME1_READY)
2843 buffer = stream->next_buf;
2844 }
2845 spin_unlock_irqrestore(&stream->vbq_lock, flags);
2846 if (buffer) {
2847 buff_addr_y = buffer->buff_addr[RKCIF_PLANE_Y];
2848 buff_addr_cbcr = buffer->buff_addr[RKCIF_PLANE_CBCR];
2849 if (capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
2850 rkcif_write_buff_addr_multi_dev_combine(stream, frm_addr_y,
2851 frm_addr_uv,
2852 buff_addr_y,
2853 buff_addr_cbcr,
2854 false);
2855 } else {
2856 rkcif_write_register(dev, frm_addr_y, buff_addr_y);
2857 if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
2858 rkcif_write_register(dev, frm_addr_uv, buff_addr_cbcr);
2859 }
2860 } else {
2861 if (dummy_buf->vaddr) {
2862 buff_addr_y = dummy_buf->dma_addr;
2863 buff_addr_cbcr = dummy_buf->dma_addr;
2864 if (capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
2865 rkcif_write_buff_addr_multi_dev_combine(stream,
2866 frm_addr_y,
2867 frm_addr_uv,
2868 buff_addr_y,
2869 buff_addr_cbcr,
2870 true);
2871 } else {
2872 rkcif_write_register(dev, frm_addr_y, buff_addr_y);
2873 if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
2874 rkcif_write_register(dev, frm_addr_uv, buff_addr_cbcr);
2875 }
2876 } else {
2877 if (dev->chip_id < CHIP_RK3588_CIF)
2878 ret = -EINVAL;
2879 else
2880 ret = 0;
2881 }
2882 dev->err_state |= (RKCIF_ERR_ID0_NOT_BUF << stream->id);
2883 dev->irq_stats.not_active_buf_cnt[stream->id]++;
2884 }
2885
2886 return ret;
2887 }
2888
rkcif_get_new_buffer_wake_up_mode_rdbk(struct rkcif_stream * stream)2889 static int rkcif_get_new_buffer_wake_up_mode_rdbk(struct rkcif_stream *stream)
2890 {
2891 struct rkcif_rx_buffer *buffer = NULL;
2892 struct rkcif_device *dev = stream->cifdev;
2893 struct v4l2_mbus_config *mbus_cfg = &dev->active_sensor->mbus;
2894 int ret = 0;
2895 unsigned long flags;
2896 u32 frm_addr_y;
2897 int frame_phase = 0;
2898
2899 spin_lock_irqsave(&stream->vbq_lock, flags);
2900 if (!list_empty(&stream->rx_buf_head)) {
2901 if (stream->line_int_cnt % 2) {
2902 buffer = list_first_entry(&stream->rx_buf_head,
2903 struct rkcif_rx_buffer, list);
2904 if (buffer) {
2905 list_del(&buffer->list);
2906 stream->curr_buf_toisp = buffer;
2907 }
2908 frame_phase = CIF_CSI_FRAME0_READY;
2909 } else {
2910 buffer = list_first_entry(&stream->rx_buf_head,
2911 struct rkcif_rx_buffer, list);
2912 if (buffer) {
2913 list_del(&buffer->list);
2914 stream->next_buf_toisp = buffer;
2915 }
2916 frame_phase = CIF_CSI_FRAME1_READY;
2917 }
2918 if (stream->lack_buf_cnt)
2919 stream->lack_buf_cnt--;
2920 } else {
2921 if (stream->lack_buf_cnt < 2)
2922 stream->lack_buf_cnt++;
2923 if (stream->curr_buf_toisp && stream->next_buf_toisp &&
2924 stream->curr_buf_toisp != stream->next_buf_toisp) {
2925 if (stream->line_int_cnt % 2)
2926 stream->curr_buf_toisp = stream->next_buf_toisp;
2927 else
2928 stream->next_buf_toisp = stream->curr_buf_toisp;
2929 buffer = stream->curr_buf_toisp;
2930 ret = 0;
2931 if (stream->cifdev->rdbk_debug)
2932 v4l2_info(&stream->cifdev->v4l2_dev,
2933 "stream[%d] hold buf %x\n",
2934 stream->id,
2935 (u32)stream->next_buf_toisp->dummy.dma_addr);
2936 } else {
2937 ret = -EINVAL;
2938 }
2939 }
2940 if (buffer) {
2941 if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY ||
2942 mbus_cfg->type == V4L2_MBUS_CSI2_CPHY ||
2943 mbus_cfg->type == V4L2_MBUS_CCP2) {
2944 frm_addr_y = frame_phase & CIF_CSI_FRAME0_READY ?
2945 get_reg_index_of_frm0_y_addr(stream->id) :
2946 get_reg_index_of_frm1_y_addr(stream->id);
2947 } else {
2948 frm_addr_y = frame_phase & CIF_CSI_FRAME0_READY ?
2949 get_dvp_reg_index_of_frm0_y_addr(stream->id) :
2950 get_dvp_reg_index_of_frm1_y_addr(stream->id);
2951 }
2952 rkcif_write_register(dev, frm_addr_y,
2953 buffer->dummy.dma_addr);
2954 if (dev->rdbk_debug > 1 &&
2955 stream->frame_idx < 15)
2956 v4l2_info(&dev->v4l2_dev,
2957 "stream[%d] rdbk update, seq %d, reg %x, buf %x\n",
2958 stream->id,
2959 stream->frame_idx - 1,
2960 frm_addr_y, (u32)buffer->dummy.dma_addr);
2961 }
2962 spin_unlock_irqrestore(&stream->vbq_lock, flags);
2963
2964 return ret;
2965 }
2966
rkcif_assign_dummy_buffer(struct rkcif_stream * stream)2967 static void rkcif_assign_dummy_buffer(struct rkcif_stream *stream)
2968 {
2969 struct rkcif_device *dev = stream->cifdev;
2970 struct v4l2_mbus_config *mbus_cfg = &dev->active_sensor->mbus;
2971 struct rkcif_dummy_buffer *dummy_buf = &dev->hw_dev->dummy_buf;
2972 unsigned long flags;
2973
2974 spin_lock_irqsave(&stream->vbq_lock, flags);
2975
2976 /* for BT.656/BT.1120 multi channels function,
2977 * yuv addr of unused channel must be set
2978 */
2979 if (mbus_cfg->type == V4L2_MBUS_BT656 && dummy_buf->vaddr) {
2980 rkcif_write_register(dev,
2981 get_dvp_reg_index_of_frm0_y_addr(stream->id),
2982 dummy_buf->dma_addr);
2983 rkcif_write_register(dev,
2984 get_dvp_reg_index_of_frm0_uv_addr(stream->id),
2985 dummy_buf->dma_addr);
2986 rkcif_write_register(dev,
2987 get_dvp_reg_index_of_frm1_y_addr(stream->id),
2988 dummy_buf->dma_addr);
2989 rkcif_write_register(dev,
2990 get_dvp_reg_index_of_frm1_uv_addr(stream->id),
2991 dummy_buf->dma_addr);
2992 }
2993
2994 spin_unlock_irqrestore(&stream->vbq_lock, flags);
2995 }
2996
rkcif_assign_new_buffer_pingpong(struct rkcif_stream * stream,int init,int channel_id)2997 static int rkcif_assign_new_buffer_pingpong(struct rkcif_stream *stream,
2998 int init, int channel_id)
2999 {
3000 int ret = 0;
3001
3002 if (init)
3003 rkcif_assign_new_buffer_init(stream, channel_id);
3004 else
3005 ret = rkcif_assign_new_buffer_update(stream, channel_id);
3006 return ret;
3007 }
3008
rkcif_assign_new_buffer_init_rockit(struct rkcif_stream * stream,int channel_id)3009 static void rkcif_assign_new_buffer_init_rockit(struct rkcif_stream *stream,
3010 int channel_id)
3011 {
3012 struct rkcif_device *dev = stream->cifdev;
3013 struct v4l2_mbus_config *mbus_cfg = &dev->active_sensor->mbus;
3014 u32 frm0_addr_y, frm0_addr_uv;
3015 u32 frm1_addr_y, frm1_addr_uv;
3016 unsigned long flags;
3017 struct rkcif_dummy_buffer *dummy_buf = &dev->hw_dev->dummy_buf;
3018 struct csi_channel_info *channel = &dev->channels[channel_id];
3019
3020 if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY ||
3021 mbus_cfg->type == V4L2_MBUS_CSI2_CPHY ||
3022 mbus_cfg->type == V4L2_MBUS_CCP2) {
3023 frm0_addr_y = get_reg_index_of_frm0_y_addr(channel_id);
3024 frm0_addr_uv = get_reg_index_of_frm0_uv_addr(channel_id);
3025 frm1_addr_y = get_reg_index_of_frm1_y_addr(channel_id);
3026 frm1_addr_uv = get_reg_index_of_frm1_uv_addr(channel_id);
3027 } else {
3028 frm0_addr_y = get_dvp_reg_index_of_frm0_y_addr(channel_id);
3029 frm0_addr_uv = get_dvp_reg_index_of_frm0_uv_addr(channel_id);
3030 frm1_addr_y = get_dvp_reg_index_of_frm1_y_addr(channel_id);
3031 frm1_addr_uv = get_dvp_reg_index_of_frm1_uv_addr(channel_id);
3032 }
3033
3034 spin_lock_irqsave(&stream->vbq_lock, flags);
3035
3036 if (!stream->curr_buf_rockit) {
3037 if (!list_empty(&stream->rockit_buf_head)) {
3038 stream->curr_buf_rockit = list_first_entry(&stream->rockit_buf_head,
3039 struct rkcif_buffer,
3040 queue);
3041 list_del(&stream->curr_buf_rockit->queue);
3042 }
3043 }
3044
3045 if (stream->curr_buf_rockit) {
3046 rkcif_write_register(dev, frm0_addr_y,
3047 stream->curr_buf_rockit->buff_addr[RKCIF_PLANE_Y]);
3048 if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
3049 rkcif_write_register(dev, frm0_addr_uv,
3050 stream->curr_buf_rockit->buff_addr[RKCIF_PLANE_CBCR]);
3051 } else {
3052 if (dummy_buf->vaddr) {
3053 rkcif_write_register(dev, frm0_addr_y, dummy_buf->dma_addr);
3054 if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
3055 rkcif_write_register(dev, frm0_addr_uv, dummy_buf->dma_addr);
3056 } else {
3057 if (stream->lack_buf_cnt < 2)
3058 stream->lack_buf_cnt++;
3059 }
3060 }
3061
3062 if (stream->cif_fmt_in->field == V4L2_FIELD_INTERLACED) {
3063 stream->next_buf_rockit = stream->curr_buf_rockit;
3064 if (stream->next_buf_rockit) {
3065 rkcif_write_register(dev, frm1_addr_y,
3066 stream->next_buf_rockit->buff_addr[RKCIF_PLANE_Y] + (channel->virtual_width / 2));
3067 if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
3068 rkcif_write_register(dev, frm1_addr_uv,
3069 stream->next_buf_rockit->buff_addr[RKCIF_PLANE_CBCR] + (channel->virtual_width / 2));
3070 }
3071 } else {
3072 if (!stream->next_buf_rockit) {
3073 if (!list_empty(&stream->rockit_buf_head)) {
3074 stream->next_buf_rockit = list_first_entry(&stream->rockit_buf_head,
3075 struct rkcif_buffer, queue);
3076 list_del(&stream->next_buf_rockit->queue);
3077 }
3078 }
3079
3080 if (stream->next_buf_rockit) {
3081 rkcif_write_register(dev, frm1_addr_y,
3082 stream->next_buf_rockit->buff_addr[RKCIF_PLANE_Y]);
3083 if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
3084 rkcif_write_register(dev, frm1_addr_uv,
3085 stream->next_buf_rockit->buff_addr[RKCIF_PLANE_CBCR]);
3086 } else {
3087 if (dummy_buf->vaddr) {
3088 rkcif_write_register(dev, frm1_addr_y, dummy_buf->dma_addr);
3089 if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
3090 rkcif_write_register(dev, frm1_addr_uv, dummy_buf->dma_addr);
3091 } else {
3092 if (stream->curr_buf_rockit) {
3093 stream->next_buf_rockit = stream->curr_buf_rockit;
3094 rkcif_write_register(dev, frm1_addr_y,
3095 stream->next_buf_rockit->buff_addr[RKCIF_PLANE_Y]);
3096 if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
3097 rkcif_write_register(dev, frm1_addr_uv,
3098 stream->next_buf_rockit->buff_addr[RKCIF_PLANE_CBCR]);
3099 }
3100 if (stream->lack_buf_cnt < 2)
3101 stream->lack_buf_cnt++;
3102 }
3103 }
3104 }
3105 spin_unlock_irqrestore(&stream->vbq_lock, flags);
3106
3107 stream->is_dvp_yuv_addr_init = true;
3108
3109 /* for BT.656/BT.1120 multi channels function,
3110 * yuv addr of unused channel must be set
3111 */
3112 if (mbus_cfg->type == V4L2_MBUS_BT656) {
3113 int ch_id;
3114
3115 for (ch_id = 0; ch_id < RKCIF_MAX_STREAM_DVP; ch_id++) {
3116 if (dev->stream[ch_id].is_dvp_yuv_addr_init)
3117 continue;
3118 if (dummy_buf->dma_addr) {
3119 rkcif_write_register(dev,
3120 get_dvp_reg_index_of_frm0_y_addr(ch_id),
3121 dummy_buf->dma_addr);
3122 rkcif_write_register(dev,
3123 get_dvp_reg_index_of_frm0_uv_addr(ch_id),
3124 dummy_buf->dma_addr);
3125 rkcif_write_register(dev,
3126 get_dvp_reg_index_of_frm1_y_addr(ch_id),
3127 dummy_buf->dma_addr);
3128 rkcif_write_register(dev,
3129 get_dvp_reg_index_of_frm1_uv_addr(ch_id),
3130 dummy_buf->dma_addr);
3131 }
3132 }
3133 }
3134 stream->buf_owner = RKCIF_DMAEN_BY_ROCKIT;
3135 }
3136
rkcif_assign_new_buffer_update_rockit(struct rkcif_stream * stream,int channel_id)3137 static int rkcif_assign_new_buffer_update_rockit(struct rkcif_stream *stream,
3138 int channel_id)
3139 {
3140 struct rkcif_device *dev = stream->cifdev;
3141 struct rkcif_dummy_buffer *dummy_buf = &dev->hw_dev->dummy_buf;
3142 struct v4l2_mbus_config *mbus_cfg = &dev->active_sensor->mbus;
3143 struct rkcif_buffer *buffer = NULL;
3144 u32 frm_addr_y, frm_addr_uv;
3145 struct csi_channel_info *channel = &dev->channels[channel_id];
3146 int ret = 0;
3147 unsigned long flags;
3148
3149 if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY ||
3150 mbus_cfg->type == V4L2_MBUS_CSI2_CPHY ||
3151 mbus_cfg->type == V4L2_MBUS_CCP2) {
3152 frm_addr_y = stream->frame_phase & CIF_CSI_FRAME0_READY ?
3153 get_reg_index_of_frm0_y_addr(channel_id) :
3154 get_reg_index_of_frm1_y_addr(channel_id);
3155 frm_addr_uv = stream->frame_phase & CIF_CSI_FRAME0_READY ?
3156 get_reg_index_of_frm0_uv_addr(channel_id) :
3157 get_reg_index_of_frm1_uv_addr(channel_id);
3158 } else {
3159 frm_addr_y = stream->frame_phase & CIF_CSI_FRAME0_READY ?
3160 get_dvp_reg_index_of_frm0_y_addr(channel_id) :
3161 get_dvp_reg_index_of_frm1_y_addr(channel_id);
3162 frm_addr_uv = stream->frame_phase & CIF_CSI_FRAME0_READY ?
3163 get_dvp_reg_index_of_frm0_uv_addr(channel_id) :
3164 get_dvp_reg_index_of_frm1_uv_addr(channel_id);
3165 }
3166
3167 spin_lock_irqsave(&stream->vbq_lock, flags);
3168 if (!list_empty(&stream->rockit_buf_head)) {
3169
3170 if (!dummy_buf->vaddr &&
3171 stream->curr_buf_rockit == stream->next_buf_rockit &&
3172 stream->cif_fmt_in->field != V4L2_FIELD_INTERLACED)
3173 ret = -EINVAL;
3174
3175 if (stream->frame_phase == CIF_CSI_FRAME0_READY) {
3176 if (!stream->curr_buf_rockit)
3177 ret = -EINVAL;
3178 stream->curr_buf_rockit = list_first_entry(&stream->rockit_buf_head,
3179 struct rkcif_buffer, queue);
3180 if (stream->curr_buf_rockit) {
3181 list_del(&stream->curr_buf_rockit->queue);
3182 buffer = stream->curr_buf_rockit;
3183 }
3184 } else if (stream->frame_phase == CIF_CSI_FRAME1_READY) {
3185 if (!stream->next_buf_rockit)
3186 ret = -EINVAL;
3187 if (stream->cif_fmt_in->field == V4L2_FIELD_INTERLACED) {
3188 if (stream->next_buf_rockit != stream->curr_buf_rockit) {
3189 stream->next_buf_rockit = stream->curr_buf_rockit;
3190 buffer = stream->next_buf_rockit;
3191 } else {
3192 buffer = NULL;
3193 }
3194
3195 } else {
3196 stream->next_buf_rockit = list_first_entry(&stream->rockit_buf_head,
3197 struct rkcif_buffer, queue);
3198 if (stream->next_buf_rockit) {
3199 list_del(&stream->next_buf_rockit->queue);
3200 buffer = stream->next_buf_rockit;
3201 }
3202 }
3203 }
3204 } else {
3205 buffer = NULL;
3206 if (dummy_buf->vaddr) {
3207 if (stream->frame_phase == CIF_CSI_FRAME0_READY) {
3208 stream->curr_buf_rockit = NULL;
3209 } else if (stream->frame_phase == CIF_CSI_FRAME1_READY) {
3210 if (stream->cif_fmt_in->field == V4L2_FIELD_INTERLACED) {
3211 stream->next_buf_rockit = stream->curr_buf_rockit;
3212 buffer = stream->next_buf_rockit;
3213 } else {
3214 stream->next_buf_rockit = NULL;
3215 }
3216 }
3217 } else if (stream->curr_buf_rockit && stream->next_buf_rockit &&
3218 stream->curr_buf_rockit != stream->next_buf_rockit) {
3219 if (stream->frame_phase == CIF_CSI_FRAME0_READY) {
3220 stream->curr_buf_rockit = stream->next_buf_rockit;
3221 buffer = stream->next_buf_rockit;
3222 } else if (stream->frame_phase == CIF_CSI_FRAME1_READY) {
3223 stream->next_buf_rockit = stream->curr_buf_rockit;
3224 buffer = stream->curr_buf_rockit;
3225 }
3226 if (stream->lack_buf_cnt < 2)
3227 stream->lack_buf_cnt++;
3228 } else {
3229 if (stream->lack_buf_cnt < 2)
3230 stream->lack_buf_cnt++;
3231 }
3232 }
3233 stream->frame_phase_cache = stream->frame_phase;
3234
3235 if (buffer) {
3236 if (stream->cif_fmt_in->field == V4L2_FIELD_INTERLACED &&
3237 stream->frame_phase == CIF_CSI_FRAME1_READY) {
3238 rkcif_write_register(dev, frm_addr_y,
3239 buffer->buff_addr[RKCIF_PLANE_Y] + (channel->virtual_width / 2));
3240 if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
3241 rkcif_write_register(dev, frm_addr_uv,
3242 buffer->buff_addr[RKCIF_PLANE_CBCR] + (channel->virtual_width / 2));
3243 } else {
3244 rkcif_write_register(dev, frm_addr_y,
3245 buffer->buff_addr[RKCIF_PLANE_Y]);
3246 if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
3247 rkcif_write_register(dev, frm_addr_uv,
3248 buffer->buff_addr[RKCIF_PLANE_CBCR]);
3249 }
3250 } else {
3251 if (dummy_buf->vaddr) {
3252 rkcif_write_register(dev, frm_addr_y, dummy_buf->dma_addr);
3253 if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
3254 rkcif_write_register(dev, frm_addr_uv, dummy_buf->dma_addr);
3255 dev->err_state |= (RKCIF_ERR_ID0_NOT_BUF << stream->id);
3256 dev->irq_stats.not_active_buf_cnt[stream->id]++;
3257 } else {
3258 ret = -EINVAL;
3259 dev->err_state |= (RKCIF_ERR_ID0_NOT_BUF << stream->id);
3260 dev->irq_stats.not_active_buf_cnt[stream->id]++;
3261 }
3262 }
3263 spin_unlock_irqrestore(&stream->vbq_lock, flags);
3264 return ret;
3265 }
3266
rkcif_assign_new_buffer_pingpong_rockit(struct rkcif_stream * stream,int init,int channel_id)3267 static int rkcif_assign_new_buffer_pingpong_rockit(struct rkcif_stream *stream,
3268 int init, int channel_id)
3269 {
3270 int ret = 0;
3271
3272 if (init)
3273 rkcif_assign_new_buffer_init_rockit(stream, channel_id);
3274 else
3275 ret = rkcif_assign_new_buffer_update_rockit(stream, channel_id);
3276 return ret;
3277 }
3278
rkcif_csi_get_vc_num(struct rkcif_device * dev,unsigned int mbus_flags)3279 static void rkcif_csi_get_vc_num(struct rkcif_device *dev,
3280 unsigned int mbus_flags)
3281 {
3282 int i, vc_num = 0;
3283
3284 for (i = 0; i < RKCIF_MAX_CSI_CHANNEL; i++) {
3285 if (mbus_flags & V4L2_MBUS_CSI2_CHANNEL_0) {
3286 dev->channels[vc_num].vc = vc_num;
3287 vc_num++;
3288 mbus_flags ^= V4L2_MBUS_CSI2_CHANNEL_0;
3289 continue;
3290 }
3291 if (mbus_flags & V4L2_MBUS_CSI2_CHANNEL_1) {
3292 dev->channels[vc_num].vc = vc_num;
3293 vc_num++;
3294 mbus_flags ^= V4L2_MBUS_CSI2_CHANNEL_1;
3295 continue;
3296 }
3297
3298 if (mbus_flags & V4L2_MBUS_CSI2_CHANNEL_2) {
3299 dev->channels[vc_num].vc = vc_num;
3300 vc_num++;
3301 mbus_flags ^= V4L2_MBUS_CSI2_CHANNEL_2;
3302 continue;
3303 }
3304
3305 if (mbus_flags & V4L2_MBUS_CSI2_CHANNEL_3) {
3306 dev->channels[vc_num].vc = vc_num;
3307 vc_num++;
3308 mbus_flags ^= V4L2_MBUS_CSI2_CHANNEL_3;
3309 continue;
3310 }
3311 }
3312
3313 dev->num_channels = vc_num ? vc_num : 1;
3314 if (dev->num_channels == 1)
3315 dev->channels[0].vc = 0;
3316 }
3317
rkcif_csi_set_lvds_sav_eav(struct rkcif_stream * stream,struct csi_channel_info * channel)3318 static void rkcif_csi_set_lvds_sav_eav(struct rkcif_stream *stream,
3319 struct csi_channel_info *channel)
3320 {
3321 struct rkcif_device *dev = stream->cifdev;
3322 struct rkmodule_lvds_cfg *lvds_cfg = &channel->lvds_cfg;
3323 struct rkmodule_lvds_frame_sync_code *frm_sync_code = NULL;
3324 struct rkmodule_lvds_frm_sync_code *odd_sync_code = NULL;
3325 struct rkmodule_lvds_frm_sync_code *even_sync_code = NULL;
3326
3327 if (dev->hdr.hdr_mode == NO_HDR || dev->hdr.hdr_mode == HDR_COMPR) {
3328 frm_sync_code = &lvds_cfg->frm_sync_code[LVDS_CODE_GRP_LINEAR];
3329 odd_sync_code = &frm_sync_code->odd_sync_code;
3330 even_sync_code = odd_sync_code;
3331 } else {
3332 if (channel->id == RKCIF_STREAM_MIPI_ID0)
3333 frm_sync_code = &lvds_cfg->frm_sync_code[LVDS_CODE_GRP_LONG];
3334
3335 if (dev->hdr.hdr_mode == HDR_X2) {
3336 if (channel->id == RKCIF_STREAM_MIPI_ID1)
3337 frm_sync_code = &lvds_cfg->frm_sync_code[LVDS_CODE_GRP_SHORT];
3338 else
3339 frm_sync_code = &lvds_cfg->frm_sync_code[LVDS_CODE_GRP_LONG];
3340 } else if (dev->hdr.hdr_mode == HDR_X3) {
3341 if (channel->id == RKCIF_STREAM_MIPI_ID1)
3342 frm_sync_code = &lvds_cfg->frm_sync_code[LVDS_CODE_GRP_MEDIUM];
3343 else if (channel->id == RKCIF_STREAM_MIPI_ID2)
3344 frm_sync_code = &lvds_cfg->frm_sync_code[LVDS_CODE_GRP_SHORT];
3345 else
3346 frm_sync_code = &lvds_cfg->frm_sync_code[LVDS_CODE_GRP_LONG];
3347 }
3348
3349 odd_sync_code = &frm_sync_code->odd_sync_code;
3350 even_sync_code = &frm_sync_code->even_sync_code;
3351 }
3352
3353 if (odd_sync_code && even_sync_code) {
3354 rkcif_write_register(stream->cifdev,
3355 get_reg_index_of_lvds_sav_eav_act0(channel->id),
3356 SW_LVDS_EAV_ACT(odd_sync_code->act.eav) |
3357 SW_LVDS_SAV_ACT(odd_sync_code->act.sav));
3358
3359 rkcif_write_register(stream->cifdev,
3360 get_reg_index_of_lvds_sav_eav_blk0(channel->id),
3361 SW_LVDS_EAV_BLK(odd_sync_code->blk.eav) |
3362 SW_LVDS_SAV_BLK(odd_sync_code->blk.sav));
3363
3364 rkcif_write_register(stream->cifdev,
3365 get_reg_index_of_lvds_sav_eav_act1(channel->id),
3366 SW_LVDS_EAV_ACT(even_sync_code->act.eav) |
3367 SW_LVDS_SAV_ACT(even_sync_code->act.sav));
3368
3369 rkcif_write_register(stream->cifdev,
3370 get_reg_index_of_lvds_sav_eav_blk1(channel->id),
3371 SW_LVDS_EAV_BLK(even_sync_code->blk.eav) |
3372 SW_LVDS_SAV_BLK(even_sync_code->blk.sav));
3373 }
3374 }
3375
get_csi_fmt_val(const struct cif_input_fmt * cif_fmt_in,struct csi_channel_info * csi_info)3376 static unsigned char get_csi_fmt_val(const struct cif_input_fmt *cif_fmt_in,
3377 struct csi_channel_info *csi_info)
3378 {
3379 unsigned char csi_fmt_val = 0;
3380
3381 if (cif_fmt_in->mbus_code == MEDIA_BUS_FMT_SPD_2X8 ||
3382 cif_fmt_in->mbus_code == MEDIA_BUS_FMT_EBD_1X8) {
3383 switch (csi_info->data_bit) {
3384 case 8:
3385 csi_fmt_val = CSI_WRDDR_TYPE_RAW8;
3386 break;
3387 case 10:
3388 csi_fmt_val = CSI_WRDDR_TYPE_RAW10;
3389 break;
3390 case 12:
3391 csi_fmt_val = CSI_WRDDR_TYPE_RAW12;
3392 break;
3393 default:
3394 csi_fmt_val = CSI_WRDDR_TYPE_RAW12;
3395 break;
3396 }
3397 } else if (cif_fmt_in->csi_fmt_val == CSI_WRDDR_TYPE_RGB888 ||
3398 cif_fmt_in->csi_fmt_val == CSI_WRDDR_TYPE_RGB565) {
3399 csi_fmt_val = CSI_WRDDR_TYPE_RAW8;
3400 } else {
3401 csi_fmt_val = cif_fmt_in->csi_fmt_val;
3402 }
3403 return csi_fmt_val;
3404 }
3405
rkcif_csi_channel_init(struct rkcif_stream * stream,struct csi_channel_info * channel)3406 static int rkcif_csi_channel_init(struct rkcif_stream *stream,
3407 struct csi_channel_info *channel)
3408 {
3409 struct rkcif_device *dev = stream->cifdev;
3410 struct sditf_priv *priv = dev->sditf[0];
3411 const struct cif_output_fmt *fmt;
3412 u32 fourcc;
3413 int vc = dev->channels[stream->id].vc;
3414
3415 channel->enable = 1;
3416 channel->width = stream->pixm.width;
3417 channel->height = stream->pixm.height;
3418
3419 channel->fmt_val = stream->cif_fmt_out->csi_fmt_val;
3420
3421 channel->cmd_mode_en = 0; /* default use DSI Video Mode */
3422 channel->dsi_input = dev->terminal_sensor.dsi_input_en;
3423
3424 if (stream->crop_enable) {
3425 channel->crop_en = 1;
3426
3427 if (channel->fmt_val == CSI_WRDDR_TYPE_RGB888)
3428 channel->crop_st_x = 3 * stream->crop[CROP_SRC_ACT].left;
3429 else if (channel->fmt_val == CSI_WRDDR_TYPE_RGB565)
3430 channel->crop_st_x = 2 * stream->crop[CROP_SRC_ACT].left;
3431 else
3432 channel->crop_st_x = stream->crop[CROP_SRC_ACT].left;
3433
3434 channel->crop_st_y = stream->crop[CROP_SRC_ACT].top;
3435 if (priv && priv->is_combine_mode && dev->sditf_cnt <= RKCIF_MAX_SDITF)
3436 channel->crop_st_y *= dev->sditf_cnt;
3437 channel->width = stream->crop[CROP_SRC_ACT].width;
3438 channel->height = stream->crop[CROP_SRC_ACT].height;
3439 } else {
3440 channel->width = stream->pixm.width;
3441 channel->height = stream->pixm.height;
3442 channel->crop_en = 0;
3443 }
3444
3445 if (priv && priv->is_combine_mode && dev->sditf_cnt <= RKCIF_MAX_SDITF)
3446 channel->height *= dev->sditf_cnt;
3447
3448 fmt = rkcif_find_output_fmt(stream, stream->pixm.pixelformat);
3449 if (!fmt) {
3450 v4l2_err(&dev->v4l2_dev, "can not find output format: 0x%x",
3451 stream->pixm.pixelformat);
3452 return -EINVAL;
3453 }
3454
3455 if (channel->capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE)
3456 channel->width /= channel->capture_info.multi_dev.dev_num;
3457 /*
3458 * for mipi or lvds, when enable compact, the virtual width of raw10/raw12
3459 * needs aligned with :ALIGN(bits_per_pixel * width / 8, 8), if enable 16bit mode
3460 * needs aligned with :ALIGN(bits_per_pixel * width * 2, 8), to optimize reading and
3461 * writing of ddr, aliged with 256
3462 */
3463 if (fmt->fmt_type == CIF_FMT_TYPE_RAW && stream->is_compact &&
3464 fmt->csi_fmt_val != CSI_WRDDR_TYPE_RGB888 &&
3465 fmt->csi_fmt_val != CSI_WRDDR_TYPE_RGB565) {
3466 if (channel->capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
3467 channel->virtual_width = ALIGN(channel->width * 2 * fmt->raw_bpp / 8, 256);
3468 channel->left_virtual_width = channel->width * fmt->raw_bpp / 8;
3469 } else {
3470 channel->virtual_width = ALIGN(channel->width * fmt->raw_bpp / 8, 256);
3471 }
3472 } else {
3473 if (channel->capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
3474 channel->virtual_width = ALIGN(channel->width * 2 * fmt->bpp[0] / 8, 8);
3475 channel->left_virtual_width = ALIGN(channel->width * fmt->bpp[0] / 8, 8);
3476 } else {
3477 channel->virtual_width = ALIGN(channel->width * fmt->bpp[0] / 8, 8);
3478 }
3479 }
3480
3481 if (channel->fmt_val == CSI_WRDDR_TYPE_RGB888 || channel->fmt_val == CSI_WRDDR_TYPE_RGB565)
3482 channel->width = channel->width * fmt->bpp[0] / 8;
3483 /*
3484 * rk cif don't support output yuyv fmt data
3485 * if user request yuyv fmt, the input mode must be RAW8
3486 * and the width is double Because the real input fmt is
3487 * yuyv
3488 */
3489 fourcc = stream->cif_fmt_out->fourcc;
3490 if (fourcc == V4L2_PIX_FMT_YUYV || fourcc == V4L2_PIX_FMT_YVYU ||
3491 fourcc == V4L2_PIX_FMT_UYVY || fourcc == V4L2_PIX_FMT_VYUY) {
3492 if (dev->chip_id < CHIP_RK3588_CIF) {
3493 channel->fmt_val = CSI_WRDDR_TYPE_RAW8;
3494 channel->width *= 2;
3495 }
3496 channel->virtual_width *= 2;
3497 if (channel->capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE)
3498 channel->left_virtual_width *= 2;
3499 }
3500 if (stream->cif_fmt_in->field == V4L2_FIELD_INTERLACED) {
3501 channel->virtual_width *= 2;
3502 channel->height /= 2;
3503 }
3504 if (stream->cif_fmt_in->mbus_code == MEDIA_BUS_FMT_EBD_1X8 ||
3505 stream->cif_fmt_in->mbus_code == MEDIA_BUS_FMT_SPD_2X8) {
3506 if (dev->channels[stream->id].data_type)
3507 channel->data_type = dev->channels[stream->id].data_type;
3508 else
3509 channel->data_type = get_data_type(stream->cif_fmt_in->mbus_code,
3510 channel->cmd_mode_en,
3511 channel->dsi_input);
3512 } else {
3513 channel->data_type = get_data_type(stream->cif_fmt_in->mbus_code,
3514 channel->cmd_mode_en,
3515 channel->dsi_input);
3516 }
3517 channel->csi_fmt_val = get_csi_fmt_val(stream->cif_fmt_in,
3518 &dev->channels[stream->id]);
3519
3520 if (dev->hdr.hdr_mode == NO_HDR ||
3521 dev->hdr.hdr_mode == HDR_COMPR ||
3522 (dev->hdr.hdr_mode == HDR_X2 && stream->id > 1) ||
3523 (dev->hdr.hdr_mode == HDR_X3 && stream->id > 2))
3524 channel->vc = vc < 4 ? vc : channel->id;
3525 else
3526 channel->vc = channel->id;
3527 v4l2_dbg(1, rkcif_debug, &dev->v4l2_dev,
3528 "%s: channel width %d, height %d, virtual_width %d, vc %d\n", __func__,
3529 channel->width, channel->height, channel->virtual_width, channel->vc);
3530 return 0;
3531 }
3532
rkcif_csi_channel_set(struct rkcif_stream * stream,struct csi_channel_info * channel,enum v4l2_mbus_type mbus_type)3533 static int rkcif_csi_channel_set(struct rkcif_stream *stream,
3534 struct csi_channel_info *channel,
3535 enum v4l2_mbus_type mbus_type)
3536 {
3537 unsigned int val = 0x0;
3538 struct rkcif_device *dev = stream->cifdev;
3539 struct rkcif_stream *detect_stream = &dev->stream[0];
3540 unsigned int wait_line = 0x3fff;
3541
3542 if (channel->id >= 4)
3543 return -EINVAL;
3544
3545 if (!channel->enable) {
3546 rkcif_write_register(dev, get_reg_index_of_id_ctrl0(channel->id),
3547 CSI_DISABLE_CAPTURE);
3548 return 0;
3549 }
3550
3551 rkcif_write_register_and(dev, CIF_REG_MIPI_LVDS_INTSTAT,
3552 ~(CSI_START_INTSTAT(channel->id) |
3553 CSI_DMA_END_INTSTAT(channel->id) |
3554 CSI_LINE_INTSTAT(channel->id)));
3555
3556 rkcif_write_register_or(dev, CIF_REG_MIPI_LVDS_INTEN,
3557 CSI_START_INTEN(channel->id));
3558
3559 if (detect_stream->is_line_wake_up) {
3560 rkcif_write_register_or(dev, CIF_REG_MIPI_LVDS_INTEN,
3561 CSI_LINE_INTEN(channel->id));
3562 wait_line = dev->wait_line;
3563 }
3564 rkcif_write_register(dev, CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID0_1,
3565 wait_line << 16 | wait_line);
3566 rkcif_write_register(dev, CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID2_3,
3567 wait_line << 16 | wait_line);
3568
3569 rkcif_write_register_or(dev, CIF_REG_MIPI_LVDS_INTEN,
3570 CSI_DMA_END_INTEN(channel->id));
3571 rkcif_write_register(dev, CIF_REG_MIPI_WATER_LINE,
3572 CIF_MIPI_LVDS_SW_WATER_LINE_25_RK1808 |
3573 CIF_MIPI_LVDS_SW_WATER_LINE_ENABLE_RK1808 |
3574 CIF_MIPI_LVDS_SW_HURRY_VALUE_RK1808(0x3) |
3575 CIF_MIPI_LVDS_SW_HURRY_ENABLE_RK1808);
3576
3577 val = CIF_MIPI_LVDS_SW_PRESS_VALUE(0x3) |
3578 CIF_MIPI_LVDS_SW_PRESS_ENABLE |
3579 CIF_MIPI_LVDS_SW_HURRY_VALUE(0x3) |
3580 CIF_MIPI_LVDS_SW_HURRY_ENABLE |
3581 CIF_MIPI_LVDS_SW_WATER_LINE_25 |
3582 CIF_MIPI_LVDS_SW_WATER_LINE_ENABLE;
3583 if (mbus_type == V4L2_MBUS_CSI2_DPHY) {
3584 val &= ~CIF_MIPI_LVDS_SW_SEL_LVDS;
3585 } else if (mbus_type == V4L2_MBUS_CCP2) {
3586 if (channel->fmt_val == CSI_WRDDR_TYPE_RAW12)
3587 val |= CIF_MIPI_LVDS_SW_LVDS_WIDTH_12BITS;
3588 else if (channel->fmt_val == CSI_WRDDR_TYPE_RAW10)
3589 val |= CIF_MIPI_LVDS_SW_LVDS_WIDTH_10BITS;
3590 else
3591 val |= CIF_MIPI_LVDS_SW_LVDS_WIDTH_8BITS;
3592 val |= CIF_MIPI_LVDS_SW_SEL_LVDS;
3593 }
3594 rkcif_write_register(dev, CIF_REG_MIPI_LVDS_CTRL, val);
3595
3596 rkcif_write_register_or(dev, CIF_REG_MIPI_LVDS_INTEN,
3597 CSI_ALL_ERROR_INTEN);
3598
3599 rkcif_write_register(dev, get_reg_index_of_id_ctrl1(channel->id),
3600 channel->width | (channel->height << 16));
3601
3602 rkcif_write_register(dev, get_reg_index_of_frm0_y_vlw(channel->id),
3603 channel->virtual_width);
3604 rkcif_write_register(dev, get_reg_index_of_frm1_y_vlw(channel->id),
3605 channel->virtual_width);
3606 rkcif_write_register(dev, get_reg_index_of_frm0_uv_vlw(channel->id),
3607 channel->virtual_width);
3608 rkcif_write_register(dev, get_reg_index_of_frm1_uv_vlw(channel->id),
3609 channel->virtual_width);
3610
3611 if (channel->crop_en)
3612 rkcif_write_register(dev, get_reg_index_of_id_crop_start(channel->id),
3613 channel->crop_st_y << 16 | channel->crop_st_x);
3614
3615 /* Set up an buffer for the next frame */
3616 rkcif_assign_new_buffer_pingpong(stream,
3617 RKCIF_YUV_ADDR_STATE_INIT,
3618 channel->id);
3619
3620 if (mbus_type == V4L2_MBUS_CSI2_DPHY) {
3621 //need always enable crop
3622 val = CSI_ENABLE_CAPTURE | channel->fmt_val |
3623 channel->cmd_mode_en << 4 | CSI_ENABLE_CROP |
3624 channel->vc << 8 | channel->data_type << 10;
3625 if (stream->is_compact)
3626 val |= CSI_ENABLE_MIPI_COMPACT;
3627 else
3628 val &= ~CSI_ENABLE_MIPI_COMPACT;
3629
3630 if (stream->cifdev->chip_id >= CHIP_RK3568_CIF)
3631 val |= stream->cif_fmt_in->csi_yuv_order;
3632 } else if (mbus_type == V4L2_MBUS_CCP2) {
3633 rkcif_csi_set_lvds_sav_eav(stream, channel);
3634 val = LVDS_ENABLE_CAPTURE | LVDS_MODE(channel->lvds_cfg.mode) |
3635 LVDS_MAIN_LANE(0) | LVDS_FID(0) |
3636 LVDS_LANES_ENABLED(dev->active_sensor->lanes);
3637
3638 if (stream->is_compact)
3639 val |= LVDS_COMPACT;
3640 else
3641 val &= ~LVDS_COMPACT;
3642 }
3643 if (stream->is_high_align)
3644 val |= CSI_HIGH_ALIGN;
3645 else
3646 val &= ~CSI_HIGH_ALIGN;
3647 rkcif_write_register(dev, get_reg_index_of_id_ctrl0(channel->id), val);
3648
3649 return 0;
3650 }
3651
rkcif_dvp_get_input_yuv_order(struct rkcif_stream * stream)3652 static int rkcif_dvp_get_input_yuv_order(struct rkcif_stream *stream)
3653 {
3654 unsigned int mask;
3655 const struct cif_input_fmt *fmt = stream->cif_fmt_in;
3656
3657 switch (fmt->mbus_code) {
3658 case MEDIA_BUS_FMT_UYVY8_2X8:
3659 mask = CSI_YUV_INPUT_ORDER_UYVY >> 11;
3660 break;
3661 case MEDIA_BUS_FMT_VYUY8_2X8:
3662 mask = CSI_YUV_INPUT_ORDER_VYUY >> 11;
3663 break;
3664 case MEDIA_BUS_FMT_YUYV8_2X8:
3665 mask = CSI_YUV_INPUT_ORDER_YUYV >> 11;
3666 break;
3667 case MEDIA_BUS_FMT_YVYU8_2X8:
3668 mask = CSI_YUV_INPUT_ORDER_YVYU >> 11;
3669 break;
3670 default:
3671 mask = CSI_YUV_INPUT_ORDER_UYVY >> 11;
3672 break;
3673 }
3674 return mask;
3675 }
3676
rkcif_csi_get_output_type_mask(struct rkcif_stream * stream)3677 static int rkcif_csi_get_output_type_mask(struct rkcif_stream *stream)
3678 {
3679 unsigned int mask;
3680 const struct cif_output_fmt *fmt = stream->cif_fmt_out;
3681
3682 switch (fmt->fourcc) {
3683 case V4L2_PIX_FMT_NV16:
3684 mask = CSI_WRDDR_TYPE_YUV422SP_RK3588 | CSI_YUV_OUTPUT_ORDER_UYVY;
3685 break;
3686 case V4L2_PIX_FMT_NV61:
3687 mask = CSI_WRDDR_TYPE_YUV422SP_RK3588 | CSI_YUV_OUTPUT_ORDER_VYUY;
3688 break;
3689 case V4L2_PIX_FMT_NV12:
3690 mask = CSI_WRDDR_TYPE_YUV420SP_RK3588 | CSI_YUV_OUTPUT_ORDER_UYVY;
3691 break;
3692 case V4L2_PIX_FMT_NV21:
3693 mask = CSI_WRDDR_TYPE_YUV420SP_RK3588 | CSI_YUV_OUTPUT_ORDER_VYUY;
3694 break;
3695 case V4L2_PIX_FMT_YUYV:
3696 mask = CSI_WRDDR_TYPE_YUV_PACKET | CSI_YUV_OUTPUT_ORDER_YUYV;
3697 break;
3698 case V4L2_PIX_FMT_YVYU:
3699 mask = CSI_WRDDR_TYPE_YUV_PACKET | CSI_YUV_OUTPUT_ORDER_YVYU;
3700 break;
3701 case V4L2_PIX_FMT_UYVY:
3702 mask = CSI_WRDDR_TYPE_YUV_PACKET | CSI_YUV_OUTPUT_ORDER_UYVY;
3703 break;
3704 case V4L2_PIX_FMT_VYUY:
3705 mask = CSI_WRDDR_TYPE_YUV_PACKET | CSI_YUV_OUTPUT_ORDER_VYUY;
3706 break;
3707 case V4L2_PIX_FMT_RGB24:
3708 case V4L2_PIX_FMT_BGR24:
3709 case V4L2_PIX_FMT_RGB565:
3710 case V4L2_PIX_FMT_BGR666:
3711 mask = CSI_WRDDR_TYPE_RAW_COMPACT;
3712 break;
3713 case V4L2_PIX_FMT_SRGGB8:
3714 case V4L2_PIX_FMT_SGRBG8:
3715 case V4L2_PIX_FMT_SGBRG8:
3716 case V4L2_PIX_FMT_SBGGR8:
3717 case V4L2_PIX_FMT_SRGGB10:
3718 case V4L2_PIX_FMT_SGRBG10:
3719 case V4L2_PIX_FMT_SGBRG10:
3720 case V4L2_PIX_FMT_SBGGR10:
3721 case V4L2_PIX_FMT_SRGGB12:
3722 case V4L2_PIX_FMT_SGRBG12:
3723 case V4L2_PIX_FMT_SGBRG12:
3724 case V4L2_PIX_FMT_SBGGR12:
3725 case V4L2_PIX_FMT_GREY:
3726 case V4L2_PIX_FMT_Y10:
3727 case V4L2_PIX_FMT_Y12:
3728 if (stream->is_compact)
3729 mask = CSI_WRDDR_TYPE_RAW_COMPACT;
3730 else
3731 mask = CSI_WRDDR_TYPE_RAW_UNCOMPACT;
3732 break;
3733 case V4L2_PIX_FMT_SBGGR16:
3734 case V4L2_PIX_FMT_SGBRG16:
3735 case V4L2_PIX_FMT_SGRBG16:
3736 case V4L2_PIX_FMT_SRGGB16:
3737 case V4L2_PIX_FMT_Y16:
3738 mask = CSI_WRDDR_TYPE_RAW_UNCOMPACT;
3739 break;
3740 default:
3741 mask = CSI_WRDDR_TYPE_RAW_COMPACT;
3742 break;
3743 }
3744 return mask;
3745 }
3746
rkcif_lvds_get_output_type_mask(struct rkcif_stream * stream)3747 static int rkcif_lvds_get_output_type_mask(struct rkcif_stream *stream)
3748 {
3749 unsigned int mask;
3750 const struct cif_output_fmt *fmt = stream->cif_fmt_out;
3751 int wr_type_offset = 0;
3752 int yuvout_offset = 0;
3753
3754 if (stream->cifdev->chip_id == CHIP_RV1106_CIF) {
3755 wr_type_offset = 17;
3756 yuvout_offset = 9;
3757 }
3758
3759 switch (fmt->fourcc) {
3760 case V4L2_PIX_FMT_NV16:
3761 mask = (CSI_WRDDR_TYPE_YUV422SP_RK3588 << wr_type_offset) |
3762 (CSI_YUV_OUTPUT_ORDER_UYVY << yuvout_offset);
3763 break;
3764 case V4L2_PIX_FMT_NV61:
3765 mask = (CSI_WRDDR_TYPE_YUV422SP_RK3588 << wr_type_offset) |
3766 (CSI_YUV_OUTPUT_ORDER_VYUY << yuvout_offset);
3767 break;
3768 case V4L2_PIX_FMT_NV12:
3769 mask = (CSI_WRDDR_TYPE_YUV420SP_RK3588 << wr_type_offset) |
3770 (CSI_YUV_OUTPUT_ORDER_UYVY << yuvout_offset);
3771 break;
3772 case V4L2_PIX_FMT_NV21:
3773 mask = (CSI_WRDDR_TYPE_YUV420SP_RK3588 << wr_type_offset) |
3774 (CSI_YUV_OUTPUT_ORDER_VYUY << yuvout_offset);
3775 break;
3776 case V4L2_PIX_FMT_YUYV:
3777 mask = (CSI_WRDDR_TYPE_YUV_PACKET << wr_type_offset) |
3778 (CSI_YUV_OUTPUT_ORDER_YUYV << yuvout_offset);
3779 break;
3780 case V4L2_PIX_FMT_YVYU:
3781 mask = (CSI_WRDDR_TYPE_YUV_PACKET << wr_type_offset) |
3782 (CSI_YUV_OUTPUT_ORDER_YVYU << yuvout_offset);
3783 break;
3784 case V4L2_PIX_FMT_UYVY:
3785 mask = (CSI_WRDDR_TYPE_YUV_PACKET << wr_type_offset) |
3786 (CSI_YUV_OUTPUT_ORDER_UYVY << yuvout_offset);
3787 break;
3788 case V4L2_PIX_FMT_VYUY:
3789 mask = (CSI_WRDDR_TYPE_YUV_PACKET << wr_type_offset) |
3790 (CSI_YUV_OUTPUT_ORDER_VYUY << yuvout_offset);
3791 break;
3792 case V4L2_PIX_FMT_RGB24:
3793 case V4L2_PIX_FMT_BGR24:
3794 case V4L2_PIX_FMT_RGB565:
3795 case V4L2_PIX_FMT_BGR666:
3796 mask = CSI_WRDDR_TYPE_RAW_COMPACT << wr_type_offset;
3797 break;
3798 case V4L2_PIX_FMT_SRGGB8:
3799 case V4L2_PIX_FMT_SGRBG8:
3800 case V4L2_PIX_FMT_SGBRG8:
3801 case V4L2_PIX_FMT_SBGGR8:
3802 case V4L2_PIX_FMT_SRGGB10:
3803 case V4L2_PIX_FMT_SGRBG10:
3804 case V4L2_PIX_FMT_SGBRG10:
3805 case V4L2_PIX_FMT_SBGGR10:
3806 case V4L2_PIX_FMT_SRGGB12:
3807 case V4L2_PIX_FMT_SGRBG12:
3808 case V4L2_PIX_FMT_SGBRG12:
3809 case V4L2_PIX_FMT_SBGGR12:
3810 case V4L2_PIX_FMT_GREY:
3811 case V4L2_PIX_FMT_Y10:
3812 case V4L2_PIX_FMT_Y12:
3813 if (stream->is_compact)
3814 mask = CSI_WRDDR_TYPE_RAW_COMPACT << wr_type_offset;
3815 else
3816 mask = CSI_WRDDR_TYPE_RAW_UNCOMPACT << wr_type_offset;
3817 break;
3818 case V4L2_PIX_FMT_SBGGR16:
3819 case V4L2_PIX_FMT_SGBRG16:
3820 case V4L2_PIX_FMT_SGRBG16:
3821 case V4L2_PIX_FMT_SRGGB16:
3822 case V4L2_PIX_FMT_Y16:
3823 mask = CSI_WRDDR_TYPE_RAW_UNCOMPACT << wr_type_offset;
3824 break;
3825 default:
3826 mask = CSI_WRDDR_TYPE_RAW_COMPACT << wr_type_offset;
3827 break;
3828 }
3829 return mask;
3830 }
3831
rkcif_modify_frame_skip_config(struct rkcif_stream * stream)3832 static void rkcif_modify_frame_skip_config(struct rkcif_stream *stream)
3833 {
3834 if (stream->skip_info.skip_to_en) {
3835 rkcif_disable_skip_frame(stream);
3836 rkcif_enable_skip_frame(stream,
3837 stream->skip_info.cap_m,
3838 stream->skip_info.skip_n);
3839 stream->skip_info.skip_to_en = false;
3840 } else if (stream->skip_info.skip_to_dis) {
3841 rkcif_disable_skip_frame(stream);
3842 }
3843 }
3844
3845 /*config reg for rk3588*/
rkcif_csi_channel_set_v1(struct rkcif_stream * stream,struct csi_channel_info * channel,enum v4l2_mbus_type mbus_type,unsigned int mode,int index)3846 static int rkcif_csi_channel_set_v1(struct rkcif_stream *stream,
3847 struct csi_channel_info *channel,
3848 enum v4l2_mbus_type mbus_type, unsigned int mode,
3849 int index)
3850 {
3851 unsigned int val = 0x0;
3852 struct rkcif_device *dev = stream->cifdev;
3853 struct rkcif_stream *detect_stream = &dev->stream[0];
3854 struct sditf_priv *priv = dev->sditf[0];
3855 struct rkmodule_capture_info *capture_info = &channel->capture_info;
3856 unsigned int wait_line = 0x3fff;
3857 unsigned int dma_en = 0;
3858 int offset = 0;
3859
3860 if (channel->id >= 4)
3861 return -EINVAL;
3862
3863 if (!channel->enable) {
3864 rkcif_write_register(dev, get_reg_index_of_id_ctrl0(channel->id),
3865 CSI_DISABLE_CAPTURE);
3866 return 0;
3867 }
3868
3869 rkcif_write_register_and(dev, CIF_REG_MIPI_LVDS_INTSTAT,
3870 ~(CSI_START_INTSTAT(channel->id) |
3871 CSI_DMA_END_INTSTAT(channel->id) |
3872 CSI_LINE_INTSTAT_V1(channel->id)));
3873
3874 if (!(capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE &&
3875 index < capture_info->multi_dev.dev_num - 1)) {
3876
3877 rkcif_write_register_or(dev, CIF_REG_MIPI_LVDS_INTEN,
3878 CSI_START_INTEN(channel->id));
3879
3880 if (priv && priv->mode.rdbk_mode && detect_stream->is_line_wake_up) {
3881 rkcif_write_register_or(dev, CIF_REG_MIPI_LVDS_INTEN,
3882 CSI_LINE_INTEN_RK3588(channel->id));
3883 wait_line = dev->wait_line;
3884 }
3885 rkcif_write_register(dev, CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID0_1,
3886 wait_line << 16 | wait_line);
3887 rkcif_write_register(dev, CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID2_3,
3888 wait_line << 16 | wait_line);
3889
3890 rkcif_write_register_or(dev, CIF_REG_MIPI_LVDS_INTEN,
3891 CSI_DMA_END_INTEN(channel->id));
3892
3893 rkcif_write_register_or(dev, CIF_REG_MIPI_LVDS_INTEN,
3894 CSI_ALL_ERROR_INTEN_V1);
3895 }
3896 if (stream->cifdev->id_use_cnt == 0) {
3897 val = CIF_MIPI_LVDS_SW_PRESS_VALUE_RK3588(0x3) |
3898 CIF_MIPI_LVDS_SW_PRESS_ENABLE |
3899 CIF_MIPI_LVDS_SW_HURRY_VALUE_RK3588(0x3) |
3900 CIF_MIPI_LVDS_SW_HURRY_ENABLE |
3901 CIF_MIPI_LVDS_SW_WATER_LINE_25 |
3902 CIF_MIPI_LVDS_SW_WATER_LINE_ENABLE;
3903 if (mbus_type == V4L2_MBUS_CSI2_DPHY ||
3904 mbus_type == V4L2_MBUS_CSI2_CPHY)
3905 val &= ~CIF_MIPI_LVDS_SW_SEL_LVDS_RV1106;
3906 else
3907 val |= CIF_MIPI_LVDS_SW_SEL_LVDS_RV1106;
3908 rkcif_write_register(dev, CIF_REG_MIPI_LVDS_CTRL, val);
3909 }
3910 #if IS_ENABLED(CONFIG_CPU_RV1106)
3911 if (channel->id == 1)
3912 rv1106_sdmmc_get_lock();
3913 #endif
3914 if (capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE &&
3915 priv && priv->mode.rdbk_mode == RKISP_VICAP_ONLINE &&
3916 (dev->hdr.hdr_mode == NO_HDR ||
3917 (dev->hdr.hdr_mode == HDR_X2 && stream->id == 1) ||
3918 (dev->hdr.hdr_mode == HDR_X3 && stream->id == 2)))
3919 offset = channel->capture_info.multi_dev.pixel_offset;
3920
3921 rkcif_write_register(dev, get_reg_index_of_id_ctrl1(channel->id),
3922 (channel->width + offset) | (channel->height << 16));
3923
3924 #if IS_ENABLED(CONFIG_CPU_RV1106)
3925 if (channel->id == 1)
3926 rv1106_sdmmc_put_lock();
3927 #endif
3928
3929 if (channel->crop_en)
3930 rkcif_write_register(dev, get_reg_index_of_id_crop_start(channel->id),
3931 channel->crop_st_y << 16 | channel->crop_st_x);
3932
3933 if (mode == RKCIF_STREAM_MODE_CAPTURE)
3934 rkcif_assign_new_buffer_pingpong(stream,
3935 RKCIF_YUV_ADDR_STATE_INIT,
3936 channel->id);
3937 else if (mode == RKCIF_STREAM_MODE_TOISP ||
3938 mode == RKCIF_STREAM_MODE_TOISP_RDBK)
3939 rkcif_assign_new_buffer_pingpong_toisp(stream,
3940 RKCIF_YUV_ADDR_STATE_INIT,
3941 channel->id);
3942 else if (mode == RKCIF_STREAM_MODE_ROCKIT)
3943 rkcif_assign_new_buffer_pingpong_rockit(stream,
3944 RKCIF_YUV_ADDR_STATE_INIT,
3945 channel->id);
3946
3947 if (capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE &&
3948 index == (capture_info->multi_dev.dev_num - 1) &&
3949 priv && priv->mode.rdbk_mode != RKISP_VICAP_ONLINE)
3950 rkcif_write_register(dev, get_reg_index_of_id_crop_start(channel->id),
3951 channel->crop_st_y << 16 |
3952 (channel->crop_st_x + capture_info->multi_dev.pixel_offset));
3953
3954 rkcif_write_register(dev, get_reg_index_of_frm0_y_vlw(channel->id),
3955 channel->virtual_width);
3956
3957 if (stream->lack_buf_cnt == 2)
3958 stream->dma_en = 0;
3959
3960 if (stream->dma_en) {
3961 if (mbus_type == V4L2_MBUS_CSI2_DPHY ||
3962 mbus_type == V4L2_MBUS_CSI2_CPHY)
3963 dma_en = CSI_DMA_ENABLE;
3964 else
3965 dma_en = LVDS_DMAEN_RV1106;
3966 }
3967 if (mbus_type == V4L2_MBUS_CSI2_DPHY ||
3968 mbus_type == V4L2_MBUS_CSI2_CPHY) {
3969
3970 if (stream->cifdev->hdr.esp.mode == HDR_LINE_CNT ||
3971 stream->cifdev->hdr.esp.mode == HDR_ID_CODE)
3972 channel->vc = 0;
3973
3974 val = CSI_ENABLE_CAPTURE | dma_en |
3975 channel->cmd_mode_en << 26 | CSI_ENABLE_CROP_V1 |
3976 channel->vc << 8 | channel->data_type << 10 |
3977 channel->csi_fmt_val;
3978
3979 val |= stream->cif_fmt_in->csi_yuv_order;
3980 val |= rkcif_csi_get_output_type_mask(stream);
3981 if (stream->cifdev->hdr.hdr_mode == NO_HDR ||
3982 stream->cifdev->hdr.hdr_mode == HDR_COMPR)
3983 val |= CSI_NO_HDR;
3984 else if (stream->cifdev->hdr.hdr_mode == HDR_X2)
3985 val |= CSI_HDR2;
3986 else if (stream->cifdev->hdr.hdr_mode == HDR_X3)
3987 val |= CSI_HDR3;
3988 if (stream->cifdev->hdr.esp.mode == HDR_NORMAL_VC)
3989 val |= CSI_HDR_MODE_VC;
3990 else if (stream->cifdev->hdr.esp.mode == HDR_LINE_CNT)
3991 val |= CSI_HDR_MODE_LINE_CNT;
3992 else if (stream->cifdev->hdr.esp.mode == HDR_ID_CODE)
3993 val |= CSI_HDR_MODE_LINE_INFO;
3994 if (stream->cifdev->hdr.hdr_mode != NO_HDR &&
3995 stream->cifdev->hdr.esp.mode == HDR_NORMAL_VC)
3996 val |= CSI_HDR_VC_MODE_PROTECT;
3997 if (stream->is_high_align)
3998 val |= CSI_HIGH_ALIGN_RK3588;
3999 else
4000 val &= ~CSI_HIGH_ALIGN_RK3588;
4001 rkcif_write_register(dev, get_reg_index_of_id_ctrl0(channel->id), val);
4002 rkcif_write_register(dev, CIF_REG_MIPI_EFFECT_CODE_ID0, 0x02410251);
4003 rkcif_write_register(dev, CIF_REG_MIPI_EFFECT_CODE_ID1, 0x02420252);
4004 } else if (mbus_type == V4L2_MBUS_CCP2) {
4005 rkcif_csi_set_lvds_sav_eav(stream, channel);
4006 val = LVDS_ENABLE_CAPTURE_RV1106 | LVDS_MODE_RV1106(channel->lvds_cfg.mode) |
4007 LVDS_MAIN_LANE_RV1106(0) | LVDS_FID_RV1106(0) |
4008 LVDS_LANES_ENABLED_RV1106(dev->active_sensor->lanes) |
4009 (channel->csi_fmt_val << 18) |
4010 rkcif_lvds_get_output_type_mask(stream) |
4011 (stream->cif_fmt_in->csi_yuv_order << 9) |
4012 dma_en;
4013 if (stream->cifdev->hdr.hdr_mode == HDR_X3)
4014 val |= BIT(12);
4015 rkcif_write_register(dev, get_reg_index_of_lvds_id_ctrl0(channel->id), val);
4016 }
4017 if (dev->chip_id >= CHIP_RV1106_CIF)
4018 rkcif_modify_frame_skip_config(stream);
4019 if (capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
4020 if (index == (capture_info->multi_dev.dev_num - 1))
4021 stream->cifdev->id_use_cnt++;
4022 } else {
4023 stream->cifdev->id_use_cnt++;
4024 }
4025 if (!(capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE &&
4026 index < capture_info->multi_dev.dev_num - 1)) {
4027 if (mode == RKCIF_STREAM_MODE_CAPTURE)
4028 rkcif_assign_new_buffer_pingpong(stream,
4029 RKCIF_YUV_ADDR_STATE_INIT,
4030 channel->id);
4031 else if (mode == RKCIF_STREAM_MODE_TOISP ||
4032 mode == RKCIF_STREAM_MODE_TOISP_RDBK)
4033 rkcif_assign_new_buffer_pingpong_toisp(stream,
4034 RKCIF_YUV_ADDR_STATE_INIT,
4035 channel->id);
4036 }
4037 return 0;
4038 }
4039
rkcif_csi_stream_start(struct rkcif_stream * stream,unsigned int mode)4040 static int rkcif_csi_stream_start(struct rkcif_stream *stream, unsigned int mode)
4041 {
4042 struct rkcif_device *dev = stream->cifdev;
4043 struct rkcif_sensor_info *active_sensor = dev->active_sensor;
4044 unsigned int flags = active_sensor->mbus.flags;
4045 enum v4l2_mbus_type mbus_type = active_sensor->mbus.type;
4046 struct csi_channel_info *channel;
4047 u32 ret = 0;
4048 int i;
4049
4050 if (stream->state < RKCIF_STATE_STREAMING) {
4051 stream->frame_idx = 0;
4052 stream->buf_wake_up_cnt = 0;
4053 stream->frame_phase = 0;
4054 stream->lack_buf_cnt = 0;
4055 stream->is_in_vblank = false;
4056 stream->is_change_toisp = false;
4057 }
4058
4059 rkcif_csi_get_vc_num(dev, flags);
4060
4061 channel = &dev->channels[stream->id];
4062 channel->id = stream->id;
4063 if (mbus_type == V4L2_MBUS_CCP2) {
4064 ret = v4l2_subdev_call(dev->terminal_sensor.sd, core,
4065 ioctl, RKMODULE_GET_LVDS_CFG,
4066 &channel->lvds_cfg);
4067 if (ret) {
4068 v4l2_err(&dev->v4l2_dev, "Err: get lvds config failed!!\n");
4069 return ret;
4070 }
4071 }
4072 rkcif_csi_channel_init(stream, channel);
4073 if (stream->state != RKCIF_STATE_STREAMING) {
4074 if (mode == RKCIF_STREAM_MODE_CAPTURE) {
4075 stream->dma_en |= RKCIF_DMAEN_BY_VICAP;
4076 } else if (mode == RKCIF_STREAM_MODE_TOISP_RDBK) {
4077 stream->dma_en |= RKCIF_DMAEN_BY_ISP;
4078 } else if (mode == RKCIF_STREAM_MODE_TOISP) {
4079 if (dev->hdr.hdr_mode == HDR_X2 &&
4080 stream->id == 0)
4081 stream->dma_en |= RKCIF_DMAEN_BY_ISP;
4082 else if (dev->hdr.hdr_mode == HDR_X3 && (stream->id == 0 || stream->id == 1))
4083 stream->dma_en |= RKCIF_DMAEN_BY_ISP;
4084 } else if (mode == RKCIF_STREAM_MODE_ROCKIT) {
4085 stream->dma_en |= RKCIF_DMAEN_BY_ROCKIT;
4086 }
4087 if (stream->cifdev->chip_id < CHIP_RK3588_CIF) {
4088 rkcif_csi_channel_set(stream, channel, mbus_type);
4089 } else {
4090 if (channel->capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
4091 for (i = 0; i < channel->capture_info.multi_dev.dev_num; i++) {
4092 dev->csi_host_idx = channel->capture_info.multi_dev.dev_idx[i];
4093 rkcif_csi_channel_set_v1(stream, channel, mbus_type, mode, i);
4094 }
4095 } else {
4096 rkcif_csi_channel_set_v1(stream, channel, mbus_type, mode, 0);
4097 }
4098 }
4099 } else {
4100 if (stream->cifdev->chip_id >= CHIP_RK3588_CIF) {
4101 if (mode == RKCIF_STREAM_MODE_CAPTURE) {
4102 stream->to_en_dma = RKCIF_DMAEN_BY_VICAP;
4103 } else if (mode == RKCIF_STREAM_MODE_TOISP_RDBK) {
4104 stream->to_en_dma = RKCIF_DMAEN_BY_ISP;
4105 } else if (mode == RKCIF_STREAM_MODE_TOISP) {
4106 if (dev->hdr.hdr_mode == HDR_X2 &&
4107 stream->id == 0 &&
4108 (!stream->dma_en))
4109 stream->to_en_dma = RKCIF_DMAEN_BY_ISP;
4110 else if (dev->hdr.hdr_mode == HDR_X3 &&
4111 (stream->id == 0 || stream->id == 1) &&
4112 (!stream->dma_en))
4113 stream->to_en_dma = RKCIF_DMAEN_BY_ISP;
4114 } else if (mode == RKCIF_STREAM_MODE_ROCKIT) {
4115 stream->to_en_dma = RKCIF_DMAEN_BY_ROCKIT;
4116 }
4117 }
4118 }
4119 if (stream->state != RKCIF_STATE_STREAMING) {
4120 stream->line_int_cnt = 0;
4121 if (stream->is_line_wake_up)
4122 stream->is_can_stop = false;
4123 else
4124 stream->is_can_stop = true;
4125 stream->state = RKCIF_STATE_STREAMING;
4126 dev->workmode = RKCIF_WORKMODE_PINGPONG;
4127 }
4128
4129 return 0;
4130 }
4131
rkcif_stream_stop(struct rkcif_stream * stream)4132 static void rkcif_stream_stop(struct rkcif_stream *stream)
4133 {
4134 struct rkcif_device *cif_dev = stream->cifdev;
4135 struct v4l2_mbus_config *mbus_cfg = &cif_dev->active_sensor->mbus;
4136 u32 val;
4137 int id;
4138 int i = 0;
4139
4140 stream->cifdev->id_use_cnt--;
4141 if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY ||
4142 mbus_cfg->type == V4L2_MBUS_CSI2_CPHY ||
4143 mbus_cfg->type == V4L2_MBUS_CCP2) {
4144 id = stream->id;
4145 val = rkcif_read_register(cif_dev, get_reg_index_of_id_ctrl0(id));
4146 if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY ||
4147 mbus_cfg->type == V4L2_MBUS_CSI2_CPHY)
4148 val &= ~(CSI_ENABLE_CAPTURE | CSI_DMA_ENABLE);
4149 else
4150 val &= ~LVDS_ENABLE_CAPTURE;
4151
4152 if (cif_dev->channels[id].capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
4153 for (i = 0; i < cif_dev->channels[id].capture_info.multi_dev.dev_num; i++) {
4154 cif_dev->csi_host_idx = cif_dev->channels[id].capture_info.multi_dev.dev_idx[i];
4155 rkcif_write_register(cif_dev, get_reg_index_of_id_ctrl0(id), val);
4156 }
4157 } else {
4158 rkcif_write_register(cif_dev, get_reg_index_of_id_ctrl0(id), val);
4159 }
4160
4161 rkcif_write_register_or(cif_dev, CIF_REG_MIPI_LVDS_INTSTAT,
4162 CSI_START_INTSTAT(id) |
4163 CSI_DMA_END_INTSTAT(id) |
4164 CSI_LINE_INTSTAT(id));
4165
4166 rkcif_write_register_and(cif_dev, CIF_REG_MIPI_LVDS_INTEN,
4167 ~(CSI_START_INTEN(id) |
4168 CSI_DMA_END_INTEN(id) |
4169 CSI_LINE_INTEN(id)));
4170
4171 if (stream->cifdev->chip_id < CHIP_RK3588_CIF) {
4172 rkcif_write_register_and(cif_dev, CIF_REG_MIPI_LVDS_INTEN,
4173 ~CSI_ALL_ERROR_INTEN);
4174 } else {
4175 if (stream->cifdev->id_use_cnt == 0) {
4176 rkcif_write_register_and(cif_dev, CIF_REG_MIPI_LVDS_INTEN,
4177 ~CSI_ALL_ERROR_INTEN_V1);
4178 if (cif_dev->channels[id].capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
4179 for (i = 0; i < cif_dev->channels[id].capture_info.multi_dev.dev_num; i++) {
4180 cif_dev->csi_host_idx = cif_dev->channels[id].capture_info.multi_dev.dev_idx[i];
4181 rkcif_write_register_and(cif_dev, CIF_REG_MIPI_LVDS_CTRL,
4182 ~CSI_ENABLE_CAPTURE);
4183 }
4184 } else {
4185 rkcif_write_register_and(cif_dev, CIF_REG_MIPI_LVDS_CTRL,
4186 ~CSI_ENABLE_CAPTURE);
4187 }
4188 }
4189 }
4190
4191 } else {
4192 if (atomic_read(&cif_dev->pipe.stream_cnt) == 1) {
4193 val = rkcif_read_register(cif_dev, CIF_REG_DVP_CTRL);
4194 rkcif_write_register(cif_dev, CIF_REG_DVP_CTRL,
4195 val & (~ENABLE_CAPTURE));
4196 rkcif_write_register(cif_dev, CIF_REG_DVP_INTEN, 0x0);
4197 rkcif_write_register(cif_dev, CIF_REG_DVP_INTSTAT, 0x3ff);
4198 rkcif_write_register(cif_dev, CIF_REG_DVP_FRAME_STATUS, 0x0);
4199 if (IS_ENABLED(CONFIG_CPU_RV1106))
4200 rkcif_config_dvp_pin(cif_dev, false);
4201 }
4202 }
4203 stream->state = RKCIF_STATE_READY;
4204 stream->dma_en = 0;
4205 }
4206
rkcif_is_extending_line_for_height(struct rkcif_device * dev,struct rkcif_stream * stream,const struct cif_input_fmt * fmt)4207 static bool rkcif_is_extending_line_for_height(struct rkcif_device *dev,
4208 struct rkcif_stream *stream,
4209 const struct cif_input_fmt *fmt)
4210 {
4211 bool is_extended = false;
4212 struct rkmodule_hdr_cfg hdr_cfg;
4213 int ret;
4214
4215 if (dev->chip_id == CHIP_RV1126_CIF ||
4216 dev->chip_id == CHIP_RV1126_CIF_LITE) {
4217 if (dev->terminal_sensor.sd) {
4218 ret = v4l2_subdev_call(dev->terminal_sensor.sd,
4219 core, ioctl,
4220 RKMODULE_GET_HDR_CFG,
4221 &hdr_cfg);
4222 if (!ret)
4223 dev->hdr = hdr_cfg;
4224 else
4225 dev->hdr.hdr_mode = NO_HDR;
4226 }
4227
4228 if (fmt && fmt->fmt_type == CIF_FMT_TYPE_RAW) {
4229 if ((dev->hdr.hdr_mode == HDR_X2 &&
4230 stream->id == RKCIF_STREAM_MIPI_ID1) ||
4231 (dev->hdr.hdr_mode == HDR_X3 &&
4232 stream->id == RKCIF_STREAM_MIPI_ID2) ||
4233 (dev->hdr.hdr_mode == NO_HDR)) {
4234 is_extended = true;
4235 }
4236 }
4237 }
4238
4239 return is_extended;
4240 }
4241
rkcif_queue_setup(struct vb2_queue * queue,unsigned int * num_buffers,unsigned int * num_planes,unsigned int sizes[],struct device * alloc_ctxs[])4242 static int rkcif_queue_setup(struct vb2_queue *queue,
4243 unsigned int *num_buffers,
4244 unsigned int *num_planes,
4245 unsigned int sizes[],
4246 struct device *alloc_ctxs[])
4247 {
4248 struct rkcif_stream *stream = queue->drv_priv;
4249 struct rkcif_extend_info *extend_line = &stream->extend_line;
4250 struct rkcif_device *dev = stream->cifdev;
4251 const struct v4l2_pix_format_mplane *pixm = NULL;
4252 const struct cif_output_fmt *cif_fmt;
4253 const struct cif_input_fmt *in_fmt;
4254 bool is_extended = false;
4255 u32 i, height;
4256
4257 pixm = &stream->pixm;
4258 cif_fmt = stream->cif_fmt_out;
4259 in_fmt = stream->cif_fmt_in;
4260
4261 *num_planes = cif_fmt->mplanes;
4262
4263 if (stream->crop_enable)
4264 height = stream->crop[CROP_SRC_ACT].height;
4265 else
4266 height = pixm->height;
4267
4268 is_extended = rkcif_is_extending_line_for_height(dev, stream, in_fmt);
4269 if (is_extended && extend_line->is_extended) {
4270 height = extend_line->pixm.height;
4271 pixm = &extend_line->pixm;
4272 }
4273
4274 for (i = 0; i < cif_fmt->mplanes; i++) {
4275 const struct v4l2_plane_pix_format *plane_fmt;
4276 int h = round_up(height, MEMORY_ALIGN_ROUND_UP_HEIGHT);
4277
4278 plane_fmt = &pixm->plane_fmt[i];
4279 sizes[i] = plane_fmt->sizeimage / height * h;
4280 }
4281 stream->total_buf_num = *num_buffers;
4282 v4l2_dbg(1, rkcif_debug, &dev->v4l2_dev, "%s count %d, size %d, extended(%d, %d)\n",
4283 v4l2_type_names[queue->type], *num_buffers, sizes[0],
4284 is_extended, extend_line->is_extended);
4285
4286 return 0;
4287 }
4288
rkcif_check_buffer_update_pingpong(struct rkcif_stream * stream,int channel_id)4289 static void rkcif_check_buffer_update_pingpong(struct rkcif_stream *stream,
4290 int channel_id)
4291 {
4292 struct rkcif_device *dev = stream->cifdev;
4293 struct v4l2_mbus_config *mbus_cfg = &dev->active_sensor->mbus;
4294 struct rkcif_buffer *buffer = NULL;
4295 struct rkcif_dummy_buffer *dummy_buf = &dev->hw_dev->dummy_buf;
4296 u32 frm_addr_y = 0, frm_addr_uv = 0;
4297 u32 frm0_addr_y = 0, frm0_addr_uv = 0;
4298 u32 frm1_addr_y = 0, frm1_addr_uv = 0;
4299 u32 buff_addr_y = 0, buff_addr_cbcr = 0;
4300 struct rkmodule_capture_info *capture_info = &dev->channels[channel_id].capture_info;
4301 unsigned long flags;
4302 int frame_phase = 0;
4303 bool is_dual_update_buf = false;
4304
4305 spin_lock_irqsave(&stream->vbq_lock, flags);
4306 if (stream->state == RKCIF_STATE_STREAMING &&
4307 ((stream->curr_buf == stream->next_buf &&
4308 stream->cif_fmt_in->field != V4L2_FIELD_INTERLACED &&
4309 (!dummy_buf->vaddr)) ||
4310 stream->curr_buf == NULL ||
4311 stream->next_buf == NULL)) {
4312 frame_phase = stream->frame_phase_cache;
4313 if (!stream->is_line_wake_up ||
4314 (stream->is_line_wake_up && stream->frame_idx < 2)) {
4315 if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY ||
4316 mbus_cfg->type == V4L2_MBUS_CSI2_CPHY ||
4317 mbus_cfg->type == V4L2_MBUS_CCP2) {
4318 frm0_addr_y = get_reg_index_of_frm0_y_addr(channel_id);
4319 frm1_addr_y = get_reg_index_of_frm1_y_addr(channel_id);
4320 frm0_addr_uv = get_reg_index_of_frm0_uv_addr(channel_id);
4321 frm1_addr_uv = get_reg_index_of_frm1_uv_addr(channel_id);
4322 } else {
4323 frm0_addr_y = get_dvp_reg_index_of_frm0_y_addr(channel_id);
4324 frm1_addr_y = get_dvp_reg_index_of_frm1_y_addr(channel_id);
4325 frm0_addr_uv = get_dvp_reg_index_of_frm0_uv_addr(channel_id);
4326 frm1_addr_uv = get_dvp_reg_index_of_frm1_uv_addr(channel_id);
4327 }
4328 if (frame_phase & CIF_CSI_FRAME0_READY) {
4329 frm_addr_y = frm0_addr_y;
4330 frm_addr_uv = frm0_addr_uv;
4331 } else {
4332 frm_addr_y = frm1_addr_y;
4333 frm_addr_uv = frm1_addr_uv;
4334 }
4335 if (!stream->dma_en && stream->curr_buf == NULL && stream->next_buf == NULL)
4336 is_dual_update_buf = true;
4337 if (!list_empty(&stream->buf_head)) {
4338 if (frame_phase == CIF_CSI_FRAME0_READY) {
4339 stream->curr_buf = list_first_entry(&stream->buf_head,
4340 struct rkcif_buffer, queue);
4341 if (stream->curr_buf) {
4342 list_del(&stream->curr_buf->queue);
4343 buffer = stream->curr_buf;
4344 }
4345 if (buffer && is_dual_update_buf)
4346 stream->next_buf = buffer;
4347 } else if (frame_phase == CIF_CSI_FRAME1_READY) {
4348 if (stream->next_buf == NULL &&
4349 stream->cif_fmt_in->field == V4L2_FIELD_INTERLACED) {
4350 stream->next_buf = stream->curr_buf;
4351 } else {
4352 stream->next_buf = list_first_entry(&stream->buf_head,
4353 struct rkcif_buffer, queue);
4354 if (stream->next_buf) {
4355 list_del(&stream->next_buf->queue);
4356 buffer = stream->next_buf;
4357 }
4358 if (buffer && is_dual_update_buf)
4359 stream->curr_buf = buffer;
4360 }
4361 }
4362 } else {
4363 v4l2_info(&dev->v4l2_dev, "%s %d\n", __func__, __LINE__);
4364 }
4365 if (buffer) {
4366 if (is_dual_update_buf) {
4367 buff_addr_y = buffer->buff_addr[RKCIF_PLANE_Y];
4368 buff_addr_cbcr = buffer->buff_addr[RKCIF_PLANE_CBCR];
4369 if (capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
4370 rkcif_write_buff_addr_multi_dev_combine(stream,
4371 frm0_addr_y,
4372 frm0_addr_uv,
4373 buff_addr_y,
4374 buff_addr_cbcr,
4375 false);
4376 rkcif_write_buff_addr_multi_dev_combine(stream,
4377 frm1_addr_y,
4378 frm1_addr_uv,
4379 buff_addr_y,
4380 buff_addr_cbcr,
4381 false);
4382 } else {
4383 rkcif_write_register(dev, frm0_addr_y, buff_addr_y);
4384 if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
4385 rkcif_write_register(dev,
4386 frm0_addr_uv,
4387 buff_addr_cbcr);
4388 rkcif_write_register(dev, frm1_addr_y, buff_addr_y);
4389 if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
4390 rkcif_write_register(dev,
4391 frm1_addr_uv,
4392 buff_addr_cbcr);
4393 }
4394 } else {
4395
4396 buff_addr_y = buffer->buff_addr[RKCIF_PLANE_Y];
4397 buff_addr_cbcr = buffer->buff_addr[RKCIF_PLANE_CBCR];
4398 if (capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
4399 rkcif_write_buff_addr_multi_dev_combine(stream,
4400 frm_addr_y,
4401 frm_addr_uv,
4402 buff_addr_y,
4403 buff_addr_cbcr,
4404 false);
4405 } else {
4406 rkcif_write_register(dev, frm_addr_y, buff_addr_y);
4407 if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
4408 rkcif_write_register(dev,
4409 frm_addr_uv,
4410 buff_addr_cbcr);
4411 }
4412 }
4413 }
4414 } else {
4415 v4l2_dbg(3, rkcif_debug, &stream->cifdev->v4l2_dev,
4416 "%s %d, is_wake_up %d, frame_idx %d\n",
4417 __func__, __LINE__, stream->is_line_wake_up, stream->frame_idx);
4418 if (stream->curr_buf == stream->next_buf) {
4419 if (stream->frame_phase_cache == CIF_CSI_FRAME0_READY) {
4420 stream->curr_buf = list_first_entry(&stream->buf_head,
4421 struct rkcif_buffer, queue);
4422 if (stream->curr_buf)
4423 list_del(&stream->curr_buf->queue);
4424 } else if (stream->frame_phase_cache == CIF_CSI_FRAME1_READY) {
4425 stream->next_buf = list_first_entry(&stream->buf_head,
4426 struct rkcif_buffer, queue);
4427 if (stream->next_buf)
4428 list_del(&stream->next_buf->queue);
4429 }
4430 stream->is_buf_active = true;
4431 }
4432 }
4433 v4l2_dbg(3, rkcif_debug, &stream->cifdev->v4l2_dev,
4434 "%s, stream[%d] update buffer, frame_phase %d, is_stop %s, lack_buf_cnt %d\n",
4435 __func__, stream->id, frame_phase,
4436 (stream->dma_en ? "false" : "true"),
4437 stream->lack_buf_cnt);
4438 if (!stream->dma_en) {
4439 if (stream->to_stop_dma) {
4440 stream->to_stop_dma = 0;
4441 wake_up(&stream->wq_stopped);
4442 } else {
4443 stream->to_en_dma = RKCIF_DMAEN_BY_VICAP;
4444 v4l2_dbg(3, rkcif_debug, &stream->cifdev->v4l2_dev,
4445 "%s stream[%d] start dma capture, frame cnt %d\n",
4446 __func__, stream->id, stream->frame_idx);
4447 }
4448 } else {
4449 v4l2_dbg(3, rkcif_debug, &stream->cifdev->v4l2_dev,
4450 "%s %d, dma_en 0x%x, frame cnt %d\n",
4451 __func__, __LINE__, stream->dma_en, stream->frame_idx);
4452 }
4453 if (stream->lack_buf_cnt)
4454 stream->lack_buf_cnt--;
4455 } else {
4456 v4l2_info(&dev->v4l2_dev, "%s %d, state %d, curr_buf %p, next_buf %p\n",
4457 __func__, __LINE__, stream->state, stream->curr_buf, stream->next_buf);
4458 }
4459 spin_unlock_irqrestore(&stream->vbq_lock, flags);
4460 if (stream->to_en_dma)
4461 rkcif_enable_dma_capture(stream, true);
4462 }
4463
4464 /*
4465 * The vb2_buffer are stored in rkcif_buffer, in order to unify
4466 * mplane buffer and none-mplane buffer.
4467 */
rkcif_buf_queue(struct vb2_buffer * vb)4468 void rkcif_buf_queue(struct vb2_buffer *vb)
4469 {
4470 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
4471 struct rkcif_buffer *cifbuf = to_rkcif_buffer(vbuf);
4472 struct vb2_queue *queue = vb->vb2_queue;
4473 struct rkcif_stream *stream = queue->drv_priv;
4474 struct v4l2_pix_format_mplane *pixm = &stream->pixm;
4475 const struct cif_output_fmt *fmt = stream->cif_fmt_out;
4476 struct rkcif_hw *hw_dev = stream->cifdev->hw_dev;
4477 struct rkcif_tools_buffer *tools_buf;
4478 struct rkcif_tools_vdev *tools_vdev = stream->tools_vdev;
4479 unsigned long flags;
4480 int i;
4481 bool is_find_tools_buf = false;
4482
4483 if (tools_vdev) {
4484 spin_lock_irqsave(&stream->tools_vdev->vbq_lock, flags);
4485 if (!list_empty(&tools_vdev->src_buf_head)) {
4486 list_for_each_entry(tools_buf, &tools_vdev->src_buf_head, list) {
4487 if (tools_buf->vb == vbuf) {
4488 is_find_tools_buf = true;
4489 break;
4490 }
4491 }
4492 if (is_find_tools_buf) {
4493 if (tools_buf->use_cnt)
4494 tools_buf->use_cnt--;
4495 if (tools_buf->use_cnt) {
4496 spin_unlock_irqrestore(&stream->tools_vdev->vbq_lock, flags);
4497 return;
4498 }
4499 }
4500 }
4501 spin_unlock_irqrestore(&stream->tools_vdev->vbq_lock, flags);
4502 }
4503
4504 memset(cifbuf->buff_addr, 0, sizeof(cifbuf->buff_addr));
4505 /* If mplanes > 1, every c-plane has its own m-plane,
4506 * otherwise, multiple c-planes are in the same m-plane
4507 */
4508 for (i = 0; i < fmt->mplanes; i++) {
4509 void *addr = vb2_plane_vaddr(vb, i);
4510
4511 if (hw_dev->is_dma_sg_ops) {
4512 struct sg_table *sgt = vb2_dma_sg_plane_desc(vb, i);
4513
4514 cifbuf->buff_addr[i] = sg_dma_address(sgt->sgl);
4515 } else {
4516 cifbuf->buff_addr[i] = vb2_dma_contig_plane_dma_addr(vb, i);
4517 }
4518 if (rkcif_debug && addr && !hw_dev->iommu_en) {
4519 memset(addr, 0, pixm->plane_fmt[i].sizeimage);
4520 v4l2_dbg(3, rkcif_debug, &stream->cifdev->v4l2_dev,
4521 "Clear buffer, size: 0x%08x\n",
4522 pixm->plane_fmt[i].sizeimage);
4523 }
4524 }
4525
4526 if (fmt->mplanes == 1) {
4527 for (i = 0; i < fmt->cplanes - 1; i++)
4528 cifbuf->buff_addr[i + 1] = cifbuf->buff_addr[i] +
4529 pixm->plane_fmt[i].bytesperline * pixm->height;
4530 }
4531 spin_lock_irqsave(&stream->vbq_lock, flags);
4532 list_add_tail(&cifbuf->queue, &stream->buf_head);
4533 spin_unlock_irqrestore(&stream->vbq_lock, flags);
4534 if (stream->dma_en & RKCIF_DMAEN_BY_ISP && (!cifbuf->dbuf)) {
4535 struct rkisp_rx_buf *dbufs = NULL;
4536
4537 dbufs = kzalloc(sizeof(struct rkisp_rx_buf), GFP_KERNEL);
4538
4539 memset(dbufs, 0, sizeof(struct rkisp_rx_buf));
4540 if (stream->cifdev->hdr.hdr_mode == HDR_X2 && stream->id == 0)
4541 dbufs->type = BUF_MIDDLE;
4542 else if (stream->cifdev->hdr.hdr_mode == HDR_X3 && stream->id == 0)
4543 dbufs->type = BUF_LONG;
4544 else if (stream->cifdev->hdr.hdr_mode == HDR_X3 && stream->id == 1)
4545 dbufs->type = BUF_MIDDLE;
4546 cifbuf->dbuf = hw_dev->mem_ops->get_dmabuf(vb->planes[0].mem_priv, O_RDWR);
4547 if (cifbuf->dbuf)
4548 dbufs->dbuf = cifbuf->dbuf;
4549 list_add_tail(&dbufs->list, &stream->rx_buf_head_vicap);
4550 }
4551 if (stream->cifdev->workmode == RKCIF_WORKMODE_PINGPONG &&
4552 stream->lack_buf_cnt)
4553 rkcif_check_buffer_update_pingpong(stream, stream->id);
4554 v4l2_dbg(3, rkcif_debug, &stream->cifdev->v4l2_dev,
4555 "stream[%d] buf queue, index: %d, dma_addr 0x%x\n",
4556 stream->id, vb->index, cifbuf->buff_addr[0]);
4557 atomic_inc(&stream->buf_cnt);
4558 }
4559
rkcif_free_rx_buf(struct rkcif_stream * stream,int buf_num)4560 void rkcif_free_rx_buf(struct rkcif_stream *stream, int buf_num)
4561 {
4562 struct rkcif_rx_buffer *buf;
4563 struct rkcif_device *dev = stream->cifdev;
4564 struct sditf_priv *priv = dev->sditf[0];
4565 int i = 0;
4566 unsigned long flags;
4567
4568 if (!priv)
4569 return;
4570
4571 spin_lock_irqsave(&stream->vbq_lock, flags);
4572 stream->curr_buf_toisp = NULL;
4573 stream->next_buf_toisp = NULL;
4574 INIT_LIST_HEAD(&stream->rx_buf_head);
4575 spin_unlock_irqrestore(&stream->vbq_lock, flags);
4576
4577 if (dev->is_thunderboot)
4578 spin_lock_irqsave(&dev->buffree_lock, flags);
4579 for (i = 0; i < buf_num; i++) {
4580 buf = &stream->rx_buf[i];
4581 if (buf->dummy.is_free)
4582 continue;
4583 if (!dev->is_thunderboot)
4584 rkcif_free_buffer(dev, &buf->dummy);
4585 else
4586 list_add_tail(&buf->list_free, &priv->buf_free_list);
4587 atomic_dec(&stream->buf_cnt);
4588 stream->total_buf_num--;
4589 }
4590
4591 if (dev->is_thunderboot) {
4592 spin_unlock_irqrestore(&dev->buffree_lock, flags);
4593 schedule_work(&priv->buffree_work.work);
4594 }
4595 stream->dma_en &= ~RKCIF_DMAEN_BY_ISP;
4596 v4l2_dbg(1, rkcif_debug, &stream->cifdev->v4l2_dev,
4597 "free rx_buf, buf_num %d\n", buf_num);
4598 }
4599
rkcif_init_rx_buf(struct rkcif_stream * stream,int buf_num)4600 int rkcif_init_rx_buf(struct rkcif_stream *stream, int buf_num)
4601 {
4602 struct rkcif_device *dev = stream->cifdev;
4603 struct v4l2_pix_format_mplane *pixm = &stream->pixm;
4604 struct rkcif_dummy_buffer *dummy;
4605 struct rkcif_rx_buffer *buf;
4606 struct sditf_priv *priv = dev->sditf[0];
4607 int frm_type = 0;
4608 int i = 0;
4609 int ret = 0;
4610
4611 if (!priv)
4612 return -EINVAL;
4613
4614 if (buf_num > RKISP_VICAP_BUF_CNT_MAX)
4615 return -EINVAL;
4616
4617 if (dev->hdr.hdr_mode == NO_HDR) {
4618 if (stream->id == 0)
4619 frm_type = BUF_SHORT;
4620 else
4621 return -EINVAL;
4622 } else if (dev->hdr.hdr_mode == HDR_X2) {
4623 if (stream->id == 0)
4624 frm_type = BUF_MIDDLE;
4625 else if (stream->id == 1)
4626 frm_type = BUF_SHORT;
4627 else
4628 return -EINVAL;
4629 } else if (dev->hdr.hdr_mode == HDR_X3) {
4630 if (stream->id == 0)
4631 frm_type = BUF_LONG;
4632 else if (stream->id == 1)
4633 frm_type = BUF_MIDDLE;
4634 else if (stream->id == 2)
4635 frm_type = BUF_SHORT;
4636 else
4637 return -EINVAL;
4638 }
4639 while (true) {
4640 buf = &stream->rx_buf[i];
4641 memset(buf, 0, sizeof(*buf));
4642 dummy = &buf->dummy;
4643 dummy->size = pixm->plane_fmt[0].sizeimage;
4644 dummy->is_need_vaddr = true;
4645 dummy->is_need_dbuf = true;
4646 if (dev->is_thunderboot) {
4647 buf->buf_idx = i;
4648 ret = rkcif_alloc_reserved_mem_buf(dev, buf);
4649 if (ret) {
4650 priv->buf_num = i;
4651 v4l2_info(&dev->v4l2_dev,
4652 "reserved mem support alloc buf num %d, require buf num %d\n",
4653 i, buf_num);
4654 break;
4655 }
4656 if (dev->rdbk_debug)
4657 v4l2_info(&dev->v4l2_dev,
4658 "stream[%d] buf addr 0x%llx\n",
4659 stream->id, (u64)dummy->dma_addr);
4660 } else {
4661 ret = rkcif_alloc_buffer(dev, dummy);
4662 if (ret) {
4663 priv->buf_num = i;
4664 v4l2_info(&dev->v4l2_dev,
4665 "alloc buf num %d, require buf num %d\n",
4666 i, buf_num);
4667 break;
4668 }
4669 buf->dbufs.dbuf = dummy->dbuf;
4670 }
4671 buf->dbufs.is_init = false;
4672 buf->dbufs.type = frm_type;
4673 list_add_tail(&buf->list, &stream->rx_buf_head);
4674 dummy->is_free = false;
4675 if (stream->is_compact)
4676 buf->dbufs.is_uncompact = false;
4677 else
4678 buf->dbufs.is_uncompact = true;
4679 if (priv && priv->mode.rdbk_mode == RKISP_VICAP_ONLINE && i == 0) {
4680 buf->dbufs.is_first = true;
4681 rkcif_s_rx_buffer(dev, &buf->dbufs);
4682 }
4683 i++;
4684 if (!dev->is_thunderboot && i >= buf_num) {
4685 break;
4686 } else if (i >= RKISP_VICAP_BUF_CNT_MAX) {
4687 priv->buf_num = i;
4688 v4l2_info(&dev->v4l2_dev,
4689 "reserved mem alloc buf num %d\n", i);
4690 break;
4691 }
4692 v4l2_dbg(1, rkcif_debug, &dev->v4l2_dev,
4693 "init rx_buf,dma_addr 0x%llx size: 0x%x\n",
4694 (u64)dummy->dma_addr, pixm->plane_fmt[0].sizeimage);
4695 }
4696 if (priv->buf_num) {
4697 stream->total_buf_num = priv->buf_num;
4698 atomic_set(&stream->buf_cnt, priv->buf_num);
4699 return 0;
4700 } else {
4701 return -EINVAL;
4702 }
4703 }
4704
rkcif_create_dummy_buf(struct rkcif_stream * stream)4705 static int rkcif_create_dummy_buf(struct rkcif_stream *stream)
4706 {
4707 struct rkcif_device *dev = stream->cifdev;
4708 struct rkcif_hw *hw = dev->hw_dev;
4709 struct rkcif_dummy_buffer *dummy_buf = &hw->dummy_buf;
4710 struct rkcif_device *tmp_dev = NULL;
4711 struct v4l2_subdev_frame_interval_enum fie;
4712 u32 max_size = 0;
4713 u32 size = 0;
4714 int ret = 0;
4715 int i, j;
4716
4717 for (i = 0; i < hw->dev_num; i++) {
4718 tmp_dev = hw->cif_dev[i];
4719 if (tmp_dev->terminal_sensor.sd) {
4720 for (j = 0; j < 32; j++) {
4721 memset(&fie, 0, sizeof(fie));
4722 fie.index = j;
4723 fie.pad = 0;
4724 fie.which = V4L2_SUBDEV_FORMAT_ACTIVE;
4725 ret = v4l2_subdev_call(tmp_dev->terminal_sensor.sd,
4726 pad, enum_frame_interval,
4727 NULL, &fie);
4728 if (!ret) {
4729 if (fie.code == MEDIA_BUS_FMT_RGB888_1X24)
4730 size = fie.width * fie.height * 3;
4731 else
4732 size = fie.width * fie.height * 2;
4733 v4l2_dbg(1, rkcif_debug, &dev->v4l2_dev,
4734 "%s enum fmt, width %d, height %d\n",
4735 __func__, fie.width, fie.height);
4736 } else {
4737 break;
4738 }
4739 if (size > max_size)
4740 max_size = size;
4741 }
4742 } else {
4743 continue;
4744 }
4745 }
4746 dummy_buf->size = max_size;
4747
4748 dummy_buf->is_need_vaddr = true;
4749 dummy_buf->is_need_dbuf = true;
4750 ret = rkcif_alloc_buffer(dev, dummy_buf);
4751 if (ret) {
4752 v4l2_err(&dev->v4l2_dev,
4753 "Failed to allocate the memory for dummy buffer\n");
4754 return -ENOMEM;
4755 }
4756
4757 v4l2_info(&dev->v4l2_dev, "Allocate dummy buffer, size: 0x%08x\n",
4758 dummy_buf->size);
4759
4760 return ret;
4761 }
4762
rkcif_destroy_dummy_buf(struct rkcif_stream * stream)4763 static void rkcif_destroy_dummy_buf(struct rkcif_stream *stream)
4764 {
4765 struct rkcif_device *dev = stream->cifdev;
4766 struct rkcif_dummy_buffer *dummy_buf = &dev->hw_dev->dummy_buf;
4767
4768 if (dummy_buf->vaddr)
4769 rkcif_free_buffer(dev, dummy_buf);
4770 dummy_buf->dma_addr = 0;
4771 dummy_buf->vaddr = NULL;
4772 }
4773
rkcif_do_cru_reset(struct rkcif_device * dev)4774 static void rkcif_do_cru_reset(struct rkcif_device *dev)
4775 {
4776 struct rkcif_hw *cif_hw = dev->hw_dev;
4777
4778 unsigned int val, i;
4779
4780 if (dev->luma_vdev.enable)
4781 rkcif_stop_luma(&dev->luma_vdev);
4782
4783 if (dev->hdr.hdr_mode != NO_HDR) {
4784 if (dev->chip_id == CHIP_RK1808_CIF) {
4785 val = rkcif_read_register(dev, CIF_REG_MIPI_WATER_LINE);
4786 val |= CIF_MIPI_LVDS_SW_DMA_IDLE_RK1808;
4787 rkcif_write_register(dev, CIF_REG_MIPI_WATER_LINE, val);
4788 } else {
4789 val = rkcif_read_register(dev, CIF_REG_MIPI_LVDS_CTRL);
4790 val |= CIF_MIPI_LVDS_SW_DMA_IDLE;
4791 rkcif_write_register(dev, CIF_REG_MIPI_LVDS_CTRL, val);
4792 }
4793 udelay(5);
4794 }
4795
4796 for (i = 0; i < ARRAY_SIZE(cif_hw->cif_rst); i++)
4797 if (cif_hw->cif_rst[i])
4798 reset_control_assert(cif_hw->cif_rst[i]);
4799
4800 udelay(10);
4801
4802 for (i = 0; i < ARRAY_SIZE(cif_hw->cif_rst); i++)
4803 if (cif_hw->cif_rst[i])
4804 reset_control_deassert(cif_hw->cif_rst[i]);
4805
4806 if (cif_hw->iommu_en) {
4807 rockchip_iommu_disable(cif_hw->dev);
4808 rockchip_iommu_enable(cif_hw->dev);
4809 }
4810 }
4811
rkcif_do_soft_reset(struct rkcif_device * dev)4812 void rkcif_do_soft_reset(struct rkcif_device *dev)
4813 {
4814 if (dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_DPHY ||
4815 dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_CPHY ||
4816 dev->active_sensor->mbus.type == V4L2_MBUS_CCP2)
4817 rkcif_write_register_or(dev, CIF_REG_MIPI_LVDS_CTRL, 0x000A0000);
4818 else
4819 rkcif_write_register_or(dev, CIF_REG_DVP_CTRL, 0x000A0000);
4820 usleep_range(10, 20);
4821 v4l2_dbg(1, rkcif_debug, &dev->v4l2_dev,
4822 "vicap do soft reset 0x%x\n", 0x000A0000);
4823 }
4824
rkcif_release_rdbk_buf(struct rkcif_stream * stream)4825 static void rkcif_release_rdbk_buf(struct rkcif_stream *stream)
4826 {
4827 struct rkcif_device *dev = stream->cifdev;
4828 struct rkcif_buffer *rdbk_buf;
4829 struct rkcif_buffer *tmp_buf;
4830 unsigned long flags;
4831 bool has_added;
4832 int index = 0;
4833
4834 if (stream->id == RKCIF_STREAM_MIPI_ID0)
4835 index = RDBK_L;
4836 else if (stream->id == RKCIF_STREAM_MIPI_ID1)
4837 index = RDBK_M;
4838 else if (stream->id == RKCIF_STREAM_MIPI_ID2)
4839 index = RDBK_S;
4840 else
4841 return;
4842
4843 spin_lock_irqsave(&dev->hdr_lock, flags);
4844 rdbk_buf = dev->rdbk_buf[index];
4845 if (rdbk_buf) {
4846 if (rdbk_buf != stream->curr_buf &&
4847 rdbk_buf != stream->next_buf) {
4848
4849 has_added = false;
4850
4851 list_for_each_entry(tmp_buf, &stream->buf_head, queue) {
4852 if (tmp_buf == rdbk_buf) {
4853 has_added = true;
4854 break;
4855 }
4856 }
4857
4858 if (!has_added)
4859 list_add_tail(&rdbk_buf->queue, &stream->buf_head);
4860 }
4861 dev->rdbk_buf[index] = NULL;
4862 }
4863 spin_unlock_irqrestore(&dev->hdr_lock, flags);
4864
4865 }
4866
rkcif_detach_sync_mode(struct rkcif_device * cif_dev)4867 static void rkcif_detach_sync_mode(struct rkcif_device *cif_dev)
4868 {
4869 int i = 0;
4870 struct rkcif_hw *hw = cif_dev->hw_dev;
4871 struct rkcif_device *tmp_dev;
4872 struct rkcif_multi_sync_config *sync_config;
4873
4874 if ((!cif_dev->sync_cfg.type) ||
4875 (atomic_read(&cif_dev->pipe.stream_cnt) != 0))
4876 return;
4877 mutex_lock(&hw->dev_lock);
4878 memset(&cif_dev->sync_cfg, 0, sizeof(cif_dev->sync_cfg));
4879 sync_config = &hw->sync_config[cif_dev->sync_cfg.group];
4880 sync_config->streaming_cnt--;
4881 if (cif_dev->sync_cfg.type == EXTERNAL_MASTER_MODE) {
4882 for (i = 0; i < sync_config->ext_master.count; i++) {
4883 tmp_dev = sync_config->ext_master.cif_dev[i];
4884 if (tmp_dev == cif_dev) {
4885 sync_config->ext_master.is_streaming[i] = false;
4886 break;
4887 }
4888 }
4889 }
4890 if (cif_dev->sync_cfg.type == INTERNAL_MASTER_MODE)
4891 sync_config->int_master.is_streaming[0] = false;
4892 if (cif_dev->sync_cfg.type == SLAVE_MODE) {
4893 for (i = 0; i < sync_config->slave.count; i++) {
4894 tmp_dev = sync_config->slave.cif_dev[i];
4895 if (tmp_dev == cif_dev) {
4896 sync_config->slave.is_streaming[i] = false;
4897 break;
4898 }
4899 }
4900 }
4901
4902 if (!sync_config->streaming_cnt && sync_config->is_attach) {
4903 sync_config->is_attach = false;
4904 sync_config->mode = RKCIF_NOSYNC_MODE;
4905 sync_config->dev_cnt = 0;
4906 }
4907 mutex_unlock(&hw->dev_lock);
4908 }
4909
rkcif_do_stop_stream(struct rkcif_stream * stream,unsigned int mode)4910 void rkcif_do_stop_stream(struct rkcif_stream *stream,
4911 unsigned int mode)
4912 {
4913 struct rkcif_vdev_node *node = &stream->vnode;
4914 struct rkcif_device *dev = stream->cifdev;
4915 struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
4916 struct rkcif_buffer *buf = NULL;
4917 int ret;
4918 struct rkcif_hw *hw_dev = dev->hw_dev;
4919 bool can_reset = true;
4920 int i;
4921 unsigned long flags;
4922 u32 vblank = 0;
4923 u32 frame_time_ns = 0;
4924 u64 cur_time = 0;
4925 u64 fs_time = 0;
4926
4927 mutex_lock(&dev->stream_lock);
4928
4929 v4l2_info(&dev->v4l2_dev, "stream[%d] start stopping, total mode 0x%x, cur 0x%x\n",
4930 stream->id, stream->cur_stream_mode, mode);
4931
4932 if (mode == stream->cur_stream_mode) {
4933 if (stream->dma_en) {
4934 if (!dev->sensor_linetime)
4935 dev->sensor_linetime = rkcif_get_linetime(stream);
4936 vblank = rkcif_get_sensor_vblank(dev);
4937 if (vblank) {
4938 frame_time_ns = (vblank + dev->terminal_sensor.raw_rect.height) *
4939 dev->sensor_linetime;
4940 spin_lock_irqsave(&stream->fps_lock, flags);
4941 fs_time = stream->readout.fs_timestamp;
4942 spin_unlock_irqrestore(&stream->fps_lock, flags);
4943 cur_time = ktime_get_ns();
4944 if (cur_time > fs_time &&
4945 cur_time - fs_time < (frame_time_ns - 10000000)) {
4946 spin_lock_irqsave(&stream->vbq_lock, flags);
4947 if (stream->dma_en & RKCIF_DMAEN_BY_VICAP)
4948 stream->to_stop_dma = RKCIF_DMAEN_BY_VICAP;
4949 else if (stream->dma_en & RKCIF_DMAEN_BY_ISP)
4950 stream->to_stop_dma = RKCIF_DMAEN_BY_ISP;
4951 stream->is_stop_capture = true;
4952 rkcif_stop_dma_capture(stream);
4953 spin_unlock_irqrestore(&stream->vbq_lock, flags);
4954 }
4955 }
4956 }
4957 stream->stopping = true;
4958 ret = wait_event_timeout(stream->wq_stopped,
4959 stream->state != RKCIF_STATE_STREAMING,
4960 msecs_to_jiffies(500));
4961 if (!ret) {
4962 rkcif_stream_stop(stream);
4963 stream->stopping = false;
4964 }
4965
4966 media_pipeline_stop(&node->vdev.entity);
4967 ret = dev->pipe.set_stream(&dev->pipe, false);
4968 if (ret < 0)
4969 v4l2_err(v4l2_dev, "pipeline stream-off failed error:%d\n",
4970 ret);
4971
4972 dev->is_start_hdr = false;
4973 stream->is_dvp_yuv_addr_init = false;
4974 if (stream->skip_info.skip_en) {
4975 stream->skip_info.skip_en = false;
4976 stream->skip_info.skip_to_en = true;
4977 }
4978 } else if (mode == RKCIF_STREAM_MODE_CAPTURE && stream->dma_en & RKCIF_DMAEN_BY_VICAP) {
4979 //only stop dma
4980 stream->to_stop_dma = RKCIF_DMAEN_BY_VICAP;
4981 wait_event_timeout(stream->wq_stopped,
4982 stream->to_stop_dma != RKCIF_DMAEN_BY_VICAP,
4983 msecs_to_jiffies(1000));
4984 } else if (mode == RKCIF_STREAM_MODE_TOISP && stream->dma_en & RKCIF_DMAEN_BY_VICAP) {
4985 //only stop dma
4986 stream->to_stop_dma = RKCIF_DMAEN_BY_ISP;
4987 wait_event_timeout(stream->wq_stopped,
4988 stream->to_stop_dma != RKCIF_DMAEN_BY_ISP,
4989 msecs_to_jiffies(1000));
4990 }
4991 if ((mode & RKCIF_STREAM_MODE_CAPTURE) == RKCIF_STREAM_MODE_CAPTURE) {
4992 /* release buffers */
4993 spin_lock_irqsave(&stream->vbq_lock, flags);
4994 if (stream->curr_buf)
4995 list_add_tail(&stream->curr_buf->queue, &stream->buf_head);
4996 if (stream->next_buf &&
4997 stream->next_buf != stream->curr_buf)
4998 list_add_tail(&stream->next_buf->queue, &stream->buf_head);
4999 spin_unlock_irqrestore(&stream->vbq_lock, flags);
5000
5001 stream->curr_buf = NULL;
5002 stream->next_buf = NULL;
5003
5004 if (dev->hdr.hdr_mode == HDR_X2 ||
5005 dev->hdr.hdr_mode == HDR_X3)
5006 rkcif_release_rdbk_buf(stream);
5007
5008 rkcif_rx_buffer_free(stream);
5009 list_for_each_entry(buf, &stream->buf_head, queue) {
5010 v4l2_dbg(3, rkcif_debug, &dev->v4l2_dev,
5011 "stream[%d] buf return addr 0x%x\n",
5012 stream->id, buf->buff_addr[0]);
5013 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
5014 }
5015 INIT_LIST_HEAD(&stream->buf_head);
5016 while (!list_empty(&stream->vb_done_list)) {
5017 buf = list_first_entry(&stream->vb_done_list,
5018 struct rkcif_buffer, queue);
5019 if (buf) {
5020 list_del(&buf->queue);
5021 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
5022 }
5023 }
5024 stream->total_buf_num = 0;
5025 atomic_set(&stream->buf_cnt, 0);
5026 stream->lack_buf_cnt = 0;
5027 stream->dma_en &= ~RKCIF_DMAEN_BY_VICAP;
5028 }
5029
5030 if (mode == stream->cur_stream_mode) {
5031 ret = dev->pipe.close(&dev->pipe);
5032 if (ret < 0)
5033 v4l2_err(v4l2_dev, "pipeline close failed error:%d\n", ret);
5034 if (dev->hdr.hdr_mode == HDR_X2) {
5035 if (dev->stream[RKCIF_STREAM_MIPI_ID0].state == RKCIF_STATE_READY &&
5036 dev->stream[RKCIF_STREAM_MIPI_ID1].state == RKCIF_STATE_READY) {
5037 dev->can_be_reset = true;
5038 }
5039 } else if (dev->hdr.hdr_mode == HDR_X3) {
5040 if (dev->stream[RKCIF_STREAM_MIPI_ID0].state == RKCIF_STATE_READY &&
5041 dev->stream[RKCIF_STREAM_MIPI_ID1].state == RKCIF_STATE_READY &&
5042 dev->stream[RKCIF_STREAM_MIPI_ID2].state == RKCIF_STATE_READY) {
5043 dev->can_be_reset = true;
5044 }
5045 } else {
5046 dev->can_be_reset = true;
5047 }
5048 mutex_lock(&hw_dev->dev_lock);
5049 for (i = 0; i < hw_dev->dev_num; i++) {
5050 if (atomic_read(&hw_dev->cif_dev[i]->pipe.stream_cnt) != 0) {
5051 can_reset = false;
5052 break;
5053 }
5054 }
5055 mutex_unlock(&hw_dev->dev_lock);
5056 if (dev->can_be_reset && dev->chip_id >= CHIP_RK3588_CIF)
5057 rkcif_do_soft_reset(dev);
5058 if (dev->can_be_reset && can_reset) {
5059 dev->can_be_reset = false;
5060 dev->reset_work_cancel = true;
5061 dev->early_line = 0;
5062 dev->sensor_linetime = 0;
5063 dev->wait_line = 0;
5064 stream->is_line_wake_up = false;
5065 }
5066 tasklet_disable(&stream->vb_done_tasklet);
5067 }
5068 if (can_reset && hw_dev->dummy_buf.vaddr)
5069 rkcif_destroy_dummy_buf(stream);
5070 stream->cur_stream_mode &= ~mode;
5071 INIT_LIST_HEAD(&stream->vb_done_list);
5072 v4l2_info(&dev->v4l2_dev, "stream[%d] stopping finished, dma_en 0x%x\n", stream->id, stream->dma_en);
5073 mutex_unlock(&dev->stream_lock);
5074 rkcif_detach_sync_mode(dev);
5075 }
5076
rkcif_stop_streaming(struct vb2_queue * queue)5077 static void rkcif_stop_streaming(struct vb2_queue *queue)
5078 {
5079 struct rkcif_stream *stream = queue->drv_priv;
5080
5081 rkcif_do_stop_stream(stream, RKCIF_STREAM_MODE_CAPTURE);
5082 }
5083
5084 /*
5085 * CIF supports the following input modes,
5086 * YUV, the default mode
5087 * PAL,
5088 * NTSC,
5089 * RAW, if the input format is raw bayer
5090 * JPEG, TODO
5091 * MIPI, TODO
5092 */
rkcif_determine_input_mode(struct rkcif_stream * stream)5093 static u32 rkcif_determine_input_mode(struct rkcif_stream *stream)
5094 {
5095 struct rkcif_device *dev = stream->cifdev;
5096 struct rkcif_sensor_info *sensor_info = dev->active_sensor;
5097 struct rkcif_sensor_info *terminal_sensor = &dev->terminal_sensor;
5098 __u32 intf = BT656_STD_RAW;
5099 u32 mode = INPUT_MODE_YUV;
5100 v4l2_std_id std;
5101 int ret;
5102
5103 ret = v4l2_subdev_call(sensor_info->sd, video, querystd, &std);
5104 if (ret == 0) {
5105 /* retrieve std from sensor if exist */
5106 switch (std) {
5107 case V4L2_STD_NTSC:
5108 mode = INPUT_MODE_NTSC;
5109 break;
5110 case V4L2_STD_PAL:
5111 mode = INPUT_MODE_PAL;
5112 break;
5113 case V4L2_STD_ATSC:
5114 mode = INPUT_MODE_BT1120;
5115 break;
5116 default:
5117 v4l2_err(&dev->v4l2_dev,
5118 "std: %lld is not supported", std);
5119 }
5120 } else {
5121 /* determine input mode by mbus_code (fmt_type) */
5122 switch (stream->cif_fmt_in->fmt_type) {
5123 case CIF_FMT_TYPE_YUV:
5124 if (dev->chip_id >= CHIP_RK3568_CIF) {
5125 if (sensor_info->mbus.type == V4L2_MBUS_BT656)
5126 mode = INPUT_MODE_BT656_YUV422;
5127 else
5128 mode = INPUT_MODE_YUV;
5129 } else {
5130 mode = INPUT_MODE_YUV;
5131 }
5132 break;
5133 case CIF_FMT_TYPE_RAW:
5134 if (dev->chip_id >= CHIP_RK3568_CIF) {
5135 ret = v4l2_subdev_call(terminal_sensor->sd,
5136 core, ioctl,
5137 RKMODULE_GET_BT656_INTF_TYPE,
5138 &intf);
5139 if (!ret) {
5140 if (intf == BT656_SONY_RAW)
5141 mode = INPUT_MODE_SONY_RAW;
5142 else
5143 mode = INPUT_MODE_RAW;
5144 } else {
5145 mode = INPUT_MODE_RAW;
5146 }
5147 } else {
5148 mode = INPUT_MODE_RAW;
5149 }
5150 break;
5151 }
5152 }
5153
5154 return mode;
5155 }
5156
rkcif_determine_input_mode_rk3588(struct rkcif_stream * stream)5157 static u32 rkcif_determine_input_mode_rk3588(struct rkcif_stream *stream)
5158 {
5159 struct rkcif_device *dev = stream->cifdev;
5160 struct rkcif_sensor_info *sensor_info = dev->active_sensor;
5161 struct rkcif_sensor_info *terminal_sensor = &dev->terminal_sensor;
5162 __u32 intf = BT656_STD_RAW;
5163 u32 mode = INPUT_MODE_YUV;
5164 v4l2_std_id std;
5165 int ret;
5166
5167 ret = v4l2_subdev_call(sensor_info->sd, video, querystd, &std);
5168 if (ret == 0) {
5169 /* retrieve std from sensor if exist */
5170 switch (std) {
5171 case V4L2_STD_NTSC:
5172 case V4L2_STD_PAL:
5173 mode = INPUT_BT656_YUV422;
5174 break;
5175 case V4L2_STD_ATSC:
5176 mode = INPUT_BT1120_YUV422;
5177 break;
5178 default:
5179 v4l2_err(&dev->v4l2_dev,
5180 "std: %lld is not supported", std);
5181 }
5182 mode |= CSI_WRDDR_TYPE_RAW8 << 6;
5183 } else {
5184 /* determine input mode by mbus_code (fmt_type) */
5185 switch (stream->cif_fmt_in->fmt_type) {
5186 case CIF_FMT_TYPE_YUV:
5187 if (sensor_info->mbus.type == V4L2_MBUS_BT656) {
5188 if ((sensor_info->mbus.flags & CIF_DVP_PCLK_DUAL_EDGE) == CIF_DVP_PCLK_DUAL_EDGE)
5189 mode = INPUT_BT1120_YUV422;
5190 else
5191 mode = INPUT_BT656_YUV422;
5192 } else {
5193 mode = INPUT_BT601_YUV422;
5194 }
5195 mode |= CSI_WRDDR_TYPE_RAW8 << 6;
5196 break;
5197 case CIF_FMT_TYPE_RAW:
5198 ret = v4l2_subdev_call(terminal_sensor->sd,
5199 core, ioctl,
5200 RKMODULE_GET_BT656_INTF_TYPE,
5201 &intf);
5202 if (!ret) {
5203 if (intf == BT656_SONY_RAW)
5204 mode = INPUT_SONY_RAW;
5205 else
5206 mode = INPUT_BT601_RAW;
5207 } else {
5208 mode = INPUT_BT601_RAW;
5209 }
5210 mode |= stream->cif_fmt_in->csi_fmt_val << 6;
5211 break;
5212 }
5213 }
5214 if (stream->cif_fmt_in->field == V4L2_FIELD_NONE)
5215 mode |= TRANSMIT_PROGRESS_RK3588;
5216 else
5217 mode |= TRANSMIT_INTERFACE_RK3588;
5218 return mode;
5219 }
5220
rkcif_scl_ctl(struct rkcif_stream * stream)5221 static inline u32 rkcif_scl_ctl(struct rkcif_stream *stream)
5222 {
5223 u32 fmt_type = stream->cif_fmt_in->fmt_type;
5224
5225 return (fmt_type == CIF_FMT_TYPE_YUV) ?
5226 ENABLE_YUV_16BIT_BYPASS : ENABLE_RAW_16BIT_BYPASS;
5227 }
5228
5229 /**
5230 * rkcif_align_bits_per_pixel() - return the bit width of per pixel for stored
5231 * In raw or jpeg mode, data is stored by 16-bits,so need to align it.
5232 */
rkcif_align_bits_per_pixel(struct rkcif_stream * stream,const struct cif_output_fmt * fmt,int plane_index)5233 static u32 rkcif_align_bits_per_pixel(struct rkcif_stream *stream,
5234 const struct cif_output_fmt *fmt,
5235 int plane_index)
5236 {
5237 u32 bpp = 0, i, cal = 0;
5238
5239 if (fmt) {
5240 switch (fmt->fourcc) {
5241 case V4L2_PIX_FMT_NV16:
5242 case V4L2_PIX_FMT_NV61:
5243 case V4L2_PIX_FMT_NV12:
5244 case V4L2_PIX_FMT_NV21:
5245 case V4L2_PIX_FMT_GREY:
5246 case V4L2_PIX_FMT_Y16:
5247 bpp = fmt->bpp[plane_index];
5248 break;
5249 case V4L2_PIX_FMT_YUYV:
5250 case V4L2_PIX_FMT_YVYU:
5251 case V4L2_PIX_FMT_UYVY:
5252 case V4L2_PIX_FMT_VYUY:
5253 if (stream->cifdev->chip_id < CHIP_RK3588_CIF)
5254 bpp = fmt->bpp[plane_index];
5255 else
5256 bpp = fmt->bpp[plane_index + 1];
5257 break;
5258 case V4L2_PIX_FMT_RGB24:
5259 case V4L2_PIX_FMT_BGR24:
5260 case V4L2_PIX_FMT_RGB565:
5261 case V4L2_PIX_FMT_BGR666:
5262 case V4L2_PIX_FMT_SRGGB8:
5263 case V4L2_PIX_FMT_SGRBG8:
5264 case V4L2_PIX_FMT_SGBRG8:
5265 case V4L2_PIX_FMT_SBGGR8:
5266 case V4L2_PIX_FMT_SRGGB10:
5267 case V4L2_PIX_FMT_SGRBG10:
5268 case V4L2_PIX_FMT_SGBRG10:
5269 case V4L2_PIX_FMT_SBGGR10:
5270 case V4L2_PIX_FMT_SRGGB12:
5271 case V4L2_PIX_FMT_SGRBG12:
5272 case V4L2_PIX_FMT_SGBRG12:
5273 case V4L2_PIX_FMT_SBGGR12:
5274 case V4L2_PIX_FMT_SBGGR16:
5275 case V4L2_PIX_FMT_SGBRG16:
5276 case V4L2_PIX_FMT_SGRBG16:
5277 case V4L2_PIX_FMT_SRGGB16:
5278 case V4l2_PIX_FMT_SPD16:
5279 case V4l2_PIX_FMT_EBD8:
5280 case V4L2_PIX_FMT_Y10:
5281 case V4L2_PIX_FMT_Y12:
5282 if (stream->cifdev->chip_id < CHIP_RV1126_CIF) {
5283 bpp = max(fmt->bpp[plane_index], (u8)CIF_RAW_STORED_BIT_WIDTH);
5284 cal = CIF_RAW_STORED_BIT_WIDTH;
5285 } else {
5286 bpp = max(fmt->bpp[plane_index], (u8)CIF_RAW_STORED_BIT_WIDTH_RV1126);
5287 cal = CIF_RAW_STORED_BIT_WIDTH_RV1126;
5288 }
5289 for (i = 1; i < 5; i++) {
5290 if (i * cal >= bpp) {
5291 bpp = i * cal;
5292 break;
5293 }
5294 }
5295 break;
5296 default:
5297 v4l2_err(&stream->cifdev->v4l2_dev, "fourcc: %d is not supported!\n",
5298 fmt->fourcc);
5299 break;
5300 }
5301 }
5302
5303 return bpp;
5304 }
5305
5306 /**
5307 * rkcif_cal_raw_vir_line_ratio() - return ratio for virtual line width setting
5308 * In raw or jpeg mode, data is stored by 16-bits,
5309 * so need to align virtual line width.
5310 */
rkcif_cal_raw_vir_line_ratio(struct rkcif_stream * stream,const struct cif_output_fmt * fmt)5311 static u32 rkcif_cal_raw_vir_line_ratio(struct rkcif_stream *stream,
5312 const struct cif_output_fmt *fmt)
5313 {
5314 u32 ratio = 0, bpp = 0;
5315
5316 if (fmt) {
5317 bpp = rkcif_align_bits_per_pixel(stream, fmt, 0);
5318 ratio = bpp / CIF_YUV_STORED_BIT_WIDTH;
5319 }
5320
5321 return ratio;
5322 }
5323
rkcif_sync_crop_info(struct rkcif_stream * stream)5324 static void rkcif_sync_crop_info(struct rkcif_stream *stream)
5325 {
5326 struct rkcif_device *dev = stream->cifdev;
5327 struct v4l2_subdev_selection input_sel;
5328 int ret;
5329
5330 if (dev->terminal_sensor.sd) {
5331 input_sel.target = V4L2_SEL_TGT_CROP_BOUNDS;
5332 input_sel.which = V4L2_SUBDEV_FORMAT_ACTIVE;
5333 input_sel.pad = 0;
5334 ret = v4l2_subdev_call(dev->terminal_sensor.sd,
5335 pad, get_selection, NULL,
5336 &input_sel);
5337 if (!ret) {
5338 stream->crop[CROP_SRC_SENSOR] = input_sel.r;
5339 stream->crop_enable = true;
5340 stream->crop_mask |= CROP_SRC_SENSOR_MASK;
5341 dev->terminal_sensor.selection = input_sel;
5342 } else {
5343 dev->terminal_sensor.selection.r = dev->terminal_sensor.raw_rect;
5344 }
5345 }
5346
5347 if ((stream->crop_mask & 0x3) == (CROP_SRC_USR_MASK | CROP_SRC_SENSOR_MASK)) {
5348 if (stream->crop[CROP_SRC_USR].left + stream->crop[CROP_SRC_USR].width >
5349 stream->crop[CROP_SRC_SENSOR].width ||
5350 stream->crop[CROP_SRC_USR].top + stream->crop[CROP_SRC_USR].height >
5351 stream->crop[CROP_SRC_SENSOR].height)
5352 stream->crop[CROP_SRC_USR] = stream->crop[CROP_SRC_SENSOR];
5353 }
5354
5355 if (stream->crop_mask & CROP_SRC_USR_MASK) {
5356 stream->crop[CROP_SRC_ACT] = stream->crop[CROP_SRC_USR];
5357 if (stream->crop_mask & CROP_SRC_SENSOR_MASK) {
5358 stream->crop[CROP_SRC_ACT].left = stream->crop[CROP_SRC_USR].left +
5359 stream->crop[CROP_SRC_SENSOR].left;
5360 stream->crop[CROP_SRC_ACT].top = stream->crop[CROP_SRC_USR].top +
5361 stream->crop[CROP_SRC_SENSOR].top;
5362 }
5363 } else {
5364 stream->crop[CROP_SRC_ACT] = stream->crop[CROP_SRC_SENSOR];
5365 }
5366 }
5367
5368 /**rkcif_sanity_check_fmt - check fmt for setting
5369 * @stream - the stream for setting
5370 * @s_crop - the crop information
5371 */
rkcif_sanity_check_fmt(struct rkcif_stream * stream,const struct v4l2_rect * s_crop)5372 static int rkcif_sanity_check_fmt(struct rkcif_stream *stream,
5373 const struct v4l2_rect *s_crop)
5374 {
5375 struct rkcif_device *dev = stream->cifdev;
5376 struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
5377 struct v4l2_rect input, *crop;
5378
5379 if (dev->terminal_sensor.sd) {
5380 stream->cif_fmt_in = rkcif_get_input_fmt(dev,
5381 &input, stream->id,
5382 &dev->channels[stream->id]);
5383 if (!stream->cif_fmt_in) {
5384 v4l2_err(v4l2_dev, "Input fmt is invalid\n");
5385 return -EINVAL;
5386 }
5387 } else {
5388 v4l2_err(v4l2_dev, "terminal_sensor is invalid\n");
5389 return -EINVAL;
5390 }
5391
5392 if (stream->cif_fmt_in->mbus_code == MEDIA_BUS_FMT_EBD_1X8 ||
5393 stream->cif_fmt_in->mbus_code == MEDIA_BUS_FMT_SPD_2X8) {
5394 stream->crop_enable = false;
5395 return 0;
5396 }
5397
5398 if (s_crop)
5399 crop = (struct v4l2_rect *)s_crop;
5400 else
5401 crop = &stream->crop[CROP_SRC_ACT];
5402
5403 if (crop->width + crop->left > input.width ||
5404 crop->height + crop->top > input.height) {
5405 v4l2_err(v4l2_dev, "crop size is bigger than input\n");
5406 return -EINVAL;
5407 }
5408
5409 if (dev->active_sensor &&
5410 (dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_DPHY ||
5411 dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_CPHY)) {
5412 if (crop->left > 0) {
5413 int align_x = get_csi_crop_align(stream->cif_fmt_in);
5414
5415 if (align_x > 0 && crop->left % align_x != 0) {
5416 v4l2_err(v4l2_dev,
5417 "ERROR: crop left must align %d\n",
5418 align_x);
5419 return -EINVAL;
5420 }
5421 }
5422 } else if (dev->active_sensor && dev->active_sensor->mbus.type == V4L2_MBUS_CCP2) {
5423 if (crop->left % 4 != 0 && crop->width % 4 != 0) {
5424 v4l2_err(v4l2_dev,
5425 "ERROR: lvds crop left and width must align %d\n", 4);
5426 return -EINVAL;
5427 }
5428 }
5429
5430 return 0;
5431 }
5432
rkcif_update_sensor_info(struct rkcif_stream * stream)5433 int rkcif_update_sensor_info(struct rkcif_stream *stream)
5434 {
5435 struct rkcif_sensor_info *sensor, *terminal_sensor;
5436 struct v4l2_subdev *sensor_sd;
5437 int ret = 0;
5438
5439 sensor_sd = get_remote_sensor(stream, NULL);
5440 if (!sensor_sd) {
5441 v4l2_err(&stream->cifdev->v4l2_dev,
5442 "%s: stream[%d] get remote sensor_sd failed!\n",
5443 __func__, stream->id);
5444 return -ENODEV;
5445 }
5446
5447 sensor = sd_to_sensor(stream->cifdev, sensor_sd);
5448 if (!sensor) {
5449 v4l2_err(&stream->cifdev->v4l2_dev,
5450 "%s: stream[%d] get remote sensor failed!\n",
5451 __func__, stream->id);
5452 return -ENODEV;
5453 }
5454 ret = v4l2_subdev_call(sensor->sd, pad, get_mbus_config,
5455 0, &sensor->mbus);
5456 if (ret && ret != -ENOIOCTLCMD) {
5457 v4l2_err(&stream->cifdev->v4l2_dev,
5458 "%s: get remote %s mbus failed!\n", __func__, sensor->sd->name);
5459 return ret;
5460 }
5461
5462 stream->cifdev->active_sensor = sensor;
5463
5464 terminal_sensor = &stream->cifdev->terminal_sensor;
5465 get_remote_terminal_sensor(stream, &terminal_sensor->sd);
5466 if (terminal_sensor->sd) {
5467 ret = v4l2_subdev_call(terminal_sensor->sd, pad, get_mbus_config,
5468 0, &terminal_sensor->mbus);
5469 if (ret && ret != -ENOIOCTLCMD) {
5470 v4l2_err(&stream->cifdev->v4l2_dev,
5471 "%s: get terminal %s mbus failed!\n",
5472 __func__, terminal_sensor->sd->name);
5473 return ret;
5474 }
5475 ret = v4l2_subdev_call(terminal_sensor->sd, video,
5476 g_frame_interval, &terminal_sensor->fi);
5477 if (ret) {
5478 v4l2_err(&stream->cifdev->v4l2_dev,
5479 "%s: get terminal %s g_frame_interval failed!\n",
5480 __func__, terminal_sensor->sd->name);
5481 return ret;
5482 }
5483 if (v4l2_subdev_call(terminal_sensor->sd, core, ioctl, RKMODULE_GET_CSI_DSI_INFO,
5484 &terminal_sensor->dsi_input_en)) {
5485 v4l2_dbg(1, rkcif_debug, &stream->cifdev->v4l2_dev,
5486 "%s: get terminal %s CSI/DSI sel failed, default csi input!\n",
5487 __func__, terminal_sensor->sd->name);
5488 terminal_sensor->dsi_input_en = 0;
5489 }
5490 } else {
5491 v4l2_err(&stream->cifdev->v4l2_dev,
5492 "%s: stream[%d] get remote terminal sensor failed!\n",
5493 __func__, stream->id);
5494 return -ENODEV;
5495 }
5496
5497 if (terminal_sensor->mbus.type == V4L2_MBUS_CSI2_DPHY ||
5498 terminal_sensor->mbus.type == V4L2_MBUS_CSI2_CPHY ||
5499 terminal_sensor->mbus.type == V4L2_MBUS_CCP2) {
5500 switch (terminal_sensor->mbus.flags & V4L2_MBUS_CSI2_LANES) {
5501 case V4L2_MBUS_CSI2_1_LANE:
5502 terminal_sensor->lanes = 1;
5503 break;
5504 case V4L2_MBUS_CSI2_2_LANE:
5505 terminal_sensor->lanes = 2;
5506 break;
5507 case V4L2_MBUS_CSI2_3_LANE:
5508 terminal_sensor->lanes = 3;
5509 break;
5510 case V4L2_MBUS_CSI2_4_LANE:
5511 terminal_sensor->lanes = 4;
5512 break;
5513 default:
5514 v4l2_err(&stream->cifdev->v4l2_dev, "%s:get sd:%s lane num failed!\n",
5515 __func__,
5516 terminal_sensor->sd ?
5517 terminal_sensor->sd->name : "null");
5518 return -EINVAL;
5519 }
5520 }
5521
5522 return ret;
5523 }
5524
rkcif_dvp_get_output_type_mask(struct rkcif_stream * stream)5525 static int rkcif_dvp_get_output_type_mask(struct rkcif_stream *stream)
5526 {
5527 unsigned int mask;
5528 const struct cif_output_fmt *fmt = stream->cif_fmt_out;
5529
5530 switch (fmt->fourcc) {
5531 case V4L2_PIX_FMT_NV16:
5532 mask = (CSI_WRDDR_TYPE_YUV422SP_RK3588 << 11) |
5533 (CSI_YUV_OUTPUT_ORDER_UYVY << 1);
5534 break;
5535 case V4L2_PIX_FMT_NV61:
5536 mask = (CSI_WRDDR_TYPE_YUV422SP_RK3588 << 11) |
5537 (CSI_YUV_OUTPUT_ORDER_VYUY << 1);
5538 break;
5539 case V4L2_PIX_FMT_NV12:
5540 mask = (CSI_WRDDR_TYPE_YUV420SP_RK3588 << 11) |
5541 (CSI_YUV_OUTPUT_ORDER_UYVY << 1);
5542 break;
5543 case V4L2_PIX_FMT_NV21:
5544 mask = (CSI_WRDDR_TYPE_YUV420SP_RK3588 << 11) |
5545 (CSI_YUV_OUTPUT_ORDER_VYUY << 1);
5546 break;
5547 case V4L2_PIX_FMT_YUYV:
5548 mask = (CSI_WRDDR_TYPE_YUV_PACKET << 11) |
5549 (CSI_YUV_OUTPUT_ORDER_YUYV << 1);
5550 break;
5551 case V4L2_PIX_FMT_YVYU:
5552 mask = (CSI_WRDDR_TYPE_YUV_PACKET << 11) |
5553 (CSI_YUV_OUTPUT_ORDER_YVYU << 1);
5554 break;
5555 case V4L2_PIX_FMT_UYVY:
5556 mask = (CSI_WRDDR_TYPE_YUV_PACKET << 11) |
5557 (CSI_YUV_OUTPUT_ORDER_UYVY << 1);
5558 break;
5559 case V4L2_PIX_FMT_VYUY:
5560 mask = (CSI_WRDDR_TYPE_YUV_PACKET << 11) |
5561 (CSI_YUV_OUTPUT_ORDER_VYUY << 1);
5562 break;
5563 case V4L2_PIX_FMT_RGB24:
5564 case V4L2_PIX_FMT_BGR24:
5565 case V4L2_PIX_FMT_RGB565:
5566 case V4L2_PIX_FMT_BGR666:
5567 mask = CSI_WRDDR_TYPE_RAW_COMPACT << 11;
5568 break;
5569 case V4L2_PIX_FMT_SRGGB8:
5570 case V4L2_PIX_FMT_SGRBG8:
5571 case V4L2_PIX_FMT_SGBRG8:
5572 case V4L2_PIX_FMT_SBGGR8:
5573 case V4L2_PIX_FMT_SRGGB10:
5574 case V4L2_PIX_FMT_SGRBG10:
5575 case V4L2_PIX_FMT_SGBRG10:
5576 case V4L2_PIX_FMT_SBGGR10:
5577 case V4L2_PIX_FMT_SRGGB12:
5578 case V4L2_PIX_FMT_SGRBG12:
5579 case V4L2_PIX_FMT_SGBRG12:
5580 case V4L2_PIX_FMT_SBGGR12:
5581 case V4L2_PIX_FMT_GREY:
5582 case V4L2_PIX_FMT_Y10:
5583 case V4L2_PIX_FMT_Y12:
5584 if (stream->is_compact)
5585 mask = CSI_WRDDR_TYPE_RAW_COMPACT << 11;
5586 else
5587 mask = CSI_WRDDR_TYPE_RAW_UNCOMPACT << 11;
5588 break;
5589 case V4L2_PIX_FMT_SBGGR16:
5590 case V4L2_PIX_FMT_SGBRG16:
5591 case V4L2_PIX_FMT_SGRBG16:
5592 case V4L2_PIX_FMT_SRGGB16:
5593 case V4L2_PIX_FMT_Y16:
5594 mask = CSI_WRDDR_TYPE_RAW_UNCOMPACT << 11;
5595 break;
5596 default:
5597 mask = CSI_WRDDR_TYPE_RAW_COMPACT << 11;
5598 break;
5599 }
5600 return mask;
5601 }
5602
rkcif_stream_start(struct rkcif_stream * stream,unsigned int mode)5603 static int rkcif_stream_start(struct rkcif_stream *stream, unsigned int mode)
5604 {
5605 u32 val, mbus_flags, href_pol, vsync_pol,
5606 xfer_mode = 0, yc_swap = 0, inputmode = 0,
5607 mipimode = 0, workmode = 0, multi_id = 0,
5608 multi_id_en = BT656_1120_MULTI_ID_DISABLE,
5609 multi_id_mode = BT656_1120_MULTI_ID_MODE_1,
5610 multi_id_sel = BT656_1120_MULTI_ID_SEL_LSB,
5611 bt1120_edge_mode = BT1120_CLOCK_SINGLE_EDGES,
5612 bt1120_flags = 0,
5613 out_fmt_mask = 0,
5614 in_fmt_yuv_order = 0;
5615 struct rkmodule_bt656_mbus_info bt1120_info;
5616 struct rkcif_device *dev = stream->cifdev;
5617 struct rkcif_sensor_info *sensor_info;
5618 struct v4l2_mbus_config *mbus;
5619 struct rkcif_dvp_sof_subdev *sof_sd = &dev->dvp_sof_subdev;
5620 const struct cif_output_fmt *fmt;
5621 unsigned int dma_en = 0;
5622 unsigned int dma_state = 0;
5623 int i = 0;
5624 u32 sav_detect = BT656_DETECT_SAV;
5625 u32 reserved = 0;
5626
5627 if (stream->state < RKCIF_STATE_STREAMING) {
5628 stream->frame_idx = 0;
5629 stream->buf_wake_up_cnt = 0;
5630 stream->lack_buf_cnt = 0;
5631 stream->frame_phase = 0;
5632 stream->is_in_vblank = false;
5633 stream->is_change_toisp = false;
5634 }
5635
5636 sensor_info = dev->active_sensor;
5637 mbus = &sensor_info->mbus;
5638
5639 dma_state = stream->dma_en;
5640 if ((mode & RKCIF_STREAM_MODE_CAPTURE) == RKCIF_STREAM_MODE_CAPTURE)
5641 stream->dma_en |= RKCIF_DMAEN_BY_VICAP;
5642 else if ((mode & RKCIF_STREAM_MODE_TOISP_RDBK) == RKCIF_STREAM_MODE_TOISP_RDBK)
5643 stream->dma_en |= RKCIF_DMAEN_BY_ISP;
5644 else if ((mode & RKCIF_STREAM_MODE_ROCKIT) == RKCIF_STREAM_MODE_ROCKIT)
5645 stream->dma_en |= RKCIF_DMAEN_BY_ROCKIT;
5646
5647 if (dma_state)
5648 return 0;
5649
5650 mbus_flags = mbus->flags;
5651 if ((mbus_flags & CIF_DVP_PCLK_DUAL_EDGE) == CIF_DVP_PCLK_DUAL_EDGE) {
5652 bt1120_edge_mode = (dev->chip_id < CHIP_RK3588_CIF ?
5653 BT1120_CLOCK_DOUBLE_EDGES : BT1120_CLOCK_DOUBLE_EDGES_RK3588);
5654 rkcif_enable_dvp_clk_dual_edge(dev, true);
5655 } else {
5656 bt1120_edge_mode = dev->chip_id < CHIP_RK3588_CIF ?
5657 BT1120_CLOCK_SINGLE_EDGES : BT1120_CLOCK_SINGLE_EDGES_RK3588;
5658 rkcif_enable_dvp_clk_dual_edge(dev, false);
5659 }
5660
5661 if (IS_ENABLED(CONFIG_CPU_RV1106))
5662 rkcif_config_dvp_pin(dev, true);
5663
5664 if (mbus_flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
5665 rkcif_config_dvp_clk_sampling_edge(dev, RKCIF_CLK_RISING);
5666 else
5667 rkcif_config_dvp_clk_sampling_edge(dev, RKCIF_CLK_FALLING);
5668
5669 #if IS_ENABLED(CONFIG_CPU_RV1106)
5670 rv1106_sdmmc_get_lock();
5671 #endif
5672 if (sensor_info->sd && mbus->type == V4L2_MBUS_BT656) {
5673 int ret;
5674
5675 multi_id_en = BT656_1120_MULTI_ID_ENABLE;
5676
5677 ret = v4l2_subdev_call(sensor_info->sd,
5678 core, ioctl,
5679 RKMODULE_GET_BT656_MBUS_INFO,
5680 &bt1120_info);
5681 if (ret) {
5682 v4l2_warn(&dev->v4l2_dev,
5683 "waring: no muti channel info for BT.656\n");
5684 } else {
5685 bt1120_flags = bt1120_info.flags;
5686 if (bt1120_flags & RKMODULE_CAMERA_BT656_PARSE_ID_LSB)
5687 multi_id_sel = BT656_1120_MULTI_ID_SEL_LSB;
5688 else
5689 multi_id_sel = BT656_1120_MULTI_ID_SEL_MSB;
5690
5691 if (((bt1120_flags & RKMODULE_CAMERA_BT656_CHANNELS) >> 2) > 3)
5692 multi_id_mode = BT656_1120_MULTI_ID_MODE_4;
5693 else if (((bt1120_flags & RKMODULE_CAMERA_BT656_CHANNELS) >> 2) > 1)
5694 multi_id_mode = BT656_1120_MULTI_ID_MODE_2;
5695 for (i = 0; i < 4; i++)
5696 multi_id |= DVP_SW_MULTI_ID(i, i, bt1120_info.id_en_bits);
5697 rkcif_write_register_or(dev, CIF_REG_DVP_MULTI_ID, multi_id);
5698 }
5699 }
5700
5701 href_pol = (mbus_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) ?
5702 HSY_HIGH_ACTIVE : HSY_LOW_ACTIVE;
5703 vsync_pol = (mbus_flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH) ?
5704 VSY_HIGH_ACTIVE : VSY_LOW_ACTIVE;
5705
5706 if (dev->chip_id < CHIP_RK3588_CIF)
5707 inputmode = rkcif_determine_input_mode(stream);
5708 else
5709 inputmode = rkcif_determine_input_mode_rk3588(stream);
5710 if (dev->chip_id <= CHIP_RK1808_CIF) {
5711 if (inputmode == INPUT_MODE_BT1120) {
5712 if (stream->cif_fmt_in->field == V4L2_FIELD_NONE)
5713 xfer_mode = BT1120_TRANSMIT_PROGRESS;
5714 else
5715 xfer_mode = BT1120_TRANSMIT_INTERFACE;
5716 if (CIF_FETCH_IS_Y_FIRST(stream->cif_fmt_in->dvp_fmt_val))
5717 yc_swap = BT1120_YC_SWAP;
5718 }
5719 } else if (dev->chip_id < CHIP_RK3588_CIF) {
5720 if (sensor_info->mbus.type == V4L2_MBUS_BT656) {
5721 if (stream->cif_fmt_in->field == V4L2_FIELD_NONE)
5722 xfer_mode = BT1120_TRANSMIT_PROGRESS;
5723 else
5724 xfer_mode = BT1120_TRANSMIT_INTERFACE;
5725 }
5726
5727 if (inputmode == INPUT_MODE_BT1120) {
5728 if (CIF_FETCH_IS_Y_FIRST(stream->cif_fmt_in->dvp_fmt_val))
5729 yc_swap = BT1120_YC_SWAP;
5730 }
5731 } else {
5732 if ((inputmode & INPUT_BT1120_YUV422) == INPUT_BT1120_YUV422)
5733 if (CIF_FETCH_IS_Y_FIRST(stream->cif_fmt_in->dvp_fmt_val))
5734 yc_swap = BT1120_YC_SWAP_RK3588;
5735 }
5736
5737 if (dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_DPHY ||
5738 dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_CPHY) {
5739 inputmode = INPUT_MODE_MIPI;
5740
5741 /* if cif is linked with mipi,
5742 * href pol must be set as high active,
5743 * vsyn pol must be set as low active.
5744 */
5745 href_pol = HSY_HIGH_ACTIVE;
5746 vsync_pol = VSY_LOW_ACTIVE;
5747
5748 if (stream->cif_fmt_in->fmt_type == CIF_FMT_TYPE_YUV)
5749 mipimode = MIPI_MODE_YUV;
5750 else if (stream->cif_fmt_in->fmt_type == CIF_FMT_TYPE_RAW)
5751 mipimode = MIPI_MODE_RGB;
5752 else
5753 mipimode = MIPI_MODE_32BITS_BYPASS;
5754 }
5755
5756 if (dev->chip_id < CHIP_RK3588_CIF) {
5757 val = vsync_pol | href_pol | inputmode | mipimode
5758 | stream->cif_fmt_out->fmt_val
5759 | stream->cif_fmt_in->dvp_fmt_val
5760 | xfer_mode | yc_swap | multi_id_en
5761 | multi_id_sel | multi_id_mode | bt1120_edge_mode;
5762 if (stream->is_high_align)
5763 val |= CIF_HIGH_ALIGN;
5764 else
5765 val &= ~CIF_HIGH_ALIGN;
5766 } else {
5767 out_fmt_mask = rkcif_dvp_get_output_type_mask(stream);
5768 in_fmt_yuv_order = rkcif_dvp_get_input_yuv_order(stream);
5769 val = vsync_pol | href_pol | inputmode
5770 | yc_swap
5771 | out_fmt_mask
5772 | in_fmt_yuv_order
5773 | multi_id_en
5774 | sav_detect
5775 | multi_id_sel | multi_id_mode | bt1120_edge_mode;
5776 if (stream->is_high_align)
5777 val |= CIF_HIGH_ALIGN_RK3588;
5778 else
5779 val &= ~CIF_HIGH_ALIGN_RK3588;
5780 }
5781 rkcif_write_register(dev, CIF_REG_DVP_FOR, val);
5782
5783 if (dev->chip_id >= CHIP_RK3588_CIF) {
5784 val = stream->pixm.plane_fmt[0].bytesperline;
5785 } else {
5786 fmt = rkcif_find_output_fmt(stream, stream->pixm.pixelformat);
5787 if (fmt->fmt_type == CIF_FMT_TYPE_RAW &&
5788 fmt->csi_fmt_val == CSI_WRDDR_TYPE_RAW8)
5789 val = ALIGN(stream->pixm.width * fmt->raw_bpp / 8, 256);
5790 else
5791 val = stream->pixm.width * rkcif_cal_raw_vir_line_ratio(stream, fmt);
5792 }
5793
5794 if (stream->crop_enable) {
5795 dev->channels[stream->id].crop_en = 1;
5796 dev->channels[stream->id].crop_st_x = stream->crop[CROP_SRC_ACT].left;
5797 dev->channels[stream->id].crop_st_y = stream->crop[CROP_SRC_ACT].top;
5798 dev->channels[stream->id].width = stream->crop[CROP_SRC_ACT].width;
5799 dev->channels[stream->id].height = stream->crop[CROP_SRC_ACT].height;
5800 } else {
5801 dev->channels[stream->id].crop_st_y = 0;
5802 dev->channels[stream->id].crop_st_x = 0;
5803 dev->channels[stream->id].width = stream->pixm.width;
5804 dev->channels[stream->id].height = stream->pixm.height;
5805 dev->channels[stream->id].crop_en = 0;
5806 }
5807
5808 rkcif_write_register(dev, CIF_REG_DVP_VIR_LINE_WIDTH, val);
5809 rkcif_write_register(dev, CIF_REG_DVP_SET_SIZE,
5810 dev->channels[stream->id].width |
5811 (dev->channels[stream->id].height << 16));
5812 rkcif_write_register(dev, CIF_REG_DVP_CROP,
5813 dev->channels[stream->id].crop_st_y << CIF_CROP_Y_SHIFT |
5814 dev->channels[stream->id].crop_st_x);
5815
5816 if (atomic_read(&dev->pipe.stream_cnt) <= 1)
5817 rkcif_write_register(dev, CIF_REG_DVP_FRAME_STATUS, FRAME_STAT_CLS);
5818
5819 if (dev->chip_id < CHIP_RK3588_CIF) {
5820 rkcif_write_register(dev, CIF_REG_DVP_INTSTAT, INTSTAT_CLS);
5821 rkcif_write_register(dev, CIF_REG_DVP_SCL_CTRL, rkcif_scl_ctl(stream));
5822 rkcif_write_register_or(dev, CIF_REG_DVP_INTEN,
5823 DVP_DMA_END_INTSTAT(stream->id) |
5824 INTSTAT_ERR | PST_INF_FRAME_END);
5825 /* enable line int for sof */
5826 rkcif_write_register(dev, CIF_REG_DVP_LINE_INT_NUM, 0x1);
5827 rkcif_write_register_or(dev, CIF_REG_DVP_INTEN, LINE_INT_EN);
5828 } else {
5829 if (dev->chip_id == CHIP_RV1106_CIF)
5830 reserved = 0xfc3c0000;
5831 else
5832 reserved = 0;
5833 rkcif_write_register(dev, CIF_REG_DVP_INTSTAT, 0x3c3ffff | reserved);
5834 rkcif_write_register_or(dev, CIF_REG_DVP_INTEN, 0x033ffff);//0x3c3ffff
5835 }
5836
5837 if (stream->dma_en) {
5838 if (dev->chip_id < CHIP_RK1808_CIF) {
5839 rkcif_assign_new_buffer_oneframe(stream,
5840 RKCIF_YUV_ADDR_STATE_INIT);
5841 } else {
5842 if (mode == RKCIF_STREAM_MODE_CAPTURE)
5843 rkcif_assign_new_buffer_pingpong(stream,
5844 RKCIF_YUV_ADDR_STATE_INIT,
5845 stream->id);
5846 else if (mode == RKCIF_STREAM_MODE_TOISP ||
5847 mode == RKCIF_STREAM_MODE_TOISP_RDBK)
5848 rkcif_assign_new_buffer_pingpong_toisp(stream,
5849 RKCIF_YUV_ADDR_STATE_INIT,
5850 stream->id);
5851 else if (mode == RKCIF_STREAM_MODE_ROCKIT)
5852 rkcif_assign_new_buffer_pingpong_rockit(stream,
5853 RKCIF_YUV_ADDR_STATE_INIT,
5854 stream->id);
5855 }
5856 }
5857 rkcif_write_register_or(dev, CIF_REG_DVP_INTEN,
5858 DVP_DMA_END_INTSTAT(stream->id) |
5859 INTSTAT_ERR | PST_INF_FRAME_END);
5860
5861 /* enable line int for sof */
5862 rkcif_write_register(dev, CIF_REG_DVP_LINE_INT_NUM, 0x1);
5863 rkcif_write_register_or(dev, CIF_REG_DVP_INTEN, LINE_INT_EN);
5864
5865 if (dev->workmode == RKCIF_WORKMODE_ONEFRAME)
5866 workmode = MODE_ONEFRAME;
5867 else if (dev->workmode == RKCIF_WORKMODE_PINGPONG)
5868 workmode = MODE_PINGPONG;
5869 else
5870 workmode = MODE_LINELOOP;
5871
5872 if ((inputmode & INPUT_MODE_BT1120) == INPUT_MODE_BT1120) {
5873 workmode = MODE_PINGPONG;
5874 dev->workmode = RKCIF_WORKMODE_PINGPONG;
5875 }
5876
5877 if (dev->chip_id == CHIP_RK3588_CIF) {
5878 if (stream->dma_en)
5879 dma_en = DVP_DMA_EN;
5880 if (stream->lack_buf_cnt == 2)
5881 dma_en = 0;
5882 rkcif_write_register(dev, CIF_REG_DVP_CTRL,
5883 DVP_SW_WATER_LINE_25
5884 | dma_en
5885 | DVP_PRESS_EN
5886 | DVP_HURRY_EN
5887 | DVP_SW_WATER_LINE_25
5888 | DVP_SW_PRESS_VALUE(3)
5889 | DVP_SW_HURRY_VALUE(3)
5890 | ENABLE_CAPTURE);
5891 } else if (dev->chip_id == CHIP_RV1106_CIF) {
5892 if (stream->dma_en)
5893 dma_en = DVP_SW_DMA_EN(stream->id);
5894 if (stream->lack_buf_cnt == 2)
5895 dma_en = 0;
5896 rkcif_write_register(dev, CIF_REG_DVP_CTRL,
5897 DVP_SW_WATER_LINE_25
5898 | DVP_PRESS_EN
5899 | DVP_HURRY_EN
5900 | DVP_SW_WATER_LINE_25
5901 | DVP_SW_PRESS_VALUE(3)
5902 | DVP_SW_HURRY_VALUE(3)
5903 | DVP_SW_CAP_EN(stream->id)
5904 | dma_en
5905 | ENABLE_CAPTURE);
5906 } else {
5907 rkcif_write_register(dev, CIF_REG_DVP_CTRL,
5908 AXI_BURST_16 | workmode | ENABLE_CAPTURE);
5909 }
5910 #if IS_ENABLED(CONFIG_CPU_RV1106)
5911 rv1106_sdmmc_put_lock();
5912 #endif
5913 atomic_set(&sof_sd->frm_sync_seq, 0);
5914 stream->state = RKCIF_STATE_STREAMING;
5915 stream->cifdev->dvp_sof_in_oneframe = 0;
5916
5917 return 0;
5918 }
5919
rkcif_attach_sync_mode(struct rkcif_device * cifdev)5920 static void rkcif_attach_sync_mode(struct rkcif_device *cifdev)
5921 {
5922 struct rkcif_hw *hw = cifdev->hw_dev;
5923 struct rkcif_device *dev;
5924 struct sditf_priv *priv;
5925 int i = 0, j = 0;
5926 int ret = 0;
5927 int count = 0;
5928 int sync_type = NO_SYNC_MODE;
5929 int sync_group = 0;
5930 struct rkcif_sync_cfg sync_cfg;
5931 struct rkcif_multi_sync_config *sync_config;
5932
5933 mutex_lock(&hw->dev_lock);
5934 if (cifdev->sditf_cnt <= 1) {
5935 ret = v4l2_subdev_call(cifdev->terminal_sensor.sd,
5936 core, ioctl,
5937 RKMODULE_GET_SYNC_MODE,
5938 &sync_type);
5939 if (!ret)
5940 sync_cfg.type = sync_type;
5941 else
5942 sync_cfg.type = NO_SYNC_MODE;
5943 ret = v4l2_subdev_call(cifdev->terminal_sensor.sd,
5944 core, ioctl,
5945 RKMODULE_GET_GROUP_ID,
5946 &sync_group);
5947 if (!ret && sync_group < RKCIF_MAX_GROUP)
5948 sync_cfg.group = sync_group;
5949 else
5950 sync_cfg.group = 0;
5951 } else {
5952 for (j = 0; j < cifdev->sditf_cnt; j++) {
5953 ret |= v4l2_subdev_call(cifdev->sditf[j]->sensor_sd,
5954 core, ioctl,
5955 RKMODULE_GET_SYNC_MODE,
5956 &sync_type);
5957 if (!ret && sync_type)
5958 break;
5959 }
5960 if (!ret)
5961 sync_cfg.type = sync_type;
5962 else
5963 sync_cfg.type = NO_SYNC_MODE;
5964 ret = v4l2_subdev_call(cifdev->sditf[j]->sensor_sd,
5965 core, ioctl,
5966 RKMODULE_GET_GROUP_ID,
5967 &sync_group);
5968 if (!ret && sync_group < RKCIF_MAX_GROUP)
5969 sync_cfg.group = sync_group;
5970 else
5971 sync_cfg.group = 0;
5972 }
5973 cifdev->sync_cfg = sync_cfg;
5974 if (sync_cfg.type == NO_SYNC_MODE ||
5975 hw->sync_config[sync_cfg.group].is_attach) {
5976 mutex_unlock(&hw->dev_lock);
5977 return;
5978 }
5979
5980 sync_config = &hw->sync_config[sync_cfg.group];
5981 memset(sync_config, 0, sizeof(struct rkcif_multi_sync_config));
5982 for (i = 0; i < hw->dev_num; i++) {
5983 dev = hw->cif_dev[i];
5984 if (dev->sditf_cnt <= 1) {
5985 ret = v4l2_subdev_call(dev->terminal_sensor.sd,
5986 core, ioctl,
5987 RKMODULE_GET_SYNC_MODE,
5988 &sync_type);
5989 if (!ret)
5990 sync_cfg.type = sync_type;
5991 else
5992 sync_cfg.type = NO_SYNC_MODE;
5993 ret = v4l2_subdev_call(dev->terminal_sensor.sd,
5994 core, ioctl,
5995 RKMODULE_GET_GROUP_ID,
5996 &sync_group);
5997 if (!ret && sync_group < RKCIF_MAX_GROUP)
5998 sync_cfg.group = sync_group;
5999 else
6000 sync_cfg.group = 0;
6001 } else {
6002 priv = dev->sditf[0];
6003 if (priv && priv->is_combine_mode && dev->sditf_cnt <= RKCIF_MAX_SDITF) {
6004 for (j = 0; j < dev->sditf_cnt; j++) {
6005 ret |= v4l2_subdev_call(dev->sditf[j]->sensor_sd,
6006 core, ioctl,
6007 RKMODULE_GET_SYNC_MODE,
6008 &sync_type);
6009 if (!ret && sync_type) {
6010 priv = dev->sditf[j];
6011 break;
6012 }
6013 }
6014 if (!ret)
6015 sync_cfg.type = sync_type;
6016 else
6017 sync_cfg.type = NO_SYNC_MODE;
6018 ret = v4l2_subdev_call(priv->sensor_sd,
6019 core, ioctl,
6020 RKMODULE_GET_GROUP_ID,
6021 &sync_group);
6022 if (!ret && sync_group < RKCIF_MAX_GROUP)
6023 sync_cfg.group = sync_group;
6024 else
6025 sync_cfg.group = 0;
6026 }
6027 }
6028 if (sync_cfg.group == cifdev->sync_cfg.group) {
6029 if (sync_cfg.type == EXTERNAL_MASTER_MODE) {
6030 count = sync_config->ext_master.count;
6031 sync_config->ext_master.cif_dev[count] = dev;
6032 sync_config->ext_master.count++;
6033 sync_config->dev_cnt++;
6034 sync_config->sync_mask |= BIT(dev->csi_host_idx);
6035 } else if (sync_cfg.type == INTERNAL_MASTER_MODE) {
6036 count = sync_config->int_master.count;
6037 sync_config->int_master.cif_dev[count] = dev;
6038 sync_config->int_master.count++;
6039 sync_config->dev_cnt++;
6040 sync_config->sync_mask |= BIT(dev->csi_host_idx);
6041 } else if (sync_cfg.type == SLAVE_MODE) {
6042 count = sync_config->slave.count;
6043 sync_config->slave.cif_dev[count] = dev;
6044 sync_config->slave.count++;
6045 sync_config->dev_cnt++;
6046 sync_config->sync_mask |= BIT(dev->csi_host_idx);
6047 }
6048 dev->sync_cfg = sync_cfg;
6049 } else {
6050 ret = v4l2_subdev_call(dev->terminal_sensor.sd,
6051 core, ioctl,
6052 RKMODULE_GET_SYNC_MODE,
6053 &sync_type);
6054 }
6055 }
6056 if (sync_config->int_master.count == 1) {
6057 if (sync_config->ext_master.count) {
6058 sync_config->mode = RKCIF_MASTER_MASTER;
6059 sync_config->is_attach = true;
6060 } else if (sync_config->slave.count) {
6061 sync_config->mode = RKCIF_MASTER_SLAVE;
6062 sync_config->is_attach = true;
6063 } else {
6064 dev_info(hw->dev,
6065 "Missing slave device, do not use sync mode\n");
6066 }
6067 if (sync_config->is_attach)
6068 dev_info(hw->dev,
6069 "group %d, int_master %d, ext_master %d, slave %d\n",
6070 i,
6071 sync_config->int_master.count,
6072 sync_config->ext_master.count,
6073 sync_config->slave.count);
6074 }
6075 mutex_unlock(&hw->dev_lock);
6076 }
6077
6078 static void rkcif_monitor_reset_event(struct rkcif_device *dev);
6079
rkcif_do_start_stream(struct rkcif_stream * stream,unsigned int mode)6080 int rkcif_do_start_stream(struct rkcif_stream *stream, unsigned int mode)
6081 {
6082 struct rkcif_vdev_node *node = &stream->vnode;
6083 struct rkcif_device *dev = stream->cifdev;
6084 struct rkcif_hw *hw_dev = dev->hw_dev;
6085 struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
6086 struct rkcif_sensor_info *sensor_info = dev->active_sensor;
6087 struct rkcif_sensor_info *terminal_sensor = NULL;
6088 struct rkmodule_hdr_cfg hdr_cfg;
6089 struct rkcif_csi_info csi_info = {0};
6090 int rkmodule_stream_seq = RKMODULE_START_STREAM_DEFAULT;
6091 int ret;
6092 int i = 0;
6093
6094 v4l2_info(&dev->v4l2_dev, "stream[%d] start streaming\n", stream->id);
6095
6096 rkcif_attach_sync_mode(dev);
6097 mutex_lock(&dev->stream_lock);
6098
6099 if ((stream->cur_stream_mode & RKCIF_STREAM_MODE_CAPTURE) == mode) {
6100 ret = -EBUSY;
6101 v4l2_err(v4l2_dev, "stream in busy state\n");
6102 goto destroy_buf;
6103 }
6104 if (stream->dma_en == 0)
6105 stream->fs_cnt_in_single_frame = 0;
6106 if (stream->is_line_wake_up)
6107 stream->is_line_inten = true;
6108 else
6109 stream->is_line_inten = false;
6110
6111 if (!dev->active_sensor) {
6112 ret = rkcif_update_sensor_info(stream);
6113 if (ret < 0) {
6114 v4l2_err(v4l2_dev,
6115 "update sensor info failed %d\n",
6116 ret);
6117 goto out;
6118 }
6119 }
6120 terminal_sensor = &dev->terminal_sensor;
6121 if (terminal_sensor->sd) {
6122 ret = v4l2_subdev_call(terminal_sensor->sd,
6123 core, ioctl,
6124 RKMODULE_GET_HDR_CFG,
6125 &hdr_cfg);
6126 if (!ret)
6127 dev->hdr = hdr_cfg;
6128 else
6129 dev->hdr.hdr_mode = NO_HDR;
6130
6131 ret = v4l2_subdev_call(terminal_sensor->sd,
6132 video, g_frame_interval, &terminal_sensor->fi);
6133 if (ret)
6134 terminal_sensor->fi.interval = (struct v4l2_fract) {1, 30};
6135
6136 ret = v4l2_subdev_call(terminal_sensor->sd,
6137 core, ioctl,
6138 RKMODULE_GET_START_STREAM_SEQ,
6139 &rkmodule_stream_seq);
6140 if (ret)
6141 rkmodule_stream_seq = RKMODULE_START_STREAM_DEFAULT;
6142
6143 rkcif_sync_crop_info(stream);
6144 }
6145
6146 ret = rkcif_sanity_check_fmt(stream, NULL);
6147 if (ret < 0)
6148 goto destroy_buf;
6149
6150 mutex_lock(&hw_dev->dev_lock);
6151 if (atomic_read(&dev->pipe.stream_cnt) == 0 &&
6152 dev->active_sensor &&
6153 (dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_DPHY ||
6154 dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_CPHY ||
6155 dev->active_sensor->mbus.type == V4L2_MBUS_CCP2)) {
6156 if (dev->channels[0].capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
6157 csi_info.csi_num = dev->channels[0].capture_info.multi_dev.dev_num;
6158 if (csi_info.csi_num > RKCIF_MAX_CSI_NUM) {
6159 v4l2_err(v4l2_dev,
6160 "csi num %d, max %d\n",
6161 csi_info.csi_num, RKCIF_MAX_CSI_NUM);
6162 goto out;
6163 }
6164 for (i = 0; i < csi_info.csi_num; i++) {
6165 csi_info.csi_idx[i] = dev->channels[0].capture_info.multi_dev.dev_idx[i];
6166 if (dev->hw_dev->is_rk3588s2)
6167 v4l2_info(v4l2_dev, "rk3588s2 combine mode attach to mipi%d\n",
6168 csi_info.csi_idx[i]);
6169 }
6170 } else {
6171 csi_info.csi_num = 1;
6172 dev->csi_host_idx = dev->csi_host_idx_def;
6173 csi_info.csi_idx[0] = dev->csi_host_idx;
6174 }
6175 ret = v4l2_subdev_call(dev->active_sensor->sd,
6176 core, ioctl,
6177 RKCIF_CMD_SET_CSI_IDX,
6178 &csi_info);
6179 if (ret)
6180 v4l2_err(&dev->v4l2_dev, "set csi idx %d fail\n", dev->csi_host_idx);
6181
6182 }
6183
6184 if (((dev->active_sensor && dev->active_sensor->mbus.type == V4L2_MBUS_BT656) ||
6185 dev->is_use_dummybuf) &&
6186 (!dev->hw_dev->dummy_buf.vaddr) &&
6187 mode == RKCIF_STREAM_MODE_CAPTURE) {
6188 ret = rkcif_create_dummy_buf(stream);
6189 if (ret < 0) {
6190 mutex_unlock(&hw_dev->dev_lock);
6191 v4l2_err(v4l2_dev, "Failed to create dummy_buf, %d\n", ret);
6192 goto destroy_buf;
6193 }
6194 }
6195 mutex_unlock(&hw_dev->dev_lock);
6196
6197 if (stream->cur_stream_mode == RKCIF_STREAM_MODE_NONE) {
6198 tasklet_enable(&stream->vb_done_tasklet);
6199 ret = dev->pipe.open(&dev->pipe, &node->vdev.entity, true);
6200 if (ret < 0) {
6201 v4l2_err(v4l2_dev, "open cif pipeline failed %d\n",
6202 ret);
6203 goto destroy_buf;
6204 }
6205
6206 /*
6207 * start sub-devices
6208 * When use bt601, the sampling edge of cif is random,
6209 * can be rising or fallling after powering on cif.
6210 * To keep the coherence of edge, open sensor in advance.
6211 */
6212 if (sensor_info->mbus.type == V4L2_MBUS_PARALLEL ||
6213 rkmodule_stream_seq == RKMODULE_START_STREAM_FRONT) {
6214 ret = dev->pipe.set_stream(&dev->pipe, true);
6215 if (ret < 0)
6216 goto runtime_put;
6217 }
6218 }
6219 if (dev->chip_id >= CHIP_RK1808_CIF) {
6220 if (dev->active_sensor &&
6221 (dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_DPHY ||
6222 dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_CPHY ||
6223 dev->active_sensor->mbus.type == V4L2_MBUS_CCP2))
6224 ret = rkcif_csi_stream_start(stream, mode);
6225 else
6226 ret = rkcif_stream_start(stream, mode);
6227 } else {
6228 ret = rkcif_stream_start(stream, mode);
6229 }
6230
6231 if (ret < 0)
6232 goto runtime_put;
6233
6234 if (stream->cur_stream_mode == RKCIF_STREAM_MODE_NONE) {
6235 ret = media_pipeline_start(&node->vdev.entity, &dev->pipe.pipe);
6236 if (ret < 0) {
6237 v4l2_err(&dev->v4l2_dev, "start pipeline failed %d\n",
6238 ret);
6239 goto pipe_stream_off;
6240 }
6241
6242 if (sensor_info->mbus.type != V4L2_MBUS_PARALLEL &&
6243 rkmodule_stream_seq != RKMODULE_START_STREAM_FRONT) {
6244 ret = dev->pipe.set_stream(&dev->pipe, true);
6245 if (ret < 0)
6246 goto stop_stream;
6247 }
6248 }
6249 if (dev->chip_id == CHIP_RV1126_CIF ||
6250 dev->chip_id == CHIP_RV1126_CIF_LITE ||
6251 dev->chip_id == CHIP_RK3568_CIF) {
6252 if (dev->hdr.hdr_mode == NO_HDR) {
6253 if (dev->stream[RKCIF_STREAM_MIPI_ID0].state == RKCIF_STATE_STREAMING)
6254 rkcif_start_luma(&dev->luma_vdev,
6255 dev->stream[RKCIF_STREAM_MIPI_ID0].cif_fmt_in);
6256 } else if (dev->hdr.hdr_mode == HDR_X2) {
6257 if (dev->stream[RKCIF_STREAM_MIPI_ID0].state == RKCIF_STATE_STREAMING &&
6258 dev->stream[RKCIF_STREAM_MIPI_ID1].state == RKCIF_STATE_STREAMING)
6259 rkcif_start_luma(&dev->luma_vdev,
6260 dev->stream[RKCIF_STREAM_MIPI_ID0].cif_fmt_in);
6261 } else if (dev->hdr.hdr_mode == HDR_X3) {
6262 if (dev->stream[RKCIF_STREAM_MIPI_ID0].state == RKCIF_STATE_STREAMING &&
6263 dev->stream[RKCIF_STREAM_MIPI_ID1].state == RKCIF_STATE_STREAMING &&
6264 dev->stream[RKCIF_STREAM_MIPI_ID2].state == RKCIF_STATE_STREAMING)
6265 rkcif_start_luma(&dev->luma_vdev,
6266 dev->stream[RKCIF_STREAM_MIPI_ID0].cif_fmt_in);
6267 }
6268 }
6269 dev->reset_work_cancel = false;
6270 stream->cur_stream_mode |= mode;
6271 rkcif_monitor_reset_event(dev);
6272 goto out;
6273
6274 stop_stream:
6275 rkcif_stream_stop(stream);
6276 pipe_stream_off:
6277 dev->pipe.set_stream(&dev->pipe, false);
6278 runtime_put:
6279 pm_runtime_put_sync(dev->dev);
6280 destroy_buf:
6281 if (stream->next_buf)
6282 vb2_buffer_done(&stream->next_buf->vb.vb2_buf,
6283 VB2_BUF_STATE_QUEUED);
6284 if (stream->curr_buf)
6285 vb2_buffer_done(&stream->curr_buf->vb.vb2_buf,
6286 VB2_BUF_STATE_QUEUED);
6287 while (!list_empty(&stream->buf_head)) {
6288 struct rkcif_buffer *buf;
6289
6290 buf = list_first_entry(&stream->buf_head,
6291 struct rkcif_buffer, queue);
6292 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_QUEUED);
6293 list_del(&buf->queue);
6294 }
6295
6296 out:
6297 mutex_unlock(&dev->stream_lock);
6298 return ret;
6299 }
6300
rkcif_start_streaming(struct vb2_queue * queue,unsigned int count)6301 static int rkcif_start_streaming(struct vb2_queue *queue, unsigned int count)
6302 {
6303 struct rkcif_stream *stream = queue->drv_priv;
6304 int ret = 0;
6305
6306 ret = rkcif_do_start_stream(stream, RKCIF_STREAM_MODE_CAPTURE);
6307 return ret;
6308 }
6309
6310 static struct vb2_ops rkcif_vb2_ops = {
6311 .queue_setup = rkcif_queue_setup,
6312 .buf_queue = rkcif_buf_queue,
6313 .wait_prepare = vb2_ops_wait_prepare,
6314 .wait_finish = vb2_ops_wait_finish,
6315 .stop_streaming = rkcif_stop_streaming,
6316 .start_streaming = rkcif_start_streaming,
6317 };
6318
rkcif_init_vb2_queue(struct vb2_queue * q,struct rkcif_stream * stream,enum v4l2_buf_type buf_type)6319 static int rkcif_init_vb2_queue(struct vb2_queue *q,
6320 struct rkcif_stream *stream,
6321 enum v4l2_buf_type buf_type)
6322 {
6323 struct rkcif_hw *hw_dev = stream->cifdev->hw_dev;
6324
6325 q->type = buf_type;
6326 q->io_modes = VB2_MMAP | VB2_DMABUF;
6327 q->drv_priv = stream;
6328 q->ops = &rkcif_vb2_ops;
6329 q->mem_ops = hw_dev->mem_ops;
6330 q->buf_struct_size = sizeof(struct rkcif_buffer);
6331 if (stream->cifdev->is_use_dummybuf)
6332 q->min_buffers_needed = 1;
6333 else
6334 q->min_buffers_needed = CIF_REQ_BUFS_MIN;
6335 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
6336 q->lock = &stream->vnode.vlock;
6337 q->dev = hw_dev->dev;
6338 q->allow_cache_hints = 1;
6339 q->bidirectional = 1;
6340 q->gfp_flags = GFP_DMA32;
6341 if (hw_dev->is_dma_contig)
6342 q->dma_attrs = DMA_ATTR_FORCE_CONTIGUOUS;
6343 return vb2_queue_init(q);
6344 }
6345
rkcif_set_fmt(struct rkcif_stream * stream,struct v4l2_pix_format_mplane * pixm,bool try)6346 int rkcif_set_fmt(struct rkcif_stream *stream,
6347 struct v4l2_pix_format_mplane *pixm,
6348 bool try)
6349 {
6350 struct rkcif_device *dev = stream->cifdev;
6351 struct sditf_priv *priv = dev->sditf[0];
6352 const struct cif_output_fmt *fmt;
6353 const struct cif_input_fmt *cif_fmt_in = NULL;
6354 struct v4l2_rect input_rect;
6355 unsigned int imagesize = 0, ex_imagesize = 0, planes;
6356 u32 xsubs = 1, ysubs = 1, i;
6357 struct rkmodule_hdr_cfg hdr_cfg;
6358 struct rkcif_extend_info *extend_line = &stream->extend_line;
6359 struct csi_channel_info *channel_info = &dev->channels[stream->id];
6360 int ret;
6361
6362 for (i = 0; i < RKCIF_MAX_PLANE; i++)
6363 memset(&pixm->plane_fmt[i], 0, sizeof(struct v4l2_plane_pix_format));
6364
6365 fmt = rkcif_find_output_fmt(stream, pixm->pixelformat);
6366 if (!fmt)
6367 fmt = &out_fmts[0];
6368
6369 input_rect.width = RKCIF_DEFAULT_WIDTH;
6370 input_rect.height = RKCIF_DEFAULT_HEIGHT;
6371
6372 if (dev->terminal_sensor.sd) {
6373 cif_fmt_in = rkcif_get_input_fmt(dev,
6374 &input_rect, stream->id,
6375 channel_info);
6376 stream->cif_fmt_in = cif_fmt_in;
6377 } else {
6378 v4l2_err(&stream->cifdev->v4l2_dev,
6379 "terminal subdev does not exist\n");
6380 return -EINVAL;
6381 }
6382
6383 ret = rkcif_output_fmt_check(stream, fmt);
6384 if (ret)
6385 return -EINVAL;
6386
6387 if (dev->terminal_sensor.sd) {
6388 ret = v4l2_subdev_call(dev->terminal_sensor.sd,
6389 core, ioctl,
6390 RKMODULE_GET_HDR_CFG,
6391 &hdr_cfg);
6392 if (!ret)
6393 dev->hdr = hdr_cfg;
6394 else
6395 dev->hdr.hdr_mode = NO_HDR;
6396
6397 dev->terminal_sensor.raw_rect = input_rect;
6398 }
6399
6400 /* CIF has not scale function,
6401 * the size should not be larger than input
6402 */
6403 pixm->width = clamp_t(u32, pixm->width,
6404 CIF_MIN_WIDTH, input_rect.width);
6405 pixm->height = clamp_t(u32, pixm->height,
6406 CIF_MIN_HEIGHT, input_rect.height);
6407 pixm->num_planes = fmt->mplanes;
6408 pixm->field = V4L2_FIELD_NONE;
6409 pixm->quantization = V4L2_QUANTIZATION_DEFAULT;
6410
6411 rkcif_sync_crop_info(stream);
6412 /* calculate plane size and image size */
6413 fcc_xysubs(fmt->fourcc, &xsubs, &ysubs);
6414
6415 planes = fmt->cplanes ? fmt->cplanes : fmt->mplanes;
6416
6417 if (cif_fmt_in &&
6418 (cif_fmt_in->mbus_code == MEDIA_BUS_FMT_SPD_2X8 ||
6419 cif_fmt_in->mbus_code == MEDIA_BUS_FMT_EBD_1X8))
6420 stream->crop_enable = false;
6421
6422 for (i = 0; i < planes; i++) {
6423 struct v4l2_plane_pix_format *plane_fmt;
6424 int width, height, bpl, size, bpp, ex_size;
6425
6426 if (i == 0) {
6427 if (stream->crop_enable) {
6428 width = stream->crop[CROP_SRC_ACT].width;
6429 height = stream->crop[CROP_SRC_ACT].height;
6430 } else {
6431 width = pixm->width;
6432 height = pixm->height;
6433 }
6434 } else {
6435 if (stream->crop_enable) {
6436 width = stream->crop[CROP_SRC_ACT].width / xsubs;
6437 height = stream->crop[CROP_SRC_ACT].height / ysubs;
6438 } else {
6439 width = pixm->width / xsubs;
6440 height = pixm->height / ysubs;
6441 }
6442 }
6443
6444 if (priv && priv->is_combine_mode && dev->sditf_cnt <= RKCIF_MAX_SDITF)
6445 height *= dev->sditf_cnt;
6446
6447 extend_line->pixm.height = height + RKMODULE_EXTEND_LINE;
6448
6449 /* compact mode need bytesperline 4bytes align,
6450 * align 8 to bring into correspondence with virtual width.
6451 * to optimize reading and writing of ddr, aliged with 256.
6452 */
6453 if (fmt->fmt_type == CIF_FMT_TYPE_RAW &&
6454 cif_fmt_in &&
6455 (cif_fmt_in->mbus_code == MEDIA_BUS_FMT_EBD_1X8 ||
6456 cif_fmt_in->mbus_code == MEDIA_BUS_FMT_SPD_2X8)) {
6457 stream->is_compact = false;
6458 }
6459
6460 if (fmt->fmt_type == CIF_FMT_TYPE_RAW && stream->is_compact &&
6461 (dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_DPHY ||
6462 dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_CPHY ||
6463 dev->active_sensor->mbus.type == V4L2_MBUS_CCP2) &&
6464 fmt->csi_fmt_val != CSI_WRDDR_TYPE_RGB888 &&
6465 fmt->csi_fmt_val != CSI_WRDDR_TYPE_RGB565) {
6466 bpl = ALIGN(width * fmt->raw_bpp / 8, 256);
6467 } else {
6468 if (fmt->fmt_type == CIF_FMT_TYPE_RAW && stream->is_compact &&
6469 fmt->csi_fmt_val != CSI_WRDDR_TYPE_RGB888 &&
6470 fmt->csi_fmt_val != CSI_WRDDR_TYPE_RGB565 &&
6471 dev->chip_id >= CHIP_RK3588_CIF) {
6472 bpl = ALIGN(width * fmt->raw_bpp / 8, 256);
6473 } else {
6474 bpp = rkcif_align_bits_per_pixel(stream, fmt, i);
6475 bpl = width * bpp / CIF_YUV_STORED_BIT_WIDTH;
6476 }
6477 }
6478 size = bpl * height;
6479 imagesize += size;
6480 ex_size = bpl * extend_line->pixm.height;
6481 ex_imagesize += ex_size;
6482
6483 if (fmt->mplanes > i) {
6484 /* Set bpl and size for each mplane */
6485 plane_fmt = pixm->plane_fmt + i;
6486 plane_fmt->bytesperline = bpl;
6487 plane_fmt->sizeimage = size;
6488
6489 plane_fmt = extend_line->pixm.plane_fmt + i;
6490 plane_fmt->bytesperline = bpl;
6491 plane_fmt->sizeimage = ex_size;
6492 }
6493 v4l2_dbg(1, rkcif_debug, &stream->cifdev->v4l2_dev,
6494 "C-Plane %i size: %d, Total imagesize: %d\n",
6495 i, size, imagesize);
6496 }
6497
6498 /* convert to non-MPLANE format.
6499 * It's important since we want to unify non-MPLANE
6500 * and MPLANE.
6501 */
6502 if (fmt->mplanes == 1) {
6503 pixm->plane_fmt[0].sizeimage = imagesize;
6504 extend_line->pixm.plane_fmt[0].sizeimage = ex_imagesize;
6505 }
6506
6507 if (!try) {
6508 stream->cif_fmt_out = fmt;
6509 stream->pixm = *pixm;
6510
6511 v4l2_dbg(1, rkcif_debug, &stream->cifdev->v4l2_dev,
6512 "%s: req(%d, %d) out(%d, %d)\n", __func__,
6513 pixm->width, pixm->height,
6514 stream->pixm.width, stream->pixm.height);
6515 }
6516 return 0;
6517 }
6518
rkcif_stream_init(struct rkcif_device * dev,u32 id)6519 void rkcif_stream_init(struct rkcif_device *dev, u32 id)
6520 {
6521 struct rkcif_stream *stream = &dev->stream[id];
6522 struct v4l2_pix_format_mplane pixm;
6523 int i;
6524
6525 memset(stream, 0, sizeof(*stream));
6526 memset(&pixm, 0, sizeof(pixm));
6527 stream->id = id;
6528 stream->cifdev = dev;
6529
6530 INIT_LIST_HEAD(&stream->buf_head);
6531 INIT_LIST_HEAD(&stream->rx_buf_head);
6532 INIT_LIST_HEAD(&stream->rx_buf_head_vicap);
6533 INIT_LIST_HEAD(&stream->rockit_buf_head);
6534 spin_lock_init(&stream->vbq_lock);
6535 spin_lock_init(&stream->fps_lock);
6536 stream->state = RKCIF_STATE_READY;
6537 init_waitqueue_head(&stream->wq_stopped);
6538
6539 /* Set default format */
6540 pixm.pixelformat = V4L2_PIX_FMT_NV12;
6541 pixm.width = RKCIF_DEFAULT_WIDTH;
6542 pixm.height = RKCIF_DEFAULT_HEIGHT;
6543 rkcif_set_fmt(stream, &pixm, false);
6544
6545 for (i = 0; i < CROP_SRC_MAX; i++) {
6546 stream->crop[i].left = 0;
6547 stream->crop[i].top = 0;
6548 stream->crop[i].width = RKCIF_DEFAULT_WIDTH;
6549 stream->crop[i].height = RKCIF_DEFAULT_HEIGHT;
6550 }
6551
6552 stream->crop_enable = false;
6553 stream->crop_dyn_en = false;
6554 stream->crop_mask = 0x0;
6555
6556 if (dev->inf_id == RKCIF_DVP) {
6557 if (dev->chip_id <= CHIP_RK3568_CIF)
6558 stream->is_compact = false;
6559 else
6560 stream->is_compact = true;
6561 } else {
6562 if (dev->chip_id >= CHIP_RV1126_CIF)
6563 stream->is_compact = true;
6564 else
6565 stream->is_compact = false;
6566 }
6567
6568 stream->is_high_align = false;
6569 stream->is_finish_stop_dma = false;
6570
6571 if (dev->chip_id == CHIP_RV1126_CIF ||
6572 dev->chip_id == CHIP_RV1126_CIF_LITE)
6573 stream->extend_line.is_extended = true;
6574 else
6575 stream->extend_line.is_extended = false;
6576
6577 stream->is_dvp_yuv_addr_init = false;
6578 stream->is_fs_fe_not_paired = false;
6579 stream->fs_cnt_in_single_frame = 0;
6580 if (dev->wait_line) {
6581 dev->wait_line_cache = dev->wait_line;
6582 dev->wait_line_bak = dev->wait_line;
6583 stream->is_line_wake_up = true;
6584 } else {
6585 stream->is_line_wake_up = false;
6586 dev->wait_line_cache = 0;
6587 dev->wait_line_bak = 0;
6588 }
6589 stream->cur_stream_mode = 0;
6590 stream->dma_en = 0;
6591 stream->to_en_dma = 0;
6592 stream->to_stop_dma = 0;
6593 stream->to_en_scale = false;
6594 stream->buf_owner = 0;
6595 stream->buf_replace_cnt = 0;
6596 stream->is_stop_capture = false;
6597 atomic_set(&stream->buf_cnt, 0);
6598 }
6599
rkcif_fh_open(struct file * filp)6600 static int rkcif_fh_open(struct file *filp)
6601 {
6602 struct video_device *vdev = video_devdata(filp);
6603 struct rkcif_vdev_node *vnode = vdev_to_node(vdev);
6604 struct rkcif_stream *stream = to_rkcif_stream(vnode);
6605 struct rkcif_device *cifdev = stream->cifdev;
6606 int ret;
6607 int i = 0;
6608
6609 ret = rkcif_attach_hw(cifdev);
6610 if (ret)
6611 return ret;
6612
6613 /* Make sure active sensor is valid before .set_fmt() */
6614 ret = rkcif_update_sensor_info(stream);
6615 if (ret < 0) {
6616 v4l2_err(vdev,
6617 "update sensor info failed %d\n",
6618 ret);
6619
6620 return ret;
6621 }
6622
6623 ret = pm_runtime_resume_and_get(cifdev->dev);
6624 if (ret < 0) {
6625 v4l2_err(vdev, "Failed to get runtime pm, %d\n",
6626 ret);
6627 return ret;
6628 }
6629
6630 ret = v4l2_fh_open(filp);
6631 if (!ret) {
6632 mutex_lock(&cifdev->stream_lock);
6633 ret = v4l2_pipeline_pm_get(&vnode->vdev.entity);
6634 v4l2_info(vdev, "open video, entity use_countt %d\n",
6635 vnode->vdev.entity.use_count);
6636 mutex_unlock(&cifdev->stream_lock);
6637 if (ret < 0)
6638 vb2_fop_release(filp);
6639 }
6640 if (cifdev->sditf_cnt > 1) {
6641 for (i = 0; i < cifdev->sditf_cnt; i++) {
6642 if (cifdev->sditf[i]->sensor_sd)
6643 ret |= v4l2_subdev_call(cifdev->sditf[i]->sensor_sd,
6644 core,
6645 s_power,
6646 1);
6647 }
6648 if (ret < 0)
6649 v4l2_err(vdev, "set sensor power on fail, ret %d\n",
6650 ret);
6651 }
6652 return ret;
6653 }
6654
rkcif_fh_release(struct file * filp)6655 static int rkcif_fh_release(struct file *filp)
6656 {
6657 struct video_device *vdev = video_devdata(filp);
6658 struct rkcif_vdev_node *vnode = vdev_to_node(vdev);
6659 struct rkcif_stream *stream = to_rkcif_stream(vnode);
6660 struct rkcif_device *cifdev = stream->cifdev;
6661 int ret = 0;
6662 int i = 0;
6663
6664 ret = vb2_fop_release(filp);
6665 if (!ret) {
6666 mutex_lock(&cifdev->stream_lock);
6667 v4l2_pipeline_pm_put(&vnode->vdev.entity);
6668 v4l2_info(vdev, "close video, entity use_count %d\n",
6669 vnode->vdev.entity.use_count);
6670 mutex_unlock(&cifdev->stream_lock);
6671 }
6672
6673 pm_runtime_put_sync(cifdev->dev);
6674 if (cifdev->sditf_cnt > 1) {
6675 for (i = 0; i < cifdev->sditf_cnt; i++) {
6676 if (cifdev->sditf[i]->sensor_sd)
6677 ret |= v4l2_subdev_call(cifdev->sditf[i]->sensor_sd,
6678 core,
6679 s_power,
6680 0);
6681 }
6682 if (ret < 0)
6683 v4l2_err(vdev, "set sensor power on fail, ret %d\n",
6684 ret);
6685 }
6686 return ret;
6687 }
6688
6689 static const struct v4l2_file_operations rkcif_fops = {
6690 .open = rkcif_fh_open,
6691 .release = rkcif_fh_release,
6692 .unlocked_ioctl = video_ioctl2,
6693 .poll = vb2_fop_poll,
6694 .mmap = vb2_fop_mmap,
6695 #ifdef CONFIG_COMPAT
6696 .compat_ioctl32 = video_ioctl2,
6697 #endif
6698 };
6699
rkcif_enum_input(struct file * file,void * priv,struct v4l2_input * input)6700 static int rkcif_enum_input(struct file *file, void *priv,
6701 struct v4l2_input *input)
6702 {
6703 if (input->index > 0)
6704 return -EINVAL;
6705
6706 input->type = V4L2_INPUT_TYPE_CAMERA;
6707 strlcpy(input->name, "Camera", sizeof(input->name));
6708
6709 return 0;
6710 }
6711
rkcif_try_fmt_vid_cap_mplane(struct file * file,void * fh,struct v4l2_format * f)6712 static int rkcif_try_fmt_vid_cap_mplane(struct file *file, void *fh,
6713 struct v4l2_format *f)
6714 {
6715 struct rkcif_stream *stream = video_drvdata(file);
6716 int ret = 0;
6717
6718 ret = rkcif_set_fmt(stream, &f->fmt.pix_mp, true);
6719
6720 return ret;
6721 }
6722
rkcif_enum_framesizes(struct file * file,void * prov,struct v4l2_frmsizeenum * fsize)6723 static int rkcif_enum_framesizes(struct file *file, void *prov,
6724 struct v4l2_frmsizeenum *fsize)
6725 {
6726 struct v4l2_frmsize_discrete *d = &fsize->discrete;
6727 struct v4l2_frmsize_stepwise *s = &fsize->stepwise;
6728 struct rkcif_stream *stream = video_drvdata(file);
6729 struct rkcif_device *dev = stream->cifdev;
6730 struct v4l2_rect input_rect;
6731 struct csi_channel_info csi_info;
6732
6733 if (fsize->index != 0)
6734 return -EINVAL;
6735
6736 if (!rkcif_find_output_fmt(stream, fsize->pixel_format))
6737 return -EINVAL;
6738
6739 input_rect.width = RKCIF_DEFAULT_WIDTH;
6740 input_rect.height = RKCIF_DEFAULT_HEIGHT;
6741
6742 if (dev->terminal_sensor.sd)
6743 rkcif_get_input_fmt(dev,
6744 &input_rect, stream->id,
6745 &csi_info);
6746
6747 if (dev->hw_dev->adapt_to_usbcamerahal) {
6748 fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE;
6749 d->width = input_rect.width;
6750 d->height = input_rect.height;
6751 } else {
6752 fsize->type = V4L2_FRMSIZE_TYPE_STEPWISE;
6753 s->min_width = CIF_MIN_WIDTH;
6754 s->min_height = CIF_MIN_HEIGHT;
6755 s->max_width = input_rect.width;
6756 s->max_height = input_rect.height;
6757 s->step_width = OUTPUT_STEP_WISE;
6758 s->step_height = OUTPUT_STEP_WISE;
6759 }
6760
6761 return 0;
6762 }
6763
rkcif_enum_frameintervals(struct file * file,void * fh,struct v4l2_frmivalenum * fival)6764 static int rkcif_enum_frameintervals(struct file *file, void *fh,
6765 struct v4l2_frmivalenum *fival)
6766 {
6767 struct rkcif_stream *stream = video_drvdata(file);
6768 struct rkcif_device *dev = stream->cifdev;
6769 struct rkcif_sensor_info *sensor = dev->active_sensor;
6770 struct v4l2_subdev_frame_interval fi;
6771 int ret;
6772
6773 if (fival->index != 0)
6774 return -EINVAL;
6775
6776 if (!sensor || !sensor->sd) {
6777 /* TODO: active_sensor is NULL if using DMARX path */
6778 v4l2_err(&dev->v4l2_dev, "%s Not active sensor\n", __func__);
6779 return -ENODEV;
6780 }
6781
6782 ret = v4l2_subdev_call(sensor->sd, video, g_frame_interval, &fi);
6783 if (ret && ret != -ENOIOCTLCMD) {
6784 return ret;
6785 } else if (ret == -ENOIOCTLCMD) {
6786 /* Set a default value for sensors not implements ioctl */
6787 fi.interval.numerator = 1;
6788 fi.interval.denominator = 30;
6789 }
6790
6791 if (dev->hw_dev->adapt_to_usbcamerahal) {
6792 fival->type = V4L2_FRMIVAL_TYPE_DISCRETE;
6793 fival->discrete.numerator = fi.interval.numerator;
6794 fival->discrete.denominator = fi.interval.denominator;
6795 } else {
6796 fival->type = V4L2_FRMIVAL_TYPE_CONTINUOUS;
6797 fival->stepwise.step.numerator = 1;
6798 fival->stepwise.step.denominator = 1;
6799 fival->stepwise.max.numerator = 1;
6800 fival->stepwise.max.denominator = 1;
6801 fival->stepwise.min.numerator = fi.interval.numerator;
6802 fival->stepwise.min.denominator = fi.interval.denominator;
6803 }
6804
6805 return 0;
6806 }
6807
rkcif_enum_fmt_vid_cap_mplane(struct file * file,void * priv,struct v4l2_fmtdesc * f)6808 static int rkcif_enum_fmt_vid_cap_mplane(struct file *file, void *priv,
6809 struct v4l2_fmtdesc *f)
6810 {
6811 const struct cif_output_fmt *fmt = NULL;
6812 struct rkcif_stream *stream = video_drvdata(file);
6813 struct rkcif_device *dev = stream->cifdev;
6814 const struct cif_input_fmt *cif_fmt_in = NULL;
6815 struct v4l2_rect input_rect;
6816 int i = 0;
6817 int ret = 0;
6818 int fource_idx = 0;
6819
6820 if (f->index >= ARRAY_SIZE(out_fmts))
6821 return -EINVAL;
6822
6823 if (dev->terminal_sensor.sd) {
6824 cif_fmt_in = rkcif_get_input_fmt(dev,
6825 &input_rect, stream->id,
6826 &dev->channels[stream->id]);
6827 stream->cif_fmt_in = cif_fmt_in;
6828 } else {
6829 v4l2_err(&stream->cifdev->v4l2_dev,
6830 "terminal subdev does not exist\n");
6831 return -EINVAL;
6832 }
6833
6834 if (f->index != 0)
6835 fource_idx = stream->new_fource_idx;
6836
6837 for (i = fource_idx; i < ARRAY_SIZE(out_fmts); i++) {
6838 fmt = &out_fmts[i];
6839 ret = rkcif_output_fmt_check(stream, fmt);
6840 if (!ret) {
6841 f->pixelformat = fmt->fourcc;
6842 stream->new_fource_idx = i + 1;
6843 break;
6844 }
6845 }
6846 if (i == ARRAY_SIZE(out_fmts))
6847 return -EINVAL;
6848
6849 switch (f->pixelformat) {
6850 case V4l2_PIX_FMT_EBD8:
6851 strscpy(f->description,
6852 "Embedded data 8-bit",
6853 sizeof(f->description));
6854 break;
6855 case V4l2_PIX_FMT_SPD16:
6856 strscpy(f->description,
6857 "Shield pix data 16-bit",
6858 sizeof(f->description));
6859 break;
6860 default:
6861 break;
6862 }
6863 return 0;
6864 }
6865
rkcif_s_fmt_vid_cap_mplane(struct file * file,void * priv,struct v4l2_format * f)6866 static int rkcif_s_fmt_vid_cap_mplane(struct file *file,
6867 void *priv, struct v4l2_format *f)
6868 {
6869 struct rkcif_stream *stream = video_drvdata(file);
6870 struct rkcif_device *dev = stream->cifdev;
6871 int ret = 0;
6872
6873 if (vb2_is_busy(&stream->vnode.buf_queue)) {
6874 v4l2_err(&dev->v4l2_dev, "%s queue busy\n", __func__);
6875 return -EBUSY;
6876 }
6877
6878 ret = rkcif_set_fmt(stream, &f->fmt.pix_mp, false);
6879
6880 return ret;
6881 }
6882
rkcif_g_fmt_vid_cap_mplane(struct file * file,void * fh,struct v4l2_format * f)6883 static int rkcif_g_fmt_vid_cap_mplane(struct file *file, void *fh,
6884 struct v4l2_format *f)
6885 {
6886 struct rkcif_stream *stream = video_drvdata(file);
6887
6888 f->fmt.pix_mp = stream->pixm;
6889
6890 return 0;
6891 }
6892
rkcif_querycap(struct file * file,void * priv,struct v4l2_capability * cap)6893 static int rkcif_querycap(struct file *file, void *priv,
6894 struct v4l2_capability *cap)
6895 {
6896 struct rkcif_stream *stream = video_drvdata(file);
6897 struct device *dev = stream->cifdev->dev;
6898
6899 strlcpy(cap->driver, dev->driver->name, sizeof(cap->driver));
6900 strlcpy(cap->card, dev->driver->name, sizeof(cap->card));
6901 snprintf(cap->bus_info, sizeof(cap->bus_info),
6902 "platform:%s", dev_name(dev));
6903
6904 return 0;
6905 }
6906
rkcif_cropcap(struct file * file,void * fh,struct v4l2_cropcap * cap)6907 static __maybe_unused int rkcif_cropcap(struct file *file, void *fh,
6908 struct v4l2_cropcap *cap)
6909 {
6910 struct rkcif_stream *stream = video_drvdata(file);
6911 struct rkcif_device *dev = stream->cifdev;
6912 struct v4l2_rect *raw_rect = &dev->terminal_sensor.raw_rect;
6913 int ret = 0;
6914
6915 if (stream->crop_mask & CROP_SRC_SENSOR) {
6916 cap->bounds.left = stream->crop[CROP_SRC_SENSOR].left;
6917 cap->bounds.top = stream->crop[CROP_SRC_SENSOR].top;
6918 cap->bounds.width = stream->crop[CROP_SRC_SENSOR].width;
6919 cap->bounds.height = stream->crop[CROP_SRC_SENSOR].height;
6920 } else {
6921 cap->bounds.left = raw_rect->left;
6922 cap->bounds.top = raw_rect->top;
6923 cap->bounds.width = raw_rect->width;
6924 cap->bounds.height = raw_rect->height;
6925 }
6926
6927 cap->defrect = cap->bounds;
6928 cap->pixelaspect.numerator = 1;
6929 cap->pixelaspect.denominator = 1;
6930
6931 return ret;
6932 }
6933
rkcif_s_selection(struct file * file,void * fh,struct v4l2_selection * s)6934 static int rkcif_s_selection(struct file *file, void *fh,
6935 struct v4l2_selection *s)
6936 {
6937 struct rkcif_stream *stream = video_drvdata(file);
6938 struct rkcif_device *dev = stream->cifdev;
6939 struct v4l2_subdev *sensor_sd;
6940 struct v4l2_subdev_selection sd_sel;
6941 const struct v4l2_rect *rect = &s->r;
6942 struct v4l2_rect sensor_crop;
6943 struct v4l2_rect *raw_rect = &dev->terminal_sensor.raw_rect;
6944 u16 pad = 0;
6945 int ret = 0;
6946
6947 if (!s) {
6948 v4l2_dbg(1, rkcif_debug, &dev->v4l2_dev, "sel is null\n");
6949 goto err;
6950 }
6951
6952 if (s->target == V4L2_SEL_TGT_CROP_BOUNDS) {
6953 sensor_sd = get_remote_sensor(stream, &pad);
6954
6955 sd_sel.r = s->r;
6956 sd_sel.pad = pad;
6957 sd_sel.target = s->target;
6958 sd_sel.which = V4L2_SUBDEV_FORMAT_ACTIVE;
6959
6960 ret = v4l2_subdev_call(sensor_sd, pad, set_selection, NULL, &sd_sel);
6961 if (!ret) {
6962 s->r = sd_sel.r;
6963 v4l2_dbg(1, rkcif_debug, &dev->v4l2_dev, "%s: pad:%d, which:%d, target:%d\n",
6964 __func__, pad, sd_sel.which, sd_sel.target);
6965 }
6966 } else if (s->target == V4L2_SEL_TGT_CROP) {
6967 ret = rkcif_sanity_check_fmt(stream, rect);
6968 if (ret) {
6969 v4l2_err(&dev->v4l2_dev, "set crop failed\n");
6970 return ret;
6971 }
6972
6973 if (stream->crop_mask & CROP_SRC_SENSOR) {
6974 sensor_crop = stream->crop[CROP_SRC_SENSOR];
6975 if (rect->left + rect->width > sensor_crop.width ||
6976 rect->top + rect->height > sensor_crop.height) {
6977 v4l2_err(&dev->v4l2_dev,
6978 "crop size is bigger than sensor input:left:%d, top:%d, width:%d, height:%d\n",
6979 sensor_crop.left, sensor_crop.top,
6980 sensor_crop.width, sensor_crop.height);
6981 return -EINVAL;
6982 }
6983 } else {
6984 if (rect->left + rect->width > raw_rect->width ||
6985 rect->top + rect->height > raw_rect->height) {
6986 v4l2_err(&dev->v4l2_dev,
6987 "crop size is bigger than sensor raw input:left:%d, top:%d, width:%d, height:%d\n",
6988 raw_rect->left, raw_rect->top,
6989 raw_rect->width, raw_rect->height);
6990 return -EINVAL;
6991 }
6992 }
6993
6994 stream->crop[CROP_SRC_USR] = *rect;
6995 stream->crop_enable = true;
6996 stream->crop_mask |= CROP_SRC_USR_MASK;
6997 stream->crop[CROP_SRC_ACT] = stream->crop[CROP_SRC_USR];
6998 if (stream->crop_mask & CROP_SRC_SENSOR) {
6999 sensor_crop = stream->crop[CROP_SRC_SENSOR];
7000 stream->crop[CROP_SRC_ACT].left = sensor_crop.left + stream->crop[CROP_SRC_USR].left;
7001 stream->crop[CROP_SRC_ACT].top = sensor_crop.top + stream->crop[CROP_SRC_USR].top;
7002 }
7003
7004 if (stream->state == RKCIF_STATE_STREAMING) {
7005 stream->crop_dyn_en = true;
7006
7007 v4l2_info(&dev->v4l2_dev, "enable dynamic crop, S_SELECTION(%ux%u@%u:%u) target: %d\n",
7008 rect->width, rect->height, rect->left, rect->top, s->target);
7009 } else {
7010 v4l2_info(&dev->v4l2_dev, "static crop, S_SELECTION(%ux%u@%u:%u) target: %d\n",
7011 rect->width, rect->height, rect->left, rect->top, s->target);
7012 }
7013 } else {
7014 goto err;
7015 }
7016
7017 return ret;
7018
7019 err:
7020 return -EINVAL;
7021 }
7022
rkcif_g_selection(struct file * file,void * fh,struct v4l2_selection * s)7023 static int rkcif_g_selection(struct file *file, void *fh,
7024 struct v4l2_selection *s)
7025 {
7026 struct rkcif_stream *stream = video_drvdata(file);
7027 struct rkcif_device *dev = stream->cifdev;
7028 struct v4l2_subdev *sensor_sd;
7029 struct v4l2_subdev_selection sd_sel;
7030 u16 pad = 0;
7031 int ret = 0;
7032
7033 if (!s) {
7034 v4l2_dbg(1, rkcif_debug, &dev->v4l2_dev, "sel is null\n");
7035 goto err;
7036 }
7037
7038 if (s->target == V4L2_SEL_TGT_CROP_BOUNDS) {
7039 sensor_sd = get_remote_sensor(stream, &pad);
7040
7041 sd_sel.pad = pad;
7042 sd_sel.target = s->target;
7043 sd_sel.which = V4L2_SUBDEV_FORMAT_ACTIVE;
7044
7045 v4l2_dbg(1, rkcif_debug, &dev->v4l2_dev, "%s(line:%d): sd:%s pad:%d, which:%d, target:%d\n",
7046 __func__, __LINE__, sensor_sd->name, pad, sd_sel.which, sd_sel.target);
7047
7048 ret = v4l2_subdev_call(sensor_sd, pad, get_selection, NULL, &sd_sel);
7049 if (!ret) {
7050 s->r = sd_sel.r;
7051 } else {
7052 s->r.left = 0;
7053 s->r.top = 0;
7054 s->r.width = stream->pixm.width;
7055 s->r.height = stream->pixm.height;
7056 }
7057 } else if (s->target == V4L2_SEL_TGT_CROP) {
7058 if (stream->crop_mask & (CROP_SRC_USR_MASK | CROP_SRC_SENSOR_MASK)) {
7059 s->r = stream->crop[CROP_SRC_ACT];
7060 } else {
7061 s->r.left = 0;
7062 s->r.top = 0;
7063 s->r.width = stream->pixm.width;
7064 s->r.height = stream->pixm.height;
7065 }
7066 } else {
7067 goto err;
7068 }
7069
7070 return ret;
7071 err:
7072 return -EINVAL;
7073 }
7074
rkcif_get_max_common_div(int a,int b)7075 static int rkcif_get_max_common_div(int a, int b)
7076 {
7077 int remainder = a % b;
7078
7079 while (remainder != 0) {
7080 a = b;
7081 b = remainder;
7082 remainder = a % b;
7083 }
7084 return b;
7085 }
7086
rkcif_set_fps(struct rkcif_stream * stream,struct rkcif_fps * fps)7087 void rkcif_set_fps(struct rkcif_stream *stream, struct rkcif_fps *fps)
7088 {
7089 struct rkcif_sensor_info *sensor = &stream->cifdev->terminal_sensor;
7090 struct rkcif_device *cif_dev = stream->cifdev;
7091 struct rkcif_stream *tmp_stream = NULL;
7092 u32 numerator, denominator;
7093 u32 def_fps = 0;
7094 u32 cur_fps = 0;
7095 int cap_m, skip_n;
7096 int i = 0;
7097 int max_common_div;
7098 bool skip_en = false;
7099 s32 vblank_def = 0;
7100 s32 vblank_curr = 0;
7101 int ret = 0;
7102
7103 if (!stream->cifdev->terminal_sensor.sd) {
7104 ret = rkcif_update_sensor_info(stream);
7105 if (ret) {
7106 v4l2_err(&stream->cifdev->v4l2_dev,
7107 "%s update sensor info fail\n",
7108 __func__);
7109 return;
7110 }
7111
7112 }
7113 if (!stream->cifdev->terminal_sensor.sd)
7114 return;
7115 numerator = sensor->fi.interval.numerator;
7116 denominator = sensor->fi.interval.denominator;
7117 def_fps = denominator / numerator;
7118
7119 vblank_def = rkcif_get_sensor_vblank_def(cif_dev);
7120 vblank_curr = rkcif_get_sensor_vblank(cif_dev);
7121 if (vblank_def)
7122 cur_fps = def_fps * (u32)(vblank_def + sensor->raw_rect.height) /
7123 (u32)(vblank_curr + sensor->raw_rect.height);
7124 else
7125 cur_fps = def_fps;
7126
7127 if (fps->fps == 0 || fps->fps > cur_fps) {
7128 v4l2_err(&stream->cifdev->v4l2_dev,
7129 "set fps %d fps failed, current fps %d fps\n",
7130 fps->fps, cur_fps);
7131 return;
7132 }
7133 cap_m = fps->fps;
7134 skip_n = cur_fps - fps->fps;
7135 max_common_div = rkcif_get_max_common_div(cap_m, skip_n);
7136 cap_m /= max_common_div;
7137 skip_n /= max_common_div;
7138 if (cap_m > 64) {
7139 skip_n = skip_n / (cap_m / 64);
7140 if (skip_n == 0)
7141 skip_n = 1;
7142 cap_m = 64;
7143 }
7144 if (skip_n > 7) {
7145 cap_m = cap_m / (skip_n / 7);
7146 if (cap_m == 0)
7147 cap_m = 1;
7148 skip_n = 7;
7149 }
7150
7151 if (fps->fps == cur_fps)
7152 skip_en = false;
7153 else
7154 skip_en = true;
7155
7156 if (fps->ch_num > 1 && fps->ch_num < 4) {
7157 for (i = 0; i < fps->ch_num; i++) {
7158 tmp_stream = &cif_dev->stream[i];
7159 if (skip_en) {
7160 tmp_stream->skip_info.skip_to_en = true;
7161 tmp_stream->skip_info.cap_m = cap_m;
7162 tmp_stream->skip_info.skip_n = skip_n;
7163 } else {
7164 tmp_stream->skip_info.skip_to_dis = true;
7165 }
7166 }
7167 } else {
7168 if (skip_en) {
7169 stream->skip_info.skip_to_en = true;
7170 stream->skip_info.cap_m = cap_m;
7171 stream->skip_info.skip_n = skip_n;
7172 } else {
7173 stream->skip_info.skip_to_dis = true;
7174 }
7175 }
7176 v4l2_dbg(1, rkcif_debug, &stream->cifdev->v4l2_dev,
7177 "skip_to_en %d, cap_m %d, skip_n %d\n",
7178 stream->skip_info.skip_to_en,
7179 cap_m,
7180 skip_n);
7181 }
7182
7183 static int rkcif_do_reset_work(struct rkcif_device *cif_dev,
7184 enum rkmodule_reset_src reset_src);
7185
rkcif_ioctl_default(struct file * file,void * fh,bool valid_prio,unsigned int cmd,void * arg)7186 static long rkcif_ioctl_default(struct file *file, void *fh,
7187 bool valid_prio, unsigned int cmd, void *arg)
7188 {
7189 struct rkcif_stream *stream = video_drvdata(file);
7190 struct rkcif_device *dev = stream->cifdev;
7191 const struct cif_input_fmt *in_fmt;
7192 struct v4l2_rect rect;
7193 struct csi_channel_info csi_info;
7194 struct rkcif_fps fps;
7195 int reset_src;
7196
7197 switch (cmd) {
7198 case RKCIF_CMD_GET_CSI_MEMORY_MODE:
7199 if (stream->is_compact) {
7200 *(int *)arg = CSI_LVDS_MEM_COMPACT;
7201 } else {
7202 if (stream->is_high_align)
7203 *(int *)arg = CSI_LVDS_MEM_WORD_HIGH_ALIGN;
7204 else
7205 *(int *)arg = CSI_LVDS_MEM_WORD_LOW_ALIGN;
7206 }
7207 break;
7208 case RKCIF_CMD_SET_CSI_MEMORY_MODE:
7209 if (dev->terminal_sensor.sd) {
7210 in_fmt = rkcif_get_input_fmt(dev,
7211 &rect, 0, &csi_info);
7212 if (in_fmt == NULL) {
7213 v4l2_err(&dev->v4l2_dev, "can't get sensor input format\n");
7214 return -EINVAL;
7215 }
7216 } else {
7217 v4l2_err(&dev->v4l2_dev, "can't get sensor device\n");
7218 return -EINVAL;
7219 }
7220 if (*(int *)arg == CSI_LVDS_MEM_COMPACT) {
7221 if (((dev->inf_id == RKCIF_DVP && dev->chip_id <= CHIP_RK3568_CIF) ||
7222 (dev->inf_id == RKCIF_MIPI_LVDS && dev->chip_id < CHIP_RV1126_CIF)) &&
7223 in_fmt->csi_fmt_val != CSI_WRDDR_TYPE_RAW8) {
7224 v4l2_err(&dev->v4l2_dev, "device not support compact\n");
7225 return -EINVAL;
7226 }
7227 stream->is_compact = true;
7228 stream->is_high_align = false;
7229 } else if (*(int *)arg == CSI_LVDS_MEM_WORD_HIGH_ALIGN) {
7230 stream->is_compact = false;
7231 stream->is_high_align = true;
7232 } else {
7233 stream->is_compact = false;
7234 stream->is_high_align = false;
7235 }
7236 break;
7237 case RKCIF_CMD_SET_FPS:
7238 fps = *(struct rkcif_fps *)arg;
7239 rkcif_set_fps(stream, &fps);
7240 break;
7241 case RKCIF_CMD_SET_RESET:
7242 reset_src = *(int *)arg;
7243 return rkcif_do_reset_work(dev, reset_src);
7244 default:
7245 return -EINVAL;
7246 }
7247
7248 return 0;
7249 }
7250
7251 static const struct v4l2_ioctl_ops rkcif_v4l2_ioctl_ops = {
7252 .vidioc_reqbufs = vb2_ioctl_reqbufs,
7253 .vidioc_querybuf = vb2_ioctl_querybuf,
7254 .vidioc_create_bufs = vb2_ioctl_create_bufs,
7255 .vidioc_qbuf = vb2_ioctl_qbuf,
7256 .vidioc_expbuf = vb2_ioctl_expbuf,
7257 .vidioc_dqbuf = vb2_ioctl_dqbuf,
7258 .vidioc_prepare_buf = vb2_ioctl_prepare_buf,
7259 .vidioc_streamon = vb2_ioctl_streamon,
7260 .vidioc_streamoff = vb2_ioctl_streamoff,
7261 .vidioc_enum_input = rkcif_enum_input,
7262 .vidioc_try_fmt_vid_cap_mplane = rkcif_try_fmt_vid_cap_mplane,
7263 .vidioc_enum_fmt_vid_cap = rkcif_enum_fmt_vid_cap_mplane,
7264 .vidioc_s_fmt_vid_cap_mplane = rkcif_s_fmt_vid_cap_mplane,
7265 .vidioc_g_fmt_vid_cap_mplane = rkcif_g_fmt_vid_cap_mplane,
7266 .vidioc_querycap = rkcif_querycap,
7267 .vidioc_s_selection = rkcif_s_selection,
7268 .vidioc_g_selection = rkcif_g_selection,
7269 .vidioc_enum_frameintervals = rkcif_enum_frameintervals,
7270 .vidioc_enum_framesizes = rkcif_enum_framesizes,
7271 .vidioc_default = rkcif_ioctl_default,
7272 };
7273
rkcif_vb_done_oneframe(struct rkcif_stream * stream,struct vb2_v4l2_buffer * vb_done)7274 void rkcif_vb_done_oneframe(struct rkcif_stream *stream,
7275 struct vb2_v4l2_buffer *vb_done)
7276 {
7277 const struct cif_output_fmt *fmt = stream->cif_fmt_out;
7278 u32 i;
7279
7280 /* Dequeue a filled buffer */
7281 for (i = 0; i < fmt->mplanes; i++) {
7282 vb2_set_plane_payload(&vb_done->vb2_buf, i,
7283 stream->pixm.plane_fmt[i].sizeimage);
7284 }
7285
7286 vb2_buffer_done(&vb_done->vb2_buf, VB2_BUF_STATE_DONE);
7287 v4l2_dbg(2, rkcif_debug, &stream->cifdev->v4l2_dev,
7288 "stream[%d] vb done, index: %d, sequence %d\n", stream->id,
7289 vb_done->vb2_buf.index, vb_done->sequence);
7290 atomic_dec(&stream->buf_cnt);
7291 }
7292
rkcif_tasklet_handle(unsigned long data)7293 static void rkcif_tasklet_handle(unsigned long data)
7294 {
7295 struct rkcif_stream *stream = (struct rkcif_stream *)data;
7296 struct rkcif_buffer *buf = NULL;
7297 unsigned long flags = 0;
7298 LIST_HEAD(local_list);
7299
7300 spin_lock_irqsave(&stream->vbq_lock, flags);
7301 list_replace_init(&stream->vb_done_list, &local_list);
7302 spin_unlock_irqrestore(&stream->vbq_lock, flags);
7303
7304 while (!list_empty(&local_list)) {
7305 buf = list_first_entry(&local_list,
7306 struct rkcif_buffer, queue);
7307 list_del(&buf->queue);
7308 rkcif_vb_done_oneframe(stream, &buf->vb);
7309 }
7310 }
7311
rkcif_vb_done_tasklet(struct rkcif_stream * stream,struct rkcif_buffer * buf)7312 void rkcif_vb_done_tasklet(struct rkcif_stream *stream, struct rkcif_buffer *buf)
7313 {
7314 unsigned long flags = 0;
7315
7316 if (!stream || !buf)
7317 return;
7318 spin_lock_irqsave(&stream->vbq_lock, flags);
7319 list_add_tail(&buf->queue, &stream->vb_done_list);
7320 spin_unlock_irqrestore(&stream->vbq_lock, flags);
7321 tasklet_schedule(&stream->vb_done_tasklet);
7322 }
7323
rkcif_unregister_stream_vdev(struct rkcif_stream * stream)7324 static void rkcif_unregister_stream_vdev(struct rkcif_stream *stream)
7325 {
7326 tasklet_kill(&stream->vb_done_tasklet);
7327 media_entity_cleanup(&stream->vnode.vdev.entity);
7328 video_unregister_device(&stream->vnode.vdev);
7329 }
7330
rkcif_register_stream_vdev(struct rkcif_stream * stream,bool is_multi_input)7331 static int rkcif_register_stream_vdev(struct rkcif_stream *stream,
7332 bool is_multi_input)
7333 {
7334 struct rkcif_device *dev = stream->cifdev;
7335 struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
7336 struct video_device *vdev = &stream->vnode.vdev;
7337 struct rkcif_vdev_node *node;
7338 int ret = 0;
7339 char *vdev_name;
7340
7341 if (dev->chip_id < CHIP_RV1126_CIF) {
7342 if (is_multi_input) {
7343 switch (stream->id) {
7344 case RKCIF_STREAM_MIPI_ID0:
7345 vdev_name = CIF_MIPI_ID0_VDEV_NAME;
7346 break;
7347 case RKCIF_STREAM_MIPI_ID1:
7348 vdev_name = CIF_MIPI_ID1_VDEV_NAME;
7349 break;
7350 case RKCIF_STREAM_MIPI_ID2:
7351 vdev_name = CIF_MIPI_ID2_VDEV_NAME;
7352 break;
7353 case RKCIF_STREAM_MIPI_ID3:
7354 vdev_name = CIF_MIPI_ID3_VDEV_NAME;
7355 break;
7356 case RKCIF_STREAM_DVP:
7357 vdev_name = CIF_DVP_VDEV_NAME;
7358 break;
7359 default:
7360 ret = -EINVAL;
7361 v4l2_err(v4l2_dev, "Invalid stream\n");
7362 goto unreg;
7363 }
7364 } else {
7365 vdev_name = CIF_VIDEODEVICE_NAME;
7366 }
7367 } else {
7368 if (dev->inf_id == RKCIF_MIPI_LVDS) {
7369 switch (stream->id) {
7370 case RKCIF_STREAM_MIPI_ID0:
7371 vdev_name = CIF_MIPI_ID0_VDEV_NAME;
7372 break;
7373 case RKCIF_STREAM_MIPI_ID1:
7374 vdev_name = CIF_MIPI_ID1_VDEV_NAME;
7375 break;
7376 case RKCIF_STREAM_MIPI_ID2:
7377 vdev_name = CIF_MIPI_ID2_VDEV_NAME;
7378 break;
7379 case RKCIF_STREAM_MIPI_ID3:
7380 vdev_name = CIF_MIPI_ID3_VDEV_NAME;
7381 break;
7382 default:
7383 ret = -EINVAL;
7384 v4l2_err(v4l2_dev, "Invalid stream\n");
7385 goto unreg;
7386 }
7387 } else {
7388 switch (stream->id) {
7389 case RKCIF_STREAM_MIPI_ID0:
7390 vdev_name = CIF_DVP_ID0_VDEV_NAME;
7391 break;
7392 case RKCIF_STREAM_MIPI_ID1:
7393 vdev_name = CIF_DVP_ID1_VDEV_NAME;
7394 break;
7395 case RKCIF_STREAM_MIPI_ID2:
7396 vdev_name = CIF_DVP_ID2_VDEV_NAME;
7397 break;
7398 case RKCIF_STREAM_MIPI_ID3:
7399 vdev_name = CIF_DVP_ID3_VDEV_NAME;
7400 break;
7401 default:
7402 ret = -EINVAL;
7403 v4l2_err(v4l2_dev, "Invalid stream\n");
7404 goto unreg;
7405 }
7406 }
7407 }
7408
7409 strlcpy(vdev->name, vdev_name, sizeof(vdev->name));
7410 node = vdev_to_node(vdev);
7411 mutex_init(&node->vlock);
7412
7413 vdev->ioctl_ops = &rkcif_v4l2_ioctl_ops;
7414 vdev->release = video_device_release_empty;
7415 vdev->fops = &rkcif_fops;
7416 vdev->minor = -1;
7417 vdev->v4l2_dev = v4l2_dev;
7418 vdev->lock = &node->vlock;
7419 vdev->device_caps = V4L2_CAP_VIDEO_CAPTURE_MPLANE |
7420 V4L2_CAP_STREAMING;
7421 video_set_drvdata(vdev, stream);
7422 vdev->vfl_dir = VFL_DIR_RX;
7423 node->pad.flags = MEDIA_PAD_FL_SINK;
7424
7425 rkcif_init_vb2_queue(&node->buf_queue, stream,
7426 V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
7427 vdev->queue = &node->buf_queue;
7428
7429 ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1);
7430 if (ret < 0) {
7431 v4l2_err(v4l2_dev,
7432 "video_register_device failed with error %d\n", ret);
7433 return ret;
7434 }
7435
7436 ret = media_entity_pads_init(&vdev->entity, 1, &node->pad);
7437 if (ret < 0)
7438 goto unreg;
7439
7440 INIT_LIST_HEAD(&stream->vb_done_list);
7441 tasklet_init(&stream->vb_done_tasklet,
7442 rkcif_tasklet_handle,
7443 (unsigned long)stream);
7444 tasklet_disable(&stream->vb_done_tasklet);
7445 return 0;
7446 unreg:
7447 video_unregister_device(vdev);
7448 return ret;
7449 }
7450
rkcif_unregister_stream_vdevs(struct rkcif_device * dev,int stream_num)7451 void rkcif_unregister_stream_vdevs(struct rkcif_device *dev,
7452 int stream_num)
7453 {
7454 struct rkcif_stream *stream;
7455 int i;
7456
7457 for (i = 0; i < stream_num; i++) {
7458 stream = &dev->stream[i];
7459 rkcif_unregister_stream_vdev(stream);
7460 }
7461 }
7462
rkcif_register_stream_vdevs(struct rkcif_device * dev,int stream_num,bool is_multi_input)7463 int rkcif_register_stream_vdevs(struct rkcif_device *dev,
7464 int stream_num,
7465 bool is_multi_input)
7466 {
7467 struct rkcif_stream *stream;
7468 int i, j, ret;
7469
7470 for (i = 0; i < stream_num; i++) {
7471 stream = &dev->stream[i];
7472 stream->cifdev = dev;
7473 ret = rkcif_register_stream_vdev(stream, is_multi_input);
7474 if (ret < 0)
7475 goto err;
7476 }
7477 dev->num_channels = stream_num;
7478 return 0;
7479 err:
7480 for (j = 0; j < i; j++) {
7481 stream = &dev->stream[j];
7482 rkcif_unregister_stream_vdev(stream);
7483 }
7484
7485 return ret;
7486 }
7487
get_lvds_remote_sensor(struct v4l2_subdev * sd)7488 static struct v4l2_subdev *get_lvds_remote_sensor(struct v4l2_subdev *sd)
7489 {
7490 struct media_pad *local, *remote;
7491 struct media_entity *sensor_me;
7492
7493 local = &sd->entity.pads[RKCIF_LVDS_PAD_SINK];
7494 remote = media_entity_remote_pad(local);
7495 if (!remote) {
7496 v4l2_warn(sd, "No link between dphy and sensor with lvds\n");
7497 return NULL;
7498 }
7499
7500 sensor_me = media_entity_remote_pad(local)->entity;
7501 return media_entity_to_v4l2_subdev(sensor_me);
7502 }
7503
rkcif_lvds_subdev_link_setup(struct media_entity * entity,const struct media_pad * local,const struct media_pad * remote,u32 flags)7504 static int rkcif_lvds_subdev_link_setup(struct media_entity *entity,
7505 const struct media_pad *local,
7506 const struct media_pad *remote,
7507 u32 flags)
7508 {
7509 return 0;
7510 }
7511
rkcif_lvds_sd_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)7512 static int rkcif_lvds_sd_set_fmt(struct v4l2_subdev *sd,
7513 struct v4l2_subdev_pad_config *cfg,
7514 struct v4l2_subdev_format *fmt)
7515 {
7516 struct v4l2_subdev *sensor = get_lvds_remote_sensor(sd);
7517
7518 /*
7519 * Do not allow format changes and just relay whatever
7520 * set currently in the sensor.
7521 */
7522 return v4l2_subdev_call(sensor, pad, get_fmt, NULL, fmt);
7523 }
7524
rkcif_lvds_sd_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)7525 static int rkcif_lvds_sd_get_fmt(struct v4l2_subdev *sd,
7526 struct v4l2_subdev_pad_config *cfg,
7527 struct v4l2_subdev_format *fmt)
7528 {
7529 struct rkcif_lvds_subdev *subdev = container_of(sd, struct rkcif_lvds_subdev, sd);
7530 struct v4l2_subdev *sensor = get_lvds_remote_sensor(sd);
7531 int ret;
7532
7533 /*
7534 * Do not allow format changes and just relay whatever
7535 * set currently in the sensor.
7536 */
7537 ret = v4l2_subdev_call(sensor, pad, get_fmt, NULL, fmt);
7538 if (!ret)
7539 subdev->in_fmt = fmt->format;
7540
7541 return ret;
7542 }
7543
rkcif_lvds_sd_get_crop(struct rkcif_lvds_subdev * subdev,struct v4l2_subdev_pad_config * cfg,enum v4l2_subdev_format_whence which)7544 static struct v4l2_rect *rkcif_lvds_sd_get_crop(struct rkcif_lvds_subdev *subdev,
7545 struct v4l2_subdev_pad_config *cfg,
7546 enum v4l2_subdev_format_whence which)
7547 {
7548 if (which == V4L2_SUBDEV_FORMAT_TRY)
7549 return v4l2_subdev_get_try_crop(&subdev->sd, cfg, RKCIF_LVDS_PAD_SINK);
7550 else
7551 return &subdev->crop;
7552 }
7553
rkcif_lvds_sd_set_selection(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_selection * sel)7554 static int rkcif_lvds_sd_set_selection(struct v4l2_subdev *sd,
7555 struct v4l2_subdev_pad_config *cfg,
7556 struct v4l2_subdev_selection *sel)
7557 {
7558 struct rkcif_lvds_subdev *subdev = container_of(sd, struct rkcif_lvds_subdev, sd);
7559 struct v4l2_subdev *sensor = get_lvds_remote_sensor(sd);
7560 int ret = 0;
7561
7562 ret = v4l2_subdev_call(sensor, pad, set_selection,
7563 cfg, sel);
7564 if (!ret)
7565 subdev->crop = sel->r;
7566
7567 return ret;
7568 }
7569
rkcif_lvds_sd_get_selection(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_selection * sel)7570 static int rkcif_lvds_sd_get_selection(struct v4l2_subdev *sd,
7571 struct v4l2_subdev_pad_config *cfg,
7572 struct v4l2_subdev_selection *sel)
7573 {
7574 struct rkcif_lvds_subdev *subdev = container_of(sd, struct rkcif_lvds_subdev, sd);
7575 struct v4l2_subdev *sensor = get_lvds_remote_sensor(sd);
7576 struct v4l2_subdev_format fmt;
7577 int ret = 0;
7578
7579 if (!sel) {
7580 v4l2_dbg(1, rkcif_debug, sd, "sel is null\n");
7581 goto err;
7582 }
7583
7584 if (sel->pad > RKCIF_LVDS_PAD_SRC_ID3) {
7585 v4l2_dbg(1, rkcif_debug, sd, "pad[%d] isn't matched\n", sel->pad);
7586 goto err;
7587 }
7588
7589 switch (sel->target) {
7590 case V4L2_SEL_TGT_CROP_BOUNDS:
7591 if (sel->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
7592 ret = v4l2_subdev_call(sensor, pad, get_selection,
7593 cfg, sel);
7594 if (ret) {
7595 fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
7596 ret = v4l2_subdev_call(sensor, pad, get_fmt, NULL, &fmt);
7597 if (!ret) {
7598 subdev->in_fmt = fmt.format;
7599 sel->r.top = 0;
7600 sel->r.left = 0;
7601 sel->r.width = subdev->in_fmt.width;
7602 sel->r.height = subdev->in_fmt.height;
7603 subdev->crop = sel->r;
7604 } else {
7605 sel->r = subdev->crop;
7606 }
7607 } else {
7608 subdev->crop = sel->r;
7609 }
7610 } else {
7611 sel->r = *v4l2_subdev_get_try_crop(sd, cfg, sel->pad);
7612 }
7613 break;
7614
7615 case V4L2_SEL_TGT_CROP:
7616 sel->r = *rkcif_lvds_sd_get_crop(subdev, cfg, sel->which);
7617 break;
7618
7619 default:
7620 return -EINVAL;
7621 }
7622
7623 return 0;
7624 err:
7625 return -EINVAL;
7626 }
7627
rkcif_lvds_g_mbus_config(struct v4l2_subdev * sd,unsigned int pad_id,struct v4l2_mbus_config * mbus)7628 static int rkcif_lvds_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
7629 struct v4l2_mbus_config *mbus)
7630 {
7631 struct v4l2_subdev *sensor_sd = get_lvds_remote_sensor(sd);
7632 int ret;
7633
7634 ret = v4l2_subdev_call(sensor_sd, pad, get_mbus_config, 0, mbus);
7635 if (ret)
7636 return ret;
7637
7638 return 0;
7639 }
7640
rkcif_lvds_sd_s_stream(struct v4l2_subdev * sd,int on)7641 static int rkcif_lvds_sd_s_stream(struct v4l2_subdev *sd, int on)
7642 {
7643 struct rkcif_lvds_subdev *subdev = container_of(sd, struct rkcif_lvds_subdev, sd);
7644
7645 if (on)
7646 atomic_set(&subdev->frm_sync_seq, 0);
7647
7648 return 0;
7649 }
7650
rkcif_lvds_sd_s_power(struct v4l2_subdev * sd,int on)7651 static int rkcif_lvds_sd_s_power(struct v4l2_subdev *sd, int on)
7652 {
7653 return 0;
7654 }
7655
rkcif_sof_subscribe_event(struct v4l2_subdev * sd,struct v4l2_fh * fh,struct v4l2_event_subscription * sub)7656 static int rkcif_sof_subscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh,
7657 struct v4l2_event_subscription *sub)
7658 {
7659 if (sub->type == V4L2_EVENT_FRAME_SYNC ||
7660 sub->type == V4L2_EVENT_RESET_DEV)
7661 return v4l2_event_subscribe(fh, sub, RKCIF_V4L2_EVENT_ELEMS, NULL);
7662 else
7663 return -EINVAL;
7664 }
7665
7666 static const struct media_entity_operations rkcif_lvds_sd_media_ops = {
7667 .link_setup = rkcif_lvds_subdev_link_setup,
7668 .link_validate = v4l2_subdev_link_validate,
7669 };
7670
7671 static const struct v4l2_subdev_pad_ops rkcif_lvds_sd_pad_ops = {
7672 .set_fmt = rkcif_lvds_sd_set_fmt,
7673 .get_fmt = rkcif_lvds_sd_get_fmt,
7674 .set_selection = rkcif_lvds_sd_set_selection,
7675 .get_selection = rkcif_lvds_sd_get_selection,
7676 .get_mbus_config = rkcif_lvds_g_mbus_config,
7677 };
7678
7679 static const struct v4l2_subdev_video_ops rkcif_lvds_sd_video_ops = {
7680 .s_stream = rkcif_lvds_sd_s_stream,
7681 };
7682
7683 static const struct v4l2_subdev_core_ops rkcif_lvds_sd_core_ops = {
7684 .s_power = rkcif_lvds_sd_s_power,
7685 .subscribe_event = rkcif_sof_subscribe_event,
7686 .unsubscribe_event = v4l2_event_subdev_unsubscribe,
7687 };
7688
7689 static struct v4l2_subdev_ops rkcif_lvds_sd_ops = {
7690 .core = &rkcif_lvds_sd_core_ops,
7691 .video = &rkcif_lvds_sd_video_ops,
7692 .pad = &rkcif_lvds_sd_pad_ops,
7693 };
7694
rkcif_lvds_event_inc_sof(struct rkcif_device * dev)7695 static void rkcif_lvds_event_inc_sof(struct rkcif_device *dev)
7696 {
7697 struct rkcif_lvds_subdev *subdev = &dev->lvds_subdev;
7698
7699 if (subdev) {
7700 struct v4l2_event event = {
7701 .type = V4L2_EVENT_FRAME_SYNC,
7702 .u.frame_sync.frame_sequence =
7703 atomic_inc_return(&subdev->frm_sync_seq) - 1,
7704 };
7705 v4l2_event_queue(subdev->sd.devnode, &event);
7706 }
7707 }
7708
rkcif_lvds_get_sof(struct rkcif_device * dev)7709 static u32 rkcif_lvds_get_sof(struct rkcif_device *dev)
7710 {
7711 if (dev)
7712 return atomic_read(&dev->lvds_subdev.frm_sync_seq) - 1;
7713
7714 return 0;
7715 }
7716
rkcif_lvds_set_sof(struct rkcif_device * dev,u32 seq)7717 static u32 rkcif_lvds_set_sof(struct rkcif_device *dev, u32 seq)
7718 {
7719 if (dev)
7720 atomic_set(&dev->lvds_subdev.frm_sync_seq, seq);
7721
7722 return 0;
7723 }
7724
rkcif_register_lvds_subdev(struct rkcif_device * dev)7725 int rkcif_register_lvds_subdev(struct rkcif_device *dev)
7726 {
7727 struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
7728 struct rkcif_lvds_subdev *lvds_subdev = &dev->lvds_subdev;
7729 struct v4l2_subdev *sd;
7730 int ret;
7731 int pad_num = 4;
7732
7733 memset(lvds_subdev, 0, sizeof(*lvds_subdev));
7734 lvds_subdev->cifdev = dev;
7735 sd = &lvds_subdev->sd;
7736 lvds_subdev->state = RKCIF_LVDS_STOP;
7737 v4l2_subdev_init(sd, &rkcif_lvds_sd_ops);
7738 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
7739 sd->entity.ops = &rkcif_lvds_sd_media_ops;
7740 if (dev->chip_id != CHIP_RV1126_CIF_LITE)
7741 snprintf(sd->name, sizeof(sd->name), "rkcif-lvds-subdev");
7742 else
7743 snprintf(sd->name, sizeof(sd->name), "rkcif-lite-lvds-subdev");
7744
7745 lvds_subdev->pads[RKCIF_LVDS_PAD_SINK].flags =
7746 MEDIA_PAD_FL_SINK | MEDIA_PAD_FL_MUST_CONNECT;
7747 lvds_subdev->pads[RKCIF_LVDS_PAD_SRC_ID0].flags = MEDIA_PAD_FL_SOURCE;
7748 lvds_subdev->pads[RKCIF_LVDS_PAD_SRC_ID1].flags = MEDIA_PAD_FL_SOURCE;
7749 lvds_subdev->pads[RKCIF_LVDS_PAD_SRC_ID2].flags = MEDIA_PAD_FL_SOURCE;
7750 lvds_subdev->pads[RKCIF_LVDS_PAD_SRC_ID3].flags = MEDIA_PAD_FL_SOURCE;
7751 if (dev->chip_id == CHIP_RV1106_CIF) {
7752 lvds_subdev->pads[RKCIF_LVDS_PAD_SCL_ID0].flags = MEDIA_PAD_FL_SOURCE;
7753 lvds_subdev->pads[RKCIF_LVDS_PAD_SCL_ID1].flags = MEDIA_PAD_FL_SOURCE;
7754 lvds_subdev->pads[RKCIF_LVDS_PAD_SCL_ID2].flags = MEDIA_PAD_FL_SOURCE;
7755 lvds_subdev->pads[RKCIF_LVDS_PAD_SCL_ID3].flags = MEDIA_PAD_FL_SOURCE;
7756 pad_num = RKCIF_LVDS_PAD_MAX;
7757 }
7758
7759 lvds_subdev->in_fmt.width = RKCIF_DEFAULT_WIDTH;
7760 lvds_subdev->in_fmt.height = RKCIF_DEFAULT_HEIGHT;
7761 lvds_subdev->crop.left = 0;
7762 lvds_subdev->crop.top = 0;
7763 lvds_subdev->crop.width = RKCIF_DEFAULT_WIDTH;
7764 lvds_subdev->crop.height = RKCIF_DEFAULT_HEIGHT;
7765
7766 ret = media_entity_pads_init(&sd->entity, pad_num,
7767 lvds_subdev->pads);
7768 if (ret < 0)
7769 return ret;
7770 sd->owner = THIS_MODULE;
7771 v4l2_set_subdevdata(sd, lvds_subdev);
7772 ret = v4l2_device_register_subdev(v4l2_dev, sd);
7773 if (ret < 0)
7774 goto free_media;
7775
7776 ret = v4l2_device_register_subdev_nodes(v4l2_dev);
7777 if (ret < 0)
7778 goto free_subdev;
7779 return ret;
7780 free_subdev:
7781 v4l2_device_unregister_subdev(sd);
7782 free_media:
7783 media_entity_cleanup(&sd->entity);
7784 v4l2_err(sd, "Failed to register subdev, ret:%d\n", ret);
7785 return ret;
7786 }
7787
rkcif_unregister_lvds_subdev(struct rkcif_device * dev)7788 void rkcif_unregister_lvds_subdev(struct rkcif_device *dev)
7789 {
7790 struct v4l2_subdev *sd = &dev->lvds_subdev.sd;
7791
7792 v4l2_device_unregister_subdev(sd);
7793 media_entity_cleanup(&sd->entity);
7794 }
7795
rkcif_dvp_event_inc_sof(struct rkcif_device * dev)7796 static void rkcif_dvp_event_inc_sof(struct rkcif_device *dev)
7797 {
7798 struct rkcif_dvp_sof_subdev *subdev = &dev->dvp_sof_subdev;
7799
7800 if (subdev) {
7801 struct v4l2_event event = {
7802 .type = V4L2_EVENT_FRAME_SYNC,
7803 .u.frame_sync.frame_sequence =
7804 atomic_inc_return(&subdev->frm_sync_seq) - 1,
7805 };
7806 v4l2_event_queue(subdev->sd.devnode, &event);
7807 }
7808 }
7809
rkcif_dvp_get_sof(struct rkcif_device * dev)7810 static u32 rkcif_dvp_get_sof(struct rkcif_device *dev)
7811 {
7812 if (dev)
7813 return atomic_read(&dev->dvp_sof_subdev.frm_sync_seq) - 1;
7814
7815 return 0;
7816 }
7817
rkcif_dvp_set_sof(struct rkcif_device * dev,u32 seq)7818 static u32 rkcif_dvp_set_sof(struct rkcif_device *dev, u32 seq)
7819 {
7820 if (dev)
7821 atomic_set(&dev->dvp_sof_subdev.frm_sync_seq, seq);
7822
7823 return 0;
7824 }
7825
7826 static const struct v4l2_subdev_core_ops rkcif_dvp_sof_sd_core_ops = {
7827 .subscribe_event = rkcif_sof_subscribe_event,
7828 .unsubscribe_event = v4l2_event_subdev_unsubscribe,
7829 };
7830
7831 static struct v4l2_subdev_ops rkcif_dvp_sof_sd_ops = {
7832 .core = &rkcif_dvp_sof_sd_core_ops,
7833 };
7834
rkcif_register_dvp_sof_subdev(struct rkcif_device * dev)7835 int rkcif_register_dvp_sof_subdev(struct rkcif_device *dev)
7836 {
7837 struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
7838 struct rkcif_dvp_sof_subdev *subdev = &dev->dvp_sof_subdev;
7839 struct v4l2_subdev *sd;
7840 int ret;
7841
7842 memset(subdev, 0, sizeof(*subdev));
7843 subdev->cifdev = dev;
7844 sd = &subdev->sd;
7845 v4l2_subdev_init(sd, &rkcif_dvp_sof_sd_ops);
7846 sd->owner = THIS_MODULE;
7847 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
7848 snprintf(sd->name, sizeof(sd->name), "rkcif-dvp-sof");
7849
7850 v4l2_set_subdevdata(sd, subdev);
7851 ret = v4l2_device_register_subdev(v4l2_dev, sd);
7852 if (ret < 0)
7853 goto end;
7854
7855 ret = v4l2_device_register_subdev_nodes(v4l2_dev);
7856 if (ret < 0)
7857 goto free_subdev;
7858
7859 return ret;
7860
7861 free_subdev:
7862 v4l2_device_unregister_subdev(sd);
7863
7864 end:
7865 v4l2_err(sd, "Failed to register subdev, ret:%d\n", ret);
7866 return ret;
7867 }
7868
rkcif_unregister_dvp_sof_subdev(struct rkcif_device * dev)7869 void rkcif_unregister_dvp_sof_subdev(struct rkcif_device *dev)
7870 {
7871 struct v4l2_subdev *sd = &dev->dvp_sof_subdev.sd;
7872
7873 v4l2_device_unregister_subdev(sd);
7874 }
7875
rkcif_irq_oneframe(struct rkcif_device * cif_dev)7876 void rkcif_irq_oneframe(struct rkcif_device *cif_dev)
7877 {
7878 /* TODO: xuhf-debug: add stream type */
7879 struct rkcif_stream *stream;
7880 u32 lastline, lastpix, ctl, cif_frmst, intstat, frmid;
7881 int ret = 0;
7882
7883 intstat = rkcif_read_register(cif_dev, CIF_REG_DVP_INTSTAT);
7884 cif_frmst = rkcif_read_register(cif_dev, CIF_REG_DVP_FRAME_STATUS);
7885 lastline = rkcif_read_register(cif_dev, CIF_REG_DVP_LAST_LINE);
7886 lastpix = rkcif_read_register(cif_dev, CIF_REG_DVP_LAST_PIX);
7887 ctl = rkcif_read_register(cif_dev, CIF_REG_DVP_CTRL);
7888 frmid = CIF_GET_FRAME_ID(cif_frmst);
7889
7890 /* There are two irqs enabled:
7891 * - PST_INF_FRAME_END: cif FIFO is ready, this is prior to FRAME_END
7892 * - FRAME_END: cif has saved frame to memory, a frame ready
7893 */
7894 stream = &cif_dev->stream[RKCIF_STREAM_CIF];
7895
7896 if ((intstat & PST_INF_FRAME_END)) {
7897 rkcif_write_register(cif_dev, CIF_REG_DVP_INTSTAT,
7898 PST_INF_FRAME_END_CLR);
7899
7900 if (stream->stopping)
7901 /* To stop CIF ASAP, before FRAME_END irq */
7902 rkcif_write_register(cif_dev, CIF_REG_DVP_CTRL,
7903 ctl & (~ENABLE_CAPTURE));
7904 }
7905
7906 if ((intstat & FRAME_END)) {
7907 struct rkcif_buffer *active_buf = NULL;
7908
7909 rkcif_write_register(cif_dev, CIF_REG_DVP_INTSTAT,
7910 FRAME_END_CLR);
7911
7912 if (stream->stopping) {
7913 rkcif_stream_stop(stream);
7914 stream->stopping = false;
7915 wake_up(&stream->wq_stopped);
7916 return;
7917 }
7918
7919 if (lastline != stream->pixm.height ||
7920 !(cif_frmst & CIF_F0_READY)) {
7921 /* Clearing status must be complete before fe packet
7922 * arrives while cif is connected with mipi,
7923 * so it should be placed before printing log here,
7924 * otherwise it would be delayed.
7925 * At the same time, don't clear the frame id
7926 * for switching address.
7927 */
7928 rkcif_write_register(cif_dev, CIF_REG_DVP_FRAME_STATUS,
7929 FRM0_STAT_CLS);
7930 v4l2_err(&cif_dev->v4l2_dev,
7931 "Bad frame, irq:0x%x frmst:0x%x size:%dx%d\n",
7932 intstat, cif_frmst, lastline, lastpix);
7933
7934 return;
7935 }
7936
7937 if (frmid % 2 != 0) {
7938 stream->frame_phase = CIF_CSI_FRAME0_READY;
7939 if (stream->curr_buf)
7940 active_buf = stream->curr_buf;
7941 } else {
7942 stream->frame_phase = CIF_CSI_FRAME1_READY;
7943 if (stream->next_buf)
7944 active_buf = stream->next_buf;
7945 }
7946
7947 /* In one-frame mode:
7948 * 1,must clear status manually by writing 0 to enable
7949 * the next frame end irq;
7950 * 2,do not clear the frame id for switching address.
7951 */
7952 rkcif_write_register(cif_dev, CIF_REG_DVP_FRAME_STATUS,
7953 cif_frmst & FRM0_STAT_CLS);
7954 ret = rkcif_assign_new_buffer_oneframe(stream,
7955 RKCIF_YUV_ADDR_STATE_UPDATE);
7956
7957 if (active_buf && (!ret)) {
7958 active_buf->vb.sequence = stream->frame_idx - 1;
7959 rkcif_vb_done_tasklet(stream, active_buf);
7960 }
7961
7962 cif_dev->irq_stats.frm_end_cnt[stream->id]++;
7963 }
7964 }
7965
rkcif_csi_g_mipi_id(struct v4l2_device * v4l2_dev,unsigned int intstat)7966 static int rkcif_csi_g_mipi_id(struct v4l2_device *v4l2_dev,
7967 unsigned int intstat)
7968 {
7969 if (intstat & CSI_FRAME_END_ID0)
7970 return RKCIF_STREAM_MIPI_ID0;
7971
7972 if (intstat & CSI_FRAME_END_ID1)
7973 return RKCIF_STREAM_MIPI_ID1;
7974
7975 if (intstat & CSI_FRAME_END_ID2)
7976 return RKCIF_STREAM_MIPI_ID2;
7977 if (intstat & CSI_FRAME_END_ID3)
7978 return RKCIF_STREAM_MIPI_ID3;
7979
7980 return -EINVAL;
7981 }
7982
rkcif_dvp_g_ch_id(struct v4l2_device * v4l2_dev,u32 * intstat,u32 frm_stat)7983 static int rkcif_dvp_g_ch_id(struct v4l2_device *v4l2_dev,
7984 u32 *intstat, u32 frm_stat)
7985 {
7986 if (*intstat & DVP_FRAME_END_ID0) {
7987 *intstat &= ~DVP_FRAME_END_ID0;
7988 return RKCIF_STREAM_MIPI_ID0;
7989 }
7990
7991 if (*intstat & DVP_FRAME_END_ID1) {
7992 *intstat &= ~DVP_FRAME_END_ID1;
7993 return RKCIF_STREAM_MIPI_ID1;
7994 }
7995
7996 if (*intstat & DVP_FRAME_END_ID2) {
7997 *intstat &= ~DVP_FRAME_END_ID2;
7998 return RKCIF_STREAM_MIPI_ID2;
7999 }
8000
8001 if (*intstat & DVP_FRAME_END_ID3) {
8002 *intstat &= ~DVP_FRAME_END_ID3;
8003 return RKCIF_STREAM_MIPI_ID3;
8004 }
8005
8006 return -EINVAL;
8007 }
8008
rkcif_dvp_g_ch_id_by_fe(struct v4l2_device * v4l2_dev,u32 intstat)8009 static int rkcif_dvp_g_ch_id_by_fe(struct v4l2_device *v4l2_dev,
8010 u32 intstat)
8011 {
8012 if (intstat & DVP_ALL_END_ID0)
8013 return RKCIF_STREAM_MIPI_ID0;
8014
8015 if (intstat & DVP_ALL_END_ID1)
8016 return RKCIF_STREAM_MIPI_ID1;
8017
8018 if (intstat & DVP_ALL_END_ID2)
8019 return RKCIF_STREAM_MIPI_ID2;
8020
8021 if (intstat & DVP_ALL_END_ID3)
8022 return RKCIF_STREAM_MIPI_ID3;
8023
8024 return -EINVAL;
8025 }
8026
rkcif_is_csi2_err_trigger_reset(struct rkcif_timer * timer)8027 static bool rkcif_is_csi2_err_trigger_reset(struct rkcif_timer *timer)
8028 {
8029 struct rkcif_device *dev = container_of(timer,
8030 struct rkcif_device,
8031 reset_watchdog_timer);
8032 struct rkcif_stream *stream = &dev->stream[RKCIF_STREAM_MIPI_ID0];
8033 bool is_triggered = false, is_assign_triggered = false, is_first_err = false;
8034 unsigned long flags;
8035 u64 cur_time, diff_time;
8036
8037 spin_lock_irqsave(&timer->csi2_err_lock, flags);
8038
8039 if (timer->csi2_err_cnt_even != 0 &&
8040 timer->csi2_err_cnt_odd != 0) {
8041 timer->csi2_err_cnt_odd = 0;
8042 timer->csi2_err_cnt_even = 0;
8043 timer->reset_src = RKCIF_RESET_SRC_ERR_CSI2;
8044 timer->csi2_err_triggered_cnt++;
8045 if (timer->csi2_err_triggered_cnt == 1) {
8046 is_first_err = true;
8047 timer->csi2_first_err_timestamp = ktime_get_ns();
8048 }
8049
8050 is_assign_triggered = true;
8051
8052 v4l2_info(&dev->v4l2_dev,
8053 "find csi2 err cnt is:%d\n",
8054 timer->csi2_err_triggered_cnt);
8055 }
8056
8057 if (!is_first_err) {
8058 if (timer->csi2_err_triggered_cnt >= 1) {
8059 cur_time = ktime_get_ns();
8060 diff_time = cur_time - timer->csi2_first_err_timestamp;
8061 diff_time = div_u64(diff_time, 1000000);
8062 if (diff_time >= timer->err_time_interval) {
8063 is_triggered = true;
8064 v4l2_info(&dev->v4l2_dev, "trigger reset for time out of csi err\n");
8065 goto end_judge;
8066 }
8067
8068 if (!is_assign_triggered &&
8069 (timer->csi2_err_cnt_odd == 0 ||
8070 timer->csi2_err_cnt_even == 0)) {
8071 is_triggered = true;
8072 v4l2_info(&dev->v4l2_dev, "trigger reset for csi err\n");
8073 goto end_judge;
8074 }
8075 }
8076 }
8077
8078 /*
8079 * when fs cnt is beyond 2, it indicates that frame end is not coming,
8080 * or fs and fe had been not paired.
8081 */
8082 if (stream->is_fs_fe_not_paired ||
8083 stream->fs_cnt_in_single_frame > RKCIF_FS_DETECTED_NUM) {
8084 is_triggered = true;
8085 v4l2_info(&dev->v4l2_dev, "reset for fs & fe not paired\n");
8086 }
8087 end_judge:
8088 spin_unlock_irqrestore(&timer->csi2_err_lock, flags);
8089
8090 return is_triggered;
8091 }
8092
rkcif_is_triggered_monitoring(struct rkcif_device * dev)8093 static bool rkcif_is_triggered_monitoring(struct rkcif_device *dev)
8094 {
8095 struct rkcif_timer *timer = &dev->reset_watchdog_timer;
8096 struct rkcif_stream *stream = &dev->stream[RKCIF_STREAM_MIPI_ID0];
8097 bool ret = false;
8098
8099 if (timer->monitor_mode == RKCIF_MONITOR_MODE_IDLE)
8100 ret = false;
8101
8102 if (timer->monitor_mode == RKCIF_MONITOR_MODE_CONTINUE ||
8103 timer->monitor_mode == RKCIF_MONITOR_MODE_HOTPLUG) {
8104 if (stream->frame_idx >= timer->triggered_frame_num)
8105 ret = true;
8106 }
8107
8108 if (timer->monitor_mode == RKCIF_MONITOR_MODE_TRIGGER) {
8109 timer->is_csi2_err_occurred = rkcif_is_csi2_err_trigger_reset(timer);
8110 ret = timer->is_csi2_err_occurred;
8111 }
8112
8113 return ret;
8114 }
8115
rkcif_get_sensor_vblank(struct rkcif_device * dev)8116 s32 rkcif_get_sensor_vblank(struct rkcif_device *dev)
8117 {
8118 struct rkcif_sensor_info *terminal_sensor = &dev->terminal_sensor;
8119 struct v4l2_subdev *sd = terminal_sensor->sd;
8120 struct v4l2_ctrl_handler *hdl = sd->ctrl_handler;
8121 struct v4l2_ctrl *ctrl = NULL;
8122
8123 if (!list_empty(&hdl->ctrls)) {
8124 list_for_each_entry(ctrl, &hdl->ctrls, node) {
8125 if (ctrl->id == V4L2_CID_VBLANK)
8126 return ctrl->val;
8127 }
8128 }
8129
8130 return 0;
8131 }
8132
rkcif_get_sensor_vblank_def(struct rkcif_device * dev)8133 s32 rkcif_get_sensor_vblank_def(struct rkcif_device *dev)
8134 {
8135 struct rkcif_sensor_info *terminal_sensor = &dev->terminal_sensor;
8136 struct v4l2_subdev *sd = terminal_sensor->sd;
8137 struct v4l2_ctrl_handler *hdl = sd->ctrl_handler;
8138 struct v4l2_ctrl *ctrl = NULL;
8139
8140 if (!list_empty(&hdl->ctrls)) {
8141 list_for_each_entry(ctrl, &hdl->ctrls, node) {
8142 if (ctrl->id == V4L2_CID_VBLANK)
8143 return ctrl->default_value;
8144 }
8145 }
8146
8147 return 0;
8148 }
8149
rkcif_cal_csi_crop_width_vwidth(struct rkcif_stream * stream,u32 raw_width,u32 * crop_width,u32 * crop_vwidth)8150 static void rkcif_cal_csi_crop_width_vwidth(struct rkcif_stream *stream,
8151 u32 raw_width, u32 *crop_width,
8152 u32 *crop_vwidth)
8153 {
8154 struct rkcif_device *dev = stream->cifdev;
8155 struct csi_channel_info *channel = &dev->channels[stream->id];
8156 const struct cif_output_fmt *fmt;
8157 u32 fourcc;
8158
8159 fmt = rkcif_find_output_fmt(stream, stream->pixm.pixelformat);
8160 if (!fmt) {
8161 v4l2_err(&dev->v4l2_dev, "can not find output format: 0x%x",
8162 stream->pixm.pixelformat);
8163 return;
8164 }
8165
8166 *crop_width = raw_width;
8167
8168 /*
8169 * for mipi or lvds, when enable compact, the virtual width of raw10/raw12
8170 * needs aligned with :ALIGN(bits_per_pixel * width / 8, 8), if enable 16bit mode
8171 * needs aligned with :ALIGN(bits_per_pixel * width * 2, 8), to optimize reading and
8172 * writing of ddr, aliged with 256
8173 */
8174 if (fmt->fmt_type == CIF_FMT_TYPE_RAW && stream->is_compact &&
8175 fmt->csi_fmt_val != CSI_WRDDR_TYPE_RGB888 &&
8176 fmt->csi_fmt_val != CSI_WRDDR_TYPE_RGB565) {
8177 *crop_vwidth = ALIGN(raw_width * fmt->raw_bpp / 8, 256);
8178 } else {
8179 *crop_vwidth = ALIGN(raw_width * fmt->bpp[0] / 8, 8);
8180 }
8181
8182 if (channel->fmt_val == CSI_WRDDR_TYPE_RGB888 || channel->fmt_val == CSI_WRDDR_TYPE_RGB565)
8183 *crop_width = raw_width * fmt->bpp[0] / 8;
8184 /*
8185 * rk cif don't support output yuyv fmt data
8186 * if user request yuyv fmt, the input mode must be RAW8
8187 * and the width is double Because the real input fmt is
8188 * yuyv
8189 */
8190 fourcc = stream->cif_fmt_out->fourcc;
8191 if (fourcc == V4L2_PIX_FMT_YUYV || fourcc == V4L2_PIX_FMT_YVYU ||
8192 fourcc == V4L2_PIX_FMT_UYVY || fourcc == V4L2_PIX_FMT_VYUY) {
8193 *crop_width = 2 * raw_width;
8194 *crop_vwidth *= 2;
8195 }
8196 }
8197
rkcif_dynamic_crop(struct rkcif_stream * stream)8198 static void rkcif_dynamic_crop(struct rkcif_stream *stream)
8199 {
8200 struct rkcif_device *cif_dev = stream->cifdev;
8201 struct v4l2_mbus_config *mbus;
8202 const struct cif_output_fmt *fmt;
8203 u32 raw_width, crop_width = 64, crop_vwidth = 64,
8204 crop_height = 64, crop_x = 0, crop_y = 0;
8205
8206 if (!cif_dev->active_sensor)
8207 return;
8208
8209 mbus = &cif_dev->active_sensor->mbus;
8210 if (mbus->type == V4L2_MBUS_CSI2_DPHY ||
8211 mbus->type == V4L2_MBUS_CSI2_CPHY ||
8212 mbus->type == V4L2_MBUS_CCP2) {
8213 struct csi_channel_info *channel = &cif_dev->channels[stream->id];
8214
8215 if (channel->fmt_val == CSI_WRDDR_TYPE_RGB888)
8216 crop_x = 3 * stream->crop[CROP_SRC_ACT].left;
8217 else if (channel->fmt_val == CSI_WRDDR_TYPE_RGB565)
8218 crop_x = 2 * stream->crop[CROP_SRC_ACT].left;
8219 else
8220 crop_x = stream->crop[CROP_SRC_ACT].left;
8221
8222 crop_y = stream->crop[CROP_SRC_ACT].top;
8223 raw_width = stream->crop[CROP_SRC_ACT].width;
8224 crop_height = stream->crop[CROP_SRC_ACT].height;
8225
8226 rkcif_cal_csi_crop_width_vwidth(stream,
8227 raw_width,
8228 &crop_width, &crop_vwidth);
8229 rkcif_write_register(cif_dev,
8230 get_reg_index_of_id_crop_start(channel->id),
8231 crop_y << 16 | crop_x);
8232 rkcif_write_register(cif_dev, get_reg_index_of_id_ctrl1(channel->id),
8233 crop_height << 16 | crop_width);
8234
8235 rkcif_write_register(cif_dev,
8236 get_reg_index_of_frm0_y_vlw(channel->id),
8237 crop_vwidth);
8238 rkcif_write_register(cif_dev,
8239 get_reg_index_of_frm1_y_vlw(channel->id),
8240 crop_vwidth);
8241 rkcif_write_register(cif_dev,
8242 get_reg_index_of_frm0_uv_vlw(channel->id),
8243 crop_vwidth);
8244 rkcif_write_register(cif_dev,
8245 get_reg_index_of_frm1_uv_vlw(channel->id),
8246 crop_vwidth);
8247 } else {
8248
8249 raw_width = stream->crop[CROP_SRC_ACT].width;
8250 crop_width = raw_width;
8251 crop_vwidth = raw_width;
8252 crop_height = stream->crop[CROP_SRC_ACT].height;
8253 crop_x = stream->crop[CROP_SRC_ACT].left;
8254 crop_y = stream->crop[CROP_SRC_ACT].top;
8255
8256 rkcif_write_register(cif_dev, CIF_REG_DVP_CROP,
8257 crop_y << CIF_CROP_Y_SHIFT | crop_x);
8258
8259 if (stream->cif_fmt_in->fmt_type == CIF_FMT_TYPE_RAW) {
8260 fmt = rkcif_find_output_fmt(stream, stream->pixm.pixelformat);
8261 crop_vwidth = raw_width * rkcif_cal_raw_vir_line_ratio(stream, fmt);
8262 }
8263 rkcif_write_register(cif_dev, CIF_REG_DVP_VIR_LINE_WIDTH, crop_vwidth);
8264
8265 rkcif_write_register(cif_dev, CIF_REG_DVP_SET_SIZE,
8266 crop_height << 16 | crop_width);
8267 }
8268
8269 stream->crop_dyn_en = false;
8270 }
8271
rkcif_monitor_reset_event(struct rkcif_device * dev)8272 static void rkcif_monitor_reset_event(struct rkcif_device *dev)
8273 {
8274 struct rkcif_stream *stream = NULL;
8275 struct rkcif_timer *timer = &dev->reset_watchdog_timer;
8276 unsigned int cycle = 0;
8277 u64 fps, timestamp0, timestamp1;
8278 unsigned long flags, fps_flags;
8279 int i = 0;
8280
8281 if (timer->is_running)
8282 return;
8283
8284 if (timer->monitor_mode == RKCIF_MONITOR_MODE_IDLE)
8285 return;
8286
8287 for (i = 0; i < RKCIF_MAX_STREAM_MIPI; i++) {
8288 stream = &dev->stream[i];
8289 if (stream->state == RKCIF_STATE_STREAMING)
8290 break;
8291 }
8292
8293 if (i >= RKCIF_MAX_STREAM_MIPI)
8294 return;
8295
8296 timer->is_triggered = rkcif_is_triggered_monitoring(dev);
8297
8298 if (timer->is_triggered) {
8299 struct v4l2_rect *raw_rect = &dev->terminal_sensor.raw_rect;
8300 enum rkcif_monitor_mode mode;
8301 s32 vblank = 0;
8302 u32 vts = 0;
8303 u64 numerator = 0;
8304 u64 denominator = 0;
8305
8306 if (stream->frame_idx > 2) {
8307 spin_lock_irqsave(&stream->fps_lock, fps_flags);
8308 timestamp0 = stream->fps_stats.frm0_timestamp;
8309 timestamp1 = stream->fps_stats.frm1_timestamp;
8310 spin_unlock_irqrestore(&stream->fps_lock, fps_flags);
8311
8312 fps = timestamp0 > timestamp1 ?
8313 timestamp0 - timestamp1 : timestamp1 - timestamp0;
8314 fps = div_u64(fps, 1000);
8315 } else {
8316 numerator = dev->terminal_sensor.fi.interval.numerator;
8317 denominator = dev->terminal_sensor.fi.interval.denominator;
8318 fps = div_u64(1000000 * numerator, denominator);
8319 }
8320 spin_lock_irqsave(&timer->timer_lock, flags);
8321
8322 timer->frame_end_cycle_us = fps;
8323
8324 vblank = rkcif_get_sensor_vblank(dev);
8325 timer->raw_height = raw_rect->height;
8326 vts = timer->raw_height + vblank;
8327 timer->vts = vts;
8328
8329 timer->line_end_cycle = div_u64(timer->frame_end_cycle_us, timer->vts);
8330 fps = div_u64(timer->frame_end_cycle_us, 1000);
8331 cycle = fps * timer->frm_num_of_monitor_cycle;
8332 timer->cycle = msecs_to_jiffies(cycle);
8333
8334 timer->run_cnt = 0;
8335 timer->is_running = true;
8336 timer->is_buf_stop_update = false;
8337 for (i = 0; i < dev->num_channels; i++) {
8338 stream = &dev->stream[i];
8339 if (stream->state == RKCIF_STATE_STREAMING)
8340 timer->last_buf_wakeup_cnt[i] = stream->buf_wake_up_cnt;
8341 }
8342 /* in trigger mode, monitoring count is fps */
8343 mode = timer->monitor_mode;
8344 if (mode == RKCIF_MONITOR_MODE_CONTINUE ||
8345 mode == RKCIF_MONITOR_MODE_HOTPLUG)
8346 timer->max_run_cnt = 0xffffffff - CIF_TIMEOUT_FRAME_NUM;
8347 else
8348 timer->max_run_cnt = div_u64(1000, fps) * 1;
8349
8350 timer->timer.expires = jiffies + timer->cycle;
8351 mod_timer(&timer->timer, timer->timer.expires);
8352
8353 spin_unlock_irqrestore(&timer->timer_lock, flags);
8354
8355 v4l2_dbg(3, rkcif_debug, &dev->v4l2_dev,
8356 "%s:mode:%d, raw height:%d,vblank:%d, cycle:%ld, fps:%llu\n",
8357 __func__, timer->monitor_mode, raw_rect->height,
8358 vblank, timer->cycle, div_u64(1000, fps));
8359 }
8360 }
8361
rkcif_rdbk_frame_end(struct rkcif_stream * stream)8362 static void rkcif_rdbk_frame_end(struct rkcif_stream *stream)
8363 {
8364 struct rkcif_device *dev = stream->cifdev;
8365 struct rkcif_sensor_info *sensor = &stream->cifdev->terminal_sensor;
8366 u32 denominator, numerator;
8367 u64 l_ts, m_ts, s_ts, time = 30000000LL;
8368 int ret, fps = -1;
8369 int i = 0;
8370 unsigned long flags;
8371
8372 if (dev->hdr.hdr_mode == HDR_X2) {
8373 if (stream->id != RKCIF_STREAM_MIPI_ID1 ||
8374 dev->stream[RKCIF_STREAM_MIPI_ID0].state != RKCIF_STATE_STREAMING ||
8375 dev->stream[RKCIF_STREAM_MIPI_ID1].state != RKCIF_STATE_STREAMING)
8376 return;
8377 } else if (dev->hdr.hdr_mode == HDR_X3) {
8378 if (stream->id != RKCIF_STREAM_MIPI_ID2 ||
8379 dev->stream[RKCIF_STREAM_MIPI_ID0].state != RKCIF_STATE_STREAMING ||
8380 dev->stream[RKCIF_STREAM_MIPI_ID1].state != RKCIF_STATE_STREAMING ||
8381 dev->stream[RKCIF_STREAM_MIPI_ID2].state != RKCIF_STATE_STREAMING)
8382 return;
8383 }
8384
8385 numerator = sensor->fi.interval.numerator;
8386 denominator = sensor->fi.interval.denominator;
8387 if (denominator && numerator)
8388 time = numerator * 1000 / denominator * 1000 * 1000;
8389
8390 if (dev->hdr.hdr_mode == HDR_X3) {
8391 if (dev->rdbk_buf[RDBK_L] &&
8392 dev->rdbk_buf[RDBK_M] &&
8393 dev->rdbk_buf[RDBK_S]) {
8394 l_ts = dev->rdbk_buf[RDBK_L]->fe_timestamp;
8395 m_ts = dev->rdbk_buf[RDBK_M]->fe_timestamp;
8396 s_ts = dev->rdbk_buf[RDBK_S]->fe_timestamp;
8397
8398 if (m_ts < l_ts || s_ts < m_ts) {
8399 v4l2_err(&dev->v4l2_dev,
8400 "s/m/l frame err, timestamp s:%lld m:%lld l:%lld\n",
8401 s_ts, m_ts, l_ts);
8402 goto RDBK_FRM_UNMATCH;
8403 }
8404
8405 if ((m_ts - l_ts) > time || (s_ts - m_ts) > time) {
8406 ret = v4l2_subdev_call(sensor->sd,
8407 video,
8408 g_frame_interval,
8409 &sensor->fi);
8410 if (!ret) {
8411 denominator = sensor->fi.interval.denominator;
8412 numerator = sensor->fi.interval.numerator;
8413 if (denominator && numerator) {
8414 time = numerator * 1000 / denominator * 1000 * 1000;
8415 fps = denominator / numerator;
8416 }
8417 }
8418
8419 if ((m_ts - l_ts) > time || (s_ts - m_ts) > time) {
8420 v4l2_err(&dev->v4l2_dev,
8421 "timestamp no match, s:%lld m:%lld l:%lld, fps:%d\n",
8422 s_ts, m_ts, l_ts, fps);
8423 goto RDBK_FRM_UNMATCH;
8424 }
8425 }
8426 dev->rdbk_buf[RDBK_M]->vb.sequence = dev->rdbk_buf[RDBK_L]->vb.sequence;
8427 dev->rdbk_buf[RDBK_S]->vb.sequence = dev->rdbk_buf[RDBK_L]->vb.sequence;
8428 if (dev->is_support_tools &&
8429 dev->stream[RKCIF_STREAM_MIPI_ID0].tools_vdev->state == RKCIF_STATE_STREAMING &&
8430 dev->stream[RKCIF_STREAM_MIPI_ID1].tools_vdev->state == RKCIF_STATE_STREAMING &&
8431 dev->stream[RKCIF_STREAM_MIPI_ID2].tools_vdev->state == RKCIF_STATE_STREAMING) {
8432 for (i = 0; i < 3; i++) {
8433 spin_lock_irqsave(&dev->stream[i].tools_vdev->vbq_lock, flags);
8434 list_add_tail(&dev->rdbk_buf[i]->queue,
8435 &dev->stream[i].tools_vdev->buf_done_head);
8436 if (!work_busy(&dev->stream[i].tools_vdev->work))
8437 schedule_work(&dev->stream[i].tools_vdev->work);
8438 spin_unlock_irqrestore(&dev->stream[i].tools_vdev->vbq_lock, flags);
8439 }
8440 } else {
8441 rkcif_vb_done_tasklet(&dev->stream[RKCIF_STREAM_MIPI_ID0], dev->rdbk_buf[RDBK_L]);
8442 rkcif_vb_done_tasklet(&dev->stream[RKCIF_STREAM_MIPI_ID1], dev->rdbk_buf[RDBK_M]);
8443 rkcif_vb_done_tasklet(&dev->stream[RKCIF_STREAM_MIPI_ID2], dev->rdbk_buf[RDBK_S]);
8444 }
8445 } else {
8446 if (!dev->rdbk_buf[RDBK_L])
8447 v4l2_err(&dev->v4l2_dev, "lost long frames\n");
8448 if (!dev->rdbk_buf[RDBK_M])
8449 v4l2_err(&dev->v4l2_dev, "lost medium frames\n");
8450 if (!dev->rdbk_buf[RDBK_S])
8451 v4l2_err(&dev->v4l2_dev, "lost short frames\n");
8452 goto RDBK_FRM_UNMATCH;
8453 }
8454 } else if (dev->hdr.hdr_mode == HDR_X2) {
8455 if (dev->rdbk_buf[RDBK_L] && dev->rdbk_buf[RDBK_M]) {
8456 l_ts = dev->rdbk_buf[RDBK_L]->fe_timestamp;
8457 s_ts = dev->rdbk_buf[RDBK_M]->fe_timestamp;
8458
8459 if (s_ts < l_ts) {
8460 v4l2_err(&dev->v4l2_dev,
8461 "s/l frame err, timestamp s:%lld l:%lld\n",
8462 s_ts, l_ts);
8463 goto RDBK_FRM_UNMATCH;
8464 }
8465
8466 if ((s_ts - l_ts) > time) {
8467 ret = v4l2_subdev_call(sensor->sd,
8468 video,
8469 g_frame_interval,
8470 &sensor->fi);
8471 if (!ret) {
8472 denominator = sensor->fi.interval.denominator;
8473 numerator = sensor->fi.interval.numerator;
8474 if (denominator && numerator) {
8475 time = numerator * 1000 / denominator * 1000 * 1000;
8476 fps = denominator / numerator;
8477 }
8478 }
8479 if ((s_ts - l_ts) > time) {
8480 v4l2_err(&dev->v4l2_dev,
8481 "timestamp no match, s:%lld l:%lld, fps:%d\n",
8482 s_ts, l_ts, fps);
8483 goto RDBK_FRM_UNMATCH;
8484 }
8485 }
8486 dev->rdbk_buf[RDBK_M]->vb.sequence = dev->rdbk_buf[RDBK_L]->vb.sequence;
8487 if (dev->is_support_tools &&
8488 dev->stream[RKCIF_STREAM_MIPI_ID0].tools_vdev->state == RKCIF_STATE_STREAMING &&
8489 dev->stream[RKCIF_STREAM_MIPI_ID1].tools_vdev->state == RKCIF_STATE_STREAMING) {
8490 for (i = 0; i < 2; i++) {
8491 spin_lock_irqsave(&dev->stream[i].tools_vdev->vbq_lock, flags);
8492 list_add_tail(&dev->rdbk_buf[i]->queue,
8493 &dev->stream[i].tools_vdev->buf_done_head);
8494 if (!work_busy(&dev->stream[i].tools_vdev->work))
8495 schedule_work(&dev->stream[i].tools_vdev->work);
8496 spin_unlock_irqrestore(&dev->stream[i].tools_vdev->vbq_lock, flags);
8497 }
8498 } else {
8499 rkcif_vb_done_tasklet(&dev->stream[RKCIF_STREAM_MIPI_ID0], dev->rdbk_buf[RDBK_L]);
8500 rkcif_vb_done_tasklet(&dev->stream[RKCIF_STREAM_MIPI_ID1], dev->rdbk_buf[RDBK_M]);
8501 }
8502 } else {
8503 if (!dev->rdbk_buf[RDBK_L])
8504 v4l2_err(&dev->v4l2_dev, "lost long frames\n");
8505 if (!dev->rdbk_buf[RDBK_M])
8506 v4l2_err(&dev->v4l2_dev, "lost short frames\n");
8507 goto RDBK_FRM_UNMATCH;
8508 }
8509 }
8510
8511 dev->rdbk_buf[RDBK_L] = NULL;
8512 dev->rdbk_buf[RDBK_M] = NULL;
8513 dev->rdbk_buf[RDBK_S] = NULL;
8514 return;
8515
8516 RDBK_FRM_UNMATCH:
8517 if (dev->rdbk_buf[RDBK_L]) {
8518 dev->rdbk_buf[RDBK_L]->vb.vb2_buf.state = VB2_BUF_STATE_ACTIVE;
8519 rkcif_buf_queue(&dev->rdbk_buf[RDBK_L]->vb.vb2_buf);
8520 }
8521 if (dev->rdbk_buf[RDBK_M]) {
8522 dev->rdbk_buf[RDBK_M]->vb.vb2_buf.state = VB2_BUF_STATE_ACTIVE;
8523 rkcif_buf_queue(&dev->rdbk_buf[RDBK_M]->vb.vb2_buf);
8524 }
8525 if (dev->rdbk_buf[RDBK_S]) {
8526 dev->rdbk_buf[RDBK_S]->vb.vb2_buf.state = VB2_BUF_STATE_ACTIVE;
8527 rkcif_buf_queue(&dev->rdbk_buf[RDBK_S]->vb.vb2_buf);
8528 }
8529
8530 dev->rdbk_buf[RDBK_L] = NULL;
8531 dev->rdbk_buf[RDBK_M] = NULL;
8532 dev->rdbk_buf[RDBK_S] = NULL;
8533 }
8534
rkcif_buf_done_with_tools(struct rkcif_stream * stream,struct rkcif_buffer * active_buf)8535 static void rkcif_buf_done_with_tools(struct rkcif_stream *stream,
8536 struct rkcif_buffer *active_buf)
8537 {
8538 unsigned long flags;
8539
8540 spin_lock_irqsave(&stream->tools_vdev->vbq_lock, flags);
8541 if (stream->tools_vdev->state == RKCIF_STATE_STREAMING) {
8542 list_add_tail(&active_buf->queue, &stream->tools_vdev->buf_done_head);
8543 if (!work_busy(&stream->tools_vdev->work))
8544 schedule_work(&stream->tools_vdev->work);
8545 } else {
8546 rkcif_vb_done_tasklet(stream, active_buf);
8547 }
8548 spin_unlock_irqrestore(&stream->tools_vdev->vbq_lock, flags);
8549 }
8550
rkcif_buf_done_prepare(struct rkcif_stream * stream,struct rkcif_buffer * active_buf,int mipi_id,u32 mode)8551 static void rkcif_buf_done_prepare(struct rkcif_stream *stream,
8552 struct rkcif_buffer *active_buf,
8553 int mipi_id,
8554 u32 mode)
8555 {
8556 unsigned long flags;
8557 struct vb2_v4l2_buffer *vb_done = NULL;
8558 struct rkcif_device *cif_dev = stream->cifdev;
8559
8560 if (active_buf) {
8561 vb_done = &active_buf->vb;
8562 vb_done->vb2_buf.timestamp = stream->readout.fs_timestamp;
8563 vb_done->sequence = stream->frame_idx - 1;
8564 active_buf->fe_timestamp = ktime_get_ns();
8565 if (stream->is_line_wake_up) {
8566 spin_lock_irqsave(&stream->fps_lock, flags);
8567 if (mode)
8568 stream->fps_stats.frm0_timestamp = vb_done->vb2_buf.timestamp;
8569 else
8570 stream->fps_stats.frm1_timestamp = vb_done->vb2_buf.timestamp;
8571 stream->readout.wk_timestamp = vb_done->vb2_buf.timestamp;
8572 spin_unlock_irqrestore(&stream->fps_lock, flags);
8573 }
8574 if (stream->cif_fmt_in->field == V4L2_FIELD_INTERLACED)
8575 vb_done->sequence /= 2;
8576 }
8577
8578 if (cif_dev->hdr.hdr_mode == NO_HDR || cif_dev->hdr.hdr_mode == HDR_COMPR) {
8579 if (stream->cif_fmt_in->field == V4L2_FIELD_INTERLACED) {
8580 if (stream->frame_phase == CIF_CSI_FRAME1_READY && active_buf) {
8581
8582 if (cif_dev->is_support_tools && stream->tools_vdev)
8583 rkcif_buf_done_with_tools(stream, active_buf);
8584 else
8585 rkcif_vb_done_tasklet(stream, active_buf);
8586 }
8587 } else {
8588 if (active_buf) {
8589 if (cif_dev->is_support_tools && stream->tools_vdev)
8590 rkcif_buf_done_with_tools(stream, active_buf);
8591 else
8592 rkcif_vb_done_tasklet(stream, active_buf);
8593 }
8594 }
8595 } else {
8596 if (cif_dev->is_start_hdr) {
8597 spin_lock_irqsave(&cif_dev->hdr_lock, flags);
8598 if (mipi_id == RKCIF_STREAM_MIPI_ID0) {
8599 if (cif_dev->rdbk_buf[RDBK_L]) {
8600 v4l2_err(&cif_dev->v4l2_dev,
8601 "multiple long data in %s frame,frm_idx:%d,state:0x%x\n",
8602 cif_dev->hdr.hdr_mode == HDR_X2 ? "hdr_x2" : "hdr_x3",
8603 stream->frame_idx,
8604 cif_dev->rdbk_buf[RDBK_L]->vb.vb2_buf.state);
8605 cif_dev->rdbk_buf[RDBK_L]->vb.vb2_buf.state = VB2_BUF_STATE_ACTIVE;
8606 rkcif_buf_queue(&cif_dev->rdbk_buf[RDBK_L]->vb.vb2_buf);
8607 cif_dev->rdbk_buf[RDBK_L] = NULL;
8608 }
8609 if (active_buf)
8610 cif_dev->rdbk_buf[RDBK_L] = active_buf;
8611 } else if (mipi_id == RKCIF_STREAM_MIPI_ID1) {
8612 if (cif_dev->rdbk_buf[RDBK_M]) {
8613 v4l2_err(&cif_dev->v4l2_dev,
8614 "multiple %s frame,frm_idx:%d,state:0x%x\n",
8615 cif_dev->hdr.hdr_mode == HDR_X2 ? "short data in hdr_x2" : "medium data in hdr_x3",
8616 stream->frame_idx,
8617 cif_dev->rdbk_buf[RDBK_M]->vb.vb2_buf.state);
8618 cif_dev->rdbk_buf[RDBK_M]->vb.vb2_buf.state = VB2_BUF_STATE_ACTIVE;
8619 rkcif_buf_queue(&cif_dev->rdbk_buf[RDBK_M]->vb.vb2_buf);
8620 cif_dev->rdbk_buf[RDBK_M] = NULL;
8621 }
8622 if (active_buf)
8623 cif_dev->rdbk_buf[RDBK_M] = active_buf;
8624 if (cif_dev->hdr.hdr_mode == HDR_X2)
8625 rkcif_rdbk_frame_end(stream);
8626 } else if (mipi_id == RKCIF_STREAM_MIPI_ID2) {
8627 if (cif_dev->rdbk_buf[RDBK_S]) {
8628 v4l2_err(&cif_dev->v4l2_dev,
8629 "multiple %s frame, frm_idx:%d,state:0x%x\n",
8630 cif_dev->hdr.hdr_mode == HDR_X2 ? "err short data in hdr_x3" : "short data in hdr_x3",
8631 stream->frame_idx,
8632 cif_dev->rdbk_buf[RDBK_S]->vb.vb2_buf.state);
8633 cif_dev->rdbk_buf[RDBK_S]->vb.vb2_buf.state = VB2_BUF_STATE_ACTIVE;
8634 rkcif_buf_queue(&cif_dev->rdbk_buf[RDBK_S]->vb.vb2_buf);
8635 cif_dev->rdbk_buf[RDBK_S] = NULL;
8636 }
8637 if (active_buf)
8638 cif_dev->rdbk_buf[RDBK_S] = active_buf;
8639 if (cif_dev->hdr.hdr_mode == HDR_X3)
8640 rkcif_rdbk_frame_end(stream);
8641 }
8642 spin_unlock_irqrestore(&cif_dev->hdr_lock, flags);
8643 } else {
8644 if (active_buf) {
8645 vb_done->vb2_buf.state = VB2_BUF_STATE_ACTIVE;
8646 rkcif_buf_queue(&vb_done->vb2_buf);
8647 }
8648
8649 v4l2_info(&cif_dev->v4l2_dev,
8650 "warning:hdr runs stream[%d], stream[0]:%s stream[1]:%s stream[2]:%s stream[3]:%s\n",
8651 stream->id,
8652 cif_dev->stream[0].state != RKCIF_STATE_STREAMING ? "stopped" : "running",
8653 cif_dev->stream[1].state != RKCIF_STATE_STREAMING ? "stopped" : "running",
8654 cif_dev->stream[2].state != RKCIF_STATE_STREAMING ? "stopped" : "running",
8655 cif_dev->stream[3].state != RKCIF_STATE_STREAMING ? "stopped" : "running");
8656 }
8657 }
8658
8659 }
8660
rkcif_line_wake_up(struct rkcif_stream * stream,int mipi_id)8661 static void rkcif_line_wake_up(struct rkcif_stream *stream, int mipi_id)
8662 {
8663 u32 mode;
8664 struct rkcif_buffer *active_buf = NULL;
8665 int ret = 0;
8666
8667 mode = stream->line_int_cnt % 2;
8668 if (mode) {
8669 if (stream->curr_buf)
8670 active_buf = stream->curr_buf;
8671 } else {
8672 if (stream->next_buf)
8673 active_buf = stream->next_buf;
8674 }
8675
8676 if (stream->stopping) {
8677 stream->is_can_stop = true;
8678 return;
8679 }
8680 ret = rkcif_get_new_buffer_wake_up_mode(stream);
8681 if (ret)
8682 return;
8683 rkcif_buf_done_prepare(stream, active_buf, mipi_id, mode);
8684 }
8685
rkcif_store_last_buf_for_online(struct rkcif_stream * stream,struct rkcif_rx_buffer * buf)8686 static void rkcif_store_last_buf_for_online(struct rkcif_stream *stream,
8687 struct rkcif_rx_buffer *buf)
8688 {
8689 struct rkcif_device *dev = stream->cifdev;
8690 struct v4l2_mbus_config *mbus_cfg = &dev->active_sensor->mbus;
8691 u32 frm0_addr_y, frm1_addr_y;
8692
8693 INIT_LIST_HEAD(&stream->rx_buf_head);
8694 stream->curr_buf_toisp = buf;
8695 stream->next_buf_toisp = buf;
8696 if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY ||
8697 mbus_cfg->type == V4L2_MBUS_CSI2_CPHY ||
8698 mbus_cfg->type == V4L2_MBUS_CCP2) {
8699 frm0_addr_y = get_reg_index_of_frm0_y_addr(stream->id);
8700 frm1_addr_y = get_reg_index_of_frm1_y_addr(stream->id);
8701 } else {
8702 frm0_addr_y = get_dvp_reg_index_of_frm0_y_addr(stream->id);
8703 frm1_addr_y = get_dvp_reg_index_of_frm1_y_addr(stream->id);
8704 }
8705 rkcif_write_register(dev, frm0_addr_y,
8706 buf->dummy.dma_addr);
8707 rkcif_write_register(dev, frm1_addr_y,
8708 buf->dummy.dma_addr);
8709 }
8710
rkcif_release_unnecessary_buf_for_online(struct rkcif_stream * stream,struct rkcif_rx_buffer * buf)8711 static void rkcif_release_unnecessary_buf_for_online(struct rkcif_stream *stream,
8712 struct rkcif_rx_buffer *buf)
8713 {
8714 struct rkcif_device *dev = stream->cifdev;
8715 struct sditf_priv *priv = dev->sditf[0];
8716 struct rkcif_rx_buffer *rx_buf = NULL;
8717 unsigned long flags;
8718 int i = 0;
8719
8720 spin_lock_irqsave(&priv->cif_dev->buffree_lock, flags);
8721 for (i = 0; i < priv->buf_num; i++) {
8722 rx_buf = &stream->rx_buf[i];
8723 if (rx_buf && (!rx_buf->dummy.is_free) && rx_buf != buf) {
8724 list_add_tail(&rx_buf->list_free, &priv->buf_free_list);
8725 stream->total_buf_num--;
8726 }
8727 }
8728 spin_unlock_irqrestore(&priv->cif_dev->buffree_lock, flags);
8729 schedule_work(&priv->buffree_work.work);
8730 }
8731
rkcif_line_wake_up_rdbk(struct rkcif_stream * stream,int mipi_id)8732 static void rkcif_line_wake_up_rdbk(struct rkcif_stream *stream, int mipi_id)
8733 {
8734 u32 mode;
8735 struct rkcif_rx_buffer *active_buf = NULL;
8736 struct sditf_priv *priv = NULL;
8737 unsigned long flags;
8738 int ret = 0;
8739
8740 mode = stream->line_int_cnt % 2;
8741 if (mode) {
8742 if (stream->curr_buf_toisp)
8743 active_buf = stream->curr_buf_toisp;
8744 stream->frame_phase = CIF_CSI_FRAME0_READY;
8745 } else {
8746 if (stream->next_buf_toisp)
8747 active_buf = stream->next_buf_toisp;
8748 stream->frame_phase = CIF_CSI_FRAME1_READY;
8749 }
8750
8751 if (!active_buf) {
8752 v4l2_err(&stream->cifdev->v4l2_dev,
8753 "err buffer state in %s\n",
8754 __func__);
8755 return;
8756 }
8757
8758 if (stream->stopping) {
8759 stream->is_can_stop = true;
8760 return;
8761 }
8762 ret = rkcif_get_new_buffer_wake_up_mode_rdbk(stream);
8763 v4l2_dbg(3, rkcif_debug, &stream->cifdev->v4l2_dev,
8764 "%d frame_idx %d, last_rx_buf_idx %d cur dma buf %x\n",
8765 __LINE__, stream->frame_idx, stream->last_rx_buf_idx,
8766 (u32)active_buf->dummy.dma_addr);
8767 if (!ret) {
8768 priv = stream->cifdev->sditf[0];
8769 if (stream->cur_stream_mode & RKCIF_STREAM_MODE_TOISP_RDBK) {
8770 spin_lock_irqsave(&stream->vbq_lock, flags);
8771 if (stream->cifdev->is_thunderboot &&
8772 (stream->frame_idx - 1) == stream->last_rx_buf_idx &&
8773 stream->cifdev->is_rdbk_to_online) {
8774 stream->cur_stream_mode &= ~RKCIF_STREAM_MODE_TOISP_RDBK;
8775 stream->cur_stream_mode |= RKCIF_STREAM_MODE_TOISP;
8776 stream->cifdev->wait_line = 0;
8777 stream->is_line_wake_up = false;
8778 if (stream->cifdev->hdr.hdr_mode == NO_HDR ||
8779 (priv->hdr_cfg.hdr_mode == HDR_X2 && stream->id == 1) ||
8780 (priv->hdr_cfg.hdr_mode == HDR_X3 && stream->id == 2)) {
8781 stream->to_stop_dma = RKCIF_DMAEN_BY_ISP;
8782 rkcif_stop_dma_capture(stream);
8783 }
8784 active_buf->dbufs.is_switch = true;
8785 if ((priv->hdr_cfg.hdr_mode == HDR_X2 && stream->id != 1) ||
8786 (priv->hdr_cfg.hdr_mode == HDR_X3 && stream->id != 2)) {
8787 rkcif_store_last_buf_for_online(stream, active_buf);
8788 stream->is_change_toisp = true;
8789 }
8790 }
8791 spin_unlock_irqrestore(&stream->vbq_lock, flags);
8792 active_buf->dbufs.sequence = stream->frame_idx - 1;
8793 active_buf->dbufs.timestamp = stream->readout.fs_timestamp;
8794 active_buf->fe_timestamp = ktime_get_ns();
8795 stream->last_frame_idx = stream->frame_idx;
8796 if (stream->cifdev->hdr.hdr_mode == NO_HDR) {
8797 rkcif_s_rx_buffer(stream->cifdev, &active_buf->dbufs);
8798 if (stream->cifdev->is_support_tools && stream->tools_vdev)
8799 rkcif_rdbk_with_tools(stream, active_buf);
8800 } else {
8801 rkcif_rdbk_frame_end_toisp(stream, active_buf);
8802 }
8803 }
8804 }
8805 }
8806
rkcif_deal_readout_time(struct rkcif_stream * stream)8807 static void rkcif_deal_readout_time(struct rkcif_stream *stream)
8808 {
8809 struct rkcif_device *cif_dev = stream->cifdev;
8810 struct rkcif_stream *detect_stream = &cif_dev->stream[0];
8811 unsigned long flags;
8812
8813 spin_lock_irqsave(&stream->fps_lock, flags);
8814 stream->readout.fe_timestamp = ktime_get_ns();
8815
8816 if (cif_dev->inf_id == RKCIF_DVP) {
8817 spin_unlock_irqrestore(&stream->fps_lock, flags);
8818 return;
8819 }
8820
8821 if (stream->id == RKCIF_STREAM_MIPI_ID0)
8822 detect_stream->readout.readout_time = stream->readout.fe_timestamp - stream->readout.fs_timestamp;
8823
8824 if ((cif_dev->hdr.hdr_mode == NO_HDR || cif_dev->hdr.hdr_mode == HDR_COMPR) &&
8825 (stream->id == RKCIF_STREAM_MIPI_ID0)) {
8826 detect_stream->readout.early_time = stream->readout.fe_timestamp - stream->readout.wk_timestamp;
8827
8828 } else if ((cif_dev->hdr.hdr_mode == HDR_X2) && (stream->id == RKCIF_STREAM_MIPI_ID1)) {
8829 detect_stream->readout.early_time = stream->readout.fe_timestamp - stream->readout.wk_timestamp;
8830 detect_stream->readout.total_time = stream->readout.fe_timestamp - detect_stream->readout.fe_timestamp;
8831 detect_stream->readout.total_time += detect_stream->readout.readout_time;
8832 } else if ((cif_dev->hdr.hdr_mode == HDR_X3) && (stream->id == RKCIF_STREAM_MIPI_ID2)) {
8833 detect_stream->readout.early_time = stream->readout.fe_timestamp - stream->readout.wk_timestamp;
8834 detect_stream->readout.total_time = stream->readout.fe_timestamp - detect_stream->readout.fe_timestamp;
8835 detect_stream->readout.total_time += detect_stream->readout.readout_time;
8836 }
8837 if (!stream->is_line_wake_up)
8838 detect_stream->readout.early_time = 0;
8839 spin_unlock_irqrestore(&stream->fps_lock, flags);
8840 }
8841
rkcif_update_stream(struct rkcif_device * cif_dev,struct rkcif_stream * stream,int mipi_id)8842 static void rkcif_update_stream(struct rkcif_device *cif_dev,
8843 struct rkcif_stream *stream,
8844 int mipi_id)
8845 {
8846 struct rkcif_buffer *active_buf = NULL;
8847 unsigned long flags;
8848 int ret = 0;
8849
8850 if (stream->frame_phase == (CIF_CSI_FRAME0_READY | CIF_CSI_FRAME1_READY)) {
8851 cif_dev->err_state |= (RKCIF_ERR_ID0_TRIG_SIMULT << stream->id);
8852 cif_dev->irq_stats.trig_simult_cnt[stream->id]++;
8853 return;
8854 }
8855 if (!stream->is_line_wake_up) {
8856
8857 spin_lock_irqsave(&stream->fps_lock, flags);
8858 if (stream->frame_phase & CIF_CSI_FRAME0_READY) {
8859 if (stream->curr_buf)
8860 active_buf = stream->curr_buf;
8861 stream->fps_stats.frm0_timestamp = ktime_get_ns();
8862 } else if (stream->frame_phase & CIF_CSI_FRAME1_READY) {
8863 if (stream->next_buf)
8864 active_buf = stream->next_buf;
8865 stream->fps_stats.frm1_timestamp = ktime_get_ns();
8866 }
8867 spin_unlock_irqrestore(&stream->fps_lock, flags);
8868 }
8869
8870 rkcif_deal_readout_time(stream);
8871
8872 if (!stream->is_line_wake_up) {
8873 ret = rkcif_assign_new_buffer_pingpong(stream,
8874 RKCIF_YUV_ADDR_STATE_UPDATE,
8875 mipi_id);
8876 if (ret && cif_dev->chip_id < CHIP_RK3588_CIF)
8877 return;
8878 } else {
8879 ret = rkcif_update_new_buffer_wake_up_mode(stream);
8880 if (ret && cif_dev->chip_id < CHIP_RK3588_CIF)
8881 return;
8882 }
8883 if (!stream->is_line_wake_up && stream->dma_en & RKCIF_DMAEN_BY_VICAP)
8884 rkcif_buf_done_prepare(stream, active_buf, mipi_id, 0);
8885
8886 if (cif_dev->chip_id == CHIP_RV1126_CIF ||
8887 cif_dev->chip_id == CHIP_RV1126_CIF_LITE ||
8888 cif_dev->chip_id == CHIP_RK3568_CIF)
8889 rkcif_luma_isr(&cif_dev->luma_vdev, mipi_id, cif_dev->stream[0].frame_idx - 1);
8890 }
8891
rkcif_update_stream_toisp(struct rkcif_device * cif_dev,struct rkcif_stream * stream,int mipi_id)8892 static void rkcif_update_stream_toisp(struct rkcif_device *cif_dev,
8893 struct rkcif_stream *stream,
8894 int mipi_id)
8895 {
8896 if (stream->frame_phase == (CIF_CSI_FRAME0_READY | CIF_CSI_FRAME1_READY)) {
8897
8898 v4l2_err(&cif_dev->v4l2_dev, "stream[%d], frm0/frm1 end simultaneously,frm id:%d\n",
8899 stream->id, stream->frame_idx);
8900 return;
8901 }
8902
8903 spin_lock(&stream->fps_lock);
8904 if (stream->frame_phase & CIF_CSI_FRAME0_READY)
8905 stream->fps_stats.frm0_timestamp = ktime_get_ns();
8906 else if (stream->frame_phase & CIF_CSI_FRAME1_READY)
8907 stream->fps_stats.frm1_timestamp = ktime_get_ns();
8908 spin_unlock(&stream->fps_lock);
8909
8910 if (cif_dev->inf_id == RKCIF_MIPI_LVDS)
8911 rkcif_deal_readout_time(stream);
8912
8913 if (!stream->is_line_wake_up)
8914 rkcif_assign_new_buffer_pingpong_toisp(stream,
8915 RKCIF_YUV_ADDR_STATE_UPDATE,
8916 mipi_id);
8917 }
8918
rkcif_update_stream_rockit(struct rkcif_device * cif_dev,struct rkcif_stream * stream,int mipi_id)8919 static void rkcif_update_stream_rockit(struct rkcif_device *cif_dev,
8920 struct rkcif_stream *stream,
8921 int mipi_id)
8922 {
8923 struct rkcif_buffer *active_buf = NULL;
8924 unsigned long flags;
8925 int ret = 0;
8926
8927 if (stream->frame_phase == (CIF_CSI_FRAME0_READY | CIF_CSI_FRAME1_READY)) {
8928
8929 v4l2_err(&cif_dev->v4l2_dev, "stream[%d], frm0/frm1 end simultaneously,frm id:%d\n",
8930 stream->id, stream->frame_idx);
8931 return;
8932 }
8933 if (!stream->is_line_wake_up) {
8934
8935 spin_lock_irqsave(&stream->fps_lock, flags);
8936 if (stream->frame_phase & CIF_CSI_FRAME0_READY) {
8937 if (stream->curr_buf_rockit)
8938 active_buf = stream->curr_buf_rockit;
8939 stream->fps_stats.frm0_timestamp = ktime_get_ns();
8940 } else if (stream->frame_phase & CIF_CSI_FRAME1_READY) {
8941 if (stream->next_buf_rockit)
8942 active_buf = stream->next_buf_rockit;
8943 stream->fps_stats.frm1_timestamp = ktime_get_ns();
8944 }
8945 spin_unlock_irqrestore(&stream->fps_lock, flags);
8946 }
8947
8948 if (cif_dev->inf_id == RKCIF_MIPI_LVDS)
8949 rkcif_deal_readout_time(stream);
8950
8951 ret = rkcif_assign_new_buffer_pingpong_rockit(stream,
8952 RKCIF_YUV_ADDR_STATE_UPDATE,
8953 mipi_id);
8954 if (ret)
8955 return;
8956
8957 if (active_buf) {
8958 active_buf->vb.vb2_buf.timestamp = stream->readout.fs_timestamp;
8959 active_buf->vb.sequence = stream->frame_idx - 1;
8960 rkcif_rockit_buf_done(stream, active_buf);
8961 }
8962 }
8963
rkcif_get_sof(struct rkcif_device * cif_dev)8964 static u32 rkcif_get_sof(struct rkcif_device *cif_dev)
8965 {
8966 u32 val = 0x0;
8967 struct rkcif_sensor_info *sensor = cif_dev->active_sensor;
8968 struct csi2_dev *csi;
8969
8970 if (sensor->mbus.type == V4L2_MBUS_CSI2_DPHY ||
8971 sensor->mbus.type == V4L2_MBUS_CSI2_CPHY) {
8972 csi = container_of(sensor->sd, struct csi2_dev, sd);
8973 val = rkcif_csi2_get_sof(csi);
8974 } else if (sensor->mbus.type == V4L2_MBUS_CCP2) {
8975 val = rkcif_lvds_get_sof(cif_dev);
8976 } else if (sensor->mbus.type == V4L2_MBUS_PARALLEL ||
8977 sensor->mbus.type == V4L2_MBUS_BT656) {
8978 val = rkcif_dvp_get_sof(cif_dev);
8979 }
8980 return val;
8981 }
8982
rkcif_set_sof(struct rkcif_device * cif_dev,u32 seq)8983 static void rkcif_set_sof(struct rkcif_device *cif_dev, u32 seq)
8984 {
8985 struct rkcif_sensor_info *sensor = cif_dev->active_sensor;
8986 struct csi2_dev *csi;
8987
8988 if (sensor->mbus.type == V4L2_MBUS_CSI2_DPHY ||
8989 sensor->mbus.type == V4L2_MBUS_CSI2_CPHY) {
8990 csi = container_of(sensor->sd, struct csi2_dev, sd);
8991 rkcif_csi2_set_sof(csi, seq);
8992 } else if (sensor->mbus.type == V4L2_MBUS_CCP2) {
8993 rkcif_lvds_set_sof(cif_dev, seq);
8994 } else if (sensor->mbus.type == V4L2_MBUS_PARALLEL ||
8995 sensor->mbus.type == V4L2_MBUS_BT656) {
8996 rkcif_dvp_set_sof(cif_dev, seq);
8997 }
8998 }
8999
rkcif_do_reset_work(struct rkcif_device * cif_dev,enum rkmodule_reset_src reset_src)9000 static int rkcif_do_reset_work(struct rkcif_device *cif_dev,
9001 enum rkmodule_reset_src reset_src)
9002 {
9003 struct rkcif_pipeline *p = &cif_dev->pipe;
9004 struct rkcif_stream *stream = NULL;
9005 struct rkcif_stream *resume_stream[RKCIF_MAX_STREAM_MIPI] = { NULL };
9006 struct rkcif_sensor_info *terminal_sensor = &cif_dev->terminal_sensor;
9007 struct rkcif_resume_info *resume_info = &cif_dev->reset_work.resume_info;
9008 struct rkcif_timer *timer = &cif_dev->reset_watchdog_timer;
9009 struct sditf_priv *priv = cif_dev->sditf[0];
9010 int i, j, ret = 0;
9011 u32 on, sof_cnt;
9012 int capture_mode = 0;
9013
9014 mutex_lock(&cif_dev->stream_lock);
9015 if (cif_dev->reset_work_cancel) {
9016 ret = 0;
9017 goto unlock_stream;
9018 }
9019 v4l2_dbg(1, rkcif_debug, &cif_dev->v4l2_dev, "do rkcif reset\n");
9020
9021 for (i = 0, j = 0; i < RKCIF_MAX_STREAM_MIPI; i++) {
9022 stream = &cif_dev->stream[i];
9023
9024 if (stream->state == RKCIF_STATE_STREAMING) {
9025
9026 v4l2_dbg(1, rkcif_debug, &cif_dev->v4l2_dev,
9027 "stream[%d] stopping\n", stream->id);
9028
9029 rkcif_stream_stop(stream);
9030
9031 if (stream->id == RKCIF_STREAM_MIPI_ID0) {
9032 sof_cnt = rkcif_get_sof(cif_dev);
9033 v4l2_dbg(1, rkcif_debug, &cif_dev->v4l2_dev,
9034 "%s: stream[%d] sync frmid & csi_sof, frm_id:%d, csi_sof:%d\n",
9035 __func__,
9036 stream->id,
9037 stream->frame_idx,
9038 sof_cnt);
9039
9040 resume_info->frm_sync_seq = stream->frame_idx;
9041 }
9042
9043 stream->state = RKCIF_STATE_RESET_IN_STREAMING;
9044 stream->is_fs_fe_not_paired = false;
9045 stream->fs_cnt_in_single_frame = 0;
9046 resume_stream[j] = stream;
9047 j += 1;
9048
9049 v4l2_dbg(1, rkcif_debug, &cif_dev->v4l2_dev,
9050 "%s stop stream[%d] in streaming, frm_id:%d, csi_sof:%d\n",
9051 __func__, stream->id, stream->frame_idx, rkcif_get_sof(cif_dev));
9052
9053 }
9054 }
9055
9056 on = 0;
9057 for (i = 0; i < p->num_subdevs; i++) {
9058
9059 if (p->subdevs[i] == terminal_sensor->sd) {
9060
9061 if (reset_src != RKCIF_RESET_SRC_ERR_APP) {
9062 ret = v4l2_subdev_call(p->subdevs[i], core, ioctl,
9063 RKMODULE_SET_QUICK_STREAM, &on);
9064 if (ret)
9065 v4l2_dbg(1, rkcif_debug, &cif_dev->v4l2_dev,
9066 "quick stream off subdev:%s failed\n",
9067 p->subdevs[i]->name);
9068 }
9069 } else {
9070 ret = v4l2_subdev_call(p->subdevs[i], video, s_stream, on);
9071 }
9072 if (ret)
9073 v4l2_dbg(1, rkcif_debug, &cif_dev->v4l2_dev,
9074 "%s:stream %s subdev:%s failed\n",
9075 __func__, on ? "on" : "off", p->subdevs[i]->name);
9076 }
9077
9078 if (priv && priv->is_combine_mode && cif_dev->sditf_cnt <= RKCIF_MAX_SDITF) {
9079 for (i = 0; i < cif_dev->sditf_cnt; i++) {
9080 if (cif_dev->sditf[i] && cif_dev->sditf[i]->sensor_sd)
9081 ret = v4l2_subdev_call(cif_dev->sditf[i]->sensor_sd, core, ioctl,
9082 RKMODULE_SET_QUICK_STREAM, &on);
9083 }
9084 }
9085
9086 rockchip_clear_system_status(SYS_STATUS_CIF0);
9087
9088 if (cif_dev->chip_id >= CHIP_RK3588_CIF) {
9089 rkcif_do_soft_reset(cif_dev);
9090 } else {
9091
9092 rkcif_do_cru_reset(cif_dev);
9093
9094 rkcif_disable_sys_clk(cif_dev->hw_dev);
9095
9096 udelay(5);
9097
9098 ret = rkcif_enable_sys_clk(cif_dev->hw_dev);
9099
9100 if (ret < 0) {
9101 v4l2_err(&cif_dev->v4l2_dev, "%s:resume cif clk failed\n", __func__);
9102 goto unlock_stream;
9103 }
9104 }
9105
9106 for (i = 0; i < j; i++) {
9107 stream = resume_stream[i];
9108 stream->fs_cnt_in_single_frame = 0;
9109 if (stream->cif_fmt_in->field == V4L2_FIELD_INTERLACED) {
9110 if (stream->curr_buf == stream->next_buf) {
9111 if (stream->curr_buf)
9112 list_add_tail(&stream->curr_buf->queue, &stream->buf_head);
9113 } else {
9114 if (stream->curr_buf)
9115 list_add_tail(&stream->curr_buf->queue, &stream->buf_head);
9116 if (stream->next_buf)
9117 list_add_tail(&stream->next_buf->queue, &stream->buf_head);
9118 }
9119 stream->curr_buf = NULL;
9120 stream->next_buf = NULL;
9121 }
9122 if (!cif_dev->sditf[0] || cif_dev->sditf[0]->mode.rdbk_mode == RKISP_VICAP_RDBK_AIQ)
9123 capture_mode = RKCIF_STREAM_MODE_CAPTURE;
9124 else {
9125 if (cif_dev->sditf[0]->mode.rdbk_mode == RKISP_VICAP_ONLINE)
9126 capture_mode = RKCIF_STREAM_MODE_TOISP;
9127 else
9128 capture_mode = RKCIF_STREAM_MODE_TOISP_RDBK;
9129 }
9130 if (cif_dev->active_sensor &&
9131 (cif_dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_DPHY ||
9132 cif_dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_CPHY ||
9133 cif_dev->active_sensor->mbus.type == V4L2_MBUS_CCP2))
9134 ret = rkcif_csi_stream_start(stream, capture_mode);
9135 else
9136 ret = rkcif_stream_start(stream, capture_mode);
9137 if (ret) {
9138 v4l2_err(&cif_dev->v4l2_dev, "%s:resume stream[%d] failed\n",
9139 __func__, stream->id);
9140 goto unlock_stream;
9141 }
9142
9143 v4l2_dbg(1, rkcif_debug, &cif_dev->v4l2_dev,
9144 "resume stream[%d], frm_idx:%d, csi_sof:%d\n",
9145 stream->id, stream->frame_idx,
9146 rkcif_get_sof(cif_dev));
9147 }
9148
9149 rockchip_set_system_status(SYS_STATUS_CIF0);
9150
9151 on = 1;
9152 for (i = 0; i < p->num_subdevs; i++) {
9153
9154 if (p->subdevs[i] == terminal_sensor->sd) {
9155
9156 rkcif_set_sof(cif_dev, resume_info->frm_sync_seq);
9157
9158 if (reset_src != RKCIF_RESET_SRC_ERR_APP) {
9159 ret = v4l2_subdev_call(p->subdevs[i], core, ioctl,
9160 RKMODULE_SET_QUICK_STREAM, &on);
9161 if (ret)
9162 v4l2_err(&cif_dev->v4l2_dev,
9163 "quick stream on subdev:%s failed\n",
9164 p->subdevs[i]->name);
9165 }
9166 } else {
9167 if (p->subdevs[i] == terminal_sensor->sd)
9168 rkcif_set_sof(cif_dev, resume_info->frm_sync_seq);
9169
9170 ret = v4l2_subdev_call(p->subdevs[i], video, s_stream, on);
9171 }
9172
9173 if (ret)
9174 v4l2_err(&cif_dev->v4l2_dev, "reset subdev:%s failed\n",
9175 p->subdevs[i]->name);
9176 }
9177
9178 if (priv && priv->is_combine_mode && cif_dev->sditf_cnt <= RKCIF_MAX_SDITF) {
9179 for (i = 0; i < cif_dev->sditf_cnt; i++) {
9180 if (cif_dev->sditf[i] && cif_dev->sditf[i]->sensor_sd)
9181 v4l2_subdev_call(cif_dev->sditf[i]->sensor_sd, core, ioctl,
9182 RKMODULE_SET_QUICK_STREAM, &on);
9183 }
9184 }
9185
9186 if (cif_dev->chip_id < CHIP_RK3588_CIF)
9187 rkcif_start_luma(&cif_dev->luma_vdev,
9188 cif_dev->stream[RKCIF_STREAM_MIPI_ID0].cif_fmt_in);
9189
9190 timer->csi2_err_triggered_cnt = 0;
9191 rkcif_monitor_reset_event(cif_dev);
9192
9193 v4l2_dbg(1, rkcif_debug, &cif_dev->v4l2_dev, "do rkcif reset successfully!\n");
9194 mutex_unlock(&cif_dev->stream_lock);
9195 return 0;
9196
9197 unlock_stream:
9198 mutex_unlock(&cif_dev->stream_lock);
9199 return ret;
9200 }
9201
rkcif_reset_work(struct work_struct * work)9202 void rkcif_reset_work(struct work_struct *work)
9203 {
9204 struct rkcif_work_struct *reset_work = container_of(work,
9205 struct rkcif_work_struct,
9206 work);
9207 struct rkcif_device *dev = container_of(reset_work,
9208 struct rkcif_device,
9209 reset_work);
9210 int ret;
9211
9212 ret = rkcif_do_reset_work(dev, reset_work->reset_src);
9213 if (ret)
9214 v4l2_info(&dev->v4l2_dev, "do reset work failed!\n");
9215 }
9216
rkcif_is_reduced_frame_rate(struct rkcif_device * dev)9217 static bool rkcif_is_reduced_frame_rate(struct rkcif_device *dev)
9218 {
9219 struct rkcif_timer *timer = &dev->reset_watchdog_timer;
9220 struct rkcif_stream *stream = &dev->stream[RKCIF_STREAM_MIPI_ID0];
9221 struct v4l2_rect *raw_rect = &dev->terminal_sensor.raw_rect;
9222 u64 fps, timestamp0, timestamp1, diff_time;
9223 unsigned long fps_flags;
9224 unsigned int deviation = 1;
9225 bool is_reduced = false;
9226 u64 cur_time = 0;
9227 u64 time_distance = 0;
9228
9229 spin_lock_irqsave(&stream->fps_lock, fps_flags);
9230 timestamp0 = stream->fps_stats.frm0_timestamp;
9231 timestamp1 = stream->fps_stats.frm1_timestamp;
9232 spin_unlock_irqrestore(&stream->fps_lock, fps_flags);
9233
9234 fps = timestamp0 > timestamp1 ?
9235 timestamp0 - timestamp1 : timestamp1 - timestamp0;
9236 fps = div_u64(fps, 1000);
9237 diff_time = fps > timer->frame_end_cycle_us ?
9238 fps - timer->frame_end_cycle_us : 0;
9239 deviation = DIV_ROUND_UP(timer->vts, 100);
9240
9241 v4l2_dbg(3, rkcif_debug, &dev->v4l2_dev, "diff_time:%lld,devi_t:%ld,devi_h:%d\n",
9242 diff_time, timer->line_end_cycle * deviation, deviation);
9243
9244 cur_time = ktime_get_ns();
9245 time_distance = timestamp0 > timestamp1 ?
9246 cur_time - timestamp0 : cur_time - timestamp1;
9247 time_distance = div_u64(time_distance, 1000);
9248 if (time_distance > fps * 2)
9249 return false;
9250
9251 if (diff_time > timer->line_end_cycle * deviation) {
9252 s32 vblank = 0;
9253 unsigned int vts;
9254
9255 is_reduced = true;
9256 vblank = rkcif_get_sensor_vblank(dev);
9257 vts = vblank + timer->raw_height;
9258
9259 v4l2_dbg(3, rkcif_debug, &dev->v4l2_dev, "old vts:%d,new vts:%d\n", timer->vts, vts);
9260
9261 v4l2_dbg(3, rkcif_debug, &dev->v4l2_dev,
9262 "reduce frame rate,vblank:%d, height(raw output):%d, fps:%lld, frm_end_t:%ld, line_t:%ld, diff:%lld\n",
9263 rkcif_get_sensor_vblank(dev),
9264 raw_rect->height,
9265 fps,
9266 timer->frame_end_cycle_us,
9267 timer->line_end_cycle,
9268 diff_time);
9269
9270 timer->vts = vts;
9271 timer->frame_end_cycle_us = fps;
9272 timer->line_end_cycle = div_u64(timer->frame_end_cycle_us, timer->vts);
9273 } else {
9274 is_reduced = false;
9275 }
9276
9277 timer->frame_end_cycle_us = fps;
9278
9279 fps = div_u64(fps, 1000);
9280 fps = fps * timer->frm_num_of_monitor_cycle;
9281 timer->cycle = msecs_to_jiffies(fps);
9282 timer->timer.expires = jiffies + timer->cycle;
9283
9284 return is_reduced;
9285
9286 }
9287
rkcif_dvp_event_reset_pipe(struct rkcif_device * dev,int reset_src)9288 static void rkcif_dvp_event_reset_pipe(struct rkcif_device *dev, int reset_src)
9289 {
9290 struct rkcif_dvp_sof_subdev *subdev = &dev->dvp_sof_subdev;
9291
9292 if (subdev) {
9293 struct v4l2_event event = {
9294 .type = V4L2_EVENT_RESET_DEV,
9295 .reserved[0] = reset_src,
9296 };
9297 v4l2_event_queue(subdev->sd.devnode, &event);
9298 }
9299 }
9300
rkcif_lvds_event_reset_pipe(struct rkcif_device * dev,int reset_src)9301 static void rkcif_lvds_event_reset_pipe(struct rkcif_device *dev, int reset_src)
9302 {
9303 struct rkcif_lvds_subdev *subdev = &dev->lvds_subdev;
9304
9305 if (subdev) {
9306 struct v4l2_event event = {
9307 .type = V4L2_EVENT_RESET_DEV,
9308 .reserved[0] = reset_src,
9309 };
9310 v4l2_event_queue(subdev->sd.devnode, &event);
9311 }
9312 }
9313
rkcif_send_reset_event(struct rkcif_device * cif_dev,int reset_src)9314 static void rkcif_send_reset_event(struct rkcif_device *cif_dev, int reset_src)
9315 {
9316 struct v4l2_mbus_config *mbus = &cif_dev->active_sensor->mbus;
9317 struct csi2_dev *csi;
9318
9319 if (mbus->type == V4L2_MBUS_CSI2_DPHY ||
9320 mbus->type == V4L2_MBUS_CSI2_CPHY) {
9321 csi = container_of(cif_dev->active_sensor->sd, struct csi2_dev, sd);
9322 rkcif_csi2_event_reset_pipe(csi, reset_src);
9323 } else if (mbus->type == V4L2_MBUS_CCP2) {
9324 rkcif_lvds_event_reset_pipe(cif_dev, reset_src);
9325 } else {
9326 rkcif_dvp_event_reset_pipe(cif_dev, reset_src);
9327 }
9328 v4l2_dbg(3, rkcif_debug, &cif_dev->v4l2_dev,
9329 "send reset event,bus type 0x%x\n",
9330 mbus->type);
9331 }
9332
rkcif_init_reset_work(struct rkcif_timer * timer)9333 static void rkcif_init_reset_work(struct rkcif_timer *timer)
9334 {
9335 struct rkcif_device *dev = container_of(timer,
9336 struct rkcif_device,
9337 reset_watchdog_timer);
9338 struct rkcif_stream *stream = NULL;
9339 unsigned long flags;
9340 int i = 0;
9341
9342 v4l2_info(&dev->v4l2_dev,
9343 "do reset work schedule, run_cnt:%d, reset source:%d\n",
9344 timer->run_cnt, timer->reset_src);
9345
9346 spin_lock_irqsave(&timer->timer_lock, flags);
9347 timer->is_running = false;
9348 timer->is_triggered = false;
9349 timer->csi2_err_cnt_odd = 0;
9350 timer->csi2_err_cnt_even = 0;
9351 timer->csi2_err_fs_fe_cnt = 0;
9352 timer->notifer_called_cnt = 0;
9353 for (i = 0; i < dev->num_channels; i++) {
9354 stream = &dev->stream[i];
9355 if (stream->state == RKCIF_STATE_STREAMING)
9356 timer->last_buf_wakeup_cnt[stream->id] = stream->buf_wake_up_cnt;
9357 }
9358 spin_unlock_irqrestore(&timer->timer_lock, flags);
9359 if (timer->is_ctrl_by_user) {
9360 rkcif_send_reset_event(dev, timer->reset_src);
9361 } else {
9362 if (!schedule_work(&dev->reset_work.work))
9363 v4l2_info(&dev->v4l2_dev,
9364 "schedule reset work failed\n");
9365 dev->reset_work.reset_src = timer->reset_src;
9366 }
9367 }
9368
rkcif_detect_reset_event(struct rkcif_stream * stream,struct rkcif_timer * timer,int check_cnt,bool * is_mod_timer)9369 static int rkcif_detect_reset_event(struct rkcif_stream *stream,
9370 struct rkcif_timer *timer,
9371 int check_cnt,
9372 bool *is_mod_timer)
9373 {
9374 struct rkcif_device *dev = stream->cifdev;
9375 struct rkcif_sensor_info *terminal_sensor = &dev->terminal_sensor;
9376 unsigned long flags;
9377 int ret, is_reset = 0;
9378 struct rkmodule_vicap_reset_info rst_info;
9379
9380 if (timer->last_buf_wakeup_cnt[stream->id] < stream->buf_wake_up_cnt &&
9381 check_cnt == 0) {
9382
9383 v4l2_dbg(1, rkcif_debug, &dev->v4l2_dev,
9384 "info: frame end still update(%d, %d) in detecting cnt:%d, mode:%d\n",
9385 timer->last_buf_wakeup_cnt[stream->id], stream->frame_idx,
9386 timer->run_cnt, timer->monitor_mode);
9387
9388 timer->last_buf_wakeup_cnt[stream->id] = stream->buf_wake_up_cnt;
9389
9390 if (stream->frame_idx > 2)
9391 rkcif_is_reduced_frame_rate(dev);
9392
9393 if (timer->monitor_mode == RKCIF_MONITOR_MODE_HOTPLUG) {
9394 ret = v4l2_subdev_call(terminal_sensor->sd,
9395 core, ioctl,
9396 RKMODULE_GET_VICAP_RST_INFO,
9397 &rst_info);
9398 if (ret)
9399 is_reset = 0;
9400 else
9401 is_reset = rst_info.is_reset;
9402 rst_info.is_reset = 0;
9403 if (is_reset)
9404 timer->reset_src = RKCIF_RESET_SRC_ERR_HOTPLUG;
9405 v4l2_subdev_call(terminal_sensor->sd, core, ioctl,
9406 RKMODULE_SET_VICAP_RST_INFO, &rst_info);
9407 if (!is_reset) {
9408 is_reset = rkcif_is_csi2_err_trigger_reset(timer);
9409 if (is_reset)
9410 timer->reset_src = RKCIF_RESET_SRC_ERR_CSI2;
9411 }
9412 } else if (timer->monitor_mode == RKCIF_MONITOR_MODE_CONTINUE) {
9413 is_reset = rkcif_is_csi2_err_trigger_reset(timer);
9414 } else if (timer->monitor_mode == RKCIF_MONITOR_MODE_TRIGGER) {
9415 is_reset = timer->is_csi2_err_occurred;
9416 if (is_reset)
9417 timer->reset_src = RKCIF_RESET_SRC_ERR_CSI2;
9418 timer->is_csi2_err_occurred = false;
9419 }
9420
9421 if (is_reset) {
9422 rkcif_init_reset_work(timer);
9423 return is_reset;
9424 }
9425
9426 if (timer->monitor_mode == RKCIF_MONITOR_MODE_CONTINUE ||
9427 timer->monitor_mode == RKCIF_MONITOR_MODE_HOTPLUG) {
9428 if (timer->run_cnt == timer->max_run_cnt)
9429 timer->run_cnt = 0x0;
9430 *is_mod_timer = true;
9431 } else {
9432 if (timer->run_cnt <= timer->max_run_cnt) {
9433 *is_mod_timer = true;
9434 } else {
9435 spin_lock_irqsave(&timer->timer_lock, flags);
9436 timer->is_triggered = false;
9437 timer->is_running = false;
9438 spin_unlock_irqrestore(&timer->timer_lock, flags);
9439 v4l2_info(&dev->v4l2_dev, "stop reset detecting!\n");
9440 }
9441 }
9442 } else if (timer->last_buf_wakeup_cnt[stream->id] == stream->buf_wake_up_cnt) {
9443
9444 bool is_reduced = false;
9445
9446 if (stream->frame_idx > 2)
9447 is_reduced = rkcif_is_reduced_frame_rate(dev);
9448 else if (timer->run_cnt < 20)
9449 is_reduced = true;
9450
9451 if (is_reduced) {
9452 *is_mod_timer = true;
9453 v4l2_dbg(3, rkcif_debug, &dev->v4l2_dev, "%s fps is reduced\n", __func__);
9454 } else {
9455
9456 v4l2_info(&dev->v4l2_dev,
9457 "do reset work due to frame end is stopped, run_cnt:%d\n",
9458 timer->run_cnt);
9459
9460 timer->reset_src = RKICF_RESET_SRC_ERR_CUTOFF;
9461 rkcif_init_reset_work(timer);
9462 is_reset = true;
9463 }
9464 }
9465
9466 return is_reset;
9467
9468 }
9469
rkcif_reset_watchdog_timer_handler(struct timer_list * t)9470 void rkcif_reset_watchdog_timer_handler(struct timer_list *t)
9471 {
9472 struct rkcif_timer *timer = container_of(t, struct rkcif_timer, timer);
9473 struct rkcif_device *dev = container_of(timer,
9474 struct rkcif_device,
9475 reset_watchdog_timer);
9476 struct rkcif_stream *stream = NULL;
9477 unsigned long flags;
9478 unsigned int i;
9479 int is_reset = 0;
9480 int check_cnt = 0;
9481 bool is_mod_timer = false;
9482
9483 for (i = 0; i < dev->num_channels; i++) {
9484 stream = &dev->stream[i];
9485 if (stream->state == RKCIF_STATE_STREAMING) {
9486 is_reset = rkcif_detect_reset_event(stream,
9487 timer,
9488 check_cnt,
9489 &is_mod_timer);
9490 check_cnt++;
9491 if (is_reset)
9492 break;
9493 }
9494 }
9495 if (!is_reset && is_mod_timer)
9496 mod_timer(&timer->timer, jiffies + timer->cycle);
9497
9498 timer->run_cnt += 1;
9499
9500 if (!check_cnt) {
9501 spin_lock_irqsave(&timer->timer_lock, flags);
9502 timer->is_triggered = false;
9503 timer->is_running = false;
9504 spin_unlock_irqrestore(&timer->timer_lock, flags);
9505
9506 v4l2_info(&dev->v4l2_dev,
9507 "all stream is stopped, stop reset detect!\n");
9508 }
9509 }
9510
rkcif_reset_notifier(struct notifier_block * nb,unsigned long action,void * data)9511 int rkcif_reset_notifier(struct notifier_block *nb,
9512 unsigned long action, void *data)
9513 {
9514 struct rkcif_hw *hw = container_of(nb, struct rkcif_hw, reset_notifier);
9515 struct rkcif_device *dev = NULL;
9516 struct rkcif_timer *timer = NULL;
9517 unsigned long flags, val;
9518 u32 *csi_idx = data;
9519 int i = 0;
9520 bool is_match_dev = false;
9521
9522 for (i = 0; i < hw->dev_num; i++) {
9523 dev = hw->cif_dev[i];
9524 if (*csi_idx == dev->csi_host_idx) {
9525 is_match_dev = true;
9526 break;
9527 }
9528 }
9529 if (!is_match_dev)
9530 return -EINVAL;
9531 timer = &dev->reset_watchdog_timer;
9532 if (timer->is_running) {
9533 val = action & CSI2_ERR_COUNT_ALL_MASK;
9534 spin_lock_irqsave(&timer->csi2_err_lock, flags);
9535 if ((val % timer->csi2_err_ref_cnt) == 0) {
9536 timer->notifer_called_cnt++;
9537 if ((timer->notifer_called_cnt % 2) == 0)
9538 timer->csi2_err_cnt_even = val;
9539 else
9540 timer->csi2_err_cnt_odd = val;
9541 }
9542
9543 timer->csi2_err_fs_fe_cnt = (action & CSI2_ERR_FSFE_MASK) >> 8;
9544 spin_unlock_irqrestore(&timer->csi2_err_lock, flags);
9545 }
9546
9547 return 0;
9548 }
9549
rkcif_modify_line_int(struct rkcif_stream * stream,bool en)9550 static void rkcif_modify_line_int(struct rkcif_stream *stream, bool en)
9551 {
9552 struct rkcif_device *cif_dev = stream->cifdev;
9553 u32 line_intr_en = 0;
9554
9555 if (cif_dev->chip_id >= CHIP_RK3588_CIF)
9556 line_intr_en = CSI_LINE_INTEN_RK3588(stream->id);
9557 else
9558 line_intr_en = CSI_LINE_INTEN(stream->id);
9559 if (en) {
9560 if (cif_dev->wait_line_bak != cif_dev->wait_line) {
9561 cif_dev->wait_line_bak = cif_dev->wait_line;
9562 rkcif_write_register(cif_dev, CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID0_1,
9563 cif_dev->wait_line << 16 | cif_dev->wait_line);
9564 rkcif_write_register(cif_dev, CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID2_3,
9565 cif_dev->wait_line << 16 | cif_dev->wait_line);
9566 }
9567 rkcif_write_register_or(cif_dev, CIF_REG_MIPI_LVDS_INTEN,
9568 line_intr_en);
9569 stream->is_line_inten = true;
9570 } else {
9571 rkcif_write_register_and(cif_dev, CIF_REG_MIPI_LVDS_INTEN,
9572 ~line_intr_en);
9573 }
9574 }
9575
rkcif_detect_wake_up_mode_change(struct rkcif_stream * stream)9576 static void rkcif_detect_wake_up_mode_change(struct rkcif_stream *stream)
9577 {
9578 struct rkcif_device *cif_dev = stream->cifdev;
9579 struct sditf_priv *priv = cif_dev->sditf[0];
9580 bool is_change = false;
9581 int ch = 0;
9582 int i = 0;
9583
9584 if (!priv || priv->mode.rdbk_mode == RKISP_VICAP_ONLINE)
9585 return;
9586
9587 if ((cif_dev->hdr.hdr_mode == NO_HDR || cif_dev->hdr.hdr_mode == HDR_COMPR) &&
9588 stream->id == RKCIF_STREAM_MIPI_ID0) {
9589 if (cif_dev->wait_line != cif_dev->wait_line_cache)
9590 cif_dev->wait_line = cif_dev->wait_line_cache;
9591 } else if (cif_dev->hdr.hdr_mode == HDR_X2 && stream->id == RKCIF_STREAM_MIPI_ID1) {
9592 if (cif_dev->wait_line != cif_dev->wait_line_cache)
9593 cif_dev->wait_line = cif_dev->wait_line_cache;
9594 } else if (cif_dev->hdr.hdr_mode == HDR_X3 && stream->id == RKCIF_STREAM_MIPI_ID2) {
9595 if (cif_dev->wait_line != cif_dev->wait_line_cache)
9596 cif_dev->wait_line = cif_dev->wait_line_cache;
9597 }
9598
9599 if (cif_dev->wait_line && (!stream->is_line_wake_up)) {
9600 is_change = true;
9601 stream->is_line_wake_up = true;
9602 if (stream->frame_phase == CIF_CSI_FRAME0_READY)
9603 stream->line_int_cnt = 1;
9604 else if (stream->frame_phase == CIF_CSI_FRAME1_READY)
9605 stream->line_int_cnt = 0;
9606 if (cif_dev->hdr.hdr_mode == HDR_X2) {
9607 cif_dev->stream[0].is_line_wake_up = true;
9608 cif_dev->stream[0].line_int_cnt = stream->line_int_cnt;
9609 } else if (cif_dev->hdr.hdr_mode == HDR_X3) {
9610 cif_dev->stream[0].is_line_wake_up = true;
9611 cif_dev->stream[1].is_line_wake_up = true;
9612 cif_dev->stream[0].line_int_cnt = stream->line_int_cnt;
9613 cif_dev->stream[1].line_int_cnt = stream->line_int_cnt;
9614 }
9615 } else if ((cif_dev->wait_line == 0) && stream->is_line_wake_up) {
9616 stream->is_line_wake_up = false;
9617 }
9618 if (stream->is_line_wake_up) {
9619 if (is_change) {
9620 if (cif_dev->hdr.hdr_mode == HDR_X2)
9621 ch = 2;
9622 else if (cif_dev->hdr.hdr_mode == HDR_X3)
9623 ch = 3;
9624 else
9625 ch = 1;
9626 for (i = 0; i < ch; i++)
9627 rkcif_modify_line_int(&cif_dev->stream[i], true);
9628 } else {
9629 rkcif_modify_line_int(stream, true);
9630 }
9631 }
9632 }
9633
rkcif_mbus_pixelcode_to_v4l2(u32 pixelcode)9634 u32 rkcif_mbus_pixelcode_to_v4l2(u32 pixelcode)
9635 {
9636 u32 pixelformat;
9637
9638 switch (pixelcode) {
9639 case MEDIA_BUS_FMT_Y8_1X8:
9640 pixelformat = V4L2_PIX_FMT_GREY;
9641 break;
9642 case MEDIA_BUS_FMT_SBGGR8_1X8:
9643 pixelformat = V4L2_PIX_FMT_SBGGR8;
9644 break;
9645 case MEDIA_BUS_FMT_SGBRG8_1X8:
9646 pixelformat = V4L2_PIX_FMT_SGBRG8;
9647 break;
9648 case MEDIA_BUS_FMT_SGRBG8_1X8:
9649 pixelformat = V4L2_PIX_FMT_SGRBG8;
9650 break;
9651 case MEDIA_BUS_FMT_SRGGB8_1X8:
9652 pixelformat = V4L2_PIX_FMT_SRGGB8;
9653 break;
9654 case MEDIA_BUS_FMT_Y10_1X10:
9655 pixelformat = V4L2_PIX_FMT_Y10;
9656 break;
9657 case MEDIA_BUS_FMT_SBGGR10_1X10:
9658 pixelformat = V4L2_PIX_FMT_SBGGR10;
9659 break;
9660 case MEDIA_BUS_FMT_SGBRG10_1X10:
9661 pixelformat = V4L2_PIX_FMT_SGBRG10;
9662 break;
9663 case MEDIA_BUS_FMT_SGRBG10_1X10:
9664 pixelformat = V4L2_PIX_FMT_SGRBG10;
9665 break;
9666 case MEDIA_BUS_FMT_SRGGB10_1X10:
9667 pixelformat = V4L2_PIX_FMT_SRGGB10;
9668 break;
9669 case MEDIA_BUS_FMT_Y12_1X12:
9670 pixelformat = V4L2_PIX_FMT_Y12;
9671 break;
9672 case MEDIA_BUS_FMT_SBGGR12_1X12:
9673 pixelformat = V4L2_PIX_FMT_SBGGR12;
9674 break;
9675 case MEDIA_BUS_FMT_SGBRG12_1X12:
9676 pixelformat = V4L2_PIX_FMT_SGBRG12;
9677 break;
9678 case MEDIA_BUS_FMT_SGRBG12_1X12:
9679 pixelformat = V4L2_PIX_FMT_SGRBG12;
9680 break;
9681 case MEDIA_BUS_FMT_SRGGB12_1X12:
9682 pixelformat = V4L2_PIX_FMT_SRGGB12;
9683 break;
9684 case MEDIA_BUS_FMT_SPD_2X8:
9685 pixelformat = V4l2_PIX_FMT_SPD16;
9686 break;
9687 case MEDIA_BUS_FMT_EBD_1X8:
9688 pixelformat = V4l2_PIX_FMT_EBD8;
9689 break;
9690 default:
9691 pixelformat = V4L2_PIX_FMT_SRGGB10;
9692 }
9693
9694 return pixelformat;
9695 }
9696
rkcif_set_default_fmt(struct rkcif_device * cif_dev)9697 void rkcif_set_default_fmt(struct rkcif_device *cif_dev)
9698 {
9699 struct v4l2_subdev_selection input_sel;
9700 struct v4l2_pix_format_mplane pixm;
9701 struct v4l2_subdev_format fmt;
9702 int stream_num = 0;
9703 int ret, i;
9704
9705 if (cif_dev->chip_id < CHIP_RV1126_CIF)
9706 return;
9707
9708 stream_num = RKCIF_MAX_STREAM_MIPI;
9709
9710 if (!cif_dev->terminal_sensor.sd)
9711 rkcif_update_sensor_info(&cif_dev->stream[0]);
9712
9713 if (cif_dev->terminal_sensor.sd) {
9714 for (i = 0; i < stream_num; i++) {
9715 if (i == RKCIF_STREAM_MIPI_ID3)
9716 cif_dev->stream[i].is_compact = false;
9717 memset(&fmt, 0, sizeof(fmt));
9718 fmt.pad = i;
9719 fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
9720 v4l2_subdev_call(cif_dev->terminal_sensor.sd, pad, get_fmt, NULL, &fmt);
9721
9722 memset(&pixm, 0, sizeof(pixm));
9723 pixm.pixelformat = rkcif_mbus_pixelcode_to_v4l2(fmt.format.code);
9724 pixm.width = fmt.format.width;
9725 pixm.height = fmt.format.height;
9726
9727 memset(&input_sel, 0, sizeof(input_sel));
9728 input_sel.pad = i;
9729 input_sel.target = V4L2_SEL_TGT_CROP_BOUNDS;
9730 input_sel.which = V4L2_SUBDEV_FORMAT_ACTIVE;
9731 ret = v4l2_subdev_call(cif_dev->terminal_sensor.sd,
9732 pad, get_selection, NULL,
9733 &input_sel);
9734 if (!ret) {
9735 pixm.width = input_sel.r.width;
9736 pixm.height = input_sel.r.height;
9737 }
9738 rkcif_set_fmt(&cif_dev->stream[i], &pixm, false);
9739 }
9740 }
9741 }
9742
rkcif_enable_dma_capture(struct rkcif_stream * stream,bool is_only_enable)9743 void rkcif_enable_dma_capture(struct rkcif_stream *stream, bool is_only_enable)
9744 {
9745 struct rkcif_device *cif_dev = stream->cifdev;
9746 struct v4l2_mbus_config *mbus_cfg = &cif_dev->active_sensor->mbus;
9747 struct csi_channel_info *channel = &cif_dev->channels[stream->id];
9748 u32 val = 0;
9749
9750 if (stream->buf_owner == RKCIF_DMAEN_BY_ISP)
9751 stream->buf_owner = RKCIF_DMAEN_BY_ISP_TO_VICAP;
9752
9753 if (stream->dma_en) {
9754 stream->dma_en |= stream->to_en_dma;
9755 stream->to_en_dma = 0;
9756 return;
9757 }
9758
9759 stream->dma_en |= stream->to_en_dma;
9760 if (!is_only_enable) {
9761 if (stream->to_en_dma == RKCIF_DMAEN_BY_VICAP) {
9762 rkcif_assign_new_buffer_pingpong(stream,
9763 RKCIF_YUV_ADDR_STATE_INIT,
9764 stream->id);
9765 rkcif_write_register(cif_dev, get_reg_index_of_frm0_y_vlw(stream->id),
9766 channel->virtual_width);
9767 } else if (stream->to_en_dma == RKCIF_DMAEN_BY_ISP) {
9768 rkcif_assign_new_buffer_pingpong_toisp(stream,
9769 RKCIF_YUV_ADDR_STATE_INIT,
9770 stream->id);
9771 }
9772 }
9773 if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY ||
9774 mbus_cfg->type == V4L2_MBUS_CSI2_CPHY)
9775 rkcif_write_register_or(cif_dev, CIF_REG_MIPI_LVDS_CTRL, 0x00010000);
9776 else
9777 rkcif_write_register_or(cif_dev, CIF_REG_DVP_CTRL, 0x00010000);
9778 if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY ||
9779 mbus_cfg->type == V4L2_MBUS_CSI2_CPHY) {
9780 val = rkcif_read_register(cif_dev, get_reg_index_of_id_ctrl0(stream->id));
9781 if (!stream->is_compact)
9782 val |= CSI_WRDDR_TYPE_RAW_UNCOMPACT;
9783 else
9784 val &= ~CSI_WRDDR_TYPE_RAW_UNCOMPACT;
9785 val |= CSI_DMA_ENABLE;
9786 rkcif_write_register(cif_dev, get_reg_index_of_id_ctrl0(stream->id), val);
9787 } else if (mbus_cfg->type == V4L2_MBUS_CCP2) {
9788 val = rkcif_read_register(cif_dev, get_reg_index_of_lvds_id_ctrl0(stream->id));
9789 if (!stream->is_compact)
9790 val |= CSI_WRDDR_TYPE_RAW_UNCOMPACT << 17;
9791 else
9792 val &= ~(CSI_WRDDR_TYPE_RAW_UNCOMPACT << 17);
9793 val |= LVDS_DMAEN_RV1106;
9794 rkcif_write_register(cif_dev, get_reg_index_of_lvds_id_ctrl0(stream->id), val);
9795 } else {
9796 val = rkcif_read_register(cif_dev, CIF_REG_DVP_FOR);
9797 if (!stream->is_compact)
9798 val |= CSI_WRDDR_TYPE_RAW_UNCOMPACT << 11;
9799 else
9800 val &= ~(CSI_WRDDR_TYPE_RAW_UNCOMPACT << 11);
9801 rkcif_write_register(cif_dev, CIF_REG_DVP_FOR, val);
9802 val = rkcif_read_register(cif_dev, CIF_REG_DVP_CTRL);
9803 if (cif_dev->chip_id == CHIP_RK3588_CIF)
9804 val |= DVP_DMA_EN;
9805 else if (cif_dev->chip_id == CHIP_RV1106_CIF)
9806 val |= DVP_SW_DMA_EN(stream->id);
9807 rkcif_write_register(cif_dev, CIF_REG_DVP_CTRL, val);
9808 }
9809
9810 stream->to_en_dma = 0;
9811 }
9812
rkcif_stop_dma_capture(struct rkcif_stream * stream)9813 static int rkcif_stop_dma_capture(struct rkcif_stream *stream)
9814 {
9815 struct rkcif_device *cif_dev = stream->cifdev;
9816 struct v4l2_mbus_config *mbus_cfg = &cif_dev->active_sensor->mbus;
9817 u32 val = 0;
9818
9819 if (stream->buf_replace_cnt)
9820 return -EINVAL;
9821
9822 stream->dma_en &= ~stream->to_stop_dma;
9823
9824 if (stream->dma_en != 0) {
9825 if (stream->dma_en & RKCIF_DMAEN_BY_ISP)
9826 stream->buf_owner = RKCIF_DMAEN_BY_ISP;
9827 stream->to_stop_dma = 0;
9828 return 0;
9829 }
9830
9831 if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY ||
9832 mbus_cfg->type == V4L2_MBUS_CSI2_CPHY) {
9833 val = rkcif_read_register(cif_dev, get_reg_index_of_id_ctrl0(stream->id));
9834 val &= ~CSI_DMA_ENABLE;
9835 if (stream->is_stop_capture) {
9836 val &= ~CSI_ENABLE_CAPTURE;
9837 stream->is_stop_capture = false;
9838 }
9839 rkcif_write_register(cif_dev, get_reg_index_of_id_ctrl0(stream->id), val);
9840 } else if (mbus_cfg->type == V4L2_MBUS_CCP2) {
9841 val = rkcif_read_register(cif_dev, get_reg_index_of_lvds_id_ctrl0(stream->id));
9842 val &= ~LVDS_DMAEN_RV1106;
9843 if (stream->is_stop_capture) {
9844 val &= ~ENABLE_CAPTURE;
9845 stream->is_stop_capture = false;
9846 }
9847 rkcif_write_register(cif_dev, get_reg_index_of_lvds_id_ctrl0(stream->id), val);
9848 } else {
9849 val = rkcif_read_register(cif_dev, CIF_REG_DVP_CTRL);
9850 if (cif_dev->chip_id == CHIP_RK3588_CIF)
9851 val &= ~DVP_DMA_EN;
9852 else if (cif_dev->chip_id == CHIP_RV1106_CIF)
9853 val &= ~(DVP_SW_DMA_EN(stream->id));
9854 if (stream->is_stop_capture) {
9855 val &= ~ENABLE_CAPTURE;
9856 stream->is_stop_capture = false;
9857 }
9858 rkcif_write_register(cif_dev, CIF_REG_DVP_CTRL, val);
9859 }
9860 stream->to_stop_dma = 0;
9861 return 0;
9862 }
9863
rkcif_send_sof(struct rkcif_device * cif_dev)9864 static void rkcif_send_sof(struct rkcif_device *cif_dev)
9865 {
9866 struct v4l2_mbus_config *mbus = &cif_dev->active_sensor->mbus;
9867 struct csi2_dev *csi;
9868
9869 if (mbus->type == V4L2_MBUS_CSI2_DPHY ||
9870 mbus->type == V4L2_MBUS_CSI2_CPHY) {
9871 csi = container_of(cif_dev->active_sensor->sd, struct csi2_dev, sd);
9872 rkcif_csi2_event_inc_sof(csi);
9873 } else if (mbus->type == V4L2_MBUS_CCP2) {
9874 rkcif_lvds_event_inc_sof(cif_dev);
9875 } else {
9876 rkcif_dvp_event_inc_sof(cif_dev);
9877 }
9878 }
9879
rkcif_g_toisp_ch(unsigned int intstat_glb,int index)9880 static int rkcif_g_toisp_ch(unsigned int intstat_glb, int index)
9881 {
9882 if (intstat_glb & TOISP_END_CH0(index))
9883 return RKCIF_TOISP_CH0;
9884 if (intstat_glb & TOISP_END_CH1(index))
9885 return RKCIF_TOISP_CH1;
9886 if (intstat_glb & TOISP_END_CH2(index))
9887 return RKCIF_TOISP_CH2;
9888
9889 return -EINVAL;
9890 }
9891
rkcif_g_toisp_fs(unsigned int intstat_glb,int index)9892 static int rkcif_g_toisp_fs(unsigned int intstat_glb, int index)
9893 {
9894 if (intstat_glb & TOISP_FS_CH0(index))
9895 return RKCIF_TOISP_CH0;
9896 if (intstat_glb & TOISP_FS_CH1(index))
9897 return RKCIF_TOISP_CH1;
9898 if (intstat_glb & TOISP_FS_CH2(index))
9899 return RKCIF_TOISP_CH2;
9900
9901 return -EINVAL;
9902 }
9903
rkcif_toisp_check_stop_status(struct sditf_priv * priv,unsigned int intstat_glb,int index)9904 static void rkcif_toisp_check_stop_status(struct sditf_priv *priv,
9905 unsigned int intstat_glb,
9906 int index)
9907 {
9908 int ch = 0;
9909 struct rkcif_stream *stream;
9910 int src_id = 0;
9911 int i = 0;
9912 u32 val = 0;
9913 u64 cur_time = 0;
9914
9915 for (i = 0; i < TOISP_CH_MAX; i++) {
9916 ch = rkcif_g_toisp_ch(intstat_glb, index);
9917 if (ch >= 0) {
9918 src_id = priv->toisp_inf.ch_info[ch].id;
9919 if (src_id == 24)
9920 stream = &priv->cif_dev->stream[0];
9921 else
9922 stream = &priv->cif_dev->stream[src_id % 4];
9923 if (stream->stopping) {
9924 v4l2_dbg(3, rkcif_debug, &priv->cif_dev->v4l2_dev,
9925 "stream[%d] stop\n",
9926 stream->id);
9927 rkcif_stream_stop(stream);
9928 stream->stopping = false;
9929 wake_up(&stream->wq_stopped);
9930 }
9931
9932 if (stream->cifdev->chip_id >= CHIP_RV1106_CIF)
9933 rkcif_modify_frame_skip_config(stream);
9934 if (stream->cifdev->rdbk_debug &&
9935 stream->frame_idx < 15)
9936 v4l2_info(&priv->cif_dev->v4l2_dev,
9937 "stream[%d] toisp fe %d\n",
9938 stream->id,
9939 stream->frame_idx - 1);
9940
9941 switch (ch) {
9942 case RKCIF_TOISP_CH0:
9943 val = TOISP_END_CH0(index);
9944 intstat_glb = intstat_glb & (~val);
9945 break;
9946 case RKCIF_TOISP_CH1:
9947 val = TOISP_END_CH1(index);
9948 intstat_glb = intstat_glb & (~val);
9949 break;
9950 case RKCIF_TOISP_CH2:
9951 val = TOISP_END_CH2(index);
9952 intstat_glb = intstat_glb & (~val);
9953 break;
9954 default:
9955 break;
9956 }
9957 }
9958 ch = rkcif_g_toisp_fs(intstat_glb, index);
9959 if (ch >= 0) {
9960 src_id = priv->toisp_inf.ch_info[ch].id;
9961 if (src_id == 24)
9962 stream = &priv->cif_dev->stream[0];
9963 else
9964 stream = &priv->cif_dev->stream[src_id % 4];
9965 if (stream->id == 0)
9966 rkcif_send_sof(stream->cifdev);
9967 stream->frame_idx++;
9968 cur_time = ktime_get_ns();
9969 stream->readout.readout_time = cur_time - stream->readout.fs_timestamp;
9970 stream->readout.fs_timestamp = cur_time;
9971 if (stream->cifdev->rdbk_debug &&
9972 stream->frame_idx < 15)
9973 v4l2_info(&priv->cif_dev->v4l2_dev,
9974 "stream[%d] toisp sof seq %d\n",
9975 stream->id,
9976 stream->frame_idx - 1);
9977 if (stream->to_en_dma)
9978 rkcif_enable_dma_capture(stream, false);
9979 if (stream->to_en_scale) {
9980 stream->to_en_scale = false;
9981 rkcif_scale_start(stream->scale_vdev);
9982 }
9983 switch (ch) {
9984 case RKCIF_TOISP_CH0:
9985 val = TOISP_FS_CH0(index);
9986 intstat_glb = intstat_glb & (~val);
9987 break;
9988 case RKCIF_TOISP_CH1:
9989 val = TOISP_FS_CH1(index);
9990 intstat_glb = intstat_glb & (~val);
9991 break;
9992 case RKCIF_TOISP_CH2:
9993 val = TOISP_FS_CH2(index);
9994 intstat_glb = intstat_glb & (~val);
9995 break;
9996 default:
9997 break;
9998 }
9999 }
10000 }
10001 }
10002
rkcif_irq_handle_toisp(struct rkcif_device * cif_dev,unsigned int intstat_glb)10003 void rkcif_irq_handle_toisp(struct rkcif_device *cif_dev, unsigned int intstat_glb)
10004 {
10005 int i = 0;
10006 bool to_check = false;
10007 struct sditf_priv *priv = cif_dev->sditf[0];
10008
10009 if (!priv || priv->mode.rdbk_mode != RKISP_VICAP_ONLINE)
10010 return;
10011
10012 for (i = 0; i < 2; i++) {
10013 if (priv->toisp_inf.link_mode == TOISP0 &&
10014 i == 0) {
10015 to_check = true;
10016 } else if (priv->toisp_inf.link_mode == TOISP1 &&
10017 i == 1) {
10018 to_check = true;
10019 } else if (priv->toisp_inf.link_mode == TOISP_UNITE &&
10020 i == 1) {
10021 to_check = true;
10022 }
10023 if (to_check)
10024 rkcif_toisp_check_stop_status(priv, intstat_glb, i);
10025 }
10026 }
10027
rkcif_check_group_sync_state(struct rkcif_device * cif_dev)10028 static int rkcif_check_group_sync_state(struct rkcif_device *cif_dev)
10029 {
10030 struct rkcif_stream *detect_stream = &cif_dev->stream[0];
10031 struct rkcif_stream *next_stream = NULL;
10032 struct rkcif_hw *hw = cif_dev->hw_dev;
10033 u64 fs_interval = 0;
10034 int i = 0;
10035 int ret = 0;
10036 struct rkcif_multi_sync_config *sync_config;
10037
10038 sync_config = &hw->sync_config[cif_dev->sync_cfg.group];
10039 sync_config->sync_code |= BIT(cif_dev->csi_host_idx);
10040 v4l2_dbg(3, rkcif_debug, &cif_dev->v4l2_dev,
10041 "sync code 0x%x, mask 0x%x, update 0x%x, cache 0x%x, timestamp %llu\n",
10042 sync_config->sync_code,
10043 sync_config->sync_mask,
10044 sync_config->update_code,
10045 sync_config->update_cache,
10046 detect_stream->readout.fs_timestamp);
10047
10048 if (sync_config->sync_code != sync_config->sync_mask)
10049 return -EINVAL;
10050
10051 for (i = 0; i < sync_config->dev_cnt; i++) {
10052 if (sync_config->mode == RKCIF_MASTER_MASTER) {
10053 if (i < sync_config->ext_master.count)
10054 next_stream = &sync_config->ext_master.cif_dev[i]->stream
10055 [0];
10056 else
10057 next_stream = &sync_config->int_master.cif_dev[0]->stream
10058 [0];
10059 } else if (sync_config->mode == RKCIF_MASTER_SLAVE) {
10060 if (i < sync_config->slave.count)
10061 next_stream = &sync_config->slave.cif_dev[i]->stream
10062 [0];
10063 else
10064 next_stream = &sync_config->int_master.cif_dev[0]->stream
10065 [0];
10066 } else {
10067 v4l2_err(&cif_dev->v4l2_dev,
10068 "ERROR: invalid group sync mode\n");
10069 ret = -EINVAL;
10070 break;
10071 }
10072 if (detect_stream == next_stream)
10073 continue;
10074 fs_interval = abs(detect_stream->readout.fs_timestamp - next_stream->readout.fs_timestamp);
10075 if (fs_interval > RKCIF_MAX_INTERVAL_NS) {
10076 ret = -EINVAL;
10077 break;
10078 }
10079 }
10080 return ret;
10081 }
10082
rkcif_deal_sof(struct rkcif_device * cif_dev)10083 static void rkcif_deal_sof(struct rkcif_device *cif_dev)
10084 {
10085 struct rkcif_stream *detect_stream = &cif_dev->stream[0];
10086 struct rkcif_hw *hw = cif_dev->hw_dev;
10087 struct rkcif_device *tmp_dev = NULL;
10088 unsigned long flags;
10089 int i = 0;
10090 int ret = 0;
10091
10092 if (cif_dev->chip_id < CHIP_RK3588_CIF)
10093 detect_stream->fs_cnt_in_single_frame++;
10094 spin_lock_irqsave(&detect_stream->fps_lock, flags);
10095 detect_stream->readout.fs_timestamp = ktime_get_ns();
10096 spin_unlock_irqrestore(&detect_stream->fps_lock, flags);
10097
10098 if (cif_dev->sync_cfg.type != RKCIF_NOSYNC_MODE) {
10099 struct rkcif_multi_sync_config *sync_config;
10100
10101 sync_config = &hw->sync_config[cif_dev->sync_cfg.group];
10102 ret = rkcif_check_group_sync_state(cif_dev);
10103 if (!ret) {
10104 sync_config->sync_code = 0;
10105 sync_config->frame_idx++;
10106 spin_lock_irqsave(&hw->group_lock, flags);
10107 sync_config->update_cache = sync_config->sync_mask;
10108 if (!sync_config->update_code) {
10109 sync_config->update_code = sync_config->update_cache;
10110 sync_config->update_cache = 0;
10111 }
10112 spin_unlock_irqrestore(&hw->group_lock, flags);
10113 for (i = 0; i < sync_config->dev_cnt; i++) {
10114 if (sync_config->mode == RKCIF_MASTER_MASTER) {
10115 if (i < sync_config->ext_master.count)
10116 tmp_dev = sync_config->ext_master.cif_dev[i];
10117 else
10118 tmp_dev = sync_config->int_master.cif_dev[0];
10119 } else if (sync_config->mode == RKCIF_MASTER_SLAVE) {
10120 if (i < sync_config->slave.count)
10121 tmp_dev = sync_config->slave.cif_dev[i];
10122 else
10123 tmp_dev = sync_config->int_master.cif_dev[0];
10124 } else {
10125 v4l2_err(&cif_dev->v4l2_dev,
10126 "ERROR: invalid group sync mode\n");
10127 }
10128 if (tmp_dev) {
10129 rkcif_send_sof(tmp_dev);
10130 tmp_dev->stream[0].frame_idx = sync_config->frame_idx;
10131 }
10132 }
10133 }
10134 } else {
10135 if (!cif_dev->sditf[0] || cif_dev->sditf[0]->mode.rdbk_mode) {
10136 rkcif_send_sof(cif_dev);
10137 detect_stream->frame_idx++;
10138 }
10139 if (detect_stream->cifdev->rdbk_debug &&
10140 detect_stream->frame_idx < 15 &&
10141 (!cif_dev->sditf[0] || cif_dev->sditf[0]->mode.rdbk_mode))
10142 v4l2_info(&cif_dev->v4l2_dev,
10143 "stream[%d] sof %d %lld\n",
10144 detect_stream->id,
10145 detect_stream->frame_idx - 1,
10146 ktime_get_ns());
10147 }
10148 }
10149
rkcif_irq_global(struct rkcif_device * cif_dev)10150 unsigned int rkcif_irq_global(struct rkcif_device *cif_dev)
10151 {
10152 unsigned int intstat_glb = 0;
10153
10154 intstat_glb = rkcif_read_register(cif_dev, CIF_REG_GLB_INTST);
10155 if (intstat_glb)
10156 v4l2_dbg(2, rkcif_debug, &cif_dev->v4l2_dev,
10157 "intstat_glb 0x%x\n",
10158 intstat_glb);
10159 else
10160 return intstat_glb;
10161
10162 if (intstat_glb & SCALE_TOISP_AXI0_ERR) {
10163 v4l2_err(&cif_dev->v4l2_dev,
10164 "ERROR: scale channel, AXI0 bus err intstat_glb:0x%x !!\n",
10165 intstat_glb);
10166 return 0;
10167 }
10168 if (intstat_glb & SCALE_TOISP_AXI1_ERR) {
10169 v4l2_err(&cif_dev->v4l2_dev,
10170 "ERROR: scale channel, AXI1 bus err intstat_glb:0x%x !!\n",
10171 intstat_glb);
10172 return 0;
10173 }
10174 rkcif_irq_handle_scale(cif_dev, intstat_glb);
10175 return intstat_glb;
10176 }
10177
rkcif_check_buffer_prepare(struct rkcif_stream * stream)10178 static bool rkcif_check_buffer_prepare(struct rkcif_stream *stream)
10179 {
10180 struct rkcif_device *cif_dev = stream->cifdev;
10181 unsigned long flags;
10182 bool is_update = false;
10183 struct rkcif_multi_sync_config *sync_config;
10184
10185 spin_lock_irqsave(&cif_dev->hw_dev->group_lock, flags);
10186 sync_config = &cif_dev->hw_dev->sync_config[cif_dev->sync_cfg.group];
10187 if (stream->id == 0 &&
10188 sync_config->update_code & BIT(cif_dev->csi_host_idx)) {
10189 is_update = true;
10190 sync_config->update_code &= ~(BIT(cif_dev->csi_host_idx));
10191 if (!sync_config->update_code &&
10192 sync_config->update_cache) {
10193 sync_config->update_code = sync_config->update_cache;
10194 sync_config->update_cache = 0;
10195 }
10196 } else {
10197 if (cif_dev->rdbk_buf[RDBK_L])
10198 is_update = true;
10199 }
10200
10201 spin_unlock_irqrestore(&cif_dev->hw_dev->group_lock, flags);
10202 return is_update;
10203 }
10204
rkcif_err_print_work(struct work_struct * work)10205 void rkcif_err_print_work(struct work_struct *work)
10206 {
10207 struct rkcif_err_state_work *err_state_work = container_of(work,
10208 struct rkcif_err_state_work,
10209 work);
10210 struct rkcif_device *dev = container_of(err_state_work,
10211 struct rkcif_device,
10212 err_state_work);
10213 u32 err_state = 0;
10214 int intstat = 0;
10215 int lastline = 0;
10216 int lastpixel = 0;
10217 u64 cur_time = 0;
10218 bool is_print = false;
10219
10220 cur_time = ktime_get_ns();
10221 if (err_state_work->last_timestamp == 0) {
10222 is_print = true;
10223 } else {
10224 if (cur_time - err_state_work->last_timestamp > 500000000)
10225 is_print = true;
10226 }
10227 err_state_work->last_timestamp = cur_time;
10228 err_state = err_state_work->err_state;
10229 intstat = err_state_work->intstat;
10230 lastline = err_state_work->lastline;
10231 lastpixel = err_state_work->lastpixel;
10232 if (err_state & RKCIF_ERR_ID0_NOT_BUF && is_print)
10233 v4l2_err(&dev->v4l2_dev,
10234 "stream[0] not active buffer, frame num %d, cnt %llu\n",
10235 dev->stream[0].frame_idx, dev->irq_stats.not_active_buf_cnt[0]);
10236 if (err_state & RKCIF_ERR_ID1_NOT_BUF && is_print)
10237 v4l2_err(&dev->v4l2_dev,
10238 "stream[1] not active buffer, frame num %d, cnt %llu\n",
10239 dev->stream[1].frame_idx, dev->irq_stats.not_active_buf_cnt[1]);
10240 if (err_state & RKCIF_ERR_ID2_NOT_BUF && is_print)
10241 v4l2_err(&dev->v4l2_dev,
10242 "stream[2] not active buffer, frame num %d, cnt %llu\n",
10243 dev->stream[2].frame_idx, dev->irq_stats.not_active_buf_cnt[2]);
10244 if (err_state & RKCIF_ERR_ID3_NOT_BUF && is_print)
10245 v4l2_err(&dev->v4l2_dev,
10246 "stream[3] not active buffer, frame num %d, cnt %llu\n",
10247 dev->stream[3].frame_idx, dev->irq_stats.not_active_buf_cnt[3]);
10248 if (err_state & RKCIF_ERR_ID0_TRIG_SIMULT && is_print)
10249 v4l2_err(&dev->v4l2_dev,
10250 "stream[0], frm0/frm1 end simultaneously,frm id:%d, cnt %llu\n",
10251 dev->stream[0].frame_idx, dev->irq_stats.trig_simult_cnt[0]);
10252 if (err_state & RKCIF_ERR_ID1_TRIG_SIMULT && is_print)
10253 v4l2_err(&dev->v4l2_dev,
10254 "stream[1], frm0/frm1 end simultaneously,frm id:%d, cnt %llu\n",
10255 dev->stream[1].frame_idx, dev->irq_stats.trig_simult_cnt[1]);
10256 if (err_state & RKCIF_ERR_ID2_TRIG_SIMULT && is_print)
10257 v4l2_err(&dev->v4l2_dev,
10258 "stream[2], frm0/frm1 end simultaneously,frm id:%d, cnt %llu\n",
10259 dev->stream[2].frame_idx, dev->irq_stats.trig_simult_cnt[2]);
10260 if (err_state & RKCIF_ERR_ID3_TRIG_SIMULT && is_print)
10261 v4l2_err(&dev->v4l2_dev,
10262 "stream[3], frm0/frm1 end simultaneously,frm id:%d, cnt %llu\n",
10263 dev->stream[3].frame_idx, dev->irq_stats.trig_simult_cnt[3]);
10264 if (err_state & RKCIF_ERR_SIZE)
10265 v4l2_err(&dev->v4l2_dev,
10266 "ERROR: csi size err, intstat:0x%x, lastline:0x%x, cnt %llu\n",
10267 intstat, lastline, dev->irq_stats.csi_size_err_cnt);
10268 if (err_state & RKCIF_ERR_OVERFLOW)
10269 v4l2_err(&dev->v4l2_dev,
10270 "ERROR: csi fifo overflow, intstat:0x%x, lastline:0x%x, cnt %llu\n",
10271 intstat, lastline, dev->irq_stats.csi_overflow_cnt);
10272 if (err_state & RKCIF_ERR_BANDWIDTH_LACK)
10273 v4l2_err(&dev->v4l2_dev,
10274 "ERROR: csi bandwidth lack, intstat:0x%x, lastline:0x%x, cnt %llu\n",
10275 intstat, lastline, dev->irq_stats.csi_bwidth_lack_cnt);
10276 if (err_state & RKCIF_ERR_ID0_MULTI_FS)
10277 v4l2_err(&dev->v4l2_dev,
10278 "ERR: multi fs in oneframe in id0, fs_num:%u\n",
10279 dev->stream[0].fs_cnt_in_single_frame);
10280 if (err_state & RKCIF_ERR_BUS)
10281 v4l2_err(&dev->v4l2_dev, "dvp bus err, intstat 0x%x, last line 0x%x\n",
10282 intstat, lastline);
10283 if (err_state & RKCIF_ERR_PIXEL)
10284 v4l2_err(&dev->v4l2_dev, "dvp pix err, intstat 0x%x, last pixel 0x%x\n",
10285 intstat, lastpixel);
10286 if (err_state & RKCIF_ERR_LINE)
10287 v4l2_err(&dev->v4l2_dev, "dvp line err, intstat 0x%x, last line 0x%x\n",
10288 intstat, lastline);
10289 }
10290
10291 /* pingpong irq for rk3588 and next */
rkcif_irq_pingpong_v1(struct rkcif_device * cif_dev)10292 void rkcif_irq_pingpong_v1(struct rkcif_device *cif_dev)
10293 {
10294 struct rkcif_stream *stream;
10295 struct rkcif_stream *detect_stream = &cif_dev->stream[0];
10296 struct v4l2_mbus_config *mbus;
10297 unsigned int intstat, i = 0xff;
10298 unsigned long flags;
10299 bool is_update = false;
10300 int ret = 0;
10301
10302 if (!cif_dev->active_sensor)
10303 return;
10304
10305 mbus = &cif_dev->active_sensor->mbus;
10306 if (mbus->type == V4L2_MBUS_CSI2_DPHY ||
10307 mbus->type == V4L2_MBUS_CSI2_CPHY ||
10308 mbus->type == V4L2_MBUS_CCP2) {
10309 int mipi_id;
10310 u32 lastline = 0;
10311
10312 intstat = rkcif_read_register(cif_dev, CIF_REG_MIPI_LVDS_INTSTAT);
10313 lastline = rkcif_read_register(cif_dev, CIF_REG_MIPI_LVDS_LINE_LINE_CNT_ID0_1);
10314 cif_dev->err_state_work.lastline = lastline;
10315 cif_dev->err_state_work.intstat = intstat;
10316
10317 /* clear all interrupts that has been triggered */
10318 if (intstat) {
10319 rkcif_write_register(cif_dev, CIF_REG_MIPI_LVDS_INTSTAT, intstat);
10320 v4l2_dbg(2, rkcif_debug, &cif_dev->v4l2_dev,
10321 "intstat 0x%x\n",
10322 intstat);
10323 } else {
10324 return;
10325 }
10326
10327 if (intstat & CSI_SIZE_ERR) {
10328 cif_dev->irq_stats.csi_size_err_cnt++;
10329 cif_dev->err_state |= RKCIF_ERR_SIZE;
10330 rkcif_write_register_or(cif_dev, CIF_REG_MIPI_LVDS_CTRL, 0x000A0000);
10331 return;
10332 }
10333
10334 if (intstat & CSI_FIFO_OVERFLOW_V1) {
10335 cif_dev->irq_stats.csi_overflow_cnt++;
10336 cif_dev->err_state |= RKCIF_ERR_OVERFLOW;
10337 return;
10338 }
10339
10340 if (intstat & CSI_BANDWIDTH_LACK_V1) {
10341 cif_dev->irq_stats.csi_bwidth_lack_cnt++;
10342 cif_dev->err_state |= RKCIF_ERR_BANDWIDTH_LACK;
10343 }
10344
10345 if (intstat & CSI_ALL_ERROR_INTEN_V1) {
10346 cif_dev->irq_stats.all_err_cnt++;
10347 return;
10348 }
10349
10350 for (i = 0; i < RKCIF_MAX_STREAM_MIPI; i++) {
10351 mipi_id = rkcif_csi_g_mipi_id(&cif_dev->v4l2_dev,
10352 intstat);
10353 if (mipi_id < 0)
10354 continue;
10355
10356 stream = &cif_dev->stream[mipi_id];
10357 if (!cif_dev->sditf[0] ||
10358 cif_dev->sditf[0]->mode.rdbk_mode)
10359 stream->buf_wake_up_cnt++;
10360
10361 if (stream->stopping && (!stream->dma_en)) {
10362 rkcif_stream_stop(stream);
10363 stream->stopping = false;
10364 wake_up(&stream->wq_stopped);
10365 continue;
10366 }
10367
10368 if (stream->state != RKCIF_STATE_STREAMING)
10369 continue;
10370 stream->is_in_vblank = true;
10371 switch (mipi_id) {
10372 case RKCIF_STREAM_MIPI_ID0:
10373 stream->frame_phase = SW_FRM_END_ID0(intstat);
10374 intstat &= ~CSI_FRAME_END_ID0;
10375 break;
10376 case RKCIF_STREAM_MIPI_ID1:
10377 stream->frame_phase = SW_FRM_END_ID1(intstat);
10378 intstat &= ~CSI_FRAME_END_ID1;
10379 break;
10380 case RKCIF_STREAM_MIPI_ID2:
10381 stream->frame_phase = SW_FRM_END_ID2(intstat);
10382 intstat &= ~CSI_FRAME_END_ID2;
10383 break;
10384 case RKCIF_STREAM_MIPI_ID3:
10385 stream->frame_phase = SW_FRM_END_ID3(intstat);
10386 intstat &= ~CSI_FRAME_END_ID3;
10387 break;
10388 }
10389 if (stream->cifdev->rdbk_debug &&
10390 stream->frame_idx < 15 &&
10391 (!cif_dev->sditf[0] || cif_dev->sditf[0]->mode.rdbk_mode))
10392 v4l2_info(&cif_dev->v4l2_dev,
10393 "stream[%d] fe %d, phase %d, %lld\n",
10394 stream->id,
10395 stream->frame_idx - 1,
10396 stream->frame_phase,
10397 ktime_get_ns());
10398
10399 if (stream->crop_dyn_en)
10400 rkcif_dynamic_crop(stream);
10401
10402 if (stream->dma_en & RKCIF_DMAEN_BY_VICAP) {
10403 if (cif_dev->sync_cfg.type == RKCIF_NOSYNC_MODE)
10404 is_update = true;
10405 else
10406 is_update = rkcif_check_buffer_prepare(stream);
10407 v4l2_dbg(4, rkcif_debug, &cif_dev->v4l2_dev,
10408 "dma capture by vicap, is_updata %d, group mode %d, dma_en %d\n",
10409 is_update, cif_dev->sync_cfg.type, stream->dma_en);
10410 if (is_update)
10411 rkcif_update_stream(cif_dev, stream, mipi_id);
10412 } else if (stream->dma_en & RKCIF_DMAEN_BY_ISP) {
10413 v4l2_dbg(4, rkcif_debug, &cif_dev->v4l2_dev,
10414 "dma capture by isp, dma_en 0x%x\n",
10415 stream->dma_en);
10416 rkcif_update_stream_toisp(cif_dev, stream, mipi_id);
10417 } else if (stream->dma_en & RKCIF_DMAEN_BY_ROCKIT) {
10418 v4l2_dbg(4, rkcif_debug, &cif_dev->v4l2_dev,
10419 "dma capture by rockit, dma_en 0x%x\n",
10420 stream->dma_en);
10421 rkcif_update_stream_rockit(cif_dev, stream, mipi_id);
10422 }
10423
10424 if (cif_dev->chip_id >= CHIP_RV1106_CIF)
10425 rkcif_modify_frame_skip_config(stream);
10426 if (stream->is_change_toisp) {
10427 stream->is_change_toisp = false;
10428 if ((cif_dev->hdr.hdr_mode == HDR_X2 && stream->id != 1) ||
10429 (cif_dev->hdr.hdr_mode == HDR_X3 && stream->id != 2))
10430 rkcif_release_unnecessary_buf_for_online(stream,
10431 stream->curr_buf_toisp);
10432 else
10433 sditf_change_to_online(cif_dev->sditf[0]);
10434 }
10435
10436 spin_lock_irqsave(&stream->vbq_lock, flags);
10437 if (stream->is_finish_stop_dma) {
10438 wake_up(&stream->wq_stopped);
10439 stream->is_finish_stop_dma = false;
10440 }
10441 if (!(stream->dma_en & RKCIF_DMAEN_BY_ISP) && stream->lack_buf_cnt == 2) {
10442 stream->to_stop_dma = RKCIF_DMAEN_BY_VICAP;
10443 rkcif_stop_dma_capture(stream);
10444 }
10445 spin_unlock_irqrestore(&stream->vbq_lock, flags);
10446 if (stream->to_en_scale) {
10447 stream->to_en_scale = false;
10448 rkcif_scale_start(stream->scale_vdev);
10449 }
10450 rkcif_detect_wake_up_mode_change(stream);
10451 if (cif_dev->chip_id < CHIP_RK3588_CIF &&
10452 mipi_id == RKCIF_STREAM_MIPI_ID0) {
10453 if ((intstat & (CSI_FRAME1_START_ID0 | CSI_FRAME0_START_ID0)) == 0 &&
10454 detect_stream->fs_cnt_in_single_frame > 1) {
10455 cif_dev->err_state |= RKCIF_ERR_ID0_MULTI_FS;
10456 detect_stream->is_fs_fe_not_paired = true;
10457 detect_stream->fs_cnt_in_single_frame = 0;
10458 } else {
10459 detect_stream->fs_cnt_in_single_frame--;
10460 }
10461 }
10462 rkcif_monitor_reset_event(cif_dev);
10463 cif_dev->irq_stats.frm_end_cnt[stream->id]++;
10464 }
10465
10466 for (i = 0; i < RKCIF_MAX_STREAM_MIPI; i++) {
10467 if (intstat & CSI_START_INTSTAT(i)) {
10468 stream = &cif_dev->stream[i];
10469 if (i == 0) {
10470 rkcif_deal_sof(cif_dev);
10471 } else {
10472 spin_lock_irqsave(&stream->fps_lock, flags);
10473 stream->readout.fs_timestamp = ktime_get_ns();
10474 stream->frame_idx++;
10475 spin_unlock_irqrestore(&stream->fps_lock, flags);
10476 }
10477 stream->is_in_vblank = false;
10478 spin_lock_irqsave(&stream->vbq_lock, flags);
10479 if (stream->stopping && stream->dma_en) {
10480 if (stream->dma_en & RKCIF_DMAEN_BY_VICAP)
10481 stream->to_stop_dma = RKCIF_DMAEN_BY_VICAP;
10482 else if (stream->dma_en & RKCIF_DMAEN_BY_ISP)
10483 stream->to_stop_dma = RKCIF_DMAEN_BY_ISP;
10484 stream->is_stop_capture = true;
10485 }
10486 if (stream->to_stop_dma) {
10487 ret = rkcif_stop_dma_capture(stream);
10488 if (!ret)
10489 stream->is_finish_stop_dma = true;
10490 }
10491 if (stream->to_en_dma)
10492 rkcif_enable_dma_capture(stream, false);
10493 spin_unlock_irqrestore(&stream->vbq_lock, flags);
10494 }
10495 if (intstat & CSI_LINE_INTSTAT_V1(i)) {
10496 stream = &cif_dev->stream[i];
10497 if (stream->is_line_inten) {
10498 stream->line_int_cnt++;
10499 if (cif_dev->rdbk_debug > 1 &&
10500 stream->frame_idx < 15)
10501 v4l2_info(&cif_dev->v4l2_dev,
10502 "line int %lld\n",
10503 stream->line_int_cnt);
10504 if (cif_dev->sditf[0] && cif_dev->sditf[0]->mode.rdbk_mode == RKISP_VICAP_RDBK_AUTO)
10505 rkcif_line_wake_up_rdbk(stream, stream->id);
10506 else
10507 rkcif_line_wake_up(stream, stream->id);
10508 rkcif_modify_line_int(stream, false);
10509 stream->is_line_inten = false;
10510 }
10511 v4l2_dbg(3, rkcif_debug, &cif_dev->v4l2_dev,
10512 "%s: id0 cur line:%d\n", __func__, lastline & 0x3fff);
10513 }
10514 }
10515 } else {
10516 struct rkcif_stream *stream;
10517 int ch_id;
10518 int lastline;
10519
10520 intstat = rkcif_read_register(cif_dev, CIF_REG_DVP_INTSTAT);
10521 if (intstat)
10522 rkcif_write_register(cif_dev, CIF_REG_DVP_INTSTAT, intstat);
10523 else
10524 return;
10525 lastline = rkcif_read_register(cif_dev, CIF_REG_DVP_LINE_CNT);
10526 cif_dev->err_state_work.lastline = lastline;
10527 cif_dev->err_state_work.intstat = intstat;
10528 stream = &cif_dev->stream[RKCIF_STREAM_CIF];
10529
10530 if (intstat & DVP_SIZE_ERR) {
10531 cif_dev->irq_stats.dvp_size_err_cnt++;
10532 rkcif_write_register_or(cif_dev, CIF_REG_DVP_CTRL, 0x000A0000);
10533 cif_dev->err_state |= RKCIF_ERR_SIZE;
10534 }
10535
10536 if (intstat & DVP_FIFO_OVERFLOW) {
10537 cif_dev->irq_stats.dvp_overflow_cnt++;
10538 cif_dev->err_state |= RKCIF_ERR_OVERFLOW;
10539 }
10540
10541 if (intstat & DVP_BANDWIDTH_LACK) {
10542 cif_dev->irq_stats.dvp_bwidth_lack_cnt++;
10543 cif_dev->err_state |= RKCIF_ERR_BANDWIDTH_LACK;
10544 }
10545
10546 if (intstat & INTSTAT_ERR_RK3588) {
10547 cif_dev->irq_stats.all_err_cnt++;
10548 }
10549
10550 for (i = 0; i < RKCIF_MAX_STREAM_DVP; i++) {
10551 ch_id = rkcif_dvp_g_ch_id_by_fe(&cif_dev->v4l2_dev, intstat);
10552
10553 if (ch_id < 0)
10554 continue;
10555
10556 stream = &cif_dev->stream[ch_id];
10557 if (!cif_dev->sditf[0] ||
10558 cif_dev->sditf[0]->mode.rdbk_mode)
10559 stream->buf_wake_up_cnt++;
10560
10561 if (stream->stopping) {
10562 rkcif_stream_stop(stream);
10563 stream->stopping = false;
10564 wake_up(&stream->wq_stopped);
10565 continue;
10566 }
10567
10568 if (stream->state != RKCIF_STATE_STREAMING)
10569 continue;
10570 stream->is_in_vblank = true;
10571 switch (ch_id) {
10572 case RKCIF_STREAM_MIPI_ID0:
10573 stream->frame_phase = SW_FRM_END_ID0(intstat);
10574 intstat &= ~DVP_ALL_END_ID0;
10575 break;
10576 case RKCIF_STREAM_MIPI_ID1:
10577 stream->frame_phase = SW_FRM_END_ID1(intstat);
10578 intstat &= ~DVP_ALL_END_ID1;
10579 break;
10580 case RKCIF_STREAM_MIPI_ID2:
10581 stream->frame_phase = SW_FRM_END_ID2(intstat);
10582 intstat &= ~DVP_ALL_END_ID2;
10583 break;
10584 case RKCIF_STREAM_MIPI_ID3:
10585 stream->frame_phase = SW_FRM_END_ID3(intstat);
10586 intstat &= ~DVP_ALL_END_ID3;
10587 break;
10588 }
10589 if (stream->dma_en & RKCIF_DMAEN_BY_VICAP) {
10590 if (cif_dev->sync_cfg.type == RKCIF_NOSYNC_MODE)
10591 is_update = true;
10592 else
10593 is_update = rkcif_check_buffer_prepare(stream);
10594 if (is_update)
10595 rkcif_update_stream(cif_dev, stream, ch_id);
10596 } else if (stream->dma_en & RKCIF_DMAEN_BY_ISP) {
10597 rkcif_update_stream_toisp(cif_dev, stream, ch_id);
10598 } else if (stream->dma_en & RKCIF_DMAEN_BY_ROCKIT) {
10599 rkcif_update_stream_rockit(cif_dev, stream, ch_id);
10600 }
10601
10602 if (stream->to_en_dma)
10603 rkcif_enable_dma_capture(stream, false);
10604 if (stream->to_stop_dma) {
10605 rkcif_stop_dma_capture(stream);
10606 wake_up(&stream->wq_stopped);
10607 }
10608 cif_dev->irq_stats.frm_end_cnt[stream->id]++;
10609 }
10610
10611 if (intstat & DVP_FRAME0_START_ID0 || intstat & DVP_FRAME1_START_ID0) {
10612 stream->is_in_vblank = false;
10613 rkcif_deal_sof(cif_dev);
10614 }
10615
10616 if (stream->crop_dyn_en)
10617 rkcif_dynamic_crop(stream);
10618 }
10619 }
10620
rkcif_irq_pingpong(struct rkcif_device * cif_dev)10621 void rkcif_irq_pingpong(struct rkcif_device *cif_dev)
10622 {
10623 struct rkcif_stream *stream;
10624 struct rkcif_stream *detect_stream = &cif_dev->stream[0];
10625 struct v4l2_mbus_config *mbus;
10626 unsigned int intstat = 0x0, i = 0xff;
10627 unsigned long flags;
10628 int ret = 0;
10629
10630 if (!cif_dev->active_sensor)
10631 return;
10632
10633 mbus = &cif_dev->active_sensor->mbus;
10634 if ((mbus->type == V4L2_MBUS_CSI2_DPHY ||
10635 mbus->type == V4L2_MBUS_CSI2_CPHY ||
10636 mbus->type == V4L2_MBUS_CCP2) &&
10637 (cif_dev->chip_id == CHIP_RK1808_CIF ||
10638 cif_dev->chip_id == CHIP_RV1126_CIF ||
10639 cif_dev->chip_id == CHIP_RK3568_CIF)) {
10640 int mipi_id;
10641 u32 lastline = 0;
10642
10643 intstat = rkcif_read_register(cif_dev, CIF_REG_MIPI_LVDS_INTSTAT);
10644 lastline = rkcif_read_register(cif_dev, CIF_REG_MIPI_LVDS_LINE_LINE_CNT_ID0_1);
10645 cif_dev->err_state_work.lastline = lastline;
10646 cif_dev->err_state_work.intstat = intstat;
10647
10648 /* clear all interrupts that has been triggered */
10649 rkcif_write_register(cif_dev, CIF_REG_MIPI_LVDS_INTSTAT, intstat);
10650
10651 if (intstat & CSI_FIFO_OVERFLOW) {
10652 cif_dev->irq_stats.csi_overflow_cnt++;
10653 cif_dev->err_state |= RKCIF_ERR_OVERFLOW;
10654 }
10655
10656 if (intstat & CSI_BANDWIDTH_LACK) {
10657 cif_dev->irq_stats.csi_bwidth_lack_cnt++;
10658 cif_dev->err_state |= RKCIF_ERR_BANDWIDTH_LACK;
10659 return;
10660 }
10661
10662 if (intstat & CSI_ALL_ERROR_INTEN) {
10663 cif_dev->irq_stats.all_err_cnt++;
10664 return;
10665 }
10666
10667 for (i = 0; i < RKCIF_MAX_STREAM_MIPI; i++) {
10668 mipi_id = rkcif_csi_g_mipi_id(&cif_dev->v4l2_dev,
10669 intstat);
10670 if (mipi_id < 0)
10671 continue;
10672
10673 stream = &cif_dev->stream[mipi_id];
10674 if (stream->stopping && stream->is_can_stop) {
10675 rkcif_stream_stop(stream);
10676 stream->stopping = false;
10677 wake_up(&stream->wq_stopped);
10678 continue;
10679 }
10680
10681 if (stream->state != RKCIF_STATE_STREAMING)
10682 continue;
10683
10684 switch (mipi_id) {
10685 case RKCIF_STREAM_MIPI_ID0:
10686 stream->frame_phase = SW_FRM_END_ID0(intstat);
10687 intstat &= ~CSI_FRAME_END_ID0;
10688 break;
10689 case RKCIF_STREAM_MIPI_ID1:
10690 stream->frame_phase = SW_FRM_END_ID1(intstat);
10691 intstat &= ~CSI_FRAME_END_ID1;
10692 break;
10693 case RKCIF_STREAM_MIPI_ID2:
10694 stream->frame_phase = SW_FRM_END_ID2(intstat);
10695 intstat &= ~CSI_FRAME_END_ID2;
10696 break;
10697 case RKCIF_STREAM_MIPI_ID3:
10698 stream->frame_phase = SW_FRM_END_ID3(intstat);
10699 intstat &= ~CSI_FRAME_END_ID3;
10700 break;
10701 }
10702
10703 if (stream->crop_dyn_en)
10704 rkcif_dynamic_crop(stream);
10705
10706 rkcif_update_stream(cif_dev, stream, mipi_id);
10707 rkcif_detect_wake_up_mode_change(stream);
10708 rkcif_monitor_reset_event(cif_dev);
10709 if (mipi_id == RKCIF_STREAM_MIPI_ID0) {
10710 if ((intstat & (CSI_FRAME1_START_ID0 | CSI_FRAME0_START_ID0)) == 0 &&
10711 detect_stream->fs_cnt_in_single_frame > 1) {
10712 cif_dev->err_state |= RKCIF_ERR_ID0_MULTI_FS;
10713 detect_stream->is_fs_fe_not_paired = true;
10714 detect_stream->fs_cnt_in_single_frame = 0;
10715 } else {
10716 detect_stream->fs_cnt_in_single_frame--;
10717 }
10718 }
10719 cif_dev->irq_stats.frm_end_cnt[stream->id]++;
10720 }
10721 for (i = 0; i < RKCIF_MAX_STREAM_MIPI; i++) {
10722 if (intstat & CSI_START_INTSTAT(i)) {
10723 stream = &cif_dev->stream[i];
10724 if (i == 0) {
10725 rkcif_deal_sof(cif_dev);
10726 } else {
10727 spin_lock_irqsave(&stream->fps_lock, flags);
10728 stream->readout.fs_timestamp = ktime_get_ns();
10729 stream->frame_idx++;
10730 spin_unlock_irqrestore(&stream->fps_lock, flags);
10731 }
10732 stream->is_in_vblank = false;
10733 }
10734 if (intstat & CSI_LINE_INTSTAT(i)) {
10735 stream = &cif_dev->stream[i];
10736 if (stream->is_line_inten) {
10737 stream->line_int_cnt++;
10738 rkcif_line_wake_up(stream, stream->id);
10739 rkcif_modify_line_int(stream, false);
10740 stream->is_line_inten = false;
10741 }
10742 v4l2_dbg(3, rkcif_debug, &cif_dev->v4l2_dev,
10743 "%s: id0 cur line:%d\n", __func__, lastline & 0x3fff);
10744 }
10745 }
10746 } else {
10747 u32 lastline, lastpix, ctl;
10748 u32 cif_frmst, frmid, int_en;
10749 struct rkcif_stream *stream;
10750 int ch_id;
10751
10752 intstat = rkcif_read_register(cif_dev, CIF_REG_DVP_INTSTAT);
10753 cif_frmst = rkcif_read_register(cif_dev, CIF_REG_DVP_FRAME_STATUS);
10754 lastline = rkcif_read_register(cif_dev, CIF_REG_DVP_LAST_LINE);
10755 lastline = CIF_FETCH_Y_LAST_LINE(lastline);
10756 lastpix = rkcif_read_register(cif_dev, CIF_REG_DVP_LAST_PIX);
10757 lastpix = CIF_FETCH_Y_LAST_LINE(lastpix);
10758 ctl = rkcif_read_register(cif_dev, CIF_REG_DVP_CTRL);
10759 cif_dev->err_state_work.lastline = lastline;
10760 cif_dev->err_state_work.lastpixel = lastpix;
10761 cif_dev->err_state_work.intstat = intstat;
10762
10763 rkcif_write_register(cif_dev, CIF_REG_DVP_INTSTAT, intstat);
10764
10765 stream = &cif_dev->stream[RKCIF_STREAM_CIF];
10766
10767 if (intstat & BUS_ERR) {
10768 cif_dev->irq_stats.dvp_bus_err_cnt++;
10769 cif_dev->err_state |= RKCIF_ERR_BUS;
10770 }
10771
10772 if (intstat & DVP_ALL_OVERFLOW) {
10773 cif_dev->irq_stats.dvp_overflow_cnt++;
10774 cif_dev->err_state |= RKCIF_ERR_OVERFLOW;
10775 }
10776
10777 if (intstat & LINE_ERR) {
10778 cif_dev->irq_stats.dvp_line_err_cnt++;
10779 cif_dev->err_state |= RKCIF_ERR_LINE;
10780 }
10781
10782 if (intstat & PIX_ERR) {
10783 cif_dev->irq_stats.dvp_pix_err_cnt++;
10784 cif_dev->err_state |= RKCIF_ERR_PIXEL;
10785 }
10786
10787 if (intstat & INTSTAT_ERR)
10788 cif_dev->irq_stats.all_err_cnt++;
10789
10790 /* There are two irqs enabled:
10791 * - PST_INF_FRAME_END: cif FIFO is ready,
10792 * this is prior to FRAME_END
10793 * - FRAME_END: cif has saved frame to memory,
10794 * a frame ready
10795 */
10796 if ((intstat & PST_INF_FRAME_END)) {
10797 stream = &cif_dev->stream[RKCIF_STREAM_CIF];
10798 if (stream->stopping)
10799 /* To stop CIF ASAP, before FRAME_END irq */
10800 rkcif_write_register(cif_dev, CIF_REG_DVP_CTRL,
10801 ctl & (~ENABLE_CAPTURE));
10802 }
10803
10804 if (cif_dev->chip_id <= CHIP_RK1808_CIF) {
10805
10806 stream = &cif_dev->stream[RKCIF_STREAM_CIF];
10807
10808 if ((intstat & FRAME_END)) {
10809 struct rkcif_buffer *active_buf = NULL;
10810
10811 int_en = rkcif_read_register(cif_dev, CIF_REG_DVP_INTEN);
10812 int_en |= LINE_INT_EN;
10813 rkcif_write_register(cif_dev, CIF_REG_DVP_INTEN, int_en);
10814 cif_dev->dvp_sof_in_oneframe = 0;
10815
10816 if (stream->stopping) {
10817 rkcif_stream_stop(stream);
10818 stream->stopping = false;
10819 rkcif_assign_dummy_buffer(stream);
10820 wake_up(&stream->wq_stopped);
10821 return;
10822 }
10823
10824 frmid = CIF_GET_FRAME_ID(cif_frmst);
10825 if ((cif_frmst == 0xfffd0002) || (cif_frmst == 0xfffe0002)) {
10826 v4l2_info(&cif_dev->v4l2_dev, "frmid:%d, frmstat:0x%x\n",
10827 frmid, cif_frmst);
10828 rkcif_write_register(cif_dev, CIF_REG_DVP_FRAME_STATUS,
10829 FRAME_STAT_CLS);
10830 }
10831
10832 if (lastline != stream->pixm.height ||
10833 (!(cif_frmst & CIF_F0_READY) &&
10834 !(cif_frmst & CIF_F1_READY))) {
10835
10836 cif_dev->dvp_sof_in_oneframe = 1;
10837 v4l2_err(&cif_dev->v4l2_dev,
10838 "Bad frame, pp irq:0x%x frmst:0x%x size:%dx%d\n",
10839 intstat, cif_frmst, lastpix, lastline);
10840 return;
10841 }
10842
10843 if (cif_frmst & CIF_F0_READY) {
10844 if (stream->curr_buf)
10845 active_buf = stream->curr_buf;
10846 stream->frame_phase = CIF_CSI_FRAME0_READY;
10847 } else if (cif_frmst & CIF_F1_READY) {
10848 if (stream->next_buf)
10849 active_buf = stream->next_buf;
10850 stream->frame_phase = CIF_CSI_FRAME1_READY;
10851 }
10852
10853 spin_lock_irqsave(&stream->fps_lock, flags);
10854 if (stream->frame_phase & CIF_CSI_FRAME0_READY)
10855 stream->fps_stats.frm0_timestamp = ktime_get_ns();
10856 else if (stream->frame_phase & CIF_CSI_FRAME1_READY)
10857 stream->fps_stats.frm1_timestamp = ktime_get_ns();
10858 spin_unlock_irqrestore(&stream->fps_lock, flags);
10859
10860 ret = rkcif_assign_new_buffer_oneframe(stream,
10861 RKCIF_YUV_ADDR_STATE_UPDATE);
10862
10863 if (active_buf && (!ret)) {
10864 active_buf->vb.sequence = stream->frame_idx;
10865 rkcif_vb_done_tasklet(stream, active_buf);
10866 }
10867 stream->frame_idx++;
10868 cif_dev->irq_stats.frm_end_cnt[stream->id]++;
10869 }
10870 } else {
10871 for (i = 0; i < RKCIF_MAX_STREAM_DVP; i++) {
10872 ch_id = rkcif_dvp_g_ch_id(&cif_dev->v4l2_dev, &intstat, cif_frmst);
10873
10874 if (ch_id < 0)
10875 continue;
10876
10877 if (ch_id == RKCIF_STREAM_MIPI_ID0) {
10878 int_en = rkcif_read_register(cif_dev, CIF_REG_DVP_INTEN);
10879 int_en |= LINE_INT_EN;
10880 rkcif_write_register(cif_dev, CIF_REG_DVP_INTEN, int_en);
10881 cif_dev->dvp_sof_in_oneframe = 0;
10882 }
10883
10884 stream = &cif_dev->stream[ch_id];
10885
10886 if (stream->stopping) {
10887 rkcif_stream_stop(stream);
10888 stream->stopping = false;
10889 wake_up(&stream->wq_stopped);
10890 continue;
10891 }
10892
10893 if (stream->state != RKCIF_STATE_STREAMING)
10894 continue;
10895
10896 switch (ch_id) {
10897 case RKCIF_STREAM_MIPI_ID0:
10898 stream->frame_phase = DVP_FRM_STS_ID0(cif_frmst);
10899 break;
10900 case RKCIF_STREAM_MIPI_ID1:
10901 stream->frame_phase = DVP_FRM_STS_ID1(cif_frmst);
10902 break;
10903 case RKCIF_STREAM_MIPI_ID2:
10904 stream->frame_phase = DVP_FRM_STS_ID2(cif_frmst);
10905 break;
10906 case RKCIF_STREAM_MIPI_ID3:
10907 stream->frame_phase = DVP_FRM_STS_ID3(cif_frmst);
10908 break;
10909 }
10910
10911
10912 frmid = CIF_GET_FRAME_ID(cif_frmst);
10913 if ((frmid == 0xfffd) || (frmid == 0xfffe)) {
10914 v4l2_info(&cif_dev->v4l2_dev, "frmid:%d, frmstat:0x%x\n",
10915 frmid, cif_frmst);
10916 rkcif_write_register(cif_dev, CIF_REG_DVP_FRAME_STATUS,
10917 FRAME_STAT_CLS);
10918 }
10919 rkcif_update_stream(cif_dev, stream, ch_id);
10920 cif_dev->irq_stats.frm_end_cnt[stream->id]++;
10921 }
10922 }
10923
10924 if ((intstat & LINE_INT_END) && !(intstat & FRAME_END) &&
10925 (cif_dev->dvp_sof_in_oneframe == 0)) {
10926 if ((intstat & (PRE_INF_FRAME_END | PST_INF_FRAME_END)) == 0x0) {
10927 if ((intstat & INTSTAT_ERR) == 0x0) {
10928 rkcif_deal_sof(cif_dev);
10929 int_en = rkcif_read_register(cif_dev, CIF_REG_DVP_INTEN);
10930 int_en &= ~LINE_INT_EN;
10931 rkcif_write_register(cif_dev, CIF_REG_DVP_INTEN, int_en);
10932 cif_dev->dvp_sof_in_oneframe = 1;
10933 }
10934 }
10935 }
10936
10937 if (stream->crop_dyn_en)
10938 rkcif_dynamic_crop(stream);
10939 }
10940 }
10941
rkcif_irq_lite_lvds(struct rkcif_device * cif_dev)10942 void rkcif_irq_lite_lvds(struct rkcif_device *cif_dev)
10943 {
10944 struct rkcif_stream *stream;
10945 struct v4l2_mbus_config *mbus = &cif_dev->active_sensor->mbus;
10946 unsigned int intstat, i = 0xff;
10947
10948 if (mbus->type == V4L2_MBUS_CCP2 &&
10949 cif_dev->chip_id == CHIP_RV1126_CIF_LITE) {
10950 int mipi_id;
10951 u32 lastline = 0;
10952
10953 intstat = rkcif_read_register(cif_dev, CIF_REG_MIPI_LVDS_INTSTAT);
10954 lastline = rkcif_read_register(cif_dev, CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID0_1);
10955 cif_dev->err_state_work.lastline = lastline;
10956 cif_dev->err_state_work.intstat = intstat;
10957
10958 /* clear all interrupts that has been triggered */
10959 rkcif_write_register(cif_dev, CIF_REG_MIPI_LVDS_INTSTAT, intstat);
10960
10961 if (intstat & CSI_FIFO_OVERFLOW) {
10962 v4l2_err(&cif_dev->v4l2_dev,
10963 "ERROR: cif lite lvds fifo overflow, intstat:0x%x, lastline:%d!!\n",
10964 intstat, lastline);
10965 return;
10966 }
10967
10968 if (intstat & CSI_BANDWIDTH_LACK) {
10969 v4l2_err(&cif_dev->v4l2_dev,
10970 "ERROR: cif lite lvds bandwidth lack, intstat:0x%x!!\n",
10971 intstat);
10972 return;
10973 }
10974
10975 if (intstat & CSI_ALL_ERROR_INTEN) {
10976 v4l2_err(&cif_dev->v4l2_dev,
10977 "ERROR: cif lite lvds all err:0x%x!!\n", intstat);
10978 return;
10979 }
10980
10981 for (i = 0; i < RKCIF_MAX_STREAM_MIPI; i++) {
10982 mipi_id = rkcif_csi_g_mipi_id(&cif_dev->v4l2_dev,
10983 intstat);
10984 if (mipi_id < 0)
10985 continue;
10986
10987 stream = &cif_dev->stream[mipi_id];
10988
10989 if (stream->stopping) {
10990 rkcif_stream_stop(stream);
10991 stream->stopping = false;
10992 wake_up(&stream->wq_stopped);
10993 continue;
10994 }
10995
10996 if (stream->state != RKCIF_STATE_STREAMING)
10997 continue;
10998
10999 switch (mipi_id) {
11000 case RKCIF_STREAM_MIPI_ID0:
11001 stream->frame_phase = SW_FRM_END_ID0(intstat);
11002 intstat &= ~CSI_FRAME_END_ID0;
11003 break;
11004 case RKCIF_STREAM_MIPI_ID1:
11005 stream->frame_phase = SW_FRM_END_ID1(intstat);
11006 intstat &= ~CSI_FRAME_END_ID1;
11007 break;
11008 case RKCIF_STREAM_MIPI_ID2:
11009 stream->frame_phase = SW_FRM_END_ID2(intstat);
11010 intstat &= ~CSI_FRAME_END_ID2;
11011 break;
11012 case RKCIF_STREAM_MIPI_ID3:
11013 stream->frame_phase = SW_FRM_END_ID3(intstat);
11014 intstat &= ~CSI_FRAME_END_ID3;
11015 break;
11016 }
11017
11018 rkcif_update_stream(cif_dev, stream, mipi_id);
11019 rkcif_monitor_reset_event(cif_dev);
11020 cif_dev->irq_stats.frm_end_cnt[stream->id]++;
11021 }
11022
11023 if (intstat & CSI_FRAME0_START_ID0)
11024 rkcif_lvds_event_inc_sof(cif_dev);
11025
11026 if (intstat & CSI_FRAME1_START_ID0)
11027 rkcif_lvds_event_inc_sof(cif_dev);
11028 }
11029 }
11030
rkcif_sditf_disconnect(struct video_device * vdev)11031 int rkcif_sditf_disconnect(struct video_device *vdev)
11032 {
11033 struct rkcif_vdev_node *vnode = vdev_to_node(vdev);
11034 struct rkcif_stream *stream = to_rkcif_stream(vnode);
11035 struct rkcif_device *cifdev = stream->cifdev;
11036 struct media_link *link;
11037 int ret;
11038
11039 link = list_first_entry(&cifdev->sditf[0]->sd.entity.links, struct media_link, list);
11040 ret = media_entity_setup_link(link, 0);
11041 if (ret)
11042 dev_err(cifdev->dev, "failed to disable link of sditf with isp");
11043
11044 return ret;
11045 }
11046 EXPORT_SYMBOL(rkcif_sditf_disconnect);
11047