1 /* 2 * Copyright 2020 Rockchip Electronics Co. LTD 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef __HAL_VP9D_REG_H__ 18 #define __HAL_VP9D_REG_H__ 19 20 #include "rk_type.h" 21 22 typedef struct { 23 struct { 24 RK_U32 minor_ver : 8; 25 RK_U32 level : 1; 26 RK_U32 dec_support : 3; 27 RK_U32 profile : 1; 28 RK_U32 reserve0 : 1; 29 RK_U32 codec_flag : 1; 30 RK_U32 reserve1 : 1; 31 RK_U32 prod_num : 16; 32 } swreg0_id; 33 34 struct { 35 RK_U32 sw_dec_e : 1;//0 36 RK_U32 sw_dec_clkgate_e : 1; // 1 37 RK_U32 reserve0 : 1;// 2 38 RK_U32 sw_timeout_mode : 1; // 3 39 RK_U32 sw_dec_irq_dis : 1;//4 // 4 40 RK_U32 sw_dec_timeout_e : 1; //5 41 RK_U32 sw_buf_empty_en : 1; // 6 42 RK_U32 sw_stmerror_waitdecfifo_empty : 1; // 7 43 RK_U32 sw_dec_irq : 1; // 8 44 RK_U32 sw_dec_irq_raw : 1; // 9 45 RK_U32 reserve2 : 2; 46 RK_U32 sw_dec_rdy_sta : 1; //12 47 RK_U32 sw_dec_bus_sta : 1; //13 48 RK_U32 sw_dec_error_sta : 1; // 14 49 RK_U32 sw_dec_timeout_sta : 1; //15 50 RK_U32 sw_dec_empty_sta : 1; // 16 51 RK_U32 sw_colmv_ref_error_sta : 1; // 17 52 RK_U32 sw_cabu_end_sta : 1; // 18 53 RK_U32 sw_h264orvp9_error_mode : 1; //19 54 RK_U32 sw_softrst_en_p : 1; //20 55 RK_U32 sw_force_softreset_valid : 1; //21 56 RK_U32 sw_softreset_rdy : 1; // 22 57 } swreg1_int; 58 59 struct { 60 RK_U32 sw_in_endian : 1; 61 RK_U32 sw_in_swap32_e : 1; 62 RK_U32 sw_in_swap64_e : 1; 63 RK_U32 sw_str_endian : 1; 64 RK_U32 sw_str_swap32_e : 1; 65 RK_U32 sw_str_swap64_e : 1; 66 RK_U32 sw_out_endian : 1; 67 RK_U32 sw_out_swap32_e : 1; 68 RK_U32 sw_out_cbcr_swap : 1; 69 RK_U32 reserve0 : 1; 70 RK_U32 sw_rlc_mode_direct_write : 1; 71 RK_U32 sw_rlc_mode : 1; 72 RK_U32 sw_strm_start_bit : 7; 73 RK_U32 reserve1 : 1; 74 RK_U32 sw_dec_mode : 2; 75 RK_U32 reserve2 : 2; 76 RK_U32 sw_h264_rps_mode : 1; 77 RK_U32 sw_h264_stream_mode : 1; 78 RK_U32 sw_h264_stream_lastpacket : 1; 79 RK_U32 sw_h264_firstslice_flag : 1; 80 RK_U32 sw_h264_frame_orslice : 1; 81 RK_U32 sw_buspr_slot_disable : 1; 82 RK_U32 reserve3 : 2; 83 } swreg2_sysctrl; 84 85 struct { 86 RK_U32 sw_y_hor_virstride : 9; 87 RK_U32 reserve : 2; 88 RK_U32 sw_slice_num_highbit : 1; 89 RK_U32 sw_uv_hor_virstride : 9; 90 RK_U32 sw_slice_num_lowbits : 11; 91 } swreg3_picpar; 92 93 RK_U32 swreg4_strm_rlc_base; 94 RK_U32 swreg5_stream_len; 95 RK_U32 swreg6_cabactbl_prob_base; 96 RK_U32 swreg7_decout_base; 97 98 struct { 99 RK_U32 sw_y_virstride : 20; 100 RK_U32 reverse0 : 12; 101 } swreg8_y_virstride; 102 103 struct { 104 RK_U32 sw_yuv_virstride : 21; 105 RK_U32 reverse : 11; 106 } swreg9_yuv_virstride; 107 108 109 //only for vp9 110 struct { 111 RK_U32 sw_vp9_cprheader_offset : 16; 112 RK_U32 reverse : 16; 113 } swreg10_vp9_cprheader_offset; 114 115 RK_U32 swreg11_vp9_referlast_base; 116 RK_U32 swreg12_vp9_refergolden_base; 117 RK_U32 swreg13_vp9_referalfter_base; 118 RK_U32 swreg14_vp9_count_base; 119 RK_U32 swreg15_vp9_segidlast_base; 120 RK_U32 swreg16_vp9_segidcur_base; 121 122 struct { 123 RK_U32 sw_framewidth_last : 16; 124 RK_U32 sw_frameheight_last : 16; 125 } swreg17_vp9_frame_size_last; 126 127 struct { 128 RK_U32 sw_framewidth_golden : 16; 129 RK_U32 sw_frameheight_golden : 16; 130 } swreg18_vp9_frame_size_golden; 131 132 133 struct { 134 RK_U32 sw_framewidth_alfter : 16; 135 RK_U32 sw_frameheight_alfter : 16; 136 } swreg19_vp9_frame_size_altref; 137 138 139 struct { 140 RK_U32 sw_vp9segid_abs_delta : 1; //NOTE: only in reg#20, this bit is valid. 141 RK_U32 sw_vp9segid_frame_qp_delta_en : 1; 142 RK_U32 sw_vp9segid_frame_qp_delta : 9; 143 RK_U32 sw_vp9segid_frame_loopfitler_value_en : 1; 144 RK_U32 sw_vp9segid_frame_loopfilter_value : 7; 145 RK_U32 sw_vp9segid_referinfo_en : 1; 146 RK_U32 sw_vp9segid_referinfo : 2; 147 RK_U32 sw_vp9segid_frame_skip_en : 1; 148 RK_U32 reverse : 9; 149 } swreg20_27_vp9_segid_grp[8]; 150 151 152 struct { 153 RK_U32 sw_vp9_tx_mode : 3; 154 RK_U32 sw_vp9_frame_reference_mode : 2; 155 RK_U32 reserved : 27; 156 } swreg28_vp9_cprheader_config; 157 158 159 struct { 160 RK_U32 sw_vp9_lref_hor_scale : 16; 161 RK_U32 sw_vp9_lref_ver_scale : 16; 162 } swreg29_vp9_lref_scale; 163 164 struct { 165 RK_U32 sw_vp9_gref_hor_scale : 16; 166 RK_U32 sw_vp9_gref_ver_scale : 16; 167 } swreg30_vp9_gref_scale; 168 169 struct { 170 RK_U32 sw_vp9_aref_hor_scale : 16; 171 RK_U32 sw_vp9_aref_ver_scale : 16; 172 } swreg31_vp9_aref_scale; 173 174 struct { 175 RK_U32 sw_vp9_ref_deltas_lastframe : 28; 176 RK_U32 reserve : 4; 177 } swreg32_vp9_ref_deltas_lastframe; 178 179 struct { 180 RK_U32 sw_vp9_mode_deltas_lastframe : 14; 181 RK_U32 reserve0 : 2; 182 RK_U32 sw_segmentation_enable_lstframe : 1; 183 RK_U32 sw_vp9_last_show_frame : 1; 184 RK_U32 sw_vp9_last_intra_only : 1; 185 RK_U32 sw_vp9_last_widthheight_eqcur : 1; 186 RK_U32 sw_vp9_color_space_lastkeyframe : 3; 187 RK_U32 reserve1 : 9; 188 } swreg33_vp9_info_lastframe; 189 190 RK_U32 swreg34_vp9_intercmd_base; 191 192 struct { 193 RK_U32 sw_vp9_intercmd_num : 24; 194 RK_U32 reserve : 8; 195 } swreg35_vp9_intercmd_num; 196 197 struct { 198 RK_U32 sw_vp9_lasttile_size : 24; 199 RK_U32 reserve : 8; 200 } swreg36_vp9_lasttile_size; 201 202 struct { 203 RK_U32 sw_vp9_lastfy_hor_virstride : 9; 204 RK_U32 reserve0 : 7; 205 RK_U32 sw_vp9_lastfuv_hor_virstride : 9; 206 RK_U32 reserve1 : 7; 207 } swreg37_vp9_lastf_hor_virstride; 208 209 struct { 210 RK_U32 sw_vp9_goldenfy_hor_virstride : 9; 211 RK_U32 reserve0 : 7; 212 RK_U32 sw_vp9_goldenuv_hor_virstride : 9; 213 RK_U32 reserve1 : 7; 214 } swreg38_vp9_goldenf_hor_virstride; 215 216 struct { 217 RK_U32 sw_vp9_altreffy_hor_virstride : 9; 218 RK_U32 reserve0 : 7; 219 RK_U32 sw_vp9_altreffuv_hor_virstride : 9; 220 RK_U32 reserve1 : 7; 221 } swreg39_vp9_altreff_hor_virstride; 222 223 struct { 224 RK_U32 sw_cur_poc : 32; 225 } swreg40_cur_poc; 226 227 struct { 228 RK_U32 reserve : 3; 229 RK_U32 sw_rlcwrite_base : 29; 230 } swreg41_rlcwrite_base; 231 232 struct { 233 RK_U32 reserve : 4; 234 RK_U32 sw_pps_base : 28; 235 } swreg42_pps_base; 236 237 struct { 238 RK_U32 reserve : 4; 239 RK_U32 sw_rps_base : 28; 240 } swreg43_rps_base; 241 242 struct { 243 RK_U32 sw_strmd_error_e : 28; 244 RK_U32 reserve : 4; 245 } swreg44_strmd_error_en; 246 247 struct { 248 RK_U32 vp9_error_info0 : 32; 249 } swreg45_vp9_error_info0; 250 251 struct { 252 RK_U32 sw_strmd_error_ctu_xoffset : 8; 253 RK_U32 sw_strmd_error_ctu_yoffset : 8; 254 RK_U32 sw_streamfifo_space2full : 7; 255 RK_U32 reserve : 1; 256 RK_U32 sw_vp9_error_ctu0_en : 1; 257 } swreg46_strmd_error_ctu; 258 259 struct { 260 RK_U32 sw_saowr_xoffet : 9; 261 RK_U32 reserve : 7; 262 RK_U32 sw_saowr_yoffset : 10; 263 } swreg47_sao_ctu_position; 264 265 struct { 266 RK_U32 sw_vp9_lastfy_virstride : 20; 267 RK_U32 reserve : 12; 268 } swreg48_vp9_last_ystride; 269 270 struct { 271 RK_U32 sw_vp9_goldeny_virstride : 20; 272 RK_U32 reserve : 12; 273 } swreg49_vp9_golden_ystride; 274 275 struct { 276 RK_U32 sw_vp9_altrefy_virstride : 20; 277 RK_U32 reserve : 12; 278 } swreg50_vp9_altrefy_ystride; 279 280 struct { 281 RK_U32 sw_vp9_lastref_yuv_virstride : 21; 282 RK_U32 reserve : 11; 283 } swreg51_vp9_lastref_yuvstride; 284 285 286 RK_U32 swreg52_vp9_refcolmv_base; 287 288 RK_U32 reg_not_use0[64 - 52 - 1]; 289 290 struct { 291 RK_U32 sw_performance_cycle : 32; 292 } swreg64_performance_cycle; 293 294 struct { 295 RK_U32 sw_axi_ddr_rdata : 32; 296 } swreg65_axi_ddr_rdata; 297 298 struct { 299 RK_U32 sw_axi_ddr_wdata : 32; 300 } swreg66_axi_ddr_wdata; 301 302 struct { 303 RK_U32 sw_busifd_resetn : 1; 304 RK_U32 sw_cabac_resetn : 1; 305 RK_U32 sw_dec_ctrl_resetn : 1; 306 RK_U32 sw_transd_resetn : 1; 307 RK_U32 sw_intra_resetn : 1; 308 RK_U32 sw_inter_resetn : 1; 309 RK_U32 sw_recon_resetn : 1; 310 RK_U32 sw_filer_resetn : 1; 311 } swreg67_fpgadebug_reset; 312 313 struct { 314 RK_U32 perf_cnt0_sel : 6; 315 RK_U32 reserve0 : 2; 316 RK_U32 perf_cnt1_sel : 6; 317 RK_U32 reserve1 : 2; 318 RK_U32 perf_cnt2_sel : 6; 319 } swreg68_performance_sel; 320 321 struct { 322 RK_U32 perf_cnt0 : 32; 323 } swreg69_performance_cnt0; 324 325 struct { 326 RK_U32 perf_cnt1 : 32; 327 } swreg70_performance_cnt1; 328 329 struct { 330 RK_U32 perf_cnt2 : 32; 331 } swreg71_performance_cnt2; 332 333 RK_U32 reg_not_use1[74 - 71 - 1]; 334 335 struct { 336 RK_U32 sw_h264_cur_poc1 : 32; 337 } swreg74_h264_cur_poc1; 338 339 struct { 340 RK_U32 vp9_error_info1 : 32; 341 } swreg75_vp9_error_info1; 342 343 struct { 344 RK_U32 vp9_error_ctu1_x : 6; 345 RK_U32 reserve0 : 2; 346 RK_U32 vp9_error_ctu1_y : 6; 347 RK_U32 reserve1 : 1; 348 RK_U32 vp9_error_ctu1_en : 1; 349 RK_U32 reserve2 : 16; 350 } swreg76_vp9_error_ctu1; 351 352 RK_U32 reg_not_use2; 353 } VP9_REGS; 354 355 #endif 356