1 /* 2 * Copyright 2020 Rockchip Electronics Co. LTD 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef __HAL_AV1D_VDPU_REG_H__ 18 #define __HAL_AV1D_VDPU_REG_H__ 19 20 #include "mpp_device.h" 21 22 /* swreg64 - swreg183 */ 23 typedef struct VdpuAv1dBase_t { 24 struct { 25 RK_U32 sw_dec_out_ybase_msb : 32; 26 } swreg64; 27 28 struct { 29 RK_U32 sw_dec_out_ybase_lsb : 32; 30 } swreg65; 31 32 struct { 33 RK_U32 sw_refer0_ybase_msb : 32; 34 } swreg66; 35 36 struct { 37 RK_U32 sw_refer0_ybase_lsb : 32; 38 } swreg67; 39 40 struct { 41 RK_U32 sw_refer1_ybase_msb : 32; 42 } swreg68; 43 44 struct { 45 RK_U32 sw_refer1_ybase_lsb : 32; 46 } swreg69; 47 48 struct { 49 RK_U32 sw_refer2_ybase_msb : 32; 50 } swreg70; 51 52 struct { 53 RK_U32 sw_refer2_ybase_lsb : 32; 54 } swreg71; 55 56 struct { 57 RK_U32 sw_refer3_ybase_msb : 32; 58 } swreg72; 59 60 struct { 61 RK_U32 sw_refer3_ybase_lsb : 32; 62 } swreg73; 63 64 struct { 65 RK_U32 sw_refer4_ybase_msb : 32; 66 } swreg74; 67 68 struct { 69 RK_U32 sw_refer4_ybase_lsb : 32; 70 } swreg75; 71 72 struct { 73 RK_U32 sw_refer5_ybase_msb : 32; 74 } swreg76; 75 76 struct { 77 RK_U32 sw_refer5_ybase_lsb : 32; 78 } swreg77; 79 80 struct { 81 RK_U32 sw_refer6_ybase_msb : 32; 82 } swreg78; 83 84 struct { 85 RK_U32 sw_refer6_ybase_lsb : 32; 86 } swreg79; 87 88 struct { 89 RK_U32 sw_segment_read_base_msb : 32; 90 } swreg80; 91 92 struct { 93 RK_U32 sw_segment_read_base_lsb : 32; 94 } swreg81; 95 96 struct { 97 RK_U32 sw_global_model_base_msb : 32; 98 } swreg82; 99 100 struct { 101 RK_U32 sw_global_model_base_lsb : 32; 102 } swreg83; 103 104 struct { 105 RK_U32 sw_cdef_colbuf_base_msb : 32; 106 } swreg84; 107 108 struct { 109 RK_U32 sw_cdef_colbuf_base_lsb : 32; 110 } swreg85; 111 112 struct { 113 RK_U32 sw_cdef_left_colbuf_base_msb : 32; 114 } swreg86; 115 116 struct { 117 RK_U32 sw_cdef_left_colbuf_base_lsb : 32; 118 } swreg87; 119 120 struct { 121 RK_U32 sw_superres_colbuf_base_msb : 32; 122 } swreg88; 123 124 struct { 125 RK_U32 sw_superres_colbuf_base_lsb : 32; 126 } swreg89; 127 128 struct { 129 RK_U32 sw_lr_colbuf_base_msb : 32; 130 } swreg90; 131 132 struct { 133 RK_U32 sw_lr_colbuf_base_lsb : 32; 134 } swreg91; 135 136 struct { 137 RK_U32 sw_superres_left_colbuf_base_msb : 32; 138 } swreg92; 139 140 struct { 141 RK_U32 sw_superres_left_colbuf_base_lsb : 32; 142 } swreg93; 143 144 struct { 145 RK_U32 sw_filmgrain_base_msb : 32; 146 } swreg94; 147 148 struct { 149 RK_U32 sw_filmgrain_base_lsb : 32; 150 } swreg95; 151 152 struct { 153 RK_U32 sw_lr_left_colbuf_base_msb : 32; 154 } swreg96; 155 156 struct { 157 RK_U32 sw_lr_left_colbuf_base_lsb : 32; 158 } swreg97; 159 160 struct { 161 RK_U32 sw_dec_out_cbase_msb : 32; 162 } swreg98; 163 164 struct { 165 RK_U32 sw_dec_out_cbase_lsb : 32; 166 } swreg99; 167 168 struct { 169 RK_U32 sw_refer0_cbase_msb : 32; 170 } swreg100; 171 172 struct { 173 RK_U32 sw_refer0_cbase_lsb : 32; 174 } swreg101; 175 176 struct { 177 RK_U32 sw_refer1_cbase_msb : 32; 178 } swreg102; 179 180 struct { 181 RK_U32 sw_refer1_cbase_lsb : 32; 182 } swreg103; 183 184 struct { 185 RK_U32 sw_refer2_cbase_msb : 32; 186 } swreg104; 187 188 struct { 189 RK_U32 sw_refer2_cbase_lsb : 32; 190 } swreg105; 191 192 struct { 193 RK_U32 sw_refer3_cbase_msb : 32; 194 } swreg106; 195 196 struct { 197 RK_U32 sw_refer3_cbase_lsb : 32; 198 } swreg107; 199 200 struct { 201 RK_U32 sw_refer4_cbase_msb : 32; 202 } swreg108; 203 204 struct { 205 RK_U32 sw_refer4_cbase_lsb : 32; 206 } swreg109; 207 208 struct { 209 RK_U32 sw_refer5_cbase_msb : 32; 210 } swreg110; 211 212 struct { 213 RK_U32 sw_refer5_cbase_lsb : 32; 214 } swreg111; 215 216 struct { 217 RK_U32 sw_refer6_cbase_msb : 32; 218 } swreg112; 219 220 struct { 221 RK_U32 sw_refer6_cbase_lsb : 32; 222 } swreg113; 223 224 struct { 225 RK_U32 sw_dec_left_vert_filt_base_msb : 32; 226 } swreg114; 227 228 struct { 229 RK_U32 sw_dec_left_vert_filt_base_lsb : 32; 230 } swreg115; 231 232 struct { 233 RK_U32 sw_dec_left_bsd_ctrl_base_msb : 32; 234 } swreg116; 235 236 struct { 237 RK_U32 sw_dec_left_bsd_ctrl_base_lsb : 32; 238 } swreg117; 239 240 RK_U32 reserved_118_131[14]; 241 struct { 242 RK_U32 sw_dec_out_dbase_msb : 32; 243 } swreg132; 244 245 struct { 246 RK_U32 sw_dec_out_dbase_lsb : 32; 247 } swreg133; 248 249 struct { 250 RK_U32 sw_refer0_dbase_msb : 32; 251 } swreg134; 252 253 struct { 254 RK_U32 sw_refer0_dbase_lsb : 32; 255 } swreg135; 256 257 struct { 258 RK_U32 sw_refer1_dbase_msb : 32; 259 } swreg136; 260 261 struct { 262 RK_U32 sw_refer1_dbase_lsb : 32; 263 } swreg137; 264 265 struct { 266 RK_U32 sw_refer2_dbase_msb : 32; 267 } swreg138; 268 269 struct { 270 RK_U32 sw_refer2_dbase_lsb : 32; 271 } swreg139; 272 273 struct { 274 RK_U32 sw_refer3_dbase_msb : 32; 275 } swreg140; 276 277 struct { 278 RK_U32 sw_refer3_dbase_lsb : 32; 279 } swreg141; 280 281 struct { 282 RK_U32 sw_refer4_dbase_msb : 32; 283 } swreg142; 284 285 struct { 286 RK_U32 sw_refer4_dbase_lsb : 32; 287 } swreg143; 288 289 struct { 290 RK_U32 sw_refer5_dbase_msb : 32; 291 } swreg144; 292 293 struct { 294 RK_U32 sw_refer5_dbase_lsb : 32; 295 } swreg145; 296 297 struct { 298 RK_U32 sw_refer6_dbase_msb : 32; 299 } swreg146; 300 301 struct { 302 RK_U32 sw_refer6_dbase_lsb : 32; 303 } swreg147; 304 305 RK_U32 reserved_148_165[18]; 306 struct { 307 RK_U32 sw_tile_base_msb : 32; 308 } swreg166; 309 310 struct { 311 RK_U32 sw_tile_base_lsb : 32; 312 } swreg167; 313 314 struct { 315 RK_U32 sw_stream_base_msb : 32; 316 } swreg168; 317 318 struct { 319 RK_U32 sw_stream_base_lsb : 32; 320 } swreg169; 321 322 struct { 323 RK_U32 sw_prob_tab_out_base_msb : 32; 324 } swreg170; 325 326 struct { 327 RK_U32 sw_prob_tab_out_base_lsb : 32; 328 } swreg171; 329 330 struct { 331 RK_U32 sw_prob_tab_base_msb : 32; 332 } swreg172; 333 334 struct { 335 RK_U32 sw_prob_tab_base_lsb : 32; 336 } swreg173; 337 338 struct { 339 RK_U32 sw_mc_sync_curr_base_msb : 32; 340 } swreg174; 341 342 struct { 343 RK_U32 sw_mc_sync_curr_base_lsb : 32; 344 } swreg175; 345 346 struct { 347 RK_U32 sw_mc_sync_left_base_msb : 32; 348 } swreg176; 349 350 struct { 351 RK_U32 sw_mc_sync_left_base_lsb : 32; 352 } swreg177; 353 354 struct { 355 RK_U32 sw_dec_vert_filt_base_msb : 32; 356 } swreg178; 357 358 struct { 359 RK_U32 sw_dec_vert_filt_base_lsb : 32; 360 } swreg179; 361 362 RK_U32 reserved_180_181[2]; 363 struct { 364 RK_U32 sw_dec_bsd_ctrl_base_msb : 32; 365 } swreg182; 366 367 struct { 368 RK_U32 sw_dec_bsd_ctrl_base_lsb : 32; 369 } swreg183; 370 } VdpuAv1dBase; 371 372 /* swreg320 - swreg511 */ 373 typedef struct VdpuAv1dPPCfg_t { 374 375 struct { 376 RK_U32 sw_pp_out_e : 1; 377 RK_U32 sw_pp_cr_first : 1; 378 RK_U32 sw_pp_out_mode : 1; 379 RK_U32 sw_pp_out_tile_e : 1; 380 RK_U32 sw_pp_status : 4; 381 RK_U32 sw_pp_in_blk_size : 3; 382 RK_U32 sw_pp_out_p010_fmt : 2; 383 RK_U32 sw_pp_out_rgb_fmt : 5; 384 RK_U32 sw_rgb_range_max : 12; 385 RK_U32 sw_pp_rgb_planar : 1; 386 RK_U32 reserved0 : 1; 387 } swreg320; 388 389 struct { 390 RK_U32 sw_rgb_range_min : 9; 391 RK_U32 sw_pp_tile_size : 2; 392 RK_U32 reserved0 : 5; 393 RK_U32 sw_pp_in_swap : 4; 394 RK_U32 sw_pp_out_swap : 4; 395 RK_U32 sw_pp_in_a1_swap : 4; 396 RK_U32 sw_pp_in_a2_swap : 4; 397 } swreg321; 398 399 struct { 400 RK_U32 sw_scale_hratio : 18; 401 RK_U32 sw_pp_out_format : 5; 402 RK_U32 sw_ver_scale_mode : 2; 403 RK_U32 sw_hor_scale_mode : 2; 404 RK_U32 sw_pp_in_format : 5; 405 } swreg322; 406 407 struct { 408 RK_U32 sw_scale_wratio : 18; 409 RK_U32 sw_rangemap_coef_c : 5; 410 RK_U32 sw_rangemap_coef_y : 5; 411 RK_U32 sw_pp_vc1_adv_e : 1; 412 RK_U32 sw_ycbcr_range : 1; 413 RK_U32 sw_rangemap_c_e : 1; 414 RK_U32 sw_rangemap_y_e : 1; 415 } swreg323; 416 417 struct { 418 RK_U32 sw_hscale_invra : 16; 419 RK_U32 sw_wscale_invra : 16; 420 } swreg324; 421 422 struct { 423 RK_U32 sw_pp_out_lu_base_msb : 32; 424 } swreg325; 425 426 struct { 427 RK_U32 sw_pp_out_lu_base_lsb : 32; 428 } swreg326; 429 430 struct { 431 RK_U32 sw_pp_out_ch_base_msb : 32; 432 } swreg327; 433 434 struct { 435 RK_U32 sw_pp_out_ch_base_lsb : 32; 436 } swreg328; 437 438 struct { 439 RK_U32 sw_pp_out_c_stride : 16; 440 RK_U32 sw_pp_out_y_stride : 16; 441 } swreg329; 442 443 struct { 444 RK_U32 sw_crop_starty : 13; 445 RK_U32 sw_rotation_mode : 2; 446 RK_U32 reserved0 : 1; 447 RK_U32 sw_crop_startx : 13; 448 RK_U32 sw_flip_mode : 2; 449 RK_U32 sw_pad_sel : 1; 450 } swreg330; 451 452 struct { 453 RK_U32 sw_pp_in_height : 16; 454 RK_U32 sw_pp_in_width : 16; 455 } swreg331; 456 457 struct { 458 RK_U32 sw_pp_out_height : 16; 459 RK_U32 sw_pp_out_width : 16; 460 } swreg332; 461 462 struct { 463 RK_U32 sw_pp_out_lu_bot_base_msb : 32; 464 } swreg333; 465 466 struct { 467 RK_U32 sw_pp_out_lu_bot_base_lsb : 32; 468 } swreg334; 469 470 struct { 471 RK_U32 sw_pp_crop2_starty : 13; 472 RK_U32 reserved0 : 3; 473 RK_U32 sw_pp_crop2_startx : 13; 474 RK_U32 reserved1 : 3; 475 // RK_U32 sw_pp_out_ch_bot_base_msb : 32; 476 } swreg335; 477 478 struct { 479 RK_U32 sw_pp_crop2_out_height : 16; 480 RK_U32 sw_pp_crop2_out_width : 16; 481 // RK_U32 sw_pp_out_ch_bot_base_lsb : 32; 482 } swreg336; 483 484 struct { 485 RK_U32 sw_pp_in_c_stride : 16; 486 RK_U32 sw_pp_in_y_stride : 16; 487 } swreg337; 488 489 struct { 490 RK_U32 sw_pp_in_lu_base_msb : 32; 491 } swreg338; 492 493 struct { 494 RK_U32 sw_pp_in_lu_base_lsb : 32; 495 } swreg339; 496 497 struct { 498 RK_U32 sw_pp_in_ch_base_msb : 32; 499 } swreg340; 500 501 struct { 502 RK_U32 sw_pp_in_ch_base_lsb : 32; 503 } swreg341; 504 505 struct { 506 RK_U32 sw_pp1_out_e : 1; 507 RK_U32 sw_pp1_cr_first : 1; 508 RK_U32 sw_pp1_out_mode : 1; 509 RK_U32 sw_pp1_out_tile_e : 1; 510 RK_U32 reserved0 : 7; 511 RK_U32 sw_pp1_out_p010_fmt : 2; 512 RK_U32 sw_pp1_out_rgb_fmt : 5; 513 RK_U32 reserved1 : 12; 514 RK_U32 sw_pp1_rgb_planar : 1; 515 RK_U32 reserved2 : 1; 516 } swreg342; 517 518 struct { 519 RK_U32 reserved0 : 9; 520 RK_U32 sw_pp1_tile_size : 2; 521 RK_U32 reserved1 : 9; 522 RK_U32 sw_pp1_out_swap : 4; 523 RK_U32 reserved2 : 8; 524 } swreg343; 525 526 struct { 527 RK_U32 sw_pp1_scale_hratio : 18; 528 RK_U32 sw_pp1_out_format : 5; 529 RK_U32 sw_pp1_ver_scale_mode : 2; 530 RK_U32 sw_pp1_hor_scale_mode : 2; 531 RK_U32 reserved0 : 5; 532 } swreg344; 533 534 struct { 535 RK_U32 sw_pp1_scale_wratio : 18; 536 RK_U32 reserved0 : 14; 537 } swreg345; 538 539 struct { 540 RK_U32 sw_pp1_hscale_invra : 16; 541 RK_U32 sw_pp1_wscale_invra : 16; 542 } swreg346; 543 544 struct { 545 RK_U32 sw_pp1_out_lu_base_msb : 32; 546 } swreg347; 547 548 struct { 549 RK_U32 sw_pp1_out_lu_base_lsb : 32; 550 } swreg348; 551 552 struct { 553 RK_U32 sw_pp1_out_ch_base_msb : 32; 554 } swreg349; 555 556 struct { 557 RK_U32 sw_pp1_out_ch_base_lsb : 32; 558 } swreg350; 559 560 struct { 561 RK_U32 sw_pp1_out_c_stride : 16; 562 RK_U32 sw_pp1_out_y_stride : 16; 563 } swreg351; 564 565 struct { 566 RK_U32 sw_pp1_crop_starty : 13; 567 RK_U32 sw_pp1_rotation_mode : 2; 568 RK_U32 reserved0 : 1; 569 RK_U32 sw_pp1_crop_startx : 13; 570 RK_U32 sw_pp1_flip_mode : 2; 571 RK_U32 sw_pp1_pad_sel : 1; 572 } swreg352; 573 574 struct { 575 RK_U32 sw_pp1_in_height : 16; 576 RK_U32 sw_pp1_in_width : 16; 577 } swreg353; 578 579 struct { 580 RK_U32 sw_pp1_out_height : 16; 581 RK_U32 sw_pp1_out_width : 16; 582 } swreg354; 583 584 struct { 585 RK_U32 sw_pp1_out_lu_bot_base_msb : 32; 586 } swreg355; 587 588 struct { 589 RK_U32 sw_pp1_out_lu_bot_base_lsb : 32; 590 } swreg356; 591 592 struct { 593 RK_U32 sw_pp1_crop2_starty : 13; 594 RK_U32 reserved0 : 3; 595 RK_U32 sw_pp1_crop2_startx : 13; 596 RK_U32 reserved1 : 3; 597 // RK_U32 sw_pp1_out_ch_bot_base_msb : 32; 598 } swreg357; 599 600 struct { 601 RK_U32 sw_pp1_crop2_out_height : 16; 602 RK_U32 sw_pp1_crop2_out_width : 16; 603 // RK_U32 sw_pp1_out_ch_bot_base_lsb : 32; 604 } swreg358; 605 606 struct { 607 RK_U32 sw_pp2_out_e : 1; 608 RK_U32 sw_pp2_cr_first : 1; 609 RK_U32 sw_pp2_out_mode : 1; 610 RK_U32 sw_pp2_out_tile_e : 1; 611 RK_U32 reserved0 : 7; 612 RK_U32 sw_pp2_out_p010_fmt : 2; 613 RK_U32 sw_pp2_out_rgb_fmt : 5; 614 RK_U32 reserved1 : 12; 615 RK_U32 sw_pp2_rgb_planar : 1; 616 RK_U32 reserved2 : 1; 617 } swreg359; 618 619 struct { 620 RK_U32 reserved0 : 9; 621 RK_U32 sw_pp2_tile_size : 2; 622 RK_U32 reserved1 : 9; 623 RK_U32 sw_pp2_out_swap : 4; 624 RK_U32 reserved2 : 8; 625 } swreg360; 626 627 struct { 628 RK_U32 sw_pp2_scale_hratio : 18; 629 RK_U32 sw_pp2_out_format : 5; 630 RK_U32 sw_pp2_ver_scale_mode : 2; 631 RK_U32 sw_pp2_hor_scale_mode : 2; 632 RK_U32 reserved0 : 5; 633 } swreg361; 634 635 struct { 636 RK_U32 sw_pp2_scale_wratio : 18; 637 RK_U32 reserved0 : 5; 638 RK_U32 reserved1 : 5; 639 RK_U32 reserved2 : 1; 640 RK_U32 reserved4 : 1; 641 RK_U32 reserved3 : 1; 642 RK_U32 reserved5 : 1; 643 } swreg362; 644 645 struct { 646 RK_U32 sw_pp2_hscale_invra : 16; 647 RK_U32 sw_pp2_wscale_invra : 16; 648 } swreg363; 649 650 struct { 651 RK_U32 sw_pp2_out_lu_base_msb : 32; 652 } swreg364; 653 654 struct { 655 RK_U32 sw_pp2_out_lu_base_lsb : 32; 656 } swreg365; 657 658 struct { 659 RK_U32 sw_pp2_out_ch_base_msb : 32; 660 } swreg366; 661 662 struct { 663 RK_U32 sw_pp2_out_ch_base_lsb : 32; 664 } swreg367; 665 666 struct { 667 RK_U32 sw_pp2_out_c_stride : 16; 668 RK_U32 sw_pp2_out_y_stride : 16; 669 } swreg368; 670 671 struct { 672 RK_U32 sw_pp2_crop_starty : 13; 673 RK_U32 sw_pp2_rotation_mode : 2; 674 RK_U32 reserved0 : 1; 675 RK_U32 sw_pp2_crop_startx : 13; 676 RK_U32 sw_pp2_flip_mode : 2; 677 RK_U32 sw_pp2_pad_sel : 1; 678 } swreg369; 679 680 struct { 681 RK_U32 sw_pp2_in_height : 16; 682 RK_U32 sw_pp2_in_width : 16; 683 } swreg370; 684 685 struct { 686 RK_U32 sw_pp2_out_height : 16; 687 RK_U32 sw_pp2_out_width : 16; 688 } swreg371; 689 690 struct { 691 // RK_U32 sw_pp2_out_b_base_msb : 32; 692 RK_U32 sw_pp2_out_lu_bot_base_msb : 32; 693 } swreg372; 694 695 struct { 696 // RK_U32 sw_pp2_out_b_base_lsb : 32; 697 RK_U32 sw_pp2_out_lu_bot_base_lsb : 32; 698 } swreg373; 699 700 struct { 701 RK_U32 sw_pp2_crop2_starty : 13; 702 RK_U32 reserved0 : 3; 703 RK_U32 sw_pp2_crop2_startx : 13; 704 RK_U32 reserved1 : 3; 705 // RK_U32 sw_pp2_out_ch_bot_base_msb : 32; 706 } swreg374; 707 708 struct { 709 RK_U32 sw_pp2_crop2_out_height : 16; 710 RK_U32 sw_pp2_crop2_out_width : 16; 711 // RK_U32 sw_pp2_out_ch_bot_base_lsb : 32; 712 } swreg375; 713 714 struct { 715 RK_U32 sw_pp3_out_e : 1; 716 RK_U32 sw_pp3_cr_first : 1; 717 RK_U32 sw_pp3_out_mode : 1; 718 RK_U32 sw_pp3_out_tile_e : 1; 719 RK_U32 reserved0 : 7; 720 RK_U32 sw_pp3_out_p010_fmt : 2; 721 RK_U32 sw_pp3_out_rgb_fmt : 5; 722 RK_U32 reserved1 : 12; 723 RK_U32 sw_pp3_rgb_planar : 1; 724 RK_U32 reserved2 : 1; 725 } swreg376; 726 727 struct { 728 RK_U32 reserved0 : 9; 729 RK_U32 sw_pp3_tile_size : 2; 730 RK_U32 reserved1 : 9; 731 RK_U32 sw_pp3_out_swap : 4; 732 RK_U32 reserved2 : 8; 733 } swreg377; 734 735 struct { 736 RK_U32 sw_pp3_scale_hratio : 18; 737 RK_U32 sw_pp3_out_format : 5; 738 RK_U32 sw_pp3_ver_scale_mode : 2; 739 RK_U32 sw_pp3_hor_scale_mode : 2; 740 RK_U32 reserved0 : 5; 741 } swreg378; 742 743 struct { 744 RK_U32 sw_pp3_scale_wratio : 18; 745 RK_U32 reserved0 : 5; 746 RK_U32 reserved1 : 5; 747 RK_U32 reserved2 : 1; 748 RK_U32 reserved4 : 1; 749 RK_U32 reserved3 : 1; 750 RK_U32 reserved5 : 1; 751 } swreg379; 752 753 struct { 754 RK_U32 sw_pp3_hscale_invra : 16; 755 RK_U32 sw_pp3_wscale_invra : 16; 756 } swreg380; 757 758 struct { 759 // RK_U32 sw_pp3_out_r_base_msb : 32; 760 RK_U32 sw_pp3_out_lu_base_msb : 32; 761 } swreg381; 762 763 struct { 764 // RK_U32 sw_pp3_out_r_base_lsb : 32; 765 RK_U32 sw_pp3_out_lu_base_lsb : 32; 766 } swreg382; 767 768 struct { 769 // RK_U32 sw_pp3_out_g_base_msb : 32; 770 RK_U32 sw_pp3_out_ch_base_msb : 32; 771 } swreg383; 772 773 struct { 774 // RK_U32 sw_pp3_out_g_base_lsb : 32; 775 RK_U32 sw_pp3_out_ch_base_lsb : 32; 776 } swreg384; 777 778 struct { 779 RK_U32 sw_pp3_out_c_stride : 16; 780 RK_U32 sw_pp3_out_y_stride : 16; 781 } swreg385; 782 783 struct { 784 RK_U32 sw_pp3_crop_starty : 13; 785 RK_U32 sw_pp3_rotation_mode : 2; 786 RK_U32 reserved0 : 1; 787 RK_U32 sw_pp3_crop_startx : 13; 788 RK_U32 sw_pp3_flip_mode : 2; 789 RK_U32 sw_pp3_pad_sel : 1; 790 } swreg386; 791 792 struct { 793 RK_U32 sw_pp3_in_height : 16; 794 RK_U32 sw_pp3_in_width : 16; 795 } swreg387; 796 797 struct { 798 RK_U32 sw_pp3_out_height : 16; 799 RK_U32 sw_pp3_out_width : 16; 800 } swreg388; 801 802 struct { 803 // RK_U32 sw_pp3_out_b_base_msb : 32; 804 RK_U32 sw_pp3_out_lu_bot_base_msb : 32; 805 } swreg389; 806 807 struct { 808 // RK_U32 sw_pp3_out_b_base_lsb : 32; 809 RK_U32 sw_pp3_out_lu_bot_base_lsb : 32; 810 } swreg390; 811 812 struct { 813 RK_U32 sw_pp3_crop2_starty : 13; 814 RK_U32 reserved0 : 3; 815 RK_U32 sw_pp3_crop2_startx : 13; 816 RK_U32 reserved1 : 3; 817 // RK_U32 sw_pp3_out_ch_bot_base_msb : 32; 818 } swreg391; 819 820 struct { 821 RK_U32 sw_pp3_crop2_out_height : 16; 822 RK_U32 sw_pp3_crop2_out_width : 16; 823 // RK_U32 sw_pp3_out_ch_bot_base_lsb : 32; 824 } swreg392; 825 826 struct { 827 RK_U32 sw_pp3_out_alpha : 8; 828 RK_U32 sw_pp2_out_alpha : 8; 829 RK_U32 sw_pp1_out_alpha : 8; 830 RK_U32 sw_pp0_out_alpha : 8; 831 } swreg393; 832 833 struct { 834 RK_U32 sw_pp1_dup_ver : 8; 835 RK_U32 sw_pp1_dup_hor : 8; 836 RK_U32 sw_pp0_dup_ver : 8; 837 RK_U32 sw_pp0_dup_hor : 8; 838 } swreg394; 839 840 struct { 841 RK_U32 sw_pp3_dup_ver : 8; 842 RK_U32 sw_pp3_dup_hor : 8; 843 RK_U32 sw_pp2_dup_ver : 8; 844 RK_U32 sw_pp2_dup_hor : 8; 845 } swreg395; 846 847 struct { 848 RK_U32 sw_pp0_scale1_out_height : 16; 849 RK_U32 sw_pp0_scale1_out_width : 16; 850 } swreg396; 851 852 struct { 853 RK_U32 sw_pp1_scale1_out_height : 16; 854 RK_U32 sw_pp1_scale1_out_width : 16; 855 } swreg397; 856 857 struct { 858 RK_U32 sw_pp2_scale1_out_height : 16; 859 RK_U32 sw_pp2_scale1_out_width : 16; 860 } swreg398; 861 862 struct { 863 RK_U32 sw_pp3_scale1_out_height : 16; 864 RK_U32 sw_pp3_scale1_out_width : 16; 865 } swreg399; 866 867 struct { 868 RK_U32 sw_dec_in_pool_base_msb : 32; 869 } swreg400; 870 871 struct { 872 RK_U32 sw_dec_in_pool_base_lsb : 32; 873 } swreg401; 874 875 struct { 876 RK_U32 sw_dec_in_bufpool_size : 32; 877 } swreg402; 878 879 struct { 880 RK_U32 sw_dec_out_pool_base_msb : 32; 881 } swreg403; 882 883 struct { 884 RK_U32 sw_dec_out_pool_base_lsb : 32; 885 } swreg404; 886 887 struct { 888 RK_U32 sw_dec_out_bufpool_size : 32; 889 } swreg405; 890 891 struct { 892 RK_U32 sw_dec_priv_pool_base_msb : 32; 893 } swreg406; 894 895 struct { 896 RK_U32 sw_dec_priv_pool_base_lsb : 32; 897 } swreg407; 898 899 struct { 900 RK_U32 sw_dec_priv_pool_size : 32; 901 } swreg408; 902 903 struct { 904 RK_U32 sw_dec_in_nsa_id : 4; 905 RK_U32 sw_dec_out_nsa_id : 4; 906 RK_U32 sw_dec_priv_nsa_id : 4; 907 RK_U32 sw_dec_pub_nsa_id : 4; 908 RK_U32 reserved0 : 16; 909 } swreg409; 910 911 struct { 912 RK_U32 sw_contrast_off1 : 12; 913 RK_U32 sw_contrast_off2 : 12; 914 RK_U32 reserved0 : 2; 915 RK_U32 sw_dither_select_b : 2; 916 RK_U32 sw_dither_select_g : 2; 917 RK_U32 sw_dither_select_r : 2; 918 } swreg410; 919 920 struct { 921 RK_U32 sw_color_coefff : 10; 922 RK_U32 sw_contrast_thr2 : 10; 923 RK_U32 sw_contrast_thr1 : 10; 924 RK_U32 reserved0 : 2; 925 } swreg411; 926 927 struct { 928 RK_U32 sw_color_coeffa1 : 16; 929 RK_U32 sw_color_coeffa2 : 16; 930 } swreg412; 931 932 struct { 933 RK_U32 sw_color_coeffb : 16; 934 RK_U32 sw_color_coeffc : 16; 935 } swreg413; 936 937 struct { 938 RK_U32 sw_color_coeffd : 16; 939 RK_U32 sw_color_coeffe : 16; 940 } swreg414; 941 942 struct { 943 RK_U32 sw_pp1_contrast_off1 : 12; 944 RK_U32 sw_pp1_contrast_off2 : 12; 945 RK_U32 reserved0 : 2; 946 RK_U32 sw_pp1_dither_select_b : 2; 947 RK_U32 sw_pp1_dither_select_g : 2; 948 RK_U32 sw_pp1_dither_select_r : 2; 949 } swreg415; 950 951 struct { 952 RK_U32 sw_pp1_color_coefff : 10; 953 RK_U32 sw_pp1_contrast_thr2 : 10; 954 RK_U32 sw_pp1_contrast_thr1 : 10; 955 RK_U32 reserved0 : 2; 956 } swreg416; 957 958 struct { 959 RK_U32 sw_pp1_color_coeffa1 : 16; 960 RK_U32 sw_pp1_color_coeffa2 : 16; 961 } swreg417; 962 963 struct { 964 RK_U32 sw_pp1_color_coeffb : 16; 965 RK_U32 sw_pp1_color_coeffc : 16; 966 } swreg418; 967 968 struct { 969 RK_U32 sw_pp1_color_coeffd : 16; 970 RK_U32 sw_pp1_color_coeffe : 16; 971 } swreg419; 972 973 struct { 974 RK_U32 sw_pp2_contrast_off1 : 12; 975 RK_U32 sw_pp2_contrast_off2 : 12; 976 RK_U32 reserved0 : 2; 977 RK_U32 sw_pp2_dither_select_b : 2; 978 RK_U32 sw_pp2_dither_select_g : 2; 979 RK_U32 sw_pp2_dither_select_r : 2; 980 } swreg420; 981 982 struct { 983 RK_U32 sw_pp2_color_coefff : 10; 984 RK_U32 sw_pp2_contrast_thr2 : 10; 985 RK_U32 sw_pp2_contrast_thr1 : 10; 986 RK_U32 reserved0 : 2; 987 } swreg421; 988 989 struct { 990 RK_U32 sw_pp2_color_coeffa1 : 16; 991 RK_U32 sw_pp2_color_coeffa2 : 16; 992 } swreg422; 993 994 struct { 995 RK_U32 sw_pp2_color_coeffb : 16; 996 RK_U32 sw_pp2_color_coeffc : 16; 997 } swreg423; 998 999 struct { 1000 RK_U32 sw_pp2_color_coeffd : 16; 1001 RK_U32 sw_pp2_color_coeffe : 16; 1002 } swreg424; 1003 1004 struct { 1005 RK_U32 sw_pp3_contrast_off1 : 12; 1006 RK_U32 sw_pp3_contrast_off2 : 12; 1007 RK_U32 reserved0 : 2; 1008 RK_U32 sw_pp3_dither_select_b : 2; 1009 RK_U32 sw_pp3_dither_select_g : 2; 1010 RK_U32 sw_pp3_dither_select_r : 2; 1011 } swreg425; 1012 1013 struct { 1014 RK_U32 sw_pp3_color_coefff : 10; 1015 RK_U32 sw_pp3_contrast_thr2 : 10; 1016 RK_U32 sw_pp3_contrast_thr1 : 10; 1017 RK_U32 reserved0 : 2; 1018 } swreg426; 1019 1020 struct { 1021 RK_U32 sw_pp3_color_coeffa1 : 16; 1022 RK_U32 sw_pp3_color_coeffa2 : 16; 1023 } swreg427; 1024 1025 struct { 1026 RK_U32 sw_pp3_color_coeffb : 16; 1027 RK_U32 sw_pp3_color_coeffc : 16; 1028 } swreg428; 1029 1030 struct { 1031 RK_U32 sw_pp3_color_coeffd : 16; 1032 RK_U32 sw_pp3_color_coeffe : 16; 1033 } swreg429; 1034 1035 struct { 1036 RK_U32 sw_delogo0_h : 10; 1037 RK_U32 sw_delogo0_w : 10; 1038 RK_U32 reserved0 : 8; 1039 RK_U32 sw_delogo0_show_border : 1; 1040 RK_U32 sw_delogo0_mode : 3; 1041 } swreg430; 1042 1043 struct { 1044 RK_U32 sw_delogo0_y : 16; 1045 RK_U32 sw_delogo0_x : 16; 1046 } swreg431; 1047 1048 struct { 1049 RK_U32 sw_delogo0_fillV : 10; 1050 RK_U32 sw_delogo0_fillU : 10; 1051 RK_U32 sw_delogo0_fillY : 10; 1052 RK_U32 reserved0 : 2; 1053 } swreg432; 1054 1055 struct { 1056 RK_U32 sw_delogo1_h : 14; 1057 RK_U32 sw_delogo1_w : 14; 1058 RK_U32 sw_delogo1_show_border : 1; 1059 RK_U32 sw_delogo1_mode : 3; 1060 } swreg433; 1061 1062 struct { 1063 RK_U32 sw_delogo1_y : 16; 1064 RK_U32 sw_delogo1_x : 16; 1065 } swreg434; 1066 1067 struct { 1068 RK_U32 sw_delogo1_fillV : 10; 1069 RK_U32 sw_delogo1_fillU : 10; 1070 RK_U32 sw_delogo1_fillY : 10; 1071 RK_U32 reserved0 : 2; 1072 } swreg435; 1073 1074 struct { 1075 RK_U32 sw_delogo0_ratio_h : 16; 1076 RK_U32 sw_delogo0_ratio_w : 16; 1077 } swreg436; 1078 1079 struct { 1080 RK_U32 sw_pp1_hcale_invra_ext : 8; 1081 RK_U32 sw_pp1_wscale_invra_ext : 8; 1082 RK_U32 sw_pp0_hcale_invra_ext : 8; 1083 RK_U32 sw_pp0_wscale_invra_ext : 8; 1084 } swreg437; 1085 1086 struct { 1087 RK_U32 sw_pp0_x_filter_size : 12; 1088 RK_U32 sw_pp0_y_filter_size : 12; 1089 RK_U32 reserved0 : 8; 1090 } swreg438; 1091 1092 struct { 1093 RK_U32 sw_pp0_lanczos_tbl_base_msb : 32; 1094 } swreg439; 1095 1096 struct { 1097 RK_U32 sw_pp0_lanczos_tbl_base_lsb : 32; 1098 } swreg440; 1099 1100 struct { 1101 RK_U32 sw_pp1_x_filter_size : 12; 1102 RK_U32 sw_pp1_y_filter_size : 12; 1103 RK_U32 reserved0 : 8; 1104 } swreg441; 1105 1106 struct { 1107 RK_U32 sw_pp1_lanczos_tbl_base_msb : 32; 1108 } swreg442; 1109 1110 struct { 1111 RK_U32 sw_pp1_lanczos_tbl_base_lsb : 32; 1112 } swreg443; 1113 1114 struct { 1115 RK_U32 sw_pp3_hcale_invra_ext : 8; 1116 RK_U32 sw_pp3_wscale_invra_ext : 8; 1117 RK_U32 sw_pp2_hcale_invra_ext : 8; 1118 RK_U32 sw_pp2_wscale_invra_ext : 8; 1119 } swreg444; 1120 1121 struct { 1122 RK_U32 sw_pp2_x_filter_size : 12; 1123 RK_U32 sw_pp2_y_filter_size : 12; 1124 RK_U32 reserved0 : 8; 1125 } swreg445; 1126 1127 struct { 1128 RK_U32 sw_pp2_lanczos_tbl_base_msb : 32; 1129 } swreg446; 1130 1131 struct { 1132 RK_U32 sw_pp2_lanczos_tbl_base_lsb : 32; 1133 } swreg447; 1134 1135 struct { 1136 RK_U32 sw_pp3_x_filter_size : 12; 1137 RK_U32 sw_pp3_y_filter_size : 12; 1138 RK_U32 reserved0 : 8; 1139 } swreg448; 1140 1141 struct { 1142 RK_U32 sw_pp3_lanczos_tbl_base_msb : 32; 1143 } swreg449; 1144 1145 struct { 1146 RK_U32 sw_pp3_lanczos_tbl_base_lsb : 32; 1147 } swreg450; 1148 1149 struct { 1150 RK_U32 sw_pp4_out_e : 1; 1151 RK_U32 sw_pp4_cr_first : 1; 1152 RK_U32 sw_pp4_out_mode : 1; 1153 RK_U32 sw_pp4_out_tile_e : 1; 1154 RK_U32 reserved0 : 7; 1155 RK_U32 sw_pp4_out_p010_fmt : 2; 1156 RK_U32 sw_pp4_out_rgb_fmt : 5; 1157 RK_U32 reserved1 : 12; 1158 RK_U32 sw_pp4_rgb_planar : 1; 1159 RK_U32 reserved2 : 1; 1160 } swreg451; 1161 1162 struct { 1163 RK_U32 reserved0 : 20; 1164 RK_U32 sw_pp4_out_swap : 4; 1165 RK_U32 reserved1 : 8; 1166 } swreg452; 1167 1168 struct { 1169 RK_U32 sw_pp4_scale_hratio : 18; 1170 RK_U32 sw_pp4_out_format : 5; 1171 RK_U32 sw_pp4_ver_scale_mode : 2; 1172 RK_U32 sw_pp4_hor_scale_mode : 2; 1173 RK_U32 reserved0 : 5; 1174 } swreg453; 1175 1176 struct { 1177 RK_U32 sw_pp4_scale_wratio : 18; 1178 RK_U32 reserved0 : 5; 1179 RK_U32 reserved1 : 5; 1180 RK_U32 reserved2 : 1; 1181 RK_U32 reserved4 : 1; 1182 RK_U32 reserved3 : 1; 1183 RK_U32 reserved5 : 1; 1184 } swreg454; 1185 1186 struct { 1187 RK_U32 sw_pp4_hscale_invra : 16; 1188 RK_U32 sw_pp4_wscale_invra : 16; 1189 } swreg455; 1190 1191 struct { 1192 // RK_U32 sw_pp4_out_r_base_msb : 32; 1193 RK_U32 sw_pp4_out_lu_base_msb : 32; 1194 } swreg456; 1195 1196 struct { 1197 // RK_U32 sw_pp4_out_r_base_lsb : 32; 1198 RK_U32 sw_pp4_out_lu_base_lsb : 32; 1199 } swreg457; 1200 1201 struct { 1202 // RK_U32 sw_pp4_out_g_base_msb : 32; 1203 RK_U32 sw_pp4_out_ch_base_msb : 32; 1204 } swreg458; 1205 1206 struct { 1207 // RK_U32 sw_pp4_out_g_base_lsb : 32; 1208 RK_U32 sw_pp4_out_ch_base_lsb : 32; 1209 } swreg459; 1210 1211 struct { 1212 RK_U32 sw_pp4_out_c_stride : 16; 1213 RK_U32 sw_pp4_out_y_stride : 16; 1214 } swreg460; 1215 1216 struct { 1217 RK_U32 sw_pp4_crop_starty : 13; 1218 RK_U32 sw_pp4_rotation_mode : 2; 1219 RK_U32 reserved0 : 1; 1220 RK_U32 sw_pp4_crop_startx : 13; 1221 RK_U32 sw_pp4_flip_mode : 2; 1222 RK_U32 sw_pp4_pad_sel : 1; 1223 } swreg461; 1224 1225 struct { 1226 RK_U32 sw_pp4_in_height : 16; 1227 RK_U32 sw_pp4_in_width : 16; 1228 } swreg462; 1229 1230 struct { 1231 RK_U32 sw_pp4_out_height : 16; 1232 RK_U32 sw_pp4_out_width : 16; 1233 } swreg463; 1234 1235 struct { 1236 // RK_U32 sw_pp4_out_b_base_msb : 32; 1237 RK_U32 sw_pp4_out_lu_bot_base_msb : 32; 1238 } swreg464; 1239 1240 struct { 1241 // RK_U32 sw_pp4_out_b_base_lsb : 32; 1242 RK_U32 sw_pp4_out_lu_bot_base_lsb : 32; 1243 } swreg465; 1244 1245 struct { 1246 RK_U32 sw_pp4_crop2_starty : 13; 1247 RK_U32 reserved0 : 3; 1248 RK_U32 sw_pp4_crop2_startx : 13; 1249 RK_U32 reserved1 : 3; 1250 // RK_U32 sw_pp4_out_ch_bot_base_msb : 32; 1251 } swreg466; 1252 1253 struct { 1254 RK_U32 sw_pp4_crop2_out_height : 16; 1255 RK_U32 sw_pp4_crop2_out_width : 16; 1256 // RK_U32 sw_pp4_out_ch_bot_base_lsb : 32; 1257 } swreg467; 1258 1259 struct { 1260 RK_U32 sw_pp4_contrast_off1 : 12; 1261 RK_U32 sw_pp4_contrast_off2 : 12; 1262 RK_U32 reserved0 : 2; 1263 RK_U32 sw_pp4_dither_select_b : 2; 1264 RK_U32 sw_pp4_dither_select_g : 2; 1265 RK_U32 sw_pp4_dither_select_r : 2; 1266 } swreg468; 1267 1268 struct { 1269 RK_U32 sw_pp4_color_coefff : 10; 1270 RK_U32 sw_pp4_contrast_thr2 : 10; 1271 RK_U32 sw_pp4_contrast_thr1 : 10; 1272 RK_U32 reserved0 : 2; 1273 } swreg469; 1274 1275 struct { 1276 RK_U32 sw_pp4_color_coeffa1 : 16; 1277 RK_U32 sw_pp4_color_coeffa2 : 16; 1278 } swreg470; 1279 1280 struct { 1281 RK_U32 sw_pp4_color_coeffb : 16; 1282 RK_U32 sw_pp4_color_coeffc : 16; 1283 } swreg471; 1284 1285 struct { 1286 RK_U32 sw_pp4_color_coeffd : 16; 1287 RK_U32 sw_pp4_color_coeffe : 16; 1288 } swreg472; 1289 1290 struct { 1291 RK_U32 sw_pp4_out_alpha : 8; 1292 RK_U32 sw_pp4_dup_hor : 8; 1293 RK_U32 sw_pp4_hcale_invra_ext : 8; 1294 RK_U32 sw_pp4_wscale_invra_ext : 8; 1295 } swreg473; 1296 1297 struct { 1298 RK_U32 sw_pp4_x_filter_size : 12; 1299 RK_U32 sw_pp4_y_filter_size : 12; 1300 RK_U32 reserved0 : 8; 1301 } swreg474; 1302 1303 struct { 1304 RK_U32 sw_pp4_lanczos_tbl_base_msb : 32; 1305 } swreg475; 1306 1307 struct { 1308 RK_U32 sw_pp4_lanczos_tbl_base_lsb : 32; 1309 } swreg476; 1310 1311 struct { 1312 RK_U32 sw_pp5_out_e : 1; 1313 RK_U32 sw_pp5_cr_first : 1; 1314 RK_U32 sw_pp5_out_mode : 1; 1315 RK_U32 sw_pp5_out_tile_e : 1; 1316 RK_U32 reserved0 : 7; 1317 RK_U32 sw_pp5_out_p010_fmt : 2; 1318 RK_U32 sw_pp5_out_rgb_fmt : 5; 1319 RK_U32 reserved1 : 12; 1320 RK_U32 sw_pp5_rgb_planar : 1; 1321 RK_U32 reserved2 : 1; 1322 } swreg477; 1323 1324 struct { 1325 RK_U32 reserved0 : 20; 1326 RK_U32 sw_pp5_out_swap : 4; 1327 RK_U32 reserved1 : 8; 1328 } swreg478; 1329 1330 struct { 1331 RK_U32 sw_pp5_scale_hratio : 18; 1332 RK_U32 sw_pp5_out_format : 5; 1333 RK_U32 sw_pp5_ver_scale_mode : 2; 1334 RK_U32 sw_pp5_hor_scale_mode : 2; 1335 RK_U32 reserved0 : 5; 1336 } swreg479; 1337 1338 struct { 1339 RK_U32 sw_pp5_scale_wratio : 18; 1340 RK_U32 reserved0 : 5; 1341 RK_U32 reserved1 : 5; 1342 RK_U32 reserved2 : 1; 1343 RK_U32 reserved4 : 1; 1344 RK_U32 reserved3 : 1; 1345 RK_U32 reserved5 : 1; 1346 } swreg480; 1347 1348 struct { 1349 RK_U32 sw_pp5_hscale_invra : 16; 1350 RK_U32 sw_pp5_wscale_invra : 16; 1351 } swreg481; 1352 1353 struct { 1354 // RK_U32 sw_pp5_out_r_base_msb : 32; 1355 RK_U32 sw_pp5_out_lu_base_msb : 32; 1356 } swreg482; 1357 1358 struct { 1359 // RK_U32 sw_pp5_out_r_base_lsb : 32; 1360 RK_U32 sw_pp5_out_lu_base_lsb : 32; 1361 } swreg483; 1362 1363 struct { 1364 // RK_U32 sw_pp5_out_g_base_msb : 32; 1365 RK_U32 sw_pp5_out_ch_base_msb : 32; 1366 } swreg484; 1367 1368 struct { 1369 // RK_U32 sw_pp5_out_g_base_lsb : 32; 1370 RK_U32 sw_pp5_out_ch_base_lsb : 32; 1371 } swreg485; 1372 1373 struct { 1374 RK_U32 sw_pp5_out_c_stride : 16; 1375 RK_U32 sw_pp5_out_y_stride : 16; 1376 } swreg486; 1377 1378 struct { 1379 RK_U32 sw_pp5_crop_starty : 13; 1380 RK_U32 sw_pp5_rotation_mode : 2; 1381 RK_U32 reserved0 : 1; 1382 RK_U32 sw_pp5_crop_startx : 13; 1383 RK_U32 sw_pp5_flip_mode : 2; 1384 RK_U32 sw_pp5_pad_sel : 1; 1385 } swreg487; 1386 1387 struct { 1388 RK_U32 sw_pp5_in_height : 16; 1389 RK_U32 sw_pp5_in_width : 16; 1390 } swreg488; 1391 1392 struct { 1393 RK_U32 sw_pp5_out_height : 16; 1394 RK_U32 sw_pp5_out_width : 16; 1395 } swreg489; 1396 1397 struct { 1398 // RK_U32 sw_pp5_out_b_base_msb : 32; 1399 RK_U32 sw_pp5_out_lu_bot_base_msb : 32; 1400 } swreg490; 1401 1402 struct { 1403 // RK_U32 sw_pp5_out_b_base_lsb : 32; 1404 RK_U32 sw_pp5_out_lu_bot_base_lsb : 32; 1405 } swreg491; 1406 1407 struct { 1408 RK_U32 sw_pp5_crop2_starty : 13; 1409 RK_U32 reserved0 : 3; 1410 RK_U32 sw_pp5_crop2_startx : 13; 1411 RK_U32 reserved1 : 3; 1412 // RK_U32 sw_pp5_out_ch_bot_base_msb : 32; 1413 } swreg492; 1414 1415 struct { 1416 RK_U32 sw_pp5_crop2_out_height : 16; 1417 RK_U32 sw_pp5_crop2_out_width : 16; 1418 // RK_U32 sw_pp5_out_ch_bot_base_lsb : 32; 1419 } swreg493; 1420 1421 struct { 1422 RK_U32 sw_pp5_contrast_off1 : 12; 1423 RK_U32 sw_pp5_contrast_off2 : 12; 1424 RK_U32 reserved0 : 2; 1425 RK_U32 sw_pp5_dither_select_b : 2; 1426 RK_U32 sw_pp5_dither_select_g : 2; 1427 RK_U32 sw_pp5_dither_select_r : 2; 1428 } swreg494; 1429 1430 struct { 1431 RK_U32 sw_pp5_color_coefff : 10; 1432 RK_U32 sw_pp5_contrast_thr2 : 10; 1433 RK_U32 sw_pp5_contrast_thr1 : 10; 1434 RK_U32 reserved0 : 2; 1435 } swreg495; 1436 1437 struct { 1438 RK_U32 sw_pp5_color_coeffa1 : 16; 1439 RK_U32 sw_pp5_color_coeffa2 : 16; 1440 } swreg496; 1441 1442 struct { 1443 RK_U32 sw_pp5_color_coeffb : 16; 1444 RK_U32 sw_pp5_color_coeffc : 16; 1445 } swreg497; 1446 1447 struct { 1448 RK_U32 sw_pp5_color_coeffd : 16; 1449 RK_U32 sw_pp5_color_coeffe : 16; 1450 } swreg498; 1451 1452 struct { 1453 RK_U32 sw_pp5_out_alpha : 8; 1454 RK_U32 sw_pp5_dup_hor : 8; 1455 RK_U32 sw_pp5_hcale_invra_ext : 8; 1456 RK_U32 sw_pp5_wscale_invra_ext : 8; 1457 } swreg499; 1458 1459 struct { 1460 RK_U32 sw_pp5_x_filter_size : 12; 1461 RK_U32 sw_pp5_y_filter_size : 12; 1462 RK_U32 reserved0 : 8; 1463 } swreg500; 1464 1465 struct { 1466 RK_U32 sw_pp5_lanczos_tbl_base_msb : 32; 1467 } swreg501; 1468 1469 struct { 1470 RK_U32 sw_pp5_lanczos_tbl_base_lsb : 32; 1471 } swreg502; 1472 1473 struct { 1474 RK_U32 sw_pp1_virtual_top : 4; 1475 RK_U32 sw_pp1_virtual_left : 4; 1476 RK_U32 sw_pp1_virtual_bottom : 4; 1477 RK_U32 sw_pp1_virtual_right : 4; 1478 RK_U32 sw_pp0_virtual_top : 4; 1479 RK_U32 sw_pp0_virtual_left : 4; 1480 RK_U32 sw_pp0_virtual_bottom : 4; 1481 RK_U32 sw_pp0_virtual_right : 4; 1482 } swreg503; 1483 1484 struct { 1485 RK_U32 sw_pp0_afbc_tile_base_msb : 32; 1486 } swreg504; 1487 1488 struct { 1489 RK_U32 sw_pp0_afbc_tile_base_lsb : 32; 1490 } swreg505; 1491 1492 struct { 1493 RK_U32 sw_pp1_afbc_tile_base_msb : 32; 1494 } swreg506; 1495 1496 struct { 1497 RK_U32 sw_pp1_afbc_tile_base_lsb : 32; 1498 } swreg507; 1499 1500 struct { 1501 RK_U32 sw_pp0_padV : 10; 1502 RK_U32 sw_pp0_padU : 10; 1503 RK_U32 sw_pp0_padY : 10; 1504 RK_U32 sw_pp0_src_sel_mode : 2; 1505 } swreg508; 1506 1507 struct { 1508 RK_U32 sw_pp1_padV : 10; 1509 RK_U32 sw_pp1_padU : 10; 1510 RK_U32 sw_pp1_padY : 10; 1511 RK_U32 sw_pp1_src_sel_mode : 2; 1512 } swreg509; 1513 1514 struct { 1515 RK_U32 sw_pp2_padV : 10; 1516 RK_U32 sw_pp2_padU : 10; 1517 RK_U32 sw_pp2_padY : 10; 1518 RK_U32 sw_pp2_src_sel_mode : 2; 1519 } swreg510; 1520 1521 struct { 1522 RK_U32 sw_pp3_padV : 10; 1523 RK_U32 sw_pp3_padU : 10; 1524 RK_U32 sw_pp3_padY : 10; 1525 RK_U32 sw_pp3_src_sel_mode : 2; 1526 } swreg511; 1527 1528 } VdpuAv1dPPCfg; 1529 1530 typedef struct VdpuAv1dRegSet_t { 1531 struct { 1532 RK_U32 reserved0 : 4; 1533 RK_U32 reserved1 : 8; 1534 RK_U32 reserved2 : 4; 1535 RK_U32 reserved3 : 4; 1536 RK_U32 reserved4 : 12; 1537 } swreg0; 1538 1539 struct { 1540 RK_U32 sw_dec_e : 1; 1541 RK_U32 reserved0 : 1; 1542 RK_U32 sw_dec_bus_int_dis : 1; 1543 RK_U32 sw_dec_timeout_source : 1; 1544 1545 RK_U32 sw_dec_irq_dis : 1; 1546 RK_U32 sw_dec_abort_e : 1; 1547 RK_U32 sw_dec_self_reset_dis : 1; 1548 RK_U32 sw_dec_tile_int_e : 1; 1549 1550 RK_U32 sw_dec_irq : 1; 1551 RK_U32 reserved1 : 2; 1552 RK_U32 sw_dec_abort_int : 1; 1553 1554 RK_U32 sw_dec_rdy_int : 1; 1555 RK_U32 sw_dec_bus_int : 1; 1556 RK_U32 sw_dec_buffer_int : 1; 1557 RK_U32 reserved2 : 1; 1558 1559 RK_U32 sw_dec_error_int : 1; 1560 RK_U32 reserved3 : 1; 1561 RK_U32 sw_dec_timeout : 1; 1562 RK_U32 reserved4 : 2; 1563 RK_U32 sw_dec_ext_timeout_int : 1; 1564 RK_U32 reserved5 : 1; 1565 RK_U32 sw_dec_tile_int : 1; 1566 1567 RK_U32 reserved6 : 8; 1568 } swreg1; 1569 1570 struct { 1571 RK_U32 reserved0 : 4; 1572 RK_U32 sw_drm_e : 1; 1573 RK_U32 reserved1 : 5; 1574 RK_U32 sw_dec_clk_gate_e : 1; 1575 RK_U32 reserved2 : 1; 1576 1577 RK_U32 sw_dec_tab_swap : 4; 1578 RK_U32 reserved3 : 4; 1579 RK_U32 sw_dec_dirmv_swap : 4; 1580 RK_U32 sw_dec_pic_swap : 4; 1581 RK_U32 sw_dec_strm_swap : 4; 1582 } swreg2; 1583 1584 struct { 1585 RK_U32 reserved0 : 8; 1586 RK_U32 sw_dec_out_ec_bypass : 1; 1587 RK_U32 reserved1 : 3; 1588 RK_U32 sw_write_mvs_e : 1; 1589 RK_U32 reserved2 : 1; 1590 RK_U32 sw_filtering_dis : 1; 1591 RK_U32 sw_dec_out_dis : 1; 1592 RK_U32 sw_dec_out_ec_byte_word : 1; 1593 RK_U32 reserved3 : 9; 1594 RK_U32 sw_skip_mode : 1; 1595 RK_U32 sw_dec_mode : 5; 1596 } swreg3; 1597 1598 struct { 1599 RK_U32 sw_ref_frames : 4; 1600 RK_U32 reserved0 : 2; 1601 RK_U32 sw_pic_height_in_cbs : 13; 1602 RK_U32 sw_pic_width_in_cbs : 13; 1603 } swreg4; 1604 1605 struct { 1606 RK_U32 sw_ref_scaling_enable : 1; 1607 RK_U32 sw_filt_level_base_gt32 : 1; 1608 RK_U32 sw_error_resilient : 1; 1609 RK_U32 sw_force_interger_mv : 1; 1610 1611 RK_U32 sw_allow_intrabc : 1; 1612 RK_U32 sw_allow_screen_content_tools : 1; 1613 RK_U32 sw_reduced_tx_set_used : 1; 1614 RK_U32 sw_enable_dual_filter : 1; 1615 1616 RK_U32 sw_enable_jnt_comp : 1; 1617 RK_U32 sw_allow_filter_intra : 1; 1618 RK_U32 sw_enable_intra_edge_filter : 1; 1619 RK_U32 sw_tempor_mvp_e : 1;//RK_U32 reserved0 : 1; 1620 1621 RK_U32 sw_allow_interintra : 1; 1622 RK_U32 sw_allow_masked_compound : 1; 1623 RK_U32 sw_enable_cdef : 1; 1624 RK_U32 sw_switchable_motion_mode : 1; 1625 1626 RK_U32 sw_show_frame : 1; 1627 RK_U32 sw_superres_is_scaled : 1; 1628 RK_U32 sw_allow_warp : 1; 1629 RK_U32 sw_disable_cdf_update : 1; 1630 1631 RK_U32 sw_preskip_segid : 1; 1632 RK_U32 sw_delta_lf_present : 1; 1633 RK_U32 sw_delta_lf_multi : 1; 1634 RK_U32 sw_delta_lf_res_log : 2; 1635 1636 // RK_U32 reserved1 : -14; 1637 RK_U32 sw_strm_start_bit : 7; 1638 } swreg5; 1639 1640 struct { 1641 RK_U32 sw_stream_len : 32; 1642 } swreg6; 1643 1644 struct { 1645 RK_U32 sw_delta_q_present : 1; 1646 RK_U32 sw_delta_q_res_log : 2; 1647 RK_U32 sw_cdef_damping : 2; 1648 RK_U32 sw_cdef_bits : 2; 1649 RK_U32 sw_apply_grain : 1; 1650 RK_U32 sw_num_y_points_b : 1; 1651 RK_U32 sw_num_cb_points_b : 1; 1652 RK_U32 sw_num_cr_points_b : 1; 1653 RK_U32 sw_overlap_flag : 1; 1654 RK_U32 sw_clip_to_restricted_range : 1; 1655 RK_U32 sw_chroma_scaling_from_luma : 1; 1656 RK_U32 sw_random_seed : 16; 1657 RK_U32 sw_blackwhite_e : 1; 1658 RK_U32 reserved0 : 1; 1659 } swreg7; 1660 1661 struct { 1662 RK_U32 sw_scaling_shift : 4; 1663 RK_U32 sw_bit_depth_c_minus8 : 2; 1664 RK_U32 sw_bit_depth_y_minus8 : 2; 1665 RK_U32 sw_quant_base_qindex : 8; 1666 RK_U32 sw_idr_pic_e : 1; 1667 RK_U32 sw_superres_pic_width : 15; 1668 } swreg8; 1669 1670 struct { 1671 RK_U32 reserved0 : 2; 1672 RK_U32 sw_ref4_sign_bias : 1; 1673 RK_U32 sw_ref5_sign_bias : 1; 1674 RK_U32 sw_ref6_sign_bias : 1; 1675 RK_U32 sw_mf1_type : 3; 1676 RK_U32 sw_mf2_type : 3; 1677 RK_U32 sw_mf3_type : 3; 1678 RK_U32 sw_scale_denom_minus9 : 3; 1679 RK_U32 sw_last_active_seg : 3; 1680 RK_U32 sw_context_update_tile_id : 12; 1681 } swreg9; 1682 1683 struct { 1684 RK_U32 sw_tile_transpose : 1; 1685 RK_U32 sw_tile_enable : 1; 1686 RK_U32 sw_multicore_full_width : 8; 1687 RK_U32 sw_num_tile_rows_8k_av1 : 7; 1688 RK_U32 sw_num_tile_cols_8k : 7; 1689 RK_U32 sw_multicore_tile_start_x : 8; 1690 } swreg10; 1691 1692 struct { 1693 RK_U32 sw_use_temporal3_mvs : 1; 1694 RK_U32 sw_use_temporal2_mvs : 1; 1695 RK_U32 sw_use_temporal1_mvs : 1; 1696 RK_U32 sw_use_temporal0_mvs : 1; 1697 RK_U32 sw_comp_pred_mode : 2; 1698 RK_U32 reserved0 : 1; 1699 RK_U32 sw_high_prec_mv_e : 1; 1700 RK_U32 sw_mcomp_filt_type : 3; 1701 RK_U32 sw_multicore_expect_context_update : 1; 1702 RK_U32 sw_multicore_sbx_offset : 7; 1703 RK_U32 sw_multicore_tile_col : 7; 1704 RK_U32 reserved1 : 1; 1705 RK_U32 sw_transform_mode : 3; 1706 RK_U32 sw_dec_tile_size_mag : 2; 1707 } swreg11; 1708 1709 struct { 1710 RK_U32 reserved0 : 2; 1711 RK_U32 sw_seg_quant_sign : 8; 1712 RK_U32 sw_max_cb_size : 3; 1713 RK_U32 sw_min_cb_size : 3; 1714 RK_U32 sw_av1_comp_pred_fixed_ref : 3; 1715 RK_U32 sw_multicore_tile_width : 7; 1716 RK_U32 sw_pic_height_pad : 3; 1717 RK_U32 sw_pic_width_pad : 3; 1718 } swreg12; 1719 1720 struct { 1721 RK_U32 sw_segment_e : 1; 1722 RK_U32 sw_segment_upd_e : 1; 1723 RK_U32 sw_segment_temp_upd_e : 1; 1724 RK_U32 sw_comp_pred_var_ref0_av1 : 3; 1725 RK_U32 sw_comp_pred_var_ref1_av1 : 3; 1726 RK_U32 sw_lossless_e : 1; 1727 RK_U32 reserved0 : 1; 1728 RK_U32 sw_qp_delta_ch_ac_av1 : 7; 1729 RK_U32 sw_qp_delta_ch_dc_av1 : 7; 1730 RK_U32 sw_qp_delta_y_dc_av1 : 7; 1731 } swreg13; 1732 1733 struct { 1734 RK_U32 sw_quant_seg0 : 8; 1735 RK_U32 sw_filt_level_seg0 : 6; 1736 RK_U32 sw_skip_seg0 : 1; 1737 RK_U32 sw_refpic_seg0 : 4; 1738 RK_U32 sw_filt_level_delta0_seg0 : 7; 1739 RK_U32 sw_filt_level0 : 6; 1740 } swreg14; 1741 1742 struct { 1743 RK_U32 sw_quant_seg1 : 8; 1744 RK_U32 sw_filt_level_seg1 : 6; 1745 RK_U32 sw_skip_seg1 : 1; 1746 RK_U32 sw_refpic_seg1 : 4; 1747 RK_U32 sw_filt_level_delta0_seg1 : 7; 1748 RK_U32 sw_filt_level1 : 6; 1749 } swreg15; 1750 1751 struct { 1752 RK_U32 sw_quant_seg2 : 8; 1753 RK_U32 sw_filt_level_seg2 : 6; 1754 RK_U32 sw_skip_seg2 : 1; 1755 RK_U32 sw_refpic_seg2 : 4; 1756 RK_U32 sw_filt_level_delta0_seg2 : 7; 1757 RK_U32 sw_filt_level2 : 6; 1758 } swreg16; 1759 1760 struct { 1761 RK_U32 sw_quant_seg3 : 8; 1762 RK_U32 sw_filt_level_seg3 : 6; 1763 RK_U32 sw_skip_seg3 : 1; 1764 RK_U32 sw_refpic_seg3 : 4; 1765 RK_U32 sw_filt_level_delta0_seg3 : 7; 1766 RK_U32 sw_filt_level3 : 6; 1767 } swreg17; 1768 1769 struct { 1770 RK_U32 sw_quant_seg4 : 8; 1771 RK_U32 sw_filt_level_seg4 : 6; 1772 RK_U32 sw_skip_seg4 : 1; 1773 RK_U32 sw_refpic_seg4 : 4; 1774 RK_U32 sw_filt_level_delta0_seg4 : 7; 1775 RK_U32 sw_lr_type : 6; 1776 } swreg18; 1777 1778 struct { 1779 RK_U32 sw_quant_seg5 : 8; 1780 RK_U32 sw_filt_level_seg5 : 6; 1781 RK_U32 sw_skip_seg5 : 1; 1782 RK_U32 sw_refpic_seg5 : 4; 1783 RK_U32 sw_filt_level_delta0_seg5 : 7; 1784 RK_U32 sw_lr_unit_size : 6; 1785 } swreg19; 1786 1787 struct { 1788 RK_U32 sw_filt_level_delta1_seg0 : 7; 1789 RK_U32 sw_filt_level_delta2_seg0 : 7; 1790 RK_U32 sw_filt_level_delta3_seg0 : 7; 1791 RK_U32 sw_global_mv_seg0 : 1; 1792 RK_U32 sw_mf1_last_offset : 9; 1793 RK_U32 reserved0 : 1; 1794 } swreg20; 1795 1796 struct { 1797 RK_U32 sw_filt_level_delta1_seg1 : 7; 1798 RK_U32 sw_filt_level_delta2_seg1 : 7; 1799 RK_U32 sw_filt_level_delta3_seg1 : 7; 1800 RK_U32 sw_global_mv_seg1 : 1; 1801 RK_U32 sw_mf1_last2_offset : 9; 1802 RK_U32 reserved0 : 1; 1803 } swreg21; 1804 1805 struct { 1806 RK_U32 sw_filt_level_delta1_seg2 : 7; 1807 RK_U32 sw_filt_level_delta2_seg2 : 7; 1808 RK_U32 sw_filt_level_delta3_seg2 : 7; 1809 RK_U32 sw_global_mv_seg2 : 1; 1810 RK_U32 sw_mf1_last3_offset : 9; 1811 RK_U32 reserved0 : 1; 1812 } swreg22; 1813 1814 struct { 1815 RK_U32 sw_filt_level_delta1_seg3 : 7; 1816 RK_U32 sw_filt_level_delta2_seg3 : 7; 1817 RK_U32 sw_filt_level_delta3_seg3 : 7; 1818 RK_U32 sw_global_mv_seg3 : 1; 1819 RK_U32 sw_mf1_golden_offset : 9; 1820 RK_U32 reserved0 : 1; 1821 } swreg23; 1822 1823 struct { 1824 RK_U32 sw_filt_level_delta1_seg4 : 7; 1825 RK_U32 sw_filt_level_delta2_seg4 : 7; 1826 RK_U32 sw_filt_level_delta3_seg4 : 7; 1827 RK_U32 sw_global_mv_seg4 : 1; 1828 RK_U32 sw_mf1_bwdref_offset : 9; 1829 RK_U32 reserved0 : 1; 1830 } swreg24; 1831 1832 struct { 1833 RK_U32 sw_filt_level_delta1_seg5 : 7; 1834 RK_U32 sw_filt_level_delta2_seg5 : 7; 1835 RK_U32 sw_filt_level_delta3_seg5 : 7; 1836 RK_U32 sw_global_mv_seg5 : 1; 1837 RK_U32 sw_mf1_altref2_offset : 9; 1838 RK_U32 reserved0 : 1; 1839 } swreg25; 1840 1841 struct { 1842 RK_U32 sw_filt_level_delta1_seg6 : 7; 1843 RK_U32 sw_filt_level_delta2_seg6 : 7; 1844 RK_U32 sw_filt_level_delta3_seg6 : 7; 1845 RK_U32 sw_global_mv_seg6 : 1; 1846 RK_U32 sw_mf1_altref_offset : 9; 1847 RK_U32 reserved0 : 1; 1848 } swreg26; 1849 1850 struct { 1851 RK_U32 sw_filt_level_delta1_seg7 : 7; 1852 RK_U32 sw_filt_level_delta2_seg7 : 7; 1853 RK_U32 sw_filt_level_delta3_seg7 : 7; 1854 RK_U32 sw_global_mv_seg7 : 1; 1855 RK_U32 sw_mf2_last_offset : 9; 1856 RK_U32 reserved0 : 1; 1857 } swreg27; 1858 1859 struct { 1860 RK_U32 sw_cb_offset : 9; 1861 RK_U32 sw_cb_luma_mult : 8; 1862 RK_U32 sw_cb_mult : 8; 1863 RK_U32 sw_quant_delta_v_dc : 7; 1864 } swreg28; 1865 1866 struct { 1867 RK_U32 sw_cr_offset : 9; 1868 RK_U32 sw_cr_luma_mult : 8; 1869 RK_U32 sw_cr_mult : 8; 1870 RK_U32 sw_quant_delta_v_ac : 7; 1871 } swreg29; 1872 1873 struct { 1874 RK_U32 sw_filt_ref_adj_5 : 7; 1875 RK_U32 sw_filt_ref_adj_4 : 7; 1876 RK_U32 sw_filt_mb_adj_1 : 7; 1877 RK_U32 sw_filt_mb_adj_0 : 7; 1878 RK_U32 sw_filt_sharpness : 3; 1879 RK_U32 reserved0 : 1; 1880 } swreg30; 1881 1882 struct { 1883 RK_U32 sw_quant_seg6 : 8; 1884 RK_U32 sw_filt_level_seg6 : 6; 1885 RK_U32 sw_skip_seg6 : 1; 1886 RK_U32 sw_refpic_seg6 : 4; 1887 RK_U32 sw_filt_level_delta0_seg6 : 7; 1888 RK_U32 sw_skip_ref0 : 4; 1889 RK_U32 reserved0 : 2; 1890 } swreg31; 1891 1892 struct { 1893 RK_U32 sw_quant_seg7 : 8; 1894 RK_U32 sw_filt_level_seg7 : 6; 1895 RK_U32 sw_skip_seg7 : 1; 1896 RK_U32 sw_refpic_seg7 : 4; 1897 RK_U32 sw_filt_level_delta0_seg7 : 7; 1898 RK_U32 sw_skip_ref1 : 4; 1899 RK_U32 reserved0 : 2; 1900 } swreg32; 1901 1902 struct { 1903 RK_U32 sw_ref0_height : 16; 1904 RK_U32 sw_ref0_width : 16; 1905 } swreg33; 1906 1907 struct { 1908 RK_U32 sw_ref1_height : 16; 1909 RK_U32 sw_ref1_width : 16; 1910 } swreg34; 1911 1912 struct { 1913 RK_U32 sw_ref2_height : 16; 1914 RK_U32 sw_ref2_width : 16; 1915 } swreg35; 1916 1917 struct { 1918 RK_U32 sw_ref0_ver_scale : 16; 1919 RK_U32 sw_ref0_hor_scale : 16; 1920 } swreg36; 1921 1922 struct { 1923 RK_U32 sw_ref1_ver_scale : 16; 1924 RK_U32 sw_ref1_hor_scale : 16; 1925 } swreg37; 1926 1927 struct { 1928 RK_U32 sw_ref2_ver_scale : 16; 1929 RK_U32 sw_ref2_hor_scale : 16; 1930 } swreg38; 1931 1932 struct { 1933 RK_U32 sw_ref3_ver_scale : 16; 1934 RK_U32 sw_ref3_hor_scale : 16; 1935 } swreg39; 1936 1937 struct { 1938 RK_U32 sw_ref4_ver_scale : 16; 1939 RK_U32 sw_ref4_hor_scale : 16; 1940 } swreg40; 1941 1942 struct { 1943 RK_U32 sw_ref5_ver_scale : 16; 1944 RK_U32 sw_ref5_hor_scale : 16; 1945 } swreg41; 1946 1947 struct { 1948 RK_U32 sw_ref6_ver_scale : 16; 1949 RK_U32 sw_ref6_hor_scale : 16; 1950 } swreg42; 1951 struct { 1952 RK_U32 sw_ref3_height : 16; 1953 RK_U32 sw_ref3_width : 16; 1954 } swreg43; 1955 1956 struct { 1957 RK_U32 sw_ref4_height : 16; 1958 RK_U32 sw_ref4_width : 16; 1959 } swreg44; 1960 1961 struct { 1962 RK_U32 sw_ref5_height : 16; 1963 RK_U32 sw_ref5_width : 16; 1964 } swreg45; 1965 1966 struct { 1967 RK_U32 sw_ref6_height : 16; 1968 RK_U32 sw_ref6_width : 16; 1969 } swreg46; 1970 1971 struct { 1972 RK_U32 sw_mf2_last2_offset : 9; 1973 RK_U32 sw_mf2_last3_offset : 9; 1974 RK_U32 sw_mf2_golden_offset : 9; 1975 RK_U32 sw_qmlevel_y : 4; 1976 RK_U32 reserved0 : 1; 1977 } swreg47; 1978 1979 struct { 1980 RK_U32 sw_mf2_bwdref_offset : 9; 1981 RK_U32 sw_mf2_altref2_offset : 9; 1982 RK_U32 sw_mf2_altref_offset : 9; 1983 RK_U32 sw_qmlevel_u : 4; 1984 RK_U32 reserved0 : 1; 1985 } swreg48; 1986 1987 struct { 1988 RK_U32 sw_filt_ref_adj_6 : 7; 1989 RK_U32 sw_filt_ref_adj_7 : 7; 1990 RK_U32 sw_qmlevel_v : 4; 1991 RK_U32 reserved0 : 14; 1992 } swreg49; 1993 1994 struct { 1995 RK_U32 SW_DEC_MAX_OWIDTH : 16; 1996 RK_U32 SW_DEC_AV1_PROF : 1; 1997 RK_U32 reserved0 : 15; 1998 } swreg50; 1999 2000 struct { 2001 RK_U32 sw_superres_chroma_step : 14; 2002 RK_U32 sw_superres_luma_step : 14; 2003 RK_U32 reserved0 : 4; 2004 } swreg51; 2005 2006 struct { 2007 RK_U32 sw_superres_init_chroma_subpel_x : 14; 2008 RK_U32 sw_superres_init_luma_subpel_x : 14; 2009 RK_U32 reserved0 : 4; 2010 } swreg52; 2011 2012 struct { 2013 RK_U32 sw_cdef_chroma_secondary_strength : 16; 2014 RK_U32 sw_cdef_luma_secondary_strength : 16; 2015 } swreg53; 2016 2017 struct { 2018 RK_U32 reserved0 : 5; 2019 RK_U32 SW_DEC_ADDR64_SUPPORTED : 1; 2020 RK_U32 reserved1 : 11; 2021 RK_U32 SW_DEC_RFC_EXIST : 2; 2022 RK_U32 reserved2 : 13; 2023 } swreg54; 2024 2025 struct { 2026 RK_U32 sw_apf_threshold : 16; 2027 RK_U32 reserved0 : 14; 2028 RK_U32 sw_apf_single_pu_mode : 1; 2029 RK_U32 sw_apf_disable : 1; 2030 } swreg55; 2031 2032 struct { 2033 RK_U32 SW_DEC_MAX_OHEIGHT : 15; 2034 RK_U32 SW_DEC_DATA_S_W : 2; 2035 RK_U32 SW_DEC_ADDR_S_W : 1; 2036 RK_U32 SW_DEC_DATA_M_W : 2; 2037 RK_U32 SW_DEC_ADDR_M_W : 1; 2038 RK_U32 SW_DEC_SLAVE_BUS : 2; 2039 RK_U32 SW_DEC_MASTER_BUS : 2; 2040 RK_U32 SW_DEC_JOINT : 1; 2041 RK_U32 reserved0 : 6; 2042 } swreg56; 2043 2044 struct { 2045 RK_U32 reserved0 : 6; 2046 RK_U32 fuse_dec_av1 : 1; 2047 RK_U32 reserved1 : 25; 2048 } swreg57; 2049 2050 struct { 2051 RK_U32 sw_dec_max_burst : 8; 2052 RK_U32 sw_dec_buswidth : 3; 2053 RK_U32 sw_dec_multicore_mode : 2; 2054 RK_U32 sw_dec_axi_wd_id_e : 1; 2055 RK_U32 sw_dec_axi_rd_id_e : 1; 2056 RK_U32 reserved0 : 2; 2057 RK_U32 sw_dec_mc_polltime : 10; 2058 RK_U32 sw_dec_mc_pollmode : 2; 2059 RK_U32 reserved1 : 3; 2060 } swreg58; 2061 2062 struct { 2063 RK_U32 sw_filt_ref_adj_3 : 7; 2064 RK_U32 sw_filt_ref_adj_2 : 7; 2065 RK_U32 sw_filt_ref_adj_1 : 7; 2066 RK_U32 sw_filt_ref_adj_0 : 7; 2067 RK_U32 sw_ref0_sign_bias : 1; 2068 RK_U32 sw_ref1_sign_bias : 1; 2069 RK_U32 sw_ref2_sign_bias : 1; 2070 RK_U32 sw_ref3_sign_bias : 1; 2071 } swreg59; 2072 2073 struct { 2074 RK_U32 sw_dec_axi_rd_id : 16; 2075 RK_U32 sw_dec_axi_wr_id : 16; 2076 } swreg60; 2077 2078 struct { 2079 RK_U32 reserved0 : 12; 2080 RK_U32 fuse_pp_maxw_352 : 1; 2081 RK_U32 fuse_pp_maxw_720 : 1; 2082 RK_U32 fuse_pp_maxw_1280 : 1; 2083 RK_U32 fuse_pp_maxw_1920 : 1; 2084 RK_U32 fuse_pp_maxw_4k : 1; 2085 RK_U32 reserved1 : 12; 2086 RK_U32 fuse_pp_ablend : 1; 2087 RK_U32 fuse_pp_scaling : 1; 2088 RK_U32 fuse_pp_pp : 1; 2089 } swreg61; 2090 2091 struct { 2092 RK_U32 sw_cu_location_y : 16; 2093 RK_U32 sw_cu_location_x : 16; 2094 } swreg62; 2095 2096 struct { 2097 RK_U32 sw_perf_cycle_count : 32; 2098 } swreg63; 2099 2100 /* swreg64 - swreg183 */ 2101 VdpuAv1dBase addr_cfg; 2102 2103 struct { 2104 RK_U32 sw_cur_last_roffset : 9; 2105 RK_U32 sw_cur_last_offset : 9; 2106 RK_U32 sw_mf3_last_offset : 9; 2107 RK_U32 sw_ref0_gm_mode : 2; 2108 RK_U32 reserved0 : 3; 2109 } swreg184; 2110 2111 struct { 2112 RK_U32 sw_cur_last2_roffset : 9; 2113 RK_U32 sw_cur_last2_offset : 9; 2114 RK_U32 sw_mf3_last2_offset : 9; 2115 RK_U32 sw_ref1_gm_mode : 2; 2116 RK_U32 reserved0 : 3; 2117 } swreg185; 2118 2119 struct { 2120 RK_U32 sw_cur_last3_roffset : 9; 2121 RK_U32 sw_cur_last3_offset : 9; 2122 RK_U32 sw_mf3_last3_offset : 9; 2123 RK_U32 sw_ref2_gm_mode : 2; 2124 RK_U32 reserved0 : 3; 2125 } swreg186; 2126 2127 struct { 2128 RK_U32 sw_cur_golden_roffset : 9; 2129 RK_U32 sw_cur_golden_offset : 9; 2130 RK_U32 sw_mf3_golden_offset : 9; 2131 RK_U32 sw_ref3_gm_mode : 2; 2132 RK_U32 reserved0 : 3; 2133 } swreg187; 2134 2135 struct { 2136 RK_U32 sw_cur_bwdref_roffset : 9; 2137 RK_U32 sw_cur_bwdref_offset : 9; 2138 RK_U32 sw_mf3_bwdref_offset : 9; 2139 RK_U32 sw_ref4_gm_mode : 2; 2140 RK_U32 reserved0 : 3; 2141 } swreg188; 2142 2143 struct { 2144 RK_U32 sw_dec_out_tybase_msb : 32; 2145 } swreg189; 2146 2147 struct { 2148 RK_U32 sw_dec_out_tybase_lsb : 32; 2149 } swreg190; 2150 2151 struct { 2152 RK_U32 sw_refer0_tybase_msb : 32; 2153 } swreg191; 2154 2155 struct { 2156 RK_U32 sw_refer0_tybase_lsb : 32; 2157 } swreg192; 2158 2159 struct { 2160 RK_U32 sw_refer1_tybase_msb : 32; 2161 } swreg193; 2162 2163 struct { 2164 RK_U32 sw_refer1_tybase_lsb : 32; 2165 } swreg194; 2166 2167 struct { 2168 RK_U32 sw_refer2_tybase_msb : 32; 2169 } swreg195; 2170 2171 struct { 2172 RK_U32 sw_refer2_tybase_lsb : 32; 2173 } swreg196; 2174 2175 struct { 2176 RK_U32 sw_refer3_tybase_msb : 32; 2177 } swreg197; 2178 2179 struct { 2180 RK_U32 sw_refer3_tybase_lsb : 32; 2181 } swreg198; 2182 2183 struct { 2184 RK_U32 sw_refer4_tybase_msb : 32; 2185 } swreg199; 2186 2187 struct { 2188 RK_U32 sw_refer4_tybase_lsb : 32; 2189 } swreg200; 2190 2191 struct { 2192 RK_U32 sw_refer5_tybase_msb : 32; 2193 } swreg201; 2194 2195 struct { 2196 RK_U32 sw_refer5_tybase_lsb : 32; 2197 } swreg202; 2198 2199 struct { 2200 RK_U32 sw_refer6_tybase_msb : 32; 2201 } swreg203; 2202 2203 struct { 2204 RK_U32 sw_refer6_tybase_lsb : 32; 2205 } swreg204; 2206 2207 RK_U32 reserved_205_222[18]; 2208 struct { 2209 RK_U32 sw_dec_out_tcbase_msb : 32; 2210 } swreg223; 2211 2212 struct { 2213 RK_U32 sw_dec_out_tcbase_lsb : 32; 2214 } swreg224; 2215 2216 struct { 2217 RK_U32 sw_refer0_tcbase_msb : 32; 2218 } swreg225; 2219 2220 struct { 2221 RK_U32 sw_refer0_tcbase_lsb : 32; 2222 } swreg226; 2223 2224 struct { 2225 RK_U32 sw_refer1_tcbase_msb : 32; 2226 } swreg227; 2227 2228 struct { 2229 RK_U32 sw_refer1_tcbase_lsb : 32; 2230 } swreg228; 2231 2232 struct { 2233 RK_U32 sw_refer2_tcbase_msb : 32; 2234 } swreg229; 2235 2236 struct { 2237 RK_U32 sw_refer2_tcbase_lsb : 32; 2238 } swreg230; 2239 2240 struct { 2241 RK_U32 sw_refer3_tcbase_msb : 32; 2242 } swreg231; 2243 2244 struct { 2245 RK_U32 sw_refer3_tcbase_lsb : 32; 2246 } swreg232; 2247 2248 struct { 2249 RK_U32 sw_refer4_tcbase_msb : 32; 2250 } swreg233; 2251 2252 struct { 2253 RK_U32 sw_refer4_tcbase_lsb : 32; 2254 } swreg234; 2255 2256 struct { 2257 RK_U32 sw_refer5_tcbase_msb : 32; 2258 } swreg235; 2259 2260 struct { 2261 RK_U32 sw_refer5_tcbase_lsb : 32; 2262 } swreg236; 2263 2264 struct { 2265 RK_U32 sw_refer6_tcbase_msb : 32; 2266 } swreg237; 2267 2268 struct { 2269 RK_U32 sw_refer6_tcbase_lsb : 32; 2270 } swreg238; 2271 2272 RK_U32 reserved_239_256[18]; 2273 struct { 2274 RK_U32 sw_cur_altref2_roffset : 9; 2275 RK_U32 sw_cur_altref2_offset : 9; 2276 RK_U32 sw_mf3_altref2_offset : 9; 2277 RK_U32 sw_ref5_gm_mode : 2; 2278 RK_U32 reserved0 : 3; 2279 } swreg257; 2280 2281 struct { 2282 RK_U32 sw_strm_buffer_len : 32; 2283 } swreg258; 2284 2285 struct { 2286 RK_U32 sw_strm_start_offset : 32; 2287 } swreg259; 2288 2289 struct { 2290 RK_U32 reserved0 : 21; 2291 RK_U32 sw_ppd_blend_exist : 1; 2292 RK_U32 reserved1 : 1; 2293 RK_U32 sw_ppd_dith_exist : 1; 2294 RK_U32 sw_ablend_crop_e : 1; 2295 RK_U32 sw_pp_format_p010_e : 1; 2296 RK_U32 sw_pp_format_customer1_e : 1; 2297 RK_U32 sw_pp_crop_exist : 1; 2298 RK_U32 sw_pp_up_level : 1; 2299 RK_U32 sw_pp_down_level : 2; 2300 RK_U32 sw_pp_exist : 1; 2301 } swreg260; 2302 2303 struct { 2304 RK_U32 sw_dec_error_code : 8; 2305 RK_U32 reserved0 : 24; 2306 } swreg261; 2307 2308 struct { 2309 RK_U32 sw_cur_altref_roffset : 9; 2310 RK_U32 sw_cur_altref_offset : 9; 2311 RK_U32 sw_mf3_altref_offset : 9; 2312 RK_U32 sw_ref6_gm_mode : 2; 2313 RK_U32 reserved0 : 3; 2314 } swreg262; 2315 2316 struct { 2317 RK_U32 sw_cdef_luma_primary_strength : 32; 2318 } swreg263; 2319 2320 struct { 2321 RK_U32 sw_cdef_chroma_primary_strength : 32; 2322 } swreg264; 2323 2324 struct { 2325 RK_U32 sw_axi_arqos : 4; 2326 RK_U32 sw_axi_awqos : 4; 2327 2328 RK_U32 sw_axi_wr_ostd_threshold : 10; 2329 RK_U32 sw_axi_rd_ostd_threshold : 10; 2330 2331 RK_U32 reserved0 : 3; 2332 RK_U32 sw_axi_wr_4k_dis : 1; 2333 } swreg265; 2334 2335 struct { 2336 RK_U32 reserved0 : 5; 2337 RK_U32 sw_128bit_mode : 1; 2338 RK_U32 reserved1 : 4; 2339 RK_U32 sw_wr_shaper_bypass : 1; 2340 RK_U32 reserved2 : 19; 2341 RK_U32 sw_error_conceal_e : 1; 2342 RK_U32 reserved3 : 1; 2343 } swreg266; 2344 2345 RK_U32 reserved_267_297[31]; 2346 struct { 2347 RK_U32 sw_superres_chroma_step_invra : 16; 2348 RK_U32 sw_superres_luma_step_invra : 16; 2349 } swreg298; 2350 2351 struct { 2352 RK_U32 sw_dec_pred_dataout_cnt : 32; 2353 } swreg299; 2354 2355 struct { 2356 RK_U32 sw_dec_axi_r_len_cnt : 32; 2357 } swreg300; 2358 2359 struct { 2360 RK_U32 sw_dec_axi_r_dat_cnt : 32; 2361 } swreg301; 2362 2363 struct { 2364 RK_U32 sw_dec_axi_r_req_cnt : 32; 2365 } swreg302; 2366 2367 struct { 2368 RK_U32 sw_dec_axi_rlast_cnt : 32; 2369 } swreg303; 2370 2371 struct { 2372 RK_U32 sw_dec_axi_w_len_cnt : 32; 2373 } swreg304; 2374 2375 struct { 2376 RK_U32 sw_dec_axi_w_dat_cnt : 32; 2377 } swreg305; 2378 2379 struct { 2380 RK_U32 sw_dec_axi_w_req_cnt : 32; 2381 } swreg306; 2382 2383 struct { 2384 RK_U32 sw_dec_axi_wlast_cnt : 32; 2385 } swreg307; 2386 2387 struct { 2388 RK_U32 sw_dec_axi_w_ack : 32; 2389 } swreg308; 2390 2391 struct { 2392 RK_U32 hw_build_id : 32; 2393 } swreg309; 2394 2395 struct { 2396 RK_U32 hw_syn_id : 16; 2397 RK_U32 reserved0 : 16; 2398 } swreg310; 2399 2400 struct { 2401 RK_U32 reserved0 : 32; 2402 } swreg311; 2403 2404 struct { 2405 RK_U32 reserved0 : 32; 2406 } swreg312; 2407 2408 struct { 2409 RK_U32 reserved0 : 32; 2410 } swreg313; 2411 2412 struct { 2413 RK_U32 sw_dec_alignment : 16; 2414 RK_U32 reserved0 : 16; 2415 } swreg314; 2416 2417 struct { 2418 RK_U32 sw_tile_left : 32; 2419 } swreg315; 2420 2421 RK_U32 reserved_316; 2422 struct { 2423 RK_U32 reserved0 : 28; 2424 RK_U32 sw_pp_line_cnt_sel : 2; 2425 RK_U32 reserved1 : 2; 2426 } swreg317; 2427 2428 struct { 2429 RK_U32 sw_ext_timeout_cycles : 31; 2430 RK_U32 sw_ext_timeout_override_e : 1; 2431 } swreg318; 2432 2433 struct { 2434 RK_U32 sw_timeout_cycles : 31; 2435 RK_U32 sw_timeout_override_e : 1; 2436 } swreg319; 2437 2438 VdpuAv1dPPCfg vdpu_av1d_pp_cfg; 2439 2440 } VdpuAv1dRegSet; 2441 2442 #endif 2443