Searched defs:sunxi_mctl_ctl_reg (Results 1 – 6 of 6) sorted by relevance
66 struct sunxi_mctl_ctl_reg { struct67 u32 pir; /* 0x00 */68 u32 pwrctl; /* 0x04 */69 u32 mrctrl0; /* 0x08 */70 u32 clken; /* 0x0c */71 u32 pgsr0; /* 0x10 */72 u32 pgsr1; /* 0x14 */73 u32 statr; /* 0x18 */74 u8 res1[0x14]; /* 0x1c */75 u32 mr0; /* 0x30 */[all …]
41 struct sunxi_mctl_ctl_reg { struct42 u8 res0[0x04]; /* 0x00 */43 u32 sctl; /* 0x04 */44 u32 sstat; /* 0x08 */45 u8 res1[0x34]; /* 0x0c */46 u32 mcmd; /* 0x40 */47 u8 res2[0x08]; /* 0x44 */48 u32 cmdstat; /* 0x4c */49 u32 cmdstaten; /* 0x50 */50 u8 res3[0x0c]; /* 0x54 */[all …]
82 struct sunxi_mctl_ctl_reg { struct83 u32 pir; /* 0x00 PHY initialization register */84 u32 pwrctl; /* 0x04 */85 u32 mrctrl; /* 0x08 */86 u32 clken; /* 0x0c */87 u32 pgsr[2]; /* 0x10 PHY general status registers */88 u32 statr; /* 0x18 */89 u8 res1[0x10]; /* 0x1c */90 u32 lp3mr11; /* 0x2c */91 u32 mr[4]; /* 0x30 mode registers */[all …]
92 struct sunxi_mctl_ctl_reg { struct93 u32 mstr; /* 0x00 */94 u32 statr; /* 0x04 */95 u8 res0[0x08]; /* 0x08 */96 u32 mrctrl0; /* 0x10 */97 u32 mrctrl1; /* 0x14 */98 u32 mrstatr; /* 0x18 */99 u8 res1[0x04]; /* 0x1c */100 u32 derateen; /* 0x20 */101 u32 deratenint; /* 0x24 */[all …]
41 struct sunxi_mctl_ctl_reg { struct42 u32 mstr; /* 0x00 master register */43 u32 stat; /* 0x04 operating mode status register */44 u8 res1[0x8]; /* 0x08 */45 u32 mrctrl[2]; /* 0x10 mode register read/write control reg */46 u32 mstat; /* 0x18 mode register read/write status reg */47 u8 res2[0x4]; /* 0x1c */48 u32 derateen; /* 0x20 temperature derate enable register */49 u32 derateint; /* 0x24 temperature derate interval register */50 u8 res3[0x8]; /* 0x28 */[all …]