Searched defs:sunxi_mctl_com_reg (Results 1 – 6 of 6) sorted by relevance
15 struct sunxi_mctl_com_reg { struct16 u32 cr; /* 0x00 */17 u32 ccr; /* 0x04 controller configuration register */18 u32 dbgcr; /* 0x08 */19 u8 res0[0x4]; /* 0x0c */20 u32 mcr0_0; /* 0x10 */21 u32 mcr1_0; /* 0x14 */22 u32 mcr0_1; /* 0x18 */23 u32 mcr1_1; /* 0x1c */24 u32 mcr0_2; /* 0x20 */[all …]
45 struct sunxi_mctl_com_reg { struct46 u32 cr; /* 0x00 */47 u32 ccr; /* 0x04 controller configuration register */48 u32 dbgcr; /* 0x08 */49 u8 res0[0x4]; /* 0x0c */50 u32 mcr0_0; /* 0x10 */51 u32 mcr1_0; /* 0x14 */52 u32 mcr0_1; /* 0x18 */53 u32 mcr1_1; /* 0x1c */54 u32 mcr0_2; /* 0x20 */[all …]
18 struct sunxi_mctl_com_reg { struct19 u32 cr; /* 0x00 control register */20 u32 cr_r1; /* 0x04 rank 1 control register (R40 only) */21 u8 res0[0x4]; /* 0x08 */22 u32 tmr; /* 0x0c (unused on H3) */23 u32 mcr[16][2]; /* 0x10 */24 u32 bwcr; /* 0x90 bandwidth control register */25 u32 maer; /* 0x94 master enable register */26 u32 mapr; /* 0x98 master priority register */27 u32 mcgcr; /* 0x9c */[all …]
15 struct sunxi_mctl_com_reg { struct16 u32 cr; /* 0x00 */17 u32 ccr; /* 0x04 controller configuration register */18 u32 dbgcr; /* 0x08 */19 u32 dbgcr1; /* 0x0c */20 u32 rmcr; /* 0x10 */21 u8 res1[0x1c]; /* 0x14 */22 u32 mmcr; /* 0x30 */23 u8 res2[0x3c]; /* 0x34 */24 u32 mbagcr; /* 0x70 */[all …]
17 struct sunxi_mctl_com_reg { struct18 u32 cr; /* 0x00 */19 u32 ccr; /* 0x04 controller configuration register */20 u32 dbgcr; /* 0x08 */21 u32 dbgcr1; /* 0x0c */22 u32 rmcr[8]; /* 0x10 */23 u32 mmcr[16]; /* 0x30 */24 u32 mbagcr[6]; /* 0x70 */25 u32 maer; /* 0x88 */26 u8 res0[0x14]; /* 0x8c */[all …]