1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __DRM_ANALOGIX_DP_H__ 8 #define __DRM_ANALOGIX_DP_H__ 9 10 #include <generic-phy.h> 11 #include <regmap.h> 12 #include <reset.h> 13 14 #include <drm/drm_dp_helper.h> 15 16 #include "rockchip_connector.h" 17 18 #define ANALOGIX_DP_TX_SW_RESET 0x14 19 #define ANALOGIX_DP_FUNC_EN_1 0x18 20 #define ANALOGIX_DP_FUNC_EN_2 0x1C 21 #define ANALOGIX_DP_VIDEO_CTL_1 0x20 22 #define ANALOGIX_DP_VIDEO_CTL_2 0x24 23 #define ANALOGIX_DP_VIDEO_CTL_3 0x28 24 #define ANALOGIX_DP_VIDEO_CTL_4 0x2C 25 #define ANALOGIX_DP_VIDEO_CTL_8 0x3C 26 #define ANALOGIX_DP_VIDEO_CTL_10 0x44 27 28 #define ANALOGIX_DP_TOTAL_LINE_CFG_L 0x48 29 #define ANALOGIX_DP_TOTAL_LINE_CFG_H 0x4C 30 #define ANALOGIX_DP_ACTIVE_LINE_CFG_L 0x50 31 #define ANALOGIX_DP_ACTIVE_LINE_CFG_H 0x54 32 #define ANALOGIX_DP_V_F_PORCH_CFG 0x58 33 #define ANALOGIX_DP_V_SYNC_WIDTH_CFG 0x5C 34 #define ANALOGIX_DP_V_B_PORCH_CFG 0x60 35 #define ANALOGIX_DP_TOTAL_PIXEL_CFG_L 0x64 36 #define ANALOGIX_DP_TOTAL_PIXEL_CFG_H 0x68 37 #define ANALOGIX_DP_ACTIVE_PIXEL_CFG_L 0x6C 38 #define ANALOGIX_DP_ACTIVE_PIXEL_CFG_H 0x70 39 #define ANALOGIX_DP_H_F_PORCH_CFG_L 0x74 40 #define ANALOGIX_DP_H_F_PORCH_CFG_H 0x78 41 #define ANALOGIX_DP_H_SYNC_CFG_L 0x7C 42 #define ANALOGIX_DP_H_SYNC_CFG_H 0x80 43 #define ANALOGIX_DP_H_B_PORCH_CFG_L 0x84 44 #define ANALOGIX_DP_H_B_PORCH_CFG_H 0x88 45 46 #define ANALOGIX_DP_PLL_REG_1 0xfc 47 #define ANALOGIX_DP_PLL_REG_2 0x9e4 48 #define ANALOGIX_DP_PLL_REG_3 0x9e8 49 #define ANALOGIX_DP_PLL_REG_4 0x9ec 50 #define ANALOGIX_DP_PLL_REG_5 0xa00 51 52 #define ANALOGIX_DP_BIAS 0x124 53 #define ANALOGIX_DP_PD 0x12c 54 55 #define ANALOGIX_DP_LANE_MAP 0x35C 56 57 #define ANALOGIX_DP_ANALOG_CTL_1 0x370 58 #define ANALOGIX_DP_ANALOG_CTL_2 0x374 59 #define ANALOGIX_DP_ANALOG_CTL_3 0x378 60 #define ANALOGIX_DP_PLL_FILTER_CTL_1 0x37C 61 #define ANALOGIX_DP_TX_AMP_TUNING_CTL 0x380 62 63 #define ANALOGIX_DP_AUX_HW_RETRY_CTL 0x390 64 65 #define ANALOGIX_DP_COMMON_INT_STA_1 0x3C4 66 #define ANALOGIX_DP_COMMON_INT_STA_2 0x3C8 67 #define ANALOGIX_DP_COMMON_INT_STA_3 0x3CC 68 #define ANALOGIX_DP_COMMON_INT_STA_4 0x3D0 69 #define ANALOGIX_DP_INT_STA 0x3DC 70 #define ANALOGIX_DP_COMMON_INT_MASK_1 0x3E0 71 #define ANALOGIX_DP_COMMON_INT_MASK_2 0x3E4 72 #define ANALOGIX_DP_COMMON_INT_MASK_3 0x3E8 73 #define ANALOGIX_DP_COMMON_INT_MASK_4 0x3EC 74 #define ANALOGIX_DP_INT_STA_MASK 0x3F8 75 #define ANALOGIX_DP_INT_CTL 0x3FC 76 77 #define ANALOGIX_DP_SYS_CTL_1 0x600 78 #define ANALOGIX_DP_SYS_CTL_2 0x604 79 #define ANALOGIX_DP_SYS_CTL_3 0x608 80 #define ANALOGIX_DP_SYS_CTL_4 0x60C 81 82 #define ANALOGIX_DP_PKT_SEND_CTL 0x640 83 #define ANALOGIX_DP_HDCP_CTL 0x648 84 85 #define ANALOGIX_DP_LINK_BW_SET 0x680 86 #define ANALOGIX_DP_LANE_COUNT_SET 0x684 87 #define ANALOGIX_DP_TRAINING_PTN_SET 0x688 88 #define ANALOGIX_DP_LN0_LINK_TRAINING_CTL 0x68C 89 #define ANALOGIX_DP_LN1_LINK_TRAINING_CTL 0x690 90 #define ANALOGIX_DP_LN2_LINK_TRAINING_CTL 0x694 91 #define ANALOGIX_DP_LN3_LINK_TRAINING_CTL 0x698 92 93 #define ANALOGIX_DP_DEBUG_CTL 0x6C0 94 #define ANALOGIX_DP_HPD_DEGLITCH_L 0x6C4 95 #define ANALOGIX_DP_HPD_DEGLITCH_H 0x6C8 96 #define ANALOGIX_DP_LINK_DEBUG_CTL 0x6E0 97 98 #define ANALOGIX_DP_M_VID_0 0x700 99 #define ANALOGIX_DP_M_VID_1 0x704 100 #define ANALOGIX_DP_M_VID_2 0x708 101 #define ANALOGIX_DP_N_VID_0 0x70C 102 #define ANALOGIX_DP_N_VID_1 0x710 103 #define ANALOGIX_DP_N_VID_2 0x714 104 105 #define ANALOGIX_DP_PLL_CTL 0x71C 106 #define ANALOGIX_DP_PHY_PD 0x720 107 #define ANALOGIX_DP_PHY_TEST 0x724 108 109 #define ANALOGIX_DP_VIDEO_FIFO_THRD 0x730 110 #define ANALOGIX_DP_AUDIO_MARGIN 0x73C 111 112 #define ANALOGIX_DP_M_VID_GEN_FILTER_TH 0x764 113 #define ANALOGIX_DP_M_AUD_GEN_FILTER_TH 0x778 114 #define ANALOGIX_DP_AUX_CH_STA 0x780 115 #define ANALOGIX_DP_AUX_CH_DEFER_CTL 0x788 116 #define ANALOGIX_DP_AUX_RX_COMM 0x78C 117 #define ANALOGIX_DP_BUFFER_DATA_CTL 0x790 118 #define ANALOGIX_DP_AUX_CH_CTL_1 0x794 119 #define ANALOGIX_DP_AUX_ADDR_7_0 0x798 120 #define ANALOGIX_DP_AUX_ADDR_15_8 0x79C 121 #define ANALOGIX_DP_AUX_ADDR_19_16 0x7A0 122 #define ANALOGIX_DP_AUX_CH_CTL_2 0x7A4 123 124 #define ANALOGIX_DP_BUF_DATA_0 0x7C0 125 126 #define ANALOGIX_DP_SOC_GENERAL_CTL 0x800 127 128 /* ANALOGIX_DP_TX_SW_RESET */ 129 #define RESET_DP_TX (0x1 << 0) 130 131 /* ANALOGIX_DP_FUNC_EN_1 */ 132 #define MASTER_VID_FUNC_EN_N (0x1 << 7) 133 #define SLAVE_VID_FUNC_EN_N (0x1 << 5) 134 #define AUD_FIFO_FUNC_EN_N (0x1 << 4) 135 #define AUD_FUNC_EN_N (0x1 << 3) 136 #define HDCP_FUNC_EN_N (0x1 << 2) 137 #define CRC_FUNC_EN_N (0x1 << 1) 138 #define SW_FUNC_EN_N (0x1 << 0) 139 140 /* ANALOGIX_DP_FUNC_EN_2 */ 141 #define SSC_FUNC_EN_N (0x1 << 7) 142 #define AUX_FUNC_EN_N (0x1 << 2) 143 #define SERDES_FIFO_FUNC_EN_N (0x1 << 1) 144 #define LS_CLK_DOMAIN_FUNC_EN_N (0x1 << 0) 145 146 /* ANALOGIX_DP_VIDEO_CTL_1 */ 147 #define VIDEO_EN (0x1 << 7) 148 #define HDCP_VIDEO_MUTE (0x1 << 6) 149 150 /* ANALOGIX_DP_VIDEO_CTL_4 */ 151 #define BIST_EN (0x1 << 3) 152 #define BIST_WIDTH(x) (((x) & 0x1) << 2) 153 #define BIST_TYPE(x) (((x) & 0x3) << 0) 154 155 /* ANALOGIX_DP_VIDEO_CTL_1 */ 156 #define IN_D_RANGE_MASK (0x1 << 7) 157 #define IN_D_RANGE_SHIFT (7) 158 #define IN_D_RANGE_CEA (0x1 << 7) 159 #define IN_D_RANGE_VESA (0x0 << 7) 160 #define IN_BPC_MASK (0x7 << 4) 161 #define IN_BPC_SHIFT (4) 162 #define IN_BPC_12_BITS (0x3 << 4) 163 #define IN_BPC_10_BITS (0x2 << 4) 164 #define IN_BPC_8_BITS (0x1 << 4) 165 #define IN_BPC_6_BITS (0x0 << 4) 166 #define IN_COLOR_F_MASK (0x3 << 0) 167 #define IN_COLOR_F_SHIFT (0) 168 #define IN_COLOR_F_YCBCR444 (0x2 << 0) 169 #define IN_COLOR_F_YCBCR422 (0x1 << 0) 170 #define IN_COLOR_F_RGB (0x0 << 0) 171 172 /* ANALOGIX_DP_VIDEO_CTL_3 */ 173 #define IN_YC_COEFFI_MASK (0x1 << 7) 174 #define IN_YC_COEFFI_SHIFT (7) 175 #define IN_YC_COEFFI_ITU709 (0x1 << 7) 176 #define IN_YC_COEFFI_ITU601 (0x0 << 7) 177 #define VID_CHK_UPDATE_TYPE_MASK (0x1 << 4) 178 #define VID_CHK_UPDATE_TYPE_SHIFT (4) 179 #define VID_CHK_UPDATE_TYPE_1 (0x1 << 4) 180 #define VID_CHK_UPDATE_TYPE_0 (0x0 << 4) 181 182 /* ANALOGIX_DP_VIDEO_CTL_8 */ 183 #define VID_HRES_TH(x) (((x) & 0xf) << 4) 184 #define VID_VRES_TH(x) (((x) & 0xf) << 0) 185 186 /* ANALOGIX_DP_VIDEO_CTL_10 */ 187 #define FORMAT_SEL (0x1 << 4) 188 #define INTERACE_SCAN_CFG (0x1 << 2) 189 #define VSYNC_POLARITY_CFG (0x1 << 1) 190 #define HSYNC_POLARITY_CFG (0x1 << 0) 191 192 /* ANALOGIX_DP_TOTAL_LINE_CFG_L */ 193 #define TOTAL_LINE_CFG_L(x) (((x) & 0xff) << 0) 194 195 /* ANALOGIX_DP_TOTAL_LINE_CFG_H */ 196 #define TOTAL_LINE_CFG_H(x) (((x) & 0xf) << 0) 197 198 /* ANALOGIX_DP_ACTIVE_LINE_CFG_L */ 199 #define ACTIVE_LINE_CFG_L(x) (((x) & 0xff) << 0) 200 201 /* ANALOGIX_DP_ACTIVE_LINE_CFG_H */ 202 #define ACTIVE_LINE_CFG_H(x) (((x) & 0xf) << 0) 203 204 /* ANALOGIX_DP_V_F_PORCH_CFG */ 205 #define V_F_PORCH_CFG(x) (((x) & 0xff) << 0) 206 207 /* ANALOGIX_DP_V_SYNC_WIDTH_CFG */ 208 #define V_SYNC_WIDTH_CFG(x) (((x) & 0xff) << 0) 209 210 /* ANALOGIX_DP_V_B_PORCH_CFG */ 211 #define V_B_PORCH_CFG(x) (((x) & 0xff) << 0) 212 213 /* ANALOGIX_DP_TOTAL_PIXEL_CFG_L */ 214 #define TOTAL_PIXEL_CFG_L(x) (((x) & 0xff) << 0) 215 216 /* ANALOGIX_DP_TOTAL_PIXEL_CFG_H */ 217 #define TOTAL_PIXEL_CFG_H(x) (((x) & 0x3f) << 0) 218 219 /* ANALOGIX_DP_ACTIVE_PIXEL_CFG_L */ 220 #define ACTIVE_PIXEL_CFG_L(x) (((x) & 0xff) << 0) 221 222 /* ANALOGIX_DP_ACTIVE_PIXEL_CFG_H */ 223 #define ACTIVE_PIXEL_CFG_H(x) (((x) & 0x3f) << 0) 224 225 /* ANALOGIX_DP_H_F_PORCH_CFG_L */ 226 #define H_F_PORCH_CFG_L(x) (((x) & 0xff) << 0) 227 228 /* ANALOGIX_DP_H_F_PORCH_CFG_H */ 229 #define H_F_PORCH_CFG_H(x) (((x) & 0xf) << 0) 230 231 /* ANALOGIX_DP_H_SYNC_CFG_L */ 232 #define H_SYNC_CFG_L(x) (((x) & 0xff) << 0) 233 234 /* ANALOGIX_DP_H_SYNC_CFG_H */ 235 #define H_SYNC_CFG_H(x) (((x) & 0xf) << 0) 236 237 /* ANALOGIX_DP_H_B_PORCH_CFG_L */ 238 #define H_B_PORCH_CFG_L(x) (((x) & 0xff) << 0) 239 240 /* ANALOGIX_DP_H_B_PORCH_CFG_H */ 241 #define H_B_PORCH_CFG_H(x) (((x) & 0xf) << 0) 242 243 /* ANALOGIX_DP_PLL_REG_1 */ 244 #define REF_CLK_24M (0x1 << 0) 245 #define REF_CLK_27M (0x0 << 0) 246 #define REF_CLK_MASK (0x1 << 0) 247 248 /* ANALOGIX_DP_LANE_MAP */ 249 #define LANE3_MAP_LOGIC_LANE_0 (0x0 << 6) 250 #define LANE3_MAP_LOGIC_LANE_1 (0x1 << 6) 251 #define LANE3_MAP_LOGIC_LANE_2 (0x2 << 6) 252 #define LANE3_MAP_LOGIC_LANE_3 (0x3 << 6) 253 #define LANE2_MAP_LOGIC_LANE_0 (0x0 << 4) 254 #define LANE2_MAP_LOGIC_LANE_1 (0x1 << 4) 255 #define LANE2_MAP_LOGIC_LANE_2 (0x2 << 4) 256 #define LANE2_MAP_LOGIC_LANE_3 (0x3 << 4) 257 #define LANE1_MAP_LOGIC_LANE_0 (0x0 << 2) 258 #define LANE1_MAP_LOGIC_LANE_1 (0x1 << 2) 259 #define LANE1_MAP_LOGIC_LANE_2 (0x2 << 2) 260 #define LANE1_MAP_LOGIC_LANE_3 (0x3 << 2) 261 #define LANE0_MAP_LOGIC_LANE_0 (0x0 << 0) 262 #define LANE0_MAP_LOGIC_LANE_1 (0x1 << 0) 263 #define LANE0_MAP_LOGIC_LANE_2 (0x2 << 0) 264 #define LANE0_MAP_LOGIC_LANE_3 (0x3 << 0) 265 266 /* ANALOGIX_DP_ANALOG_CTL_1 */ 267 #define TX_TERMINAL_CTRL_50_OHM (0x1 << 4) 268 269 /* ANALOGIX_DP_ANALOG_CTL_2 */ 270 #define SEL_24M (0x1 << 3) 271 #define TX_DVDD_BIT_1_0625V (0x4 << 0) 272 273 /* ANALOGIX_DP_ANALOG_CTL_3 */ 274 #define DRIVE_DVDD_BIT_1_0625V (0x4 << 5) 275 #define VCO_BIT_600_MICRO (0x5 << 0) 276 277 /* ANALOGIX_DP_PLL_FILTER_CTL_1 */ 278 #define PD_RING_OSC (0x1 << 6) 279 #define AUX_TERMINAL_CTRL_50_OHM (0x2 << 4) 280 #define TX_CUR1_2X (0x1 << 2) 281 #define TX_CUR_16_MA (0x3 << 0) 282 283 /* ANALOGIX_DP_TX_AMP_TUNING_CTL */ 284 #define CH3_AMP_400_MV (0x0 << 24) 285 #define CH2_AMP_400_MV (0x0 << 16) 286 #define CH1_AMP_400_MV (0x0 << 8) 287 #define CH0_AMP_400_MV (0x0 << 0) 288 289 /* ANALOGIX_DP_AUX_HW_RETRY_CTL */ 290 #define AUX_BIT_PERIOD_EXPECTED_DELAY(x) (((x) & 0x7) << 8) 291 #define AUX_HW_RETRY_INTERVAL_MASK (0x3 << 3) 292 #define AUX_HW_RETRY_INTERVAL_600_MICROSECONDS (0x0 << 3) 293 #define AUX_HW_RETRY_INTERVAL_800_MICROSECONDS (0x1 << 3) 294 #define AUX_HW_RETRY_INTERVAL_1000_MICROSECONDS (0x2 << 3) 295 #define AUX_HW_RETRY_INTERVAL_1800_MICROSECONDS (0x3 << 3) 296 #define AUX_HW_RETRY_COUNT_SEL(x) (((x) & 0x7) << 0) 297 298 /* ANALOGIX_DP_COMMON_INT_STA_1 */ 299 #define VSYNC_DET (0x1 << 7) 300 #define PLL_LOCK_CHG (0x1 << 6) 301 #define SPDIF_ERR (0x1 << 5) 302 #define SPDIF_UNSTBL (0x1 << 4) 303 #define VID_FORMAT_CHG (0x1 << 3) 304 #define AUD_CLK_CHG (0x1 << 2) 305 #define VID_CLK_CHG (0x1 << 1) 306 #define SW_INT (0x1 << 0) 307 308 /* ANALOGIX_DP_COMMON_INT_STA_2 */ 309 #define ENC_EN_CHG (0x1 << 6) 310 #define HW_BKSV_RDY (0x1 << 3) 311 #define HW_SHA_DONE (0x1 << 2) 312 #define HW_AUTH_STATE_CHG (0x1 << 1) 313 #define HW_AUTH_DONE (0x1 << 0) 314 315 /* ANALOGIX_DP_COMMON_INT_STA_3 */ 316 #define AFIFO_UNDER (0x1 << 7) 317 #define AFIFO_OVER (0x1 << 6) 318 #define R0_CHK_FLAG (0x1 << 5) 319 320 /* ANALOGIX_DP_COMMON_INT_STA_4 */ 321 #define PSR_ACTIVE (0x1 << 7) 322 #define PSR_INACTIVE (0x1 << 6) 323 #define SPDIF_BI_PHASE_ERR (0x1 << 5) 324 #define HOTPLUG_CHG (0x1 << 2) 325 #define HPD_LOST (0x1 << 1) 326 #define PLUG (0x1 << 0) 327 328 /* ANALOGIX_DP_INT_STA */ 329 #define INT_HPD (0x1 << 6) 330 #define HW_TRAINING_FINISH (0x1 << 5) 331 #define RPLY_RECEIV (0x1 << 1) 332 #define AUX_ERR (0x1 << 0) 333 334 /* ANALOGIX_DP_INT_CTL */ 335 #define SOFT_INT_CTRL (0x1 << 2) 336 #define INT_POL1 (0x1 << 1) 337 #define INT_POL0 (0x1 << 0) 338 339 /* ANALOGIX_DP_SYS_CTL_1 */ 340 #define DET_STA (0x1 << 2) 341 #define FORCE_DET (0x1 << 1) 342 #define DET_CTRL (0x1 << 0) 343 344 /* ANALOGIX_DP_SYS_CTL_2 */ 345 #define CHA_CRI(x) (((x) & 0xf) << 4) 346 #define CHA_STA (0x1 << 2) 347 #define FORCE_CHA (0x1 << 1) 348 #define CHA_CTRL (0x1 << 0) 349 350 /* ANALOGIX_DP_SYS_CTL_3 */ 351 #define HPD_STATUS (0x1 << 6) 352 #define F_HPD (0x1 << 5) 353 #define HPD_CTRL (0x1 << 4) 354 #define HDCP_RDY (0x1 << 3) 355 #define STRM_VALID (0x1 << 2) 356 #define F_VALID (0x1 << 1) 357 #define VALID_CTRL (0x1 << 0) 358 359 /* ANALOGIX_DP_SYS_CTL_4 */ 360 #define FIX_M_AUD (0x1 << 4) 361 #define ENHANCED (0x1 << 3) 362 #define FIX_M_VID (0x1 << 2) 363 #define M_VID_UPDATE_CTRL (0x3 << 0) 364 365 /* ANALOGIX_DP_TRAINING_PTN_SET */ 366 #define SCRAMBLER_TYPE (0x1 << 9) 367 #define HW_LINK_TRAINING_PATTERN (0x1 << 8) 368 #define SCRAMBLING_DISABLE (0x1 << 5) 369 #define SCRAMBLING_ENABLE (0x0 << 5) 370 #define LINK_QUAL_PATTERN_SET_MASK (0x3 << 2) 371 #define LINK_QUAL_PATTERN_SET_PRBS7 (0x3 << 2) 372 #define LINK_QUAL_PATTERN_SET_D10_2 (0x1 << 2) 373 #define LINK_QUAL_PATTERN_SET_DISABLE (0x0 << 2) 374 #define SW_TRAINING_PATTERN_SET_MASK (0x3 << 0) 375 #define SW_TRAINING_PATTERN_SET_PTN3 (0x3 << 0) 376 #define SW_TRAINING_PATTERN_SET_PTN2 (0x2 << 0) 377 #define SW_TRAINING_PATTERN_SET_PTN1 (0x1 << 0) 378 #define SW_TRAINING_PATTERN_SET_NORMAL (0x0 << 0) 379 380 /* ANALOGIX_DP_LN0_LINK_TRAINING_CTL */ 381 #define PRE_EMPHASIS_SET_MASK (0x3 << 3) 382 #define PRE_EMPHASIS_SET_SHIFT (3) 383 384 /* ANALOGIX_DP_DEBUG_CTL */ 385 #define PLL_LOCK (0x1 << 4) 386 #define F_PLL_LOCK (0x1 << 3) 387 #define PLL_LOCK_CTRL (0x1 << 2) 388 #define PN_INV (0x1 << 0) 389 390 /* ANALOGIX_DP_PLL_CTL */ 391 #define DP_PLL_PD (0x1 << 7) 392 #define DP_PLL_RESET (0x1 << 6) 393 #define DP_PLL_LOOP_BIT_DEFAULT (0x1 << 4) 394 #define DP_PLL_REF_BIT_1_1250V (0x5 << 0) 395 #define DP_PLL_REF_BIT_1_2500V (0x7 << 0) 396 397 /* ANALOGIX_DP_PHY_PD */ 398 #define DP_PHY_PD (0x1 << 5) 399 #define AUX_PD (0x1 << 4) 400 #define CH3_PD (0x1 << 3) 401 #define CH2_PD (0x1 << 2) 402 #define CH1_PD (0x1 << 1) 403 #define CH0_PD (0x1 << 0) 404 405 /* ANALOGIX_DP_PHY_TEST */ 406 #define MACRO_RST (0x1 << 5) 407 #define CH1_TEST (0x1 << 1) 408 #define CH0_TEST (0x1 << 0) 409 410 /* ANALOGIX_DP_AUX_CH_STA */ 411 #define AUX_BUSY (0x1 << 4) 412 #define AUX_STATUS_MASK (0xf << 0) 413 414 /* ANALOGIX_DP_AUX_CH_DEFER_CTL */ 415 #define DEFER_CTRL_EN (0x1 << 7) 416 #define DEFER_COUNT(x) (((x) & 0x7f) << 0) 417 418 /* ANALOGIX_DP_AUX_RX_COMM */ 419 #define AUX_RX_COMM_I2C_DEFER (0x2 << 2) 420 #define AUX_RX_COMM_AUX_DEFER (0x2 << 0) 421 422 /* ANALOGIX_DP_BUFFER_DATA_CTL */ 423 #define BUF_CLR (0x1 << 7) 424 #define BUF_DATA_COUNT(x) (((x) & 0x1f) << 0) 425 426 /* ANALOGIX_DP_AUX_CH_CTL_1 */ 427 #define AUX_LENGTH(x) (((x - 1) & 0xf) << 4) 428 #define AUX_TX_COMM_MASK (0xf << 0) 429 #define AUX_TX_COMM_DP_TRANSACTION (0x1 << 3) 430 #define AUX_TX_COMM_I2C_TRANSACTION (0x0 << 3) 431 #define AUX_TX_COMM_MOT (0x1 << 2) 432 #define AUX_TX_COMM_WRITE (0x0 << 0) 433 #define AUX_TX_COMM_READ (0x1 << 0) 434 435 /* ANALOGIX_DP_AUX_ADDR_7_0 */ 436 #define AUX_ADDR_7_0(x) (((x) >> 0) & 0xff) 437 438 /* ANALOGIX_DP_AUX_ADDR_15_8 */ 439 #define AUX_ADDR_15_8(x) (((x) >> 8) & 0xff) 440 441 /* ANALOGIX_DP_AUX_ADDR_19_16 */ 442 #define AUX_ADDR_19_16(x) (((x) >> 16) & 0x0f) 443 444 /* ANALOGIX_DP_AUX_CH_CTL_2 */ 445 #define ADDR_ONLY (0x1 << 1) 446 #define AUX_EN (0x1 << 0) 447 448 /* ANALOGIX_DP_SOC_GENERAL_CTL */ 449 #define AUDIO_MODE_SPDIF_MODE (0x1 << 8) 450 #define AUDIO_MODE_MASTER_MODE (0x0 << 8) 451 #define MASTER_VIDEO_INTERLACE_EN (0x1 << 4) 452 #define VIDEO_MASTER_CLK_SEL (0x1 << 2) 453 #define VIDEO_MASTER_MODE_EN (0x1 << 1) 454 #define VIDEO_MODE_MASK (0x1 << 0) 455 #define VIDEO_MODE_SLAVE_MODE (0x1 << 0) 456 #define VIDEO_MODE_MASTER_MODE (0x0 << 0) 457 458 #define DP_TIMEOUT_LOOP_COUNT 100 459 #define MAX_CR_LOOP 5 460 #define MAX_EQ_LOOP 5 461 462 /* I2C EDID Chip ID, Slave Address */ 463 #define I2C_EDID_DEVICE_ADDR 0x50 464 #define I2C_E_EDID_DEVICE_ADDR 0x30 465 466 #define EDID_BLOCK_LENGTH 0x80 467 #define EDID_HEADER_PATTERN 0x00 468 #define EDID_EXTENSION_FLAG 0x7e 469 #define EDID_CHECKSUM 0x7f 470 471 /* DP_MAX_LANE_COUNT */ 472 #define DPCD_ENHANCED_FRAME_CAP(x) (((x) >> 7) & 0x1) 473 #define DPCD_MAX_LANE_COUNT(x) ((x) & 0x1f) 474 475 /* DP_LANE_COUNT_SET */ 476 #define DPCD_LANE_COUNT_SET(x) ((x) & 0x1f) 477 478 /* DP_TRAINING_LANE0_SET */ 479 #define DPCD_PRE_EMPHASIS_SET(x) (((x) & 0x3) << 3) 480 #define DPCD_PRE_EMPHASIS_GET(x) (((x) >> 3) & 0x3) 481 #define DPCD_VOLTAGE_SWING_SET(x) (((x) & 0x3) << 0) 482 #define DPCD_VOLTAGE_SWING_GET(x) (((x) >> 0) & 0x3) 483 484 enum link_lane_count_type { 485 LANE_COUNT1 = 1, 486 LANE_COUNT2 = 2, 487 LANE_COUNT4 = 4 488 }; 489 490 enum link_training_state { 491 START, 492 CLOCK_RECOVERY, 493 EQUALIZER_TRAINING, 494 FINISHED, 495 FAILED 496 }; 497 498 enum voltage_swing_level { 499 VOLTAGE_LEVEL_0, 500 VOLTAGE_LEVEL_1, 501 VOLTAGE_LEVEL_2, 502 VOLTAGE_LEVEL_3, 503 }; 504 505 enum pre_emphasis_level { 506 PRE_EMPHASIS_LEVEL_0, 507 PRE_EMPHASIS_LEVEL_1, 508 PRE_EMPHASIS_LEVEL_2, 509 PRE_EMPHASIS_LEVEL_3, 510 }; 511 512 enum pattern_set { 513 PRBS7, 514 D10_2, 515 TRAINING_PTN1, 516 TRAINING_PTN2, 517 TRAINING_PTN3, 518 DP_NONE 519 }; 520 521 enum color_space { 522 COLOR_RGB, 523 COLOR_YCBCR422, 524 COLOR_YCBCR444 525 }; 526 527 enum color_depth { 528 COLOR_6, 529 COLOR_8, 530 COLOR_10, 531 COLOR_12 532 }; 533 534 enum color_coefficient { 535 COLOR_YCBCR601, 536 COLOR_YCBCR709 537 }; 538 539 enum dynamic_range { 540 VESA, 541 CEA 542 }; 543 544 enum pll_status { 545 PLL_UNLOCKED, 546 PLL_LOCKED 547 }; 548 549 enum clock_recovery_m_value_type { 550 CALCULATED_M, 551 REGISTER_M 552 }; 553 554 enum video_timing_recognition_type { 555 VIDEO_TIMING_FROM_CAPTURE, 556 VIDEO_TIMING_FROM_REGISTER 557 }; 558 559 enum analog_power_block { 560 AUX_BLOCK, 561 CH0_BLOCK, 562 CH1_BLOCK, 563 CH2_BLOCK, 564 CH3_BLOCK, 565 ANALOG_TOTAL, 566 POWER_ALL 567 }; 568 569 enum dp_irq_type { 570 DP_IRQ_TYPE_HP_CABLE_IN = BIT(0), 571 DP_IRQ_TYPE_HP_CABLE_OUT = BIT(1), 572 DP_IRQ_TYPE_HP_CHANGE = BIT(2), 573 DP_IRQ_TYPE_UNKNOWN = BIT(3), 574 }; 575 576 struct video_info { 577 char *name; 578 579 bool h_sync_polarity; 580 bool v_sync_polarity; 581 bool interlaced; 582 583 enum color_space color_space; 584 enum dynamic_range dynamic_range; 585 enum color_coefficient ycbcr_coeff; 586 enum color_depth color_depth; 587 588 int max_link_rate; 589 enum link_lane_count_type max_lane_count; 590 591 bool force_stream_valid; 592 }; 593 594 struct link_train { 595 int eq_loop; 596 int cr_loop[4]; 597 598 u8 link_rate; 599 u8 lane_count; 600 u8 training_lane[4]; 601 bool ssc; 602 603 enum link_training_state lt_state; 604 }; 605 606 enum analogix_dp_devtype { 607 EXYNOS_DP, 608 ROCKCHIP_DP, 609 }; 610 611 enum analogix_dp_sub_devtype { 612 RK3288_DP, 613 RK3368_EDP, 614 RK3399_EDP, 615 RK3568_EDP, 616 RK3588_EDP 617 }; 618 619 struct analogix_dp_plat_data { 620 enum analogix_dp_devtype dev_type; 621 enum analogix_dp_sub_devtype subdev_type; 622 bool ssc; 623 }; 624 625 struct analogix_dp_device { 626 struct rockchip_connector connector; 627 int id; 628 struct udevice *dev; 629 void *reg_base; 630 struct regmap *grf; 631 struct phy phy; 632 struct reset_ctl_bulk resets; 633 struct gpio_desc hpd_gpio; 634 bool force_hpd; 635 struct video_info video_info; 636 struct link_train link_train; 637 struct drm_display_mode *mode; 638 struct analogix_dp_plat_data plat_data; 639 unsigned char edid[EDID_BLOCK_LENGTH * 2]; 640 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 641 bool video_bist_enable; 642 u32 lane_map[4]; 643 }; 644 645 /* analogix_dp_reg.c */ 646 void analogix_dp_enable_video_mute(struct analogix_dp_device *dp, bool enable); 647 void analogix_dp_stop_video(struct analogix_dp_device *dp); 648 void analogix_dp_init_analog_param(struct analogix_dp_device *dp); 649 void analogix_dp_init_interrupt(struct analogix_dp_device *dp); 650 void analogix_dp_reset(struct analogix_dp_device *dp); 651 void analogix_dp_swreset(struct analogix_dp_device *dp); 652 void analogix_dp_config_interrupt(struct analogix_dp_device *dp); 653 void analogix_dp_mute_hpd_interrupt(struct analogix_dp_device *dp); 654 void analogix_dp_unmute_hpd_interrupt(struct analogix_dp_device *dp); 655 enum pll_status analogix_dp_get_pll_lock_status(struct analogix_dp_device *dp); 656 void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable); 657 void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp, 658 enum analog_power_block block, 659 bool enable); 660 void analogix_dp_init_analog_func(struct analogix_dp_device *dp); 661 void analogix_dp_init_hpd(struct analogix_dp_device *dp); 662 void analogix_dp_force_hpd(struct analogix_dp_device *dp); 663 enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp); 664 void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp); 665 void analogix_dp_reset_aux(struct analogix_dp_device *dp); 666 void analogix_dp_init_aux(struct analogix_dp_device *dp); 667 int analogix_dp_get_plug_in_status(struct analogix_dp_device *dp); 668 int analogix_dp_detect(struct analogix_dp_device *dp); 669 void analogix_dp_enable_sw_function(struct analogix_dp_device *dp); 670 int analogix_dp_start_aux_transaction(struct analogix_dp_device *dp); 671 int analogix_dp_write_byte_to_dpcd(struct analogix_dp_device *dp, 672 unsigned int reg_addr, 673 unsigned char data); 674 int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp, 675 unsigned int reg_addr, 676 unsigned char *data); 677 int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp, 678 unsigned int reg_addr, 679 unsigned int count, 680 unsigned char data[]); 681 int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp, 682 unsigned int reg_addr, 683 unsigned int count, 684 unsigned char data[]); 685 int analogix_dp_select_i2c_device(struct analogix_dp_device *dp, 686 unsigned int device_addr, 687 unsigned int reg_addr); 688 int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp, 689 unsigned int device_addr, 690 unsigned int reg_addr, 691 unsigned int *data); 692 int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp, 693 unsigned int device_addr, 694 unsigned int reg_addr, 695 unsigned int count, 696 unsigned char edid[]); 697 void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype); 698 void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype); 699 void analogix_dp_set_lane_count(struct analogix_dp_device *dp, u32 count); 700 void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count); 701 void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp, 702 bool enable); 703 void analogix_dp_set_training_pattern(struct analogix_dp_device *dp, 704 enum pattern_set pattern); 705 void analogix_dp_set_lane_link_training(struct analogix_dp_device *dp); 706 u32 analogix_dp_get_lane_link_training(struct analogix_dp_device *dp, u8 lane); 707 void analogix_dp_reset_macro(struct analogix_dp_device *dp); 708 void analogix_dp_init_video(struct analogix_dp_device *dp); 709 710 void analogix_dp_set_video_color_format(struct analogix_dp_device *dp); 711 int analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device *dp); 712 void analogix_dp_set_video_cr_mn(struct analogix_dp_device *dp, 713 enum clock_recovery_m_value_type type, 714 u32 m_value, 715 u32 n_value); 716 void analogix_dp_set_video_timing_mode(struct analogix_dp_device *dp, u32 type); 717 void analogix_dp_enable_video_master(struct analogix_dp_device *dp, 718 bool enable); 719 void analogix_dp_start_video(struct analogix_dp_device *dp); 720 int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp); 721 void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp); 722 void analogix_dp_enable_scrambling(struct analogix_dp_device *dp); 723 void analogix_dp_disable_scrambling(struct analogix_dp_device *dp); 724 bool analogix_dp_ssc_supported(struct analogix_dp_device *dp); 725 void analogix_dp_set_video_format(struct analogix_dp_device *dp, 726 const struct drm_display_mode *mode); 727 void analogix_dp_video_bist_enable(struct analogix_dp_device *dp); 728 729 #endif /* __DRM_ANALOGIX_DP__ */ 730