1 // SPDX-License-Identifier: BSD-2-Clause
2 /*
3 * Copyright (C) 2018-2025, STMicroelectronics
4 */
5 #include <assert.h>
6 #include <drivers/clk.h>
7 #include <drivers/clk_dt.h>
8 #include <drivers/rtc.h>
9 #include <drivers/stm32_rtc.h>
10 #include <drivers/stm32_rif.h>
11 #include <drivers/stm32_rtc.h>
12 #include <io.h>
13 #include <keep.h>
14 #include <kernel/dt.h>
15 #include <kernel/dt_driver.h>
16 #include <kernel/interrupt.h>
17 #include <kernel/notif.h>
18 #include <kernel/panic.h>
19 #include <kernel/pm.h>
20 #include <kernel/spinlock.h>
21 #include <libfdt.h>
22 #include <mm/core_memprot.h>
23
24 /*
25 * Registers
26 */
27 #define RTC_TR U(0x00)
28 #define RTC_DR U(0x04)
29 #define RTC_SSR U(0x08)
30 #define RTC_ICSR U(0x0C)
31 #define RTC_PRER U(0x10)
32 #define RTC_WUTR U(0x14)
33 #define RTC_CR U(0x18)
34 #define RTC_PRIVCFGR U(0x1C)
35 /* RTC_SMCR is linked to RTC3v1_2 */
36 #define RTC_SMCR U(0x20)
37 /* RTC_SECCFGR is linked to RTC3v3_2 and above */
38 #define RTC_SECCFGR U(0x20)
39 #define RTC_WPR U(0x24)
40 #define RTC_CALR U(0x28)
41 #define RTC_SHIFTR U(0x2C)
42 #define RTC_TSTR U(0x30)
43 #define RTC_TSDR U(0x34)
44 #define RTC_TSSSR U(0x38)
45 #define RTC_ALRMAR U(0x40)
46 #define RTC_ALRMASSR U(0x44)
47 #define RTC_ALRMBR U(0x48)
48 #define RTC_ALRMBSSR U(0x4C)
49 #define RTC_SR U(0x50)
50 #define RTC_SCR U(0x5C)
51 #define RTC_OR U(0x60)
52 #define RTC_CIDCFGR(x) (U(0x80) + U(0x4) * (x))
53
54 #define RTC_TR_SU_MASK GENMASK_32(3, 0)
55 #define RTC_TR_ST_MASK GENMASK_32(6, 4)
56 #define RTC_TR_ST_SHIFT U(4)
57 #define RTC_TR_MNU_MASK GENMASK_32(11, 8)
58 #define RTC_TR_MNU_SHIFT U(8)
59 #define RTC_TR_MNT_MASK GENMASK_32(14, 12)
60 #define RTC_TR_MNT_SHIFT U(12)
61 #define RTC_TR_HU_MASK GENMASK_32(19, 16)
62 #define RTC_TR_HU_SHIFT U(16)
63 #define RTC_TR_HT_MASK GENMASK_32(21, 20)
64 #define RTC_TR_HT_SHIFT U(20)
65 #define RTC_TR_PM BIT(22)
66
67 #define RTC_DR_DU_MASK GENMASK_32(3, 0)
68 #define RTC_DR_DT_MASK GENMASK_32(5, 4)
69 #define RTC_DR_DT_SHIFT U(4)
70 #define RTC_DR_MU_MASK GENMASK_32(11, 8)
71 #define RTC_DR_MU_SHIFT U(8)
72 #define RTC_DR_MT_MASK BIT(12)
73 #define RTC_DR_MT_SHIFT U(12)
74 #define RTC_DR_WDU_MASK GENMASK_32(15, 13)
75 #define RTC_DR_WDU_SHIFT U(13)
76 #define RTC_DR_YU_MASK GENMASK_32(19, 16)
77 #define RTC_DR_YU_SHIFT U(16)
78 #define RTC_DR_YT_MASK GENMASK_32(23, 20)
79 #define RTC_DR_YT_SHIFT U(20)
80
81 #define RTC_SSR_SS_MASK GENMASK_32(15, 0)
82
83 #define RTC_ICSR_RSF BIT(5)
84 #define RTC_ICSR_INITF BIT(6)
85 #define RTC_ICSR_INIT BIT(7)
86
87 #define RTC_PRER_PREDIV_S_SHIFT U(0)
88 #define RTC_PRER_PREDIV_S_MASK GENMASK_32(14, 0)
89 #define RTC_PRER_PREDIV_A_SHIFT U(16)
90 #define RTC_PRER_PREDIV_A_MASK GENMASK_32(22, 16)
91
92 #define RTC_CR_BYPSHAD BIT(5)
93 #define RTC_CR_BYPSHAD_SHIFT U(5)
94 #define RTC_CR_FMT BIT(6)
95 #define RTC_CR_ALRAE BIT(8)
96 #define RTC_CR_ALRAIE BIT(12)
97 #define RTC_CR_TAMPTS BIT(25)
98
99 #define RTC_PRIVCFGR_VALUES GENMASK_32(3, 0)
100 #define RTC_PRIVCFGR_VALUES_TO_SHIFT GENMASK_32(5, 4)
101 #define RTC_PRIVCFGR_SHIFT U(9)
102 #define RTC_PRIVCFGR_MASK (GENMASK_32(14, 13) | GENMASK_32(3, 0))
103 #define RTC_PRIVCFGR_FULL_PRIV BIT(15)
104
105 #define RTC_SMCR_TS_DPROT BIT(3)
106
107 #define RTC_SECCFGR_VALUES GENMASK_32(3, 0)
108 #define RTC_SECCFGR_TS_SEC BIT(3)
109 #define RTC_SECCFGR_VALUES_TO_SHIFT GENMASK_32(5, 4)
110 #define RTC_SECCFGR_SHIFT U(9)
111 #define RTC_SECCFGR_MASK (GENMASK_32(14, 13) | GENMASK_32(3, 0))
112 #define RTC_SECCFGR_FULL_SEC BIT(15)
113
114 #define RTC_WPR_KEY1 U(0xCA)
115 #define RTC_WPR_KEY2 U(0x53)
116 #define RTC_WPR_KEY_LOCK U(0xFF)
117
118 #define RTC_TSDR_MU_MASK GENMASK_32(11, 8)
119 #define RTC_TSDR_MU_SHIFT U(8)
120 #define RTC_TSDR_DT_MASK GENMASK_32(5, 4)
121 #define RTC_TSDR_DT_SHIFT U(4)
122 #define RTC_TSDR_DU_MASK GENMASK_32(3, 0)
123 #define RTC_TSDR_DU_SHIFT U(0)
124
125 #define RTC_ALRMXR_SEC_UNITS_MASK GENMASK_32(3, 0)
126 #define RTC_ALRMXR_SEC_UNITS_SHIFT U(0)
127 #define RTC_ALRMXR_SEC_TENS_MASK GENMASK_32(6, 4)
128 #define RTC_ALRMXR_SEC_TENS_SHIFT U(4)
129 #define RTC_ALRMXR_SEC_MASK BIT(7)
130 #define RTC_ALRMXR_MIN_UNITS_MASK GENMASK_32(11, 8)
131 #define RTC_ALRMXR_MIN_UNITS_SHIFT U(8)
132 #define RTC_ALRMXR_MIN_TENS_MASK GENMASK_32(14, 12)
133 #define RTC_ALRMXR_MIN_TENS_SHIFT U(12)
134 #define RTC_ALRMXR_MIN_MASK BIT(15)
135 #define RTC_ALRMXR_HOUR_UNITS_MASK GENMASK_32(19, 16)
136 #define RTC_ALRMXR_HOUR_UNITS_SHIFT U(16)
137 #define RTC_ALRMXR_HOUR_TENS_MASK GENMASK_32(21, 20)
138 #define RTC_ALRMXR_HOUR_TENS_SHIFT U(20)
139 #define RTC_ALRMXR_PM BIT(22)
140 #define RTC_ALRMXR_HOUR_MASK BIT(23)
141 #define RTC_ALRMXR_DATE_UNITS_MASK GENMASK_32(27, 24)
142 #define RTC_ALRMXR_DATE_UNITS_SHIFT U(24)
143 #define RTC_ALRMXR_DATE_TENS_MASK GENMASK_32(29, 28)
144 #define RTC_ALRMXR_DATE_TENS_SHIFT U(28)
145
146 #define RTC_SR_ALRAF BIT(0)
147 #define RTC_SR_TSF BIT(3)
148 #define RTC_SR_TSOVF BIT(4)
149
150 #define RTC_SCR_CALRAF BIT(0)
151 #define RTC_SCR_CTSF BIT(3)
152 #define RTC_SCR_CTSOVF BIT(4)
153
154 #define RTC_CIDCFGR_SCID_MASK GENMASK_32(6, 4)
155 #define RTC_CIDCFGR_SCID_MASK_SHIFT U(4)
156 #define RTC_CIDCFGR_CONF_MASK (_CIDCFGR_CFEN | \
157 RTC_CIDCFGR_SCID_MASK)
158
159 /*
160 * RIF miscellaneous
161 */
162 #define RTC_NB_RIF_RESOURCES U(6)
163
164 #define RTC_RIF_FULL_PRIVILEGED U(0x3F)
165 #define RTC_RIF_FULL_SECURED U(0x3F)
166
167 #define RTC_NB_MAX_CID_SUPPORTED U(7)
168
169 /*
170 * Driver miscellaneous
171 */
172 #define RTC_RES_TIMESTAMP U(3)
173 #define RTC_RES_CALIBRATION U(4)
174 #define RTC_RES_INITIALIZATION U(5)
175
176 #define RTC_FLAGS_READ_TWICE BIT(0)
177
178 #define TIMEOUT_US_RTC_SHADOW U(10000)
179 #define TIMEOUT_US_RTC_GENERIC U(100000)
180
181 #define YEAR_REF ULL(2000)
182 #define YEAR_MAX (YEAR_REF + ULL(99))
183
184 struct rtc_compat {
185 bool has_seccfgr;
186 bool has_rif_support;
187 };
188
189 /*
190 * struct rtc_device - RTC device data
191 * @base: RTC IOMEM base address
192 * @compat: RTC compatible data
193 * @pclk: RTC bus clock
194 * @rtc_ck: RTC kernel clock
195 * @conf_data: RTC RIF configuration data, when supported
196 * @nb_res: Number of protectible RTC resources
197 * @ts_lock: Lock used for time stamping events handling
198 * @flags: RTC driver flags
199 * @is_secured: True if the RTC is fully secured
200 * @itr_chip: Interrupt chip
201 * @itr_num: Interrupt number
202 * @itr_handler: Interrupt handler
203 * @notif_id: Notification ID
204 * @wait_alarm_return_status: Status of the wait alarm thread
205 * @rtc: information for OP-TEE RTC device
206 */
207 struct rtc_device {
208 struct io_pa_va base;
209 const struct rtc_compat *compat;
210 struct clk *pclk;
211 struct clk *rtc_ck;
212 struct rif_conf_data *conf_data;
213 unsigned int nb_res;
214 unsigned int ts_lock;
215 uint8_t flags;
216 bool is_secured;
217 struct itr_chip *itr_chip;
218 size_t itr_num;
219 struct itr_handler *itr_handler;
220 uint32_t notif_id;
221 enum rtc_wait_alarm_status wait_alarm_return_status;
222 struct rtc *rtc;
223 };
224
225 /* Expect a single RTC instance */
226 static struct rtc_device rtc_dev;
227
get_base(void)228 static vaddr_t get_base(void)
229 {
230 assert(rtc_dev.base.pa);
231
232 return io_pa_or_va(&rtc_dev.base, 1);
233 }
234
stm32_rtc_write_unprotect(void)235 static void stm32_rtc_write_unprotect(void)
236 {
237 vaddr_t rtc_base = get_base();
238
239 io_write32(rtc_base + RTC_WPR, RTC_WPR_KEY1);
240 io_write32(rtc_base + RTC_WPR, RTC_WPR_KEY2);
241 }
242
stm32_rtc_write_protect(void)243 static void stm32_rtc_write_protect(void)
244 {
245 vaddr_t rtc_base = get_base();
246
247 io_write32(rtc_base + RTC_WPR, RTC_WPR_KEY_LOCK);
248 }
249
stm32_rtc_get_bypshad(void)250 static bool stm32_rtc_get_bypshad(void)
251 {
252 return io_read32(get_base() + RTC_CR) & RTC_CR_BYPSHAD;
253 }
254
255 /* Get the subsecond value. */
stm32_rtc_get_subsecond(uint32_t ssr)256 static uint32_t stm32_rtc_get_subsecond(uint32_t ssr)
257 {
258 uint32_t prediv_s = io_read32(get_base() + RTC_PRER) &
259 RTC_PRER_PREDIV_S_MASK;
260
261 return prediv_s - ssr;
262 }
263
264 /*
265 * Get the subsecond scale.
266 *
267 * Number of subseconds in a second is linked to RTC PREDIV_S value.
268 * The higher PREDIV_S is, the more subsecond is precise.
269 */
stm32_rtc_get_subsecond_scale(void)270 static uint32_t stm32_rtc_get_subsecond_scale(void)
271 {
272 return (io_read32(get_base() + RTC_PRER) & RTC_PRER_PREDIV_S_MASK) + 1;
273 }
274
cid1_has_access(unsigned int resource)275 static bool cid1_has_access(unsigned int resource)
276 {
277 uint32_t cidcfgr = io_read32(get_base() + RTC_CIDCFGR(resource));
278
279 return !(cidcfgr & _CIDCFGR_CFEN) ||
280 get_field_u32(cidcfgr, RTC_CIDCFGR_SCID_MASK) == RIF_CID1;
281 }
282
check_rif_config(void)283 static TEE_Result check_rif_config(void)
284 {
285 if (!cid1_has_access(RTC_RES_TIMESTAMP) ||
286 !cid1_has_access(RTC_RES_CALIBRATION) ||
287 !cid1_has_access(RTC_RES_INITIALIZATION))
288 return TEE_ERROR_ACCESS_DENIED;
289
290 return TEE_SUCCESS;
291 }
292
apply_rif_config(bool is_tdcid)293 static void apply_rif_config(bool is_tdcid)
294 {
295 vaddr_t base = get_base();
296 unsigned int shifted_values = 0;
297 uint32_t seccfgr = 0;
298 uint32_t privcfgr = 0;
299 uint32_t access_mask_reg = 0;
300 unsigned int i = 0;
301
302 if (!rtc_dev.conf_data)
303 return;
304
305 /* Build access mask for RTC_SECCFGR and RTC_PRIVCFGR */
306 for (i = 0; i < RTC_NB_RIF_RESOURCES; i++) {
307 if (rtc_dev.conf_data->access_mask[0] & BIT(i)) {
308 if (i <= RTC_RES_TIMESTAMP)
309 access_mask_reg |= BIT(i);
310 else
311 access_mask_reg |= BIT(i) << RTC_SECCFGR_SHIFT;
312 }
313 }
314
315 for (i = 0; i < RTC_NB_RIF_RESOURCES; i++) {
316 if (!(BIT(i) & rtc_dev.conf_data->access_mask[0]))
317 continue;
318
319 /*
320 * When TDCID, OP-TEE should be the one to set the CID filtering
321 * configuration. Clearing previous configuration prevents
322 * undesired events during the only legitimate configuration.
323 */
324 if (is_tdcid)
325 io_clrbits32(base + RTC_CIDCFGR(i),
326 RTC_CIDCFGR_CONF_MASK);
327 }
328
329 /* Security RIF configuration */
330 seccfgr = rtc_dev.conf_data->sec_conf[0];
331
332 /* Check if all resources must be secured */
333 if (seccfgr == RTC_RIF_FULL_SECURED) {
334 io_setbits32(base + RTC_SECCFGR, RTC_SECCFGR_FULL_SEC);
335
336 if (!(io_read32(base + RTC_SECCFGR) & RTC_SECCFGR_FULL_SEC))
337 panic("Bad RTC seccfgr configuration");
338 }
339
340 /* Shift some values to align with the register */
341 shifted_values = SHIFT_U32(seccfgr & RTC_SECCFGR_VALUES_TO_SHIFT,
342 RTC_SECCFGR_SHIFT);
343 seccfgr = (seccfgr & RTC_SECCFGR_VALUES) + shifted_values;
344
345 io_clrsetbits32(base + RTC_SECCFGR,
346 RTC_SECCFGR_MASK & access_mask_reg, seccfgr);
347
348 /* Privilege RIF configuration */
349 privcfgr = rtc_dev.conf_data->priv_conf[0];
350
351 /* Check if all resources must be privileged */
352 if (privcfgr == RTC_RIF_FULL_PRIVILEGED) {
353 io_setbits32(base + RTC_PRIVCFGR, RTC_PRIVCFGR_FULL_PRIV);
354
355 if (!(io_read32(base + RTC_PRIVCFGR) & RTC_PRIVCFGR_FULL_PRIV))
356 panic("Bad RTC privcfgr configuration");
357 }
358
359 /* Shift some values to align with the register */
360 shifted_values = SHIFT_U32(privcfgr & RTC_PRIVCFGR_VALUES_TO_SHIFT,
361 RTC_PRIVCFGR_SHIFT);
362 privcfgr = (privcfgr & RTC_PRIVCFGR_VALUES) + shifted_values;
363
364 io_clrsetbits32(base + RTC_PRIVCFGR,
365 RTC_PRIVCFGR_MASK & access_mask_reg, privcfgr);
366
367 if (!is_tdcid)
368 return;
369
370 for (i = 0; i < RTC_NB_RIF_RESOURCES; i++) {
371 if (!(BIT(i) & rtc_dev.conf_data->access_mask[0]))
372 continue;
373 /*
374 * When at least one resource has CID filtering enabled,
375 * the RTC_PRIVCFGR_FULL_PRIV and RTC_SECCFGR_FULL_SEC bits are
376 * cleared.
377 */
378 io_clrsetbits32(base + RTC_CIDCFGR(i),
379 RTC_CIDCFGR_CONF_MASK,
380 rtc_dev.conf_data->cid_confs[i]);
381 }
382 }
383
stm32_rtc_clear_events(uint32_t flags)384 static void stm32_rtc_clear_events(uint32_t flags)
385 {
386 io_write32(get_base() + RTC_SCR, flags);
387 }
388
stm32_rtc_it_handler(struct itr_handler * h __unused)389 static enum itr_return stm32_rtc_it_handler(struct itr_handler *h __unused)
390 {
391 vaddr_t rtc_base = get_base();
392 uint32_t status = io_read32(rtc_base + RTC_SR);
393 uint32_t cr = io_read32(rtc_base + RTC_CR);
394
395 if ((status & RTC_SR_ALRAF) && (cr & RTC_CR_ALRAIE)) {
396 DMSG("Alarm occurred");
397 /* Clear event's flags */
398 stm32_rtc_clear_events(RTC_SCR_CALRAF);
399 /*
400 * Notify the caller of 'stm32_rtc_wait_alarm' to re-schedule
401 * the calling thread.
402 */
403 notif_send_async(rtc_dev.notif_id, 0);
404 }
405
406 return ITRR_HANDLED;
407 }
408 DECLARE_KEEP_PAGER(stm32_rtc_it_handler);
409
parse_dt(const void * fdt,int node)410 static TEE_Result parse_dt(const void *fdt, int node)
411 {
412 TEE_Result res = TEE_ERROR_GENERIC;
413 const fdt32_t *cuint = NULL;
414 size_t reg_size = 0;
415 unsigned int i = 0;
416 int lenp = 0;
417
418 if (fdt_reg_info(fdt, node, &rtc_dev.base.pa, ®_size))
419 panic();
420
421 io_pa_or_va(&rtc_dev.base, reg_size);
422 assert(rtc_dev.base.va);
423
424 res = clk_dt_get_by_name(fdt, node, "pclk", &rtc_dev.pclk);
425 if (res)
426 return res;
427
428 res = clk_dt_get_by_name(fdt, node, "rtc_ck", &rtc_dev.rtc_ck);
429 if (res)
430 return res;
431
432 if (rtc_dev.compat->has_rif_support)
433 cuint = fdt_getprop(fdt, node, "st,protreg", &lenp);
434
435 if (cuint) {
436 rtc_dev.conf_data = calloc(1, sizeof(*rtc_dev.conf_data));
437 if (!rtc_dev.conf_data)
438 panic();
439
440 rtc_dev.nb_res = (unsigned int)(lenp / sizeof(uint32_t));
441 assert(rtc_dev.nb_res <= RTC_NB_RIF_RESOURCES);
442
443 rtc_dev.conf_data->cid_confs = calloc(RTC_NB_RIF_RESOURCES,
444 sizeof(uint32_t));
445 rtc_dev.conf_data->sec_conf = calloc(1, sizeof(uint32_t));
446 rtc_dev.conf_data->priv_conf = calloc(1, sizeof(uint32_t));
447 rtc_dev.conf_data->access_mask = calloc(1, sizeof(uint32_t));
448 if (!rtc_dev.conf_data->cid_confs ||
449 !rtc_dev.conf_data->sec_conf ||
450 !rtc_dev.conf_data->priv_conf ||
451 !rtc_dev.conf_data->access_mask)
452 panic("Not enough memory capacity for RTC RIF config");
453
454 for (i = 0; i < rtc_dev.nb_res; i++)
455 stm32_rif_parse_cfg(fdt32_to_cpu(cuint[i]),
456 rtc_dev.conf_data,
457 RTC_NB_RIF_RESOURCES);
458
459 if (rtc_dev.conf_data->sec_conf[0] == RTC_RIF_FULL_SECURED)
460 rtc_dev.is_secured = true;
461 }
462
463 cuint = fdt_getprop(fdt, node, "wakeup-source", NULL);
464 /*
465 * if the wakeup-source property is not present in the DT
466 * AND
467 * the RTC_PTA is disable or ASYNC_NOTIF are disable
468 * or the RTC is not secured.
469 * Then we should not register the interrupt line.
470 */
471 if (!cuint && !(IS_ENABLED(CFG_RTC_PTA) &&
472 IS_ENABLED(CFG_CORE_ASYNC_NOTIF) && rtc_dev.is_secured))
473 return TEE_SUCCESS;
474
475 res = interrupt_dt_get(fdt, node, &rtc_dev.itr_chip, &rtc_dev.itr_num);
476 if (res)
477 goto err;
478
479 if (cuint) {
480 if (!interrupt_can_set_wake(rtc_dev.itr_chip)) {
481 EMSG("%s does not have wakeup capabilities",
482 rtc_dev.itr_chip->name);
483 res = TEE_ERROR_NOT_SUPPORTED;
484 goto err;
485 }
486 rtc_dev.rtc->is_wakeup_source = true;
487 }
488
489 return TEE_SUCCESS;
490
491 err:
492 if (rtc_dev.conf_data) {
493 free(rtc_dev.conf_data->cid_confs);
494 free(rtc_dev.conf_data->sec_conf);
495 free(rtc_dev.conf_data->priv_conf);
496 free(rtc_dev.conf_data->access_mask);
497 free(rtc_dev.conf_data);
498 }
499
500 return res;
501 }
502
stm32_rtc_enter_init_mode(void)503 static TEE_Result stm32_rtc_enter_init_mode(void)
504 {
505 vaddr_t base = get_base();
506 uint32_t icsr = io_read32(base + RTC_ICSR);
507 uint32_t value = 0;
508
509 if (!(icsr & RTC_ICSR_INITF)) {
510 icsr |= RTC_ICSR_INIT;
511 io_write32(base + RTC_ICSR, icsr);
512
513 if (IO_READ32_POLL_TIMEOUT(base + RTC_ICSR, value,
514 value & RTC_ICSR_INITF,
515 10, TIMEOUT_US_RTC_GENERIC))
516 return TEE_ERROR_BUSY;
517 }
518
519 return TEE_SUCCESS;
520 }
521
stm32_rtc_exit_init_mode(void)522 static TEE_Result stm32_rtc_exit_init_mode(void)
523 {
524 vaddr_t base = get_base();
525 uint32_t value = 0;
526
527 io_clrbits32(base + RTC_ICSR, RTC_ICSR_INIT);
528 dsb();
529
530 io_clrbits32(base + RTC_ICSR, RTC_ICSR_RSF);
531
532 if (IO_READ32_POLL_TIMEOUT(base + RTC_ICSR, value,
533 value & RTC_ICSR_RSF, 10,
534 TIMEOUT_US_RTC_GENERIC))
535 return TEE_ERROR_BUSY;
536
537 return TEE_SUCCESS;
538 }
539
stm32_rtc_to_tm(uint32_t ssr,uint32_t tr,uint32_t dr,struct optee_rtc_time * tm)540 static void stm32_rtc_to_tm(uint32_t ssr, uint32_t tr, uint32_t dr,
541 struct optee_rtc_time *tm)
542 {
543 tm->tm_hour = ((tr & RTC_TR_HT_MASK) >> RTC_TR_HT_SHIFT) * 10 +
544 ((tr & RTC_TR_HU_MASK) >> RTC_TR_HU_SHIFT);
545
546 if (tr & RTC_TR_PM)
547 tm->tm_hour += 12;
548
549 tm->tm_ms = (stm32_rtc_get_subsecond(ssr) * MS_PER_SEC) /
550 stm32_rtc_get_subsecond_scale();
551
552 tm->tm_sec = ((tr & RTC_TR_ST_MASK) >> RTC_TR_ST_SHIFT) * 10 +
553 (tr & RTC_TR_SU_MASK);
554
555 tm->tm_min = ((tr & RTC_TR_MNT_MASK) >> RTC_TR_MNT_SHIFT) * 10 +
556 ((tr & RTC_TR_MNU_MASK) >> RTC_TR_MNU_SHIFT);
557
558 tm->tm_wday = ((dr & RTC_DR_WDU_MASK) >> RTC_DR_WDU_SHIFT) % 7;
559
560 tm->tm_mday = ((dr & RTC_DR_DT_MASK) >> RTC_DR_DT_SHIFT) * 10 +
561 (dr & RTC_DR_DU_MASK);
562
563 tm->tm_mon = ((dr & RTC_DR_MT_MASK) >> RTC_DR_MT_SHIFT) * 10 +
564 ((dr & RTC_DR_MU_MASK) >> RTC_DR_MU_SHIFT) - 1;
565
566 tm->tm_year = ((dr & RTC_DR_YT_MASK) >> RTC_DR_YT_SHIFT) * 10 +
567 ((dr & RTC_DR_YU_MASK) >> RTC_DR_YU_SHIFT) + YEAR_REF;
568 }
569
stm32_rtc_init(void)570 static TEE_Result stm32_rtc_init(void)
571 {
572 uint32_t pred_a_max = RTC_PRER_PREDIV_A_MASK >> RTC_PRER_PREDIV_A_SHIFT;
573 uint32_t pred_s_max = RTC_PRER_PREDIV_S_MASK >> RTC_PRER_PREDIV_S_SHIFT;
574 unsigned long rate = clk_get_rate(rtc_dev.rtc_ck);
575 TEE_Result res = TEE_ERROR_GENERIC;
576 vaddr_t base = get_base();
577 uint32_t pred_a = 0;
578 uint32_t pred_s = 0;
579 uint32_t prer = io_read32(base + RTC_PRER);
580 uint32_t cr = io_read32(base + RTC_CR);
581
582 if (rate > (pred_a_max + 1) * (pred_s_max + 1))
583 panic("rtc_ck rate is too high");
584
585 if (cr & RTC_CR_FMT && !IS_ENABLED(CFG_STM32_RTC_HIGH_ACCURACY))
586 return TEE_SUCCESS;
587
588 if (IS_ENABLED(CFG_STM32_RTC_HIGH_ACCURACY)) {
589 /*
590 * Compute the prescaler values whom divides the clock in order
591 * to get a * 1 Hz output by maximizing accuracy
592 * (maximizing PREDIV_S).
593 */
594 for (pred_a = 0; pred_a <= pred_a_max; pred_a++) {
595 pred_s = (rate / (pred_a + 1)) - 1;
596 if (pred_s <= pred_s_max &&
597 ((pred_s + 1) * (pred_a + 1)) == rate)
598 break;
599 }
600
601 /*
602 * 1 Hz output not possible, give priority to RTC power
603 * consumption by choosing the higher possible value for
604 * prediv_a
605 */
606 if (pred_s > pred_s_max || pred_a > pred_a_max) {
607 pred_a = pred_a_max;
608 pred_s = (rate / (pred_a + 1)) - 1;
609
610 DMSG("rtc_ck is %s",
611 (rate < ((pred_a + 1) * (pred_s + 1))) ?
612 "fast" : "slow");
613 }
614
615 prer &= RTC_PRER_PREDIV_S_MASK | RTC_PRER_PREDIV_A_MASK;
616 pred_s = SHIFT_U32(pred_s, RTC_PRER_PREDIV_S_SHIFT) &
617 RTC_PRER_PREDIV_S_MASK;
618 pred_a = SHIFT_U32(pred_a, RTC_PRER_PREDIV_A_SHIFT) &
619 RTC_PRER_PREDIV_A_MASK;
620
621 /* Return if there is nothing to initialize */
622 if (cr & RTC_CR_FMT && prer == (pred_s | pred_a))
623 return TEE_SUCCESS;
624 }
625
626 stm32_rtc_write_unprotect();
627
628 res = stm32_rtc_enter_init_mode();
629 if (res) {
630 EMSG("Can't enter init mode. Fail to initialize RTC.");
631 stm32_rtc_write_protect();
632 return res;
633 }
634
635 if (IS_ENABLED(CFG_STM32_RTC_HIGH_ACCURACY)) {
636 io_write32(base + RTC_PRER, pred_s);
637 io_write32(base + RTC_PRER, pred_a | pred_s);
638 }
639
640 /* Force 24h time format */
641 cr &= ~RTC_CR_FMT;
642 io_write32(base + RTC_CR, cr);
643
644 res = stm32_rtc_exit_init_mode();
645 if (res)
646 EMSG("Can't exit init mode. Fail to initialize RTC.");
647
648 stm32_rtc_write_protect();
649
650 return res;
651 }
652
stm32_rtc_get_time(struct rtc * rtc __unused,struct optee_rtc_time * tm)653 static TEE_Result stm32_rtc_get_time(struct rtc *rtc __unused,
654 struct optee_rtc_time *tm)
655 {
656 vaddr_t base = get_base();
657 uint32_t ssr = 0;
658 uint32_t dr = 0;
659 uint32_t tr = 0;
660
661 if (!stm32_rtc_get_bypshad()) {
662 uint32_t icsr = 0;
663
664 /* Wait calendar registers are ready */
665 io_clrbits32(base + RTC_ICSR, RTC_ICSR_RSF);
666
667 if (IO_READ32_POLL_TIMEOUT(base + RTC_ICSR, icsr,
668 icsr & RTC_ICSR_RSF, 0,
669 TIMEOUT_US_RTC_SHADOW))
670 panic();
671 }
672
673 /*
674 * In our RTC we start :
675 * - year at 0
676 * - month at 1
677 * - day at 1
678 * - weekday at Monday = 1
679 * Change month value so it becomes 0=January, 1 = February, ...
680 * Change week day value so it becomes 0=Sunday, 1 = Monday, ...
681 */
682
683 ssr = io_read32(base + RTC_SSR);
684 tr = io_read32(base + RTC_TR);
685 dr = io_read32(base + RTC_DR);
686
687 stm32_rtc_to_tm(ssr, tr, dr, tm);
688
689 return TEE_SUCCESS;
690 }
691
stm32_rtc_set_time(struct rtc * rtc,struct optee_rtc_time * tm)692 static TEE_Result stm32_rtc_set_time(struct rtc *rtc, struct optee_rtc_time *tm)
693 {
694 TEE_Result res = TEE_ERROR_GENERIC;
695 vaddr_t rtc_base = get_base();
696 uint32_t tr = 0;
697 uint32_t dr = 0;
698
699 /*
700 * In our RTC we start :
701 * - year at 0
702 * - month at 1
703 * - day at 1
704 * - weekday at Monday = 1
705 * Change month value so it becomes 1=January, 2 = February, ...
706 * Change week day value so it becomes 7=Sunday, 1 = Monday, ...
707 */
708 tr = ((tm->tm_sec % 10) & RTC_TR_SU_MASK) |
709 (SHIFT_U32(tm->tm_sec / 10, RTC_TR_ST_SHIFT) & RTC_TR_ST_MASK) |
710 (SHIFT_U32(tm->tm_min % 10, RTC_TR_MNU_SHIFT) & RTC_TR_MNU_MASK) |
711 (SHIFT_U32(tm->tm_min / 10, RTC_TR_MNT_SHIFT) & RTC_TR_MNT_MASK) |
712 (SHIFT_U32(tm->tm_hour % 10, RTC_TR_HU_SHIFT) & RTC_TR_HU_MASK) |
713 (SHIFT_U32(tm->tm_hour / 10, RTC_TR_HT_SHIFT) & RTC_TR_HT_MASK);
714
715 dr = ((tm->tm_mday % 10) & RTC_DR_DU_MASK) |
716 (SHIFT_U32(tm->tm_mday / 10, RTC_DR_DT_SHIFT) & RTC_DR_DT_MASK) |
717 (SHIFT_U32((tm->tm_mon + 1) % 10, RTC_DR_MU_SHIFT) &
718 RTC_DR_MU_MASK) |
719 (SHIFT_U32((tm->tm_mon + 1) / 10, RTC_DR_MT_SHIFT) &
720 RTC_DR_MT_MASK) |
721 (SHIFT_U32(tm->tm_wday ? tm->tm_wday : 7, RTC_DR_WDU_SHIFT) &
722 RTC_DR_WDU_MASK) |
723 (SHIFT_U32((tm->tm_year - rtc->range_min.tm_year) % 10,
724 RTC_DR_YU_SHIFT) & RTC_DR_YU_MASK) |
725 (SHIFT_U32((tm->tm_year - rtc->range_min.tm_year) / 10,
726 RTC_DR_YT_SHIFT) & RTC_DR_YT_MASK);
727
728 stm32_rtc_write_unprotect();
729
730 res = stm32_rtc_enter_init_mode();
731 if (res)
732 goto end;
733
734 io_write32(rtc_base + RTC_TR, tr);
735 io_write32(rtc_base + RTC_DR, dr);
736
737 res = stm32_rtc_exit_init_mode();
738 end:
739 stm32_rtc_write_protect();
740
741 return res;
742 }
743
stm32_rtc_get_timestamp(struct optee_rtc_time * tm)744 TEE_Result stm32_rtc_get_timestamp(struct optee_rtc_time *tm)
745 {
746 vaddr_t base = get_base();
747 uint32_t exceptions = 0;
748 uint32_t value = 0;
749 uint32_t ssr = 0;
750 uint32_t dr = 0;
751 uint32_t tr = 0;
752
753 exceptions = cpu_spin_lock_xsave(&rtc_dev.ts_lock);
754
755 if (IO_READ32_POLL_TIMEOUT(base + RTC_SR, value,
756 value & RTC_SR_TSF,
757 10, TIMEOUT_US_RTC_GENERIC)) {
758 cpu_spin_unlock_xrestore(&rtc_dev.ts_lock, exceptions);
759 return TEE_ERROR_NO_DATA;
760 }
761
762 ssr = io_read32(base + RTC_TSSSR);
763 tr = io_read32(base + RTC_TSTR);
764 dr = io_read32(base + RTC_TSDR);
765
766 io_setbits32(base + RTC_SCR, RTC_SCR_CTSF);
767
768 /* Tamper event overflow detection */
769 if (io_read32(base + RTC_SR) & RTC_SR_TSOVF) {
770 io_setbits32(base + RTC_SCR, RTC_SCR_CTSOVF);
771 DMSG("A timestamp event occurred while handling current event");
772 }
773
774 cpu_spin_unlock_xrestore(&rtc_dev.ts_lock, exceptions);
775
776 stm32_rtc_to_tm(ssr, tr, dr, tm);
777
778 /* No year timestamp available */
779 tm->tm_year = 0;
780
781 return TEE_SUCCESS;
782 }
783
stm32_rtc_set_tamper_timestamp(void)784 TEE_Result stm32_rtc_set_tamper_timestamp(void)
785 {
786 vaddr_t base = get_base();
787
788 stm32_rtc_write_unprotect();
789
790 /* Secure Timestamp bit */
791 if (!rtc_dev.compat->has_seccfgr) {
792 /* Inverted logic */
793 io_clrbits32(base + RTC_SMCR, RTC_SMCR_TS_DPROT);
794 } else {
795 io_setbits32(base + RTC_SECCFGR, RTC_SECCFGR_TS_SEC);
796 }
797
798 /* Enable tamper timestamper */
799 io_setbits32(base + RTC_CR, RTC_CR_TAMPTS);
800
801 stm32_rtc_write_protect();
802
803 return TEE_SUCCESS;
804 }
805
stm32_rtc_is_timestamp_enabled(bool * ret)806 TEE_Result stm32_rtc_is_timestamp_enabled(bool *ret)
807 {
808 *ret = io_read32(get_base() + RTC_CR) & RTC_CR_TAMPTS;
809
810 return TEE_SUCCESS;
811 }
812
stm32_rtc_driver_is_initialized(void)813 TEE_Result stm32_rtc_driver_is_initialized(void)
814 {
815 if (rtc_dev.pclk)
816 return TEE_SUCCESS;
817
818 return TEE_ERROR_DEFER_DRIVER_INIT;
819 }
820
stm32_rtc_read_alarm(struct rtc * rtc,struct optee_rtc_alarm * alarm)821 static TEE_Result stm32_rtc_read_alarm(struct rtc *rtc,
822 struct optee_rtc_alarm *alarm)
823 {
824 struct optee_rtc_time *alarm_tm = NULL;
825 struct optee_rtc_time current_tm = { };
826 TEE_Result res = TEE_ERROR_GENERIC;
827 vaddr_t rtc_base = get_base();
828 uint32_t alrmar = io_read32(rtc_base + RTC_ALRMAR);
829 uint32_t cr = io_read32(rtc_base + RTC_CR);
830 uint32_t status = io_read32(rtc_base + RTC_SR);
831
832 alarm_tm = &alarm->time;
833
834 res = stm32_rtc_get_time(rtc, ¤t_tm);
835 if (res)
836 return res;
837
838 alarm_tm->tm_year = current_tm.tm_year;
839 alarm_tm->tm_mon = current_tm.tm_mon;
840 alarm_tm->tm_mday = ((alrmar & RTC_ALRMXR_DATE_UNITS_MASK) >>
841 RTC_ALRMXR_DATE_UNITS_SHIFT) +
842 ((alrmar & RTC_ALRMXR_DATE_TENS_MASK) >>
843 RTC_ALRMXR_DATE_TENS_SHIFT) * 10;
844 alarm_tm->tm_hour = ((alrmar & RTC_ALRMXR_HOUR_UNITS_MASK) >>
845 RTC_ALRMXR_HOUR_UNITS_SHIFT) +
846 ((alrmar & RTC_ALRMXR_HOUR_TENS_MASK) >>
847 RTC_ALRMXR_HOUR_TENS_SHIFT) * 10;
848 alarm_tm->tm_min = ((alrmar & RTC_ALRMXR_MIN_UNITS_MASK) >>
849 RTC_ALRMXR_MIN_UNITS_SHIFT) +
850 ((alrmar & RTC_ALRMXR_MIN_TENS_MASK) >>
851 RTC_ALRMXR_MIN_TENS_SHIFT) * 10;
852 alarm_tm->tm_sec = ((alrmar & RTC_ALRMXR_MIN_UNITS_MASK) >>
853 RTC_ALRMXR_MIN_UNITS_SHIFT) +
854 ((alrmar & RTC_ALRMXR_MIN_TENS_MASK) >>
855 RTC_ALRMXR_MIN_TENS_SHIFT) * 10;
856
857 if (rtc_timecmp(alarm_tm, ¤t_tm) < 0) {
858 if (current_tm.tm_mon == 11) {
859 alarm_tm->tm_mon = 0;
860 alarm_tm->tm_year += 1;
861 } else {
862 alarm_tm->tm_mon += 1;
863 }
864 }
865
866 alarm->enabled = cr & RTC_CR_ALRAE;
867 alarm->pending = status & RTC_SR_ALRAF;
868
869 return TEE_SUCCESS;
870 }
871
stm32_rtc_enable_alarm(struct rtc * rtc __unused,bool enabled)872 static TEE_Result stm32_rtc_enable_alarm(struct rtc *rtc __unused, bool enabled)
873 {
874 vaddr_t rtc_base = get_base();
875
876 stm32_rtc_write_unprotect();
877
878 if (enabled)
879 io_setbits32(rtc_base + RTC_CR, RTC_CR_ALRAIE | RTC_CR_ALRAE);
880 else
881 io_clrbits32(rtc_base + RTC_CR, RTC_CR_ALRAIE | RTC_CR_ALRAE);
882
883 stm32_rtc_clear_events(RTC_SCR_CALRAF);
884
885 stm32_rtc_write_protect();
886
887 return TEE_SUCCESS;
888 }
889
stm32_rtc_add_one_month(struct optee_rtc_time * tm)890 static void stm32_rtc_add_one_month(struct optee_rtc_time *tm)
891 {
892 tm->tm_mon++;
893 if (tm->tm_mon > 11) {
894 tm->tm_mon = 0;
895 tm->tm_year++;
896 }
897
898 /* Saturate to the next month last day */
899 tm->tm_mday = MIN(tm->tm_mday,
900 rtc_get_month_days(tm->tm_mon, tm->tm_year));
901 }
902
stm32_rtc_valid_alarm_time(struct rtc * rtc,struct optee_rtc_time * tm)903 static TEE_Result stm32_rtc_valid_alarm_time(struct rtc *rtc,
904 struct optee_rtc_time *tm)
905 {
906 struct optee_rtc_time current_tm = { };
907 TEE_Result res = TEE_ERROR_GENERIC;
908 struct optee_rtc_time *max = NULL;
909
910 /*
911 * Assuming current date is M-D-Y H:M:S.
912 * RTC alarm can't be set on a specific month and year.
913 * So the valid alarm range is:
914 * M-D-Y H:M:S < alarm <= (M+1)-D-Y H:M:S
915 */
916
917 res = stm32_rtc_get_time(rtc, ¤t_tm);
918 if (res)
919 return res;
920
921 /* Don't allow alarm to be set in the past. */
922 if (rtc_timecmp(¤t_tm, tm) >= 0)
923 return TEE_ERROR_BAD_PARAMETERS;
924
925 max = ¤t_tm;
926
927 stm32_rtc_add_one_month(max);
928
929 if (rtc_timecmp(max, tm) <= 0)
930 return TEE_ERROR_BAD_PARAMETERS;
931
932 return TEE_SUCCESS;
933 }
934
stm32_rtc_set_alarm(struct rtc * rtc,struct optee_rtc_alarm * alarm)935 static TEE_Result stm32_rtc_set_alarm(struct rtc *rtc,
936 struct optee_rtc_alarm *alarm)
937 {
938 struct optee_rtc_time *alarm_time = &alarm->time;
939 TEE_Result res = TEE_ERROR_GENERIC;
940 vaddr_t rtc_base = get_base();
941 uint32_t alrmar = 0;
942 uint32_t cr = io_read32(rtc_base + RTC_CR);
943 uint32_t prer = io_read32(rtc_base + RTC_PRER);
944 uint32_t prediv_s = prer & RTC_PRER_PREDIV_S_MASK;
945
946 /* tm_year and tm_mon are not used because not supported by RTC */
947 alrmar |= ((alarm_time->tm_mday / 10) << RTC_ALRMXR_DATE_TENS_SHIFT) &
948 RTC_ALRMXR_DATE_TENS_MASK;
949 alrmar |= ((alarm_time->tm_mday % 10) << RTC_ALRMXR_DATE_UNITS_SHIFT) &
950 RTC_ALRMXR_DATE_UNITS_MASK;
951 /* 24-hour format */
952 alrmar &= ~RTC_ALRMXR_PM;
953 alrmar |= ((alarm_time->tm_hour / 10) << RTC_ALRMXR_HOUR_TENS_SHIFT) &
954 RTC_ALRMXR_HOUR_TENS_MASK;
955 alrmar |= ((alarm_time->tm_hour % 10) << RTC_ALRMXR_HOUR_UNITS_SHIFT) &
956 RTC_ALRMXR_HOUR_UNITS_MASK;
957 alrmar |= ((alarm_time->tm_min / 10) << RTC_ALRMXR_MIN_TENS_SHIFT) &
958 RTC_ALRMXR_MIN_TENS_MASK;
959 alrmar |= ((alarm_time->tm_min % 10) << RTC_ALRMXR_MIN_UNITS_SHIFT) &
960 RTC_ALRMXR_MIN_UNITS_MASK;
961 alrmar |= ((alarm_time->tm_sec / 10) << RTC_ALRMXR_SEC_TENS_SHIFT) &
962 RTC_ALRMXR_SEC_TENS_MASK;
963 alrmar |= ((alarm_time->tm_sec % 10) << RTC_ALRMXR_SEC_UNITS_SHIFT) &
964 RTC_ALRMXR_SEC_UNITS_MASK;
965
966 if ((alrmar & !RTC_ALRMXR_SEC_MASK) && prediv_s < 3) {
967 EMSG("RTC Alarm conditions not met");
968 return TEE_ERROR_BAD_STATE;
969 }
970
971 stm32_rtc_write_unprotect();
972
973 res = stm32_rtc_valid_alarm_time(rtc, alarm_time);
974 if (res) {
975 stm32_rtc_write_unprotect();
976 return res;
977 }
978
979 /* Disable Alarm */
980 cr &= ~RTC_CR_ALRAE;
981 io_write32(rtc_base + RTC_CR, cr);
982
983 io_write32(rtc_base + RTC_ALRMAR, alrmar);
984
985 stm32_rtc_enable_alarm(rtc, alarm->enabled);
986
987 stm32_rtc_write_protect();
988
989 return TEE_SUCCESS;
990 }
991
stm32_rtc_cancel_wait_alarm(struct rtc * rtc __unused)992 static TEE_Result stm32_rtc_cancel_wait_alarm(struct rtc *rtc __unused)
993 {
994 rtc_dev.wait_alarm_return_status = RTC_WAIT_ALARM_CANCELED;
995 notif_send_async(rtc_dev.notif_id, 0);
996
997 return TEE_SUCCESS;
998 }
999
1000 static TEE_Result
stm32_rtc_wait_alarm(struct rtc * rtc __unused,enum rtc_wait_alarm_status * return_status)1001 stm32_rtc_wait_alarm(struct rtc *rtc __unused,
1002 enum rtc_wait_alarm_status *return_status)
1003 {
1004 TEE_Result res = TEE_ERROR_GENERIC;
1005
1006 rtc_dev.wait_alarm_return_status = RTC_WAIT_ALARM_RESET;
1007
1008 /* Wait until a notification arrives - blocking */
1009 res = notif_wait(rtc_dev.notif_id);
1010 if (res)
1011 return res;
1012
1013 if (rtc_dev.wait_alarm_return_status ==
1014 RTC_WAIT_ALARM_CANCELED) {
1015 *return_status = RTC_WAIT_ALARM_CANCELED;
1016 stm32_rtc_enable_alarm(rtc, 0);
1017 } else {
1018 *return_status = RTC_WAIT_ALARM_ALARM_OCCURRED;
1019 }
1020
1021 return TEE_SUCCESS;
1022 }
1023
stm32_rtc_set_alarm_wakeup_status(struct rtc * rtc __unused,bool status)1024 static TEE_Result stm32_rtc_set_alarm_wakeup_status(struct rtc *rtc __unused,
1025 bool status)
1026 {
1027 if (!rtc_dev.rtc->is_wakeup_source)
1028 return TEE_ERROR_NOT_SUPPORTED;
1029
1030 interrupt_set_wake(rtc_dev.itr_chip, rtc_dev.itr_num, status);
1031
1032 return TEE_SUCCESS;
1033 }
1034
1035 static const struct rtc_ops stm32_rtc_ops = {
1036 .get_time = stm32_rtc_get_time,
1037 .set_time = stm32_rtc_set_time,
1038 .read_alarm = stm32_rtc_read_alarm,
1039 .set_alarm = stm32_rtc_set_alarm,
1040 .enable_alarm = stm32_rtc_enable_alarm,
1041 .wait_alarm = stm32_rtc_wait_alarm,
1042 .cancel_wait = stm32_rtc_cancel_wait_alarm,
1043 .set_alarm_wakeup_status = stm32_rtc_set_alarm_wakeup_status,
1044 };
1045
1046 static struct rtc stm32_rtc = {
1047 .ops = &stm32_rtc_ops,
1048 .range_min = RTC_TIME(YEAR_REF, 0, 1, 0, 0, 0, 0, 0),
1049 .range_max = RTC_TIME(YEAR_MAX, 11, 31, 4, 23, 59, 59, 999),
1050 };
1051
stm32_rtc_probe(const void * fdt,int node,const void * compat_data)1052 static TEE_Result stm32_rtc_probe(const void *fdt, int node,
1053 const void *compat_data)
1054 {
1055 TEE_Result res = TEE_ERROR_GENERIC;
1056 bool is_tdcid = false;
1057
1058 rtc_dev.compat = compat_data;
1059 rtc_dev.rtc = &stm32_rtc;
1060
1061 if (rtc_dev.compat->has_rif_support) {
1062 res = stm32_rifsc_check_tdcid(&is_tdcid);
1063 if (res)
1064 return res;
1065 }
1066
1067 res = parse_dt(fdt, node);
1068 if (res) {
1069 memset(&rtc_dev, 0, sizeof(rtc_dev));
1070 return res;
1071 }
1072
1073 /* Unbalanced clock enable to ensure RTC core clock is always on */
1074 res = clk_enable(rtc_dev.rtc_ck);
1075 if (res)
1076 panic("Couldn't enable RTC clock");
1077
1078 if (clk_get_rate(rtc_dev.pclk) < (clk_get_rate(rtc_dev.rtc_ck) * 7))
1079 rtc_dev.flags |= RTC_FLAGS_READ_TWICE;
1080
1081 if (rtc_dev.compat->has_rif_support) {
1082 res = clk_enable(rtc_dev.pclk);
1083 if (res)
1084 panic("Could not enable RTC bus clock");
1085
1086 apply_rif_config(is_tdcid);
1087
1088 /*
1089 * Verify if applied RIF config will not disable
1090 * other functionalities of this driver.
1091 */
1092 res = check_rif_config();
1093 if (res)
1094 panic("Incompatible RTC RIF configuration");
1095
1096 clk_disable(rtc_dev.pclk);
1097 }
1098
1099 res = stm32_rtc_init();
1100 if (res)
1101 return res;
1102
1103 rtc_register(&stm32_rtc);
1104
1105 if (IS_ENABLED(CFG_RTC_PTA) && IS_ENABLED(CFG_CORE_ASYNC_NOTIF) &&
1106 rtc_dev.is_secured && rtc_dev.itr_chip) {
1107 res = notif_alloc_async_value(&rtc_dev.notif_id);
1108 if (res)
1109 return res;
1110
1111 res = interrupt_create_handler(rtc_dev.itr_chip,
1112 rtc_dev.itr_num,
1113 stm32_rtc_it_handler,
1114 &rtc_dev, 0,
1115 &rtc_dev.itr_handler);
1116 if (res)
1117 goto out_rtc_secured_and_itr_chip;
1118
1119 /* Unbalanced clock enable to ensure IRQ interface is alive */
1120 res = clk_enable(rtc_dev.pclk);
1121 if (res)
1122 goto out_rtc_secured_and_itr_chip;
1123
1124 interrupt_enable(rtc_dev.itr_chip, rtc_dev.itr_num);
1125
1126 return TEE_SUCCESS;
1127
1128 out_rtc_secured_and_itr_chip:
1129 interrupt_remove_handler(rtc_dev.itr_handler);
1130 notif_free_async_value(rtc_dev.notif_id);
1131 return res;
1132 }
1133
1134 return TEE_SUCCESS;
1135 }
1136
1137 static const struct rtc_compat mp25_compat = {
1138 .has_seccfgr = true,
1139 .has_rif_support = true,
1140 };
1141
1142 static const struct rtc_compat mp15_compat = {
1143 .has_seccfgr = false,
1144 .has_rif_support = false,
1145 };
1146
1147 static const struct rtc_compat mp13_compat = {
1148 .has_seccfgr = true,
1149 .has_rif_support = false,
1150 };
1151
1152 static const struct dt_device_match stm32_rtc_match_table[] = {
1153 {
1154 .compatible = "st,stm32mp25-rtc",
1155 .compat_data = &mp25_compat,
1156 },
1157 {
1158 .compatible = "st,stm32mp1-rtc",
1159 .compat_data = &mp15_compat,
1160 },
1161 {
1162 .compatible = "st,stm32mp13-rtc",
1163 .compat_data = &mp13_compat,
1164 },
1165 { }
1166 };
1167
1168 DEFINE_DT_DRIVER(stm32_rtc_dt_driver) = {
1169 .name = "stm32-rtc",
1170 .match_table = stm32_rtc_match_table,
1171 .probe = stm32_rtc_probe,
1172 };
1173