1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
2 /*
3 * Copyright (c) 2017-2024, STMicroelectronics
4 *
5 * The driver API is defined in header file stm32_i2c.h.
6 *
7 * I2C bus driver does not register to the PM framework. It is the
8 * responsibility of the bus owner to call the related STM32 I2C driver
9 * API functions when bus suspends or resumes.
10 */
11
12 #include <arm.h>
13 #include <atomic.h>
14 #include <drivers/clk.h>
15 #include <drivers/clk_dt.h>
16 #include <drivers/pinctrl.h>
17 #include <drivers/stm32_gpio.h>
18 #include <drivers/stm32_i2c.h>
19 #include <io.h>
20 #include <kernel/boot.h>
21 #include <kernel/delay.h>
22 #include <kernel/dt.h>
23 #include <kernel/dt_driver.h>
24 #include <kernel/interrupt.h>
25 #include <kernel/mutex_pm_aware.h>
26 #include <kernel/notif.h>
27 #include <kernel/panic.h>
28 #include <kernel/thread.h>
29 #include <libfdt.h>
30 #include <stdbool.h>
31 #include <stdlib.h>
32 #include <stm32_util.h>
33 #include <trace.h>
34
35 /* STM32 I2C registers offsets */
36 #define I2C_CR1 0x00U
37 #define I2C_CR2 0x04U
38 #define I2C_OAR1 0x08U
39 #define I2C_OAR2 0x0CU
40 #define I2C_TIMINGR 0x10U
41 #define I2C_TIMEOUTR 0x14U
42 #define I2C_ISR 0x18U
43 #define I2C_ICR 0x1CU
44 #define I2C_PECR 0x20U
45 #define I2C_RXDR 0x24U
46 #define I2C_TXDR 0x28U
47 #define I2C_SIZE 0x2CU
48
49 /* Bit definition for I2C_CR1 register */
50 #define I2C_CR1_PE BIT(0)
51 #define I2C_CR1_TXIE BIT(1)
52 #define I2C_CR1_RXIE BIT(2)
53 #define I2C_CR1_ADDRIE BIT(3)
54 #define I2C_CR1_NACKIE BIT(4)
55 #define I2C_CR1_STOPIE BIT(5)
56 #define I2C_CR1_TCIE BIT(6)
57 #define I2C_CR1_ERRIE BIT(7)
58 #define I2C_CR1_DNF GENMASK_32(11, 8)
59 #define I2C_CR1_ANFOFF BIT(12)
60 #define I2C_CR1_SWRST BIT(13)
61 #define I2C_CR1_TXDMAEN BIT(14)
62 #define I2C_CR1_RXDMAEN BIT(15)
63 #define I2C_CR1_SBC BIT(16)
64 #define I2C_CR1_NOSTRETCH BIT(17)
65 #define I2C_CR1_WUPEN BIT(18)
66 #define I2C_CR1_GCEN BIT(19)
67 #define I2C_CR1_SMBHEN BIT(22)
68 #define I2C_CR1_SMBDEN BIT(21)
69 #define I2C_CR1_ALERTEN BIT(22)
70 #define I2C_CR1_PECEN BIT(23)
71
72 /* Bit definition for I2C_CR2 register */
73 #define I2C_CR2_SADD GENMASK_32(9, 0)
74 #define I2C_CR2_RD_WRN BIT(10)
75 #define I2C_CR2_RD_WRN_OFFSET 10U
76 #define I2C_CR2_ADD10 BIT(11)
77 #define I2C_CR2_HEAD10R BIT(12)
78 #define I2C_CR2_START BIT(13)
79 #define I2C_CR2_STOP BIT(14)
80 #define I2C_CR2_NACK BIT(15)
81 #define I2C_CR2_NBYTES GENMASK_32(23, 16)
82 #define I2C_CR2_NBYTES_OFFSET 16U
83 #define I2C_CR2_RELOAD BIT(24)
84 #define I2C_CR2_AUTOEND BIT(25)
85 #define I2C_CR2_PECBYTE BIT(26)
86
87 /* Bit definition for I2C_OAR1 register */
88 #define I2C_OAR1_OA1 GENMASK_32(9, 0)
89 #define I2C_OAR1_OA1MODE BIT(10)
90 #define I2C_OAR1_OA1EN BIT(15)
91
92 /* Bit definition for I2C_OAR2 register */
93 #define I2C_OAR2_OA2 GENMASK_32(7, 1)
94 #define I2C_OAR2_OA2MSK GENMASK_32(10, 8)
95 #define I2C_OAR2_OA2NOMASK 0
96 #define I2C_OAR2_OA2MASK01 BIT(8)
97 #define I2C_OAR2_OA2MASK02 BIT(9)
98 #define I2C_OAR2_OA2MASK03 GENMASK_32(9, 8)
99 #define I2C_OAR2_OA2MASK04 BIT(10)
100 #define I2C_OAR2_OA2MASK05 (BIT(8) | BIT(10))
101 #define I2C_OAR2_OA2MASK06 (BIT(9) | BIT(10))
102 #define I2C_OAR2_OA2MASK07 GENMASK_32(10, 8)
103 #define I2C_OAR2_OA2EN BIT(15)
104
105 /* Bit definition for I2C_TIMINGR register */
106 #define I2C_TIMINGR_SCLL GENMASK_32(7, 0)
107 #define I2C_TIMINGR_SCLH GENMASK_32(15, 8)
108 #define I2C_TIMINGR_SDADEL GENMASK_32(19, 16)
109 #define I2C_TIMINGR_SCLDEL GENMASK_32(23, 20)
110 #define I2C_TIMINGR_PRESC GENMASK_32(31, 28)
111 #define I2C_TIMINGR_SCLL_MAX (I2C_TIMINGR_SCLL + 1)
112 #define I2C_TIMINGR_SCLH_MAX ((I2C_TIMINGR_SCLH >> 8) + 1)
113 #define I2C_TIMINGR_SDADEL_MAX ((I2C_TIMINGR_SDADEL >> 16) + 1)
114 #define I2C_TIMINGR_SCLDEL_MAX ((I2C_TIMINGR_SCLDEL >> 20) + 1)
115 #define I2C_TIMINGR_PRESC_MAX ((I2C_TIMINGR_PRESC >> 28) + 1)
116 #define I2C_SET_TIMINGR_SCLL(n) ((n) & \
117 (I2C_TIMINGR_SCLL_MAX - 1))
118 #define I2C_SET_TIMINGR_SCLH(n) (((n) & \
119 (I2C_TIMINGR_SCLH_MAX - 1)) << 8)
120 #define I2C_SET_TIMINGR_SDADEL(n) (((n) & \
121 (I2C_TIMINGR_SDADEL_MAX - 1)) << 16)
122 #define I2C_SET_TIMINGR_SCLDEL(n) (((n) & \
123 (I2C_TIMINGR_SCLDEL_MAX - 1)) << 20)
124 #define I2C_SET_TIMINGR_PRESC(n) (((n) & \
125 (I2C_TIMINGR_PRESC_MAX - 1)) << 28)
126
127 /* Bit definition for I2C_TIMEOUTR register */
128 #define I2C_TIMEOUTR_TIMEOUTA GENMASK_32(11, 0)
129 #define I2C_TIMEOUTR_TIDLE BIT(12)
130 #define I2C_TIMEOUTR_TIMOUTEN BIT(15)
131 #define I2C_TIMEOUTR_TIMEOUTB GENMASK_32(27, 16)
132 #define I2C_TIMEOUTR_TEXTEN BIT(31)
133
134 /* Bit definition for I2C_ISR register */
135 #define I2C_ISR_TXE BIT(0)
136 #define I2C_ISR_TXIS BIT(1)
137 #define I2C_ISR_RXNE BIT(2)
138 #define I2C_ISR_ADDR BIT(3)
139 #define I2C_ISR_NACKF BIT(4)
140 #define I2C_ISR_STOPF BIT(5)
141 #define I2C_ISR_TC BIT(6)
142 #define I2C_ISR_TCR BIT(7)
143 #define I2C_ISR_BERR BIT(8)
144 #define I2C_ISR_ARLO BIT(9)
145 #define I2C_ISR_OVR BIT(10)
146 #define I2C_ISR_PECERR BIT(11)
147 #define I2C_ISR_TIMEOUT BIT(12)
148 #define I2C_ISR_ALERT BIT(13)
149 #define I2C_ISR_BUSY BIT(15)
150 #define I2C_ISR_DIR BIT(16)
151 #define I2C_ISR_ADDCODE GENMASK_32(23, 17)
152
153 /* Bit definition for I2C_ICR register */
154 #define I2C_ICR_ADDRCF BIT(3)
155 #define I2C_ICR_NACKCF BIT(4)
156 #define I2C_ICR_STOPCF BIT(5)
157 #define I2C_ICR_BERRCF BIT(8)
158 #define I2C_ICR_ARLOCF BIT(9)
159 #define I2C_ICR_OVRCF BIT(10)
160 #define I2C_ICR_PECCF BIT(11)
161 #define I2C_ICR_TIMOUTCF BIT(12)
162 #define I2C_ICR_ALERTCF BIT(13)
163
164 /* Max data size for a single I2C transfer */
165 #define MAX_NBYTE_SIZE 255U
166
167 #define I2C_NSEC_PER_SEC 1000000000UL
168 #define I2C_TIMEOUT_BUSY_MS 25
169 #define I2C_TIMEOUT_BUSY_US (I2C_TIMEOUT_BUSY_MS * 1000)
170 #define I2C_TIMEOUT_RXNE_MS 5
171 #define I2C_TIMEOUT_ITR_LOCKED_MS 100
172
173 #define I2C_TIMEOUT_DEFAULT_MS 100
174
175 #define CR2_RESET_MASK (I2C_CR2_SADD | I2C_CR2_HEAD10R | \
176 I2C_CR2_NBYTES | I2C_CR2_RELOAD | \
177 I2C_CR2_RD_WRN)
178
179 #define TIMINGR_CLEAR_MASK (I2C_TIMINGR_SCLL | I2C_TIMINGR_SCLH | \
180 I2C_TIMINGR_SDADEL | \
181 I2C_TIMINGR_SCLDEL | I2C_TIMINGR_PRESC)
182
183 /*
184 * I2C transfer modes
185 * I2C_RELOAD: Enable Reload mode
186 * I2C_AUTOEND_MODE: Enable automatic end mode
187 * I2C_SOFTEND_MODE: Enable software end mode
188 */
189 #define I2C_RELOAD_MODE I2C_CR2_RELOAD
190 #define I2C_AUTOEND_MODE I2C_CR2_AUTOEND
191 #define I2C_SOFTEND_MODE 0x0
192
193 /*
194 * Start/restart/stop I2C transfer requests.
195 *
196 * I2C_NO_STARTSTOP: Don't Generate stop and start condition
197 * I2C_GENERATE_STOP: Generate stop condition (size should be set to 0)
198 * I2C_GENERATE_START_READ: Generate Restart for read request.
199 * I2C_GENERATE_START_WRITE: Generate Restart for write request
200 */
201 #define I2C_NO_STARTSTOP 0x0
202 #define I2C_GENERATE_STOP (BIT(31) | I2C_CR2_STOP)
203 #define I2C_GENERATE_START_READ (BIT(31) | I2C_CR2_START | \
204 I2C_CR2_RD_WRN)
205 #define I2C_GENERATE_START_WRITE (BIT(31) | I2C_CR2_START)
206
207 /* Memory address byte sizes */
208 #define I2C_MEMADD_SIZE_8BIT 1
209 #define I2C_MEMADD_SIZE_16BIT 2
210
211 /* Effective rate cannot be lower than 80% target rate */
212 #define RATE_MIN(rate) (((rate) * 80U) / 100U)
213
214 /*
215 * struct i2c_spec_s - Private I2C timing specifications.
216 * @rate: I2C bus speed (Hz)
217 * @fall_max: Max fall time of both SDA and SCL signals (ns)
218 * @rise_max: Max rise time of both SDA and SCL signals (ns)
219 * @hddat_min: Min data hold time (ns)
220 * @vddat_max: Max data valid time (ns)
221 * @sudat_min: Min data setup time (ns)
222 * @l_min: Min low period of the SCL clock (ns)
223 * @h_min: Min high period of the SCL clock (ns)
224 */
225 struct i2c_spec_s {
226 uint32_t rate;
227 uint32_t fall_max;
228 uint32_t rise_max;
229 uint32_t hddat_min;
230 uint32_t vddat_max;
231 uint32_t sudat_min;
232 uint32_t l_min;
233 uint32_t h_min;
234 };
235
236 /*
237 * struct i2c_timing_s - Private I2C output parameters.
238 * @scldel: Data setup time
239 * @sdadel: Data hold time
240 * @sclh: SCL high period (master mode)
241 * @sclh: SCL low period (master mode)
242 * @is_saved: True if relating to a configuration candidate
243 */
244 struct i2c_timing_s {
245 uint8_t scldel;
246 uint8_t sdadel;
247 uint8_t sclh;
248 uint8_t scll;
249 bool is_saved;
250 };
251
252 /* This table must be sorted in increasing value for field @rate */
253 static const struct i2c_spec_s i2c_specs[] = {
254 /* Standard - 100KHz */
255 {
256 .rate = I2C_STANDARD_RATE,
257 .fall_max = 300,
258 .rise_max = 1000,
259 .hddat_min = 0,
260 .vddat_max = 3450,
261 .sudat_min = 250,
262 .l_min = 4700,
263 .h_min = 4000,
264 },
265 /* Fast - 400KHz */
266 {
267 .rate = I2C_FAST_RATE,
268 .fall_max = 300,
269 .rise_max = 300,
270 .hddat_min = 0,
271 .vddat_max = 900,
272 .sudat_min = 100,
273 .l_min = 1300,
274 .h_min = 600,
275 },
276 /* FastPlus - 1MHz */
277 {
278 .rate = I2C_FAST_PLUS_RATE,
279 .fall_max = 100,
280 .rise_max = 120,
281 .hddat_min = 0,
282 .vddat_max = 450,
283 .sudat_min = 50,
284 .l_min = 500,
285 .h_min = 260,
286 },
287 };
288
289 /*
290 * I2C request parameters
291 * @dev_addr: I2C address of the target device
292 * @mode: Communication mode, one of I2C_MODE_(MASTER|MEM)
293 * @mem_addr: Target memory cell accessed in device (memory mode)
294 * @mem_addr_size: Byte size of the memory cell address (memory mode)
295 * @timeout_ms: Timeout in millisenconds for the request
296 */
297 struct i2c_request {
298 uint32_t dev_addr;
299 enum i2c_mode_e mode;
300 uint32_t mem_addr;
301 uint32_t mem_addr_size;
302 unsigned int timeout_ms;
303 };
304
305 /* Place holder for STM32MP15 non-secure I2C bus compat data */
306 static const int non_secure_bus;
307
get_base(struct i2c_handle_s * hi2c)308 static vaddr_t get_base(struct i2c_handle_s *hi2c)
309 {
310 return io_pa_or_va_secure(&hi2c->base, hi2c->reg_size);
311 }
312
notif_i2c_timeout(struct i2c_handle_s * hi2c)313 static void notif_i2c_timeout(struct i2c_handle_s *hi2c)
314 {
315 hi2c->i2c_err |= I2C_ERROR_TIMEOUT;
316 hi2c->i2c_state = I2C_STATE_READY;
317 }
318
get_specs(uint32_t rate)319 static const struct i2c_spec_s *get_specs(uint32_t rate)
320 {
321 size_t i = 0;
322
323 for (i = 0; i < ARRAY_SIZE(i2c_specs); i++)
324 if (rate <= i2c_specs[i].rate)
325 return i2c_specs + i;
326
327 return NULL;
328 }
329
save_cfg(struct i2c_handle_s * hi2c,struct i2c_cfg * cfg)330 static void save_cfg(struct i2c_handle_s *hi2c, struct i2c_cfg *cfg)
331 {
332 vaddr_t base = get_base(hi2c);
333
334 clk_enable(hi2c->clock);
335
336 cfg->cr1 = io_read32(base + I2C_CR1);
337 cfg->cr2 = io_read32(base + I2C_CR2);
338 cfg->oar1 = io_read32(base + I2C_OAR1);
339 cfg->oar2 = io_read32(base + I2C_OAR2);
340 cfg->timingr = io_read32(base + I2C_TIMINGR);
341
342 clk_disable(hi2c->clock);
343 }
344
restore_cfg(struct i2c_handle_s * hi2c,struct i2c_cfg * cfg)345 static void restore_cfg(struct i2c_handle_s *hi2c, struct i2c_cfg *cfg)
346 {
347 vaddr_t base = get_base(hi2c);
348
349 clk_enable(hi2c->clock);
350
351 io_clrbits32(base + I2C_CR1, I2C_CR1_PE);
352 io_write32(base + I2C_TIMINGR, cfg->timingr & TIMINGR_CLEAR_MASK);
353 io_write32(base + I2C_OAR1, cfg->oar1);
354 io_write32(base + I2C_CR2, cfg->cr2);
355 io_write32(base + I2C_OAR2, cfg->oar2);
356 io_write32(base + I2C_CR1, cfg->cr1 & ~I2C_CR1_PE);
357 io_setbits32(base + I2C_CR1, cfg->cr1 & I2C_CR1_PE);
358
359 clk_disable(hi2c->clock);
360 }
361
dump_cfg(struct i2c_cfg * cfg __maybe_unused)362 static void __maybe_unused dump_cfg(struct i2c_cfg *cfg __maybe_unused)
363 {
364 DMSG("CR1: %#"PRIx32, cfg->cr1);
365 DMSG("CR2: %#"PRIx32, cfg->cr2);
366 DMSG("OAR1: %#"PRIx32, cfg->oar1);
367 DMSG("OAR2: %#"PRIx32, cfg->oar2);
368 DMSG("TIM: %#"PRIx32, cfg->timingr);
369 }
370
dump_i2c(struct i2c_handle_s * hi2c)371 static void __maybe_unused dump_i2c(struct i2c_handle_s *hi2c)
372 {
373 vaddr_t __maybe_unused base = get_base(hi2c);
374
375 clk_enable(hi2c->clock);
376
377 DMSG("CR1: %#"PRIx32, io_read32(base + I2C_CR1));
378 DMSG("CR2: %#"PRIx32, io_read32(base + I2C_CR2));
379 DMSG("OAR1: %#"PRIx32, io_read32(base + I2C_OAR1));
380 DMSG("OAR2: %#"PRIx32, io_read32(base + I2C_OAR2));
381 DMSG("TIM: %#"PRIx32, io_read32(base + I2C_TIMINGR));
382
383 clk_disable(hi2c->clock);
384 }
385
386 /*
387 * Compute the I2C device timings
388 *
389 * @init: Ref to the initialization configuration structure
390 * @clock_src: I2C clock source frequency (Hz)
391 * @timing: Pointer to the final computed timing result
392 * Return 0 on success or a negative value
393 */
i2c_compute_timing(struct stm32_i2c_init_s * init,unsigned long clock_src,uint32_t * timing)394 static int i2c_compute_timing(struct stm32_i2c_init_s *init,
395 unsigned long clock_src, uint32_t *timing)
396 {
397 const struct i2c_spec_s *specs = NULL;
398 uint32_t speed_freq = 0;
399 uint32_t i2cbus = UDIV_ROUND_NEAREST(I2C_NSEC_PER_SEC, speed_freq);
400 uint32_t i2cclk = UDIV_ROUND_NEAREST(I2C_NSEC_PER_SEC, clock_src);
401 uint32_t p_prev = I2C_TIMINGR_PRESC_MAX;
402 uint32_t af_delay_min = 0;
403 uint32_t af_delay_max = 0;
404 uint32_t dnf_delay = 0;
405 uint32_t tsync = 0;
406 uint32_t clk_min = 0;
407 uint32_t clk_max = 0;
408 int clk_error_prev = 0;
409 uint16_t p = 0;
410 uint16_t l = 0;
411 uint16_t a = 0;
412 uint16_t h = 0;
413 unsigned int sdadel_min = 0;
414 unsigned int sdadel_max = 0;
415 unsigned int scldel_min = 0;
416 unsigned int delay = 0;
417 int s = -1;
418 struct i2c_timing_s solutions[I2C_TIMINGR_PRESC_MAX] = { 0 };
419
420 specs = get_specs(init->bus_rate);
421 if (!specs) {
422 DMSG("I2C speed out of bound: %"PRId32"Hz", init->bus_rate);
423 return -1;
424 }
425
426 speed_freq = specs->rate;
427 i2cbus = UDIV_ROUND_NEAREST(I2C_NSEC_PER_SEC, speed_freq);
428 clk_error_prev = INT_MAX;
429
430 if (init->rise_time > specs->rise_max ||
431 init->fall_time > specs->fall_max) {
432 DMSG("I2C rise{%"PRId32">%"PRId32"}/fall{%"PRId32">%"PRId32"}",
433 init->rise_time, specs->rise_max,
434 init->fall_time, specs->fall_max);
435 return -1;
436 }
437
438 if (init->digital_filter_coef > STM32_I2C_DIGITAL_FILTER_MAX) {
439 DMSG("DNF out of bound %"PRId8"/%d",
440 init->digital_filter_coef, STM32_I2C_DIGITAL_FILTER_MAX);
441 return -1;
442 }
443
444 /* Analog and Digital Filters */
445 if (init->analog_filter) {
446 af_delay_min = STM32_I2C_ANALOG_FILTER_DELAY_MIN;
447 af_delay_max = STM32_I2C_ANALOG_FILTER_DELAY_MAX;
448 }
449 dnf_delay = init->digital_filter_coef * i2cclk;
450
451 sdadel_min = specs->hddat_min + init->fall_time;
452 delay = af_delay_min - ((init->digital_filter_coef + 3) * i2cclk);
453 if (SUB_OVERFLOW(sdadel_min, delay, &sdadel_min))
454 sdadel_min = 0;
455
456 sdadel_max = specs->vddat_max - init->rise_time;
457 delay = af_delay_max - ((init->digital_filter_coef + 4) * i2cclk);
458 if (SUB_OVERFLOW(sdadel_max, delay, &sdadel_max))
459 sdadel_max = 0;
460
461 scldel_min = init->rise_time + specs->sudat_min;
462
463 DMSG("I2C SDADEL(min/max): %u/%u, SCLDEL(Min): %u",
464 sdadel_min, sdadel_max, scldel_min);
465
466 /* Compute possible values for PRESC, SCLDEL and SDADEL */
467 for (p = 0; p < I2C_TIMINGR_PRESC_MAX; p++) {
468 for (l = 0; l < I2C_TIMINGR_SCLDEL_MAX; l++) {
469 uint32_t scldel = (l + 1) * (p + 1) * i2cclk;
470
471 if (scldel < scldel_min)
472 continue;
473
474 for (a = 0; a < I2C_TIMINGR_SDADEL_MAX; a++) {
475 uint32_t sdadel = (a * (p + 1) + 1) * i2cclk;
476
477 if ((sdadel >= sdadel_min) &&
478 (sdadel <= sdadel_max) &&
479 (p != p_prev)) {
480 solutions[p].scldel = l;
481 solutions[p].sdadel = a;
482 solutions[p].is_saved = true;
483 p_prev = p;
484 break;
485 }
486 }
487
488 if (p_prev == p)
489 break;
490 }
491 }
492
493 if (p_prev == I2C_TIMINGR_PRESC_MAX) {
494 DMSG("I2C no Prescaler solution");
495 return -1;
496 }
497
498 tsync = af_delay_min + dnf_delay + (2 * i2cclk);
499 clk_max = I2C_NSEC_PER_SEC / RATE_MIN(specs->rate);
500 clk_min = I2C_NSEC_PER_SEC / specs->rate;
501
502 /*
503 * Among prescaler possibilities discovered above figures out SCL Low
504 * and High Period. Provided:
505 * - SCL Low Period has to be higher than Low Period of the SCL Clock
506 * defined by I2C Specification. I2C Clock has to be lower than
507 * (SCL Low Period - Analog/Digital filters) / 4.
508 * - SCL High Period has to be lower than High Period of the SCL Clock
509 * defined by I2C Specification.
510 * - I2C Clock has to be lower than SCL High Period.
511 */
512 for (p = 0; p < I2C_TIMINGR_PRESC_MAX; p++) {
513 uint32_t prescaler = (p + 1) * i2cclk;
514
515 if (!solutions[p].is_saved)
516 continue;
517
518 for (l = 0; l < I2C_TIMINGR_SCLL_MAX; l++) {
519 uint32_t tscl_l = ((l + 1) * prescaler) + tsync;
520
521 if (tscl_l < specs->l_min ||
522 i2cclk >= ((tscl_l - af_delay_min - dnf_delay) / 4))
523 continue;
524
525 for (h = 0; h < I2C_TIMINGR_SCLH_MAX; h++) {
526 uint32_t tscl_h = ((h + 1) * prescaler) + tsync;
527 uint32_t tscl = tscl_l + tscl_h +
528 init->rise_time +
529 init->fall_time;
530
531 if (tscl >= clk_min && tscl <= clk_max &&
532 tscl_h >= specs->h_min && i2cclk < tscl_h) {
533 int clk_error = tscl - i2cbus;
534
535 if (clk_error < 0)
536 clk_error = -clk_error;
537
538 if (clk_error < clk_error_prev) {
539 clk_error_prev = clk_error;
540 solutions[p].scll = l;
541 solutions[p].sclh = h;
542 s = p;
543 }
544 }
545 }
546 }
547 }
548
549 if (s < 0) {
550 DMSG("I2C no solution at all");
551 return -1;
552 }
553
554 /* Finalize timing settings */
555 *timing = I2C_SET_TIMINGR_PRESC(s) |
556 I2C_SET_TIMINGR_SCLDEL(solutions[s].scldel) |
557 I2C_SET_TIMINGR_SDADEL(solutions[s].sdadel) |
558 I2C_SET_TIMINGR_SCLH(solutions[s].sclh) |
559 I2C_SET_TIMINGR_SCLL(solutions[s].scll);
560
561 DMSG("I2C TIMINGR (PRESC/SCLDEL/SDADEL): %i/%"PRIu8"/%"PRIu8,
562 s, solutions[s].scldel, solutions[s].sdadel);
563 DMSG("I2C TIMINGR (SCLH/SCLL): %"PRIu8"/%"PRIu8,
564 solutions[s].sclh, solutions[s].scll);
565 DMSG("I2C TIMINGR: 0x%"PRIx32, *timing);
566
567 return 0;
568 }
569
570 /* i2c_specs[] must be sorted by increasing rate */
i2c_specs_is_consistent(void)571 static bool __maybe_unused i2c_specs_is_consistent(void)
572 {
573 size_t i = 0;
574
575 COMPILE_TIME_ASSERT(ARRAY_SIZE(i2c_specs));
576
577 for (i = 1; i < ARRAY_SIZE(i2c_specs); i++)
578 if (i2c_specs[i - 1].rate >= i2c_specs[i].rate)
579 return false;
580
581 return true;
582 }
583
584 /*
585 * @brief From requested rate, get the closest I2C rate without exceeding it,
586 * within I2C specification values defined in @i2c_specs.
587 * @param rate: The requested rate.
588 * @retval Found rate, else the lowest value supported by platform.
589 */
get_lower_rate(uint32_t rate)590 static uint32_t get_lower_rate(uint32_t rate)
591 {
592 size_t i = 0;
593
594 for (i = ARRAY_SIZE(i2c_specs); i > 0; i--)
595 if (rate > i2c_specs[i - 1].rate)
596 return i2c_specs[i - 1].rate;
597
598 return i2c_specs[0].rate;
599 }
600
601 /*
602 * Setup the I2C device timings
603 *
604 * @hi2c: I2C handle structure
605 * @init: Ref to the initialization configuration structure
606 * @timing: Output TIMINGR register configuration value
607 * @retval 0 if OK, negative value else
608 */
i2c_setup_timing(struct i2c_handle_s * hi2c,struct stm32_i2c_init_s * init,uint32_t * timing)609 static int i2c_setup_timing(struct i2c_handle_s *hi2c,
610 struct stm32_i2c_init_s *init,
611 uint32_t *timing)
612 {
613 int rc = 0;
614 unsigned long clock_src = 0;
615
616 assert(i2c_specs_is_consistent());
617
618 clock_src = clk_get_rate(hi2c->clock);
619 if (!clock_src) {
620 DMSG("Null I2C clock rate");
621 return -1;
622 }
623
624 /*
625 * If the timing has already been computed, and the frequency is the
626 * same as when it was computed, then use the saved timing.
627 */
628 if (clock_src == hi2c->saved_frequency) {
629 *timing = hi2c->saved_timing;
630 return 0;
631 }
632
633 do {
634 rc = i2c_compute_timing(init, clock_src, timing);
635 if (rc) {
636 DMSG("Failed to compute I2C timings");
637 if (init->bus_rate > I2C_STANDARD_RATE) {
638 init->bus_rate = get_lower_rate(init->bus_rate);
639 IMSG("Downgrade I2C speed to %"PRIu32"Hz)",
640 init->bus_rate);
641 } else {
642 break;
643 }
644 }
645 } while (rc);
646
647 if (rc) {
648 DMSG("Impossible to compute I2C timings");
649 return rc;
650 }
651
652 DMSG("I2C Freq(%"PRIu32"Hz), Clk Source(%lu)",
653 init->bus_rate, clock_src);
654 DMSG("I2C Rise(%"PRId32") and Fall(%"PRId32") Time",
655 init->rise_time, init->fall_time);
656 DMSG("I2C Analog Filter(%s), DNF(%"PRIu8")",
657 init->analog_filter ? "On" : "Off", init->digital_filter_coef);
658
659 hi2c->saved_timing = *timing;
660 hi2c->saved_frequency = clock_src;
661
662 return 0;
663 }
664
665 /*
666 * Configure I2C Analog noise filter.
667 * @hi2c: I2C handle structure
668 * @analog_filter_on: True if enabling analog filter, false otherwise
669 */
i2c_config_analog_filter(struct i2c_handle_s * hi2c,bool analog_filter_on)670 static void i2c_config_analog_filter(struct i2c_handle_s *hi2c,
671 bool analog_filter_on)
672 {
673 vaddr_t base = get_base(hi2c);
674
675 /* Disable the selected I2C peripheral */
676 io_clrbits32(base + I2C_CR1, I2C_CR1_PE);
677
678 /* Reset I2Cx ANOFF bit */
679 io_clrbits32(base + I2C_CR1, I2C_CR1_ANFOFF);
680
681 /* Set analog filter bit if filter is disabled */
682 if (!analog_filter_on)
683 io_setbits32(base + I2C_CR1, I2C_CR1_ANFOFF);
684
685 /* Enable the selected I2C peripheral */
686 io_setbits32(base + I2C_CR1, I2C_CR1_PE);
687 }
688
stm32_i2c_get_setup_from_fdt(void * fdt,int node,struct stm32_i2c_init_s * init,struct pinctrl_state ** pinctrl,struct pinctrl_state ** pinctrl_sleep)689 TEE_Result stm32_i2c_get_setup_from_fdt(void *fdt, int node,
690 struct stm32_i2c_init_s *init,
691 struct pinctrl_state **pinctrl,
692 struct pinctrl_state **pinctrl_sleep)
693 {
694 TEE_Result res = TEE_ERROR_GENERIC;
695 const fdt32_t *cuint = NULL;
696 struct dt_node_info info = { .status = 0 };
697 int __maybe_unused count = 0;
698
699 /* Default STM32 specific configs caller may need to overwrite */
700 memset(init, 0, sizeof(*init));
701
702 fdt_fill_device_info(fdt, &info, node);
703 assert(info.reg != DT_INFO_INVALID_REG &&
704 info.reg_size != DT_INFO_INVALID_REG_SIZE);
705
706 init->pbase = info.reg;
707 init->reg_size = info.reg_size;
708
709 res = clk_dt_get_by_index(fdt, node, 0, &init->clock);
710 if (res)
711 return res;
712
713 cuint = fdt_getprop(fdt, node, "i2c-scl-rising-time-ns", NULL);
714 if (cuint)
715 init->rise_time = fdt32_to_cpu(*cuint);
716 else
717 init->rise_time = STM32_I2C_RISE_TIME_DEFAULT;
718
719 cuint = fdt_getprop(fdt, node, "i2c-scl-falling-time-ns", NULL);
720 if (cuint)
721 init->fall_time = fdt32_to_cpu(*cuint);
722 else
723 init->fall_time = STM32_I2C_FALL_TIME_DEFAULT;
724
725 cuint = fdt_getprop(fdt, node, "clock-frequency", NULL);
726 if (cuint) {
727 init->bus_rate = fdt32_to_cpu(*cuint);
728
729 if (init->bus_rate > I2C_FAST_PLUS_RATE) {
730 DMSG("Invalid bus speed (%"PRIu32" > %i)",
731 init->bus_rate, I2C_FAST_PLUS_RATE);
732 return TEE_ERROR_GENERIC;
733 }
734 } else {
735 init->bus_rate = I2C_STANDARD_RATE;
736 }
737
738 if (pinctrl) {
739 res = pinctrl_get_state_by_name(fdt, node, "default", pinctrl);
740 if (res)
741 return res;
742 }
743
744 if (pinctrl_sleep) {
745 res = pinctrl_get_state_by_name(fdt, node, "sleep",
746 pinctrl_sleep);
747 if (res == TEE_ERROR_ITEM_NOT_FOUND)
748 res = TEE_SUCCESS;
749 if (res)
750 return res;
751 }
752
753 return TEE_SUCCESS;
754 }
755
init_i2c_bus_access_lock(struct i2c_handle_s * hi2c)756 static void init_i2c_bus_access_lock(struct i2c_handle_s *hi2c)
757 {
758 mutex_pm_aware_init(&hi2c->mu);
759 hi2c->consumer_itr_lock = 0;
760 }
761
is_thread_context(void)762 static bool is_thread_context(void)
763 {
764 return thread_is_in_normal_mode() && thread_get_id_may_fail() >= 0;
765 }
766
lock_i2c_bus_access(struct i2c_handle_s * hi2c)767 static void lock_i2c_bus_access(struct i2c_handle_s *hi2c)
768 {
769 /*
770 * In order to support cases when a PMIC interrupt triggers
771 * before async notif is supported, we allow I2C access under
772 * interrupt context. To do so, thread context ensures PMIC
773 * interrupt (actually the related PWR interrupt) is masked
774 * while we're accessing the I2C from a thread context. We
775 * must also make sure any pending interrupts under execution
776 * complete before accessing the bus on async notif enable
777 * transition.
778 */
779 if (is_thread_context()) {
780 struct stm32_itr_dep *itr_dep = NULL;
781 uint32_t exceptions = 0;
782 uint64_t timeout = 0;
783
784 /* Lock thread access */
785 mutex_pm_aware_lock(&hi2c->mu);
786 FMSG("Thread access");
787
788 /*
789 * When async notif is not started, mask registered consumer
790 * interrupt during the thread context I2C access so we don't
791 * conflict with a interrupt access to the I2C bus. When async
792 * notif is started, all PMIC interrupts are routed to a thread
793 * execution context so we don't need to mask them.
794 */
795 if (!notif_async_is_started(0)) {
796 exceptions = thread_mask_exceptions(THREAD_EXCP_ALL);
797
798 hi2c->consumer_itr_masked = true;
799
800 /* Ensure next pending interrupts are masked */
801 SLIST_FOREACH(itr_dep, &hi2c->consumer_itr_head, link)
802 interrupt_mask(itr_dep->chip, itr_dep->num);
803
804 thread_unmask_exceptions(exceptions);
805 }
806
807 /* Wait possibly executing interrupt transfer completion */
808 timeout = timeout_init_us(I2C_TIMEOUT_ITR_LOCKED_MS * 1000);
809 while (!timeout_elapsed(timeout))
810 if (!atomic_load_int(&hi2c->consumer_itr_lock))
811 break;
812
813 if (atomic_load_int(&hi2c->consumer_itr_lock)) {
814 EMSG("Unexpected lengthy I2C xfer, base PA %"PRIxPA,
815 hi2c->base.pa);
816 panic();
817 }
818 } else {
819 FMSG("Interrupt access");
820 atomic_store_int(&hi2c->consumer_itr_lock, 1);
821 }
822 }
823
unlock_i2c_bus_access(struct i2c_handle_s * hi2c)824 static void unlock_i2c_bus_access(struct i2c_handle_s *hi2c)
825 {
826 if (is_thread_context()) {
827 FMSG("Thread access completed");
828
829 if (hi2c->consumer_itr_masked) {
830 struct stm32_itr_dep *itr_dep = NULL;
831
832 /* Unmask possibly pending interrupts */
833 SLIST_FOREACH(itr_dep, &hi2c->consumer_itr_head, link)
834 interrupt_unmask(itr_dep->chip, itr_dep->num);
835
836 hi2c->consumer_itr_masked = false;
837 }
838
839 /* Unlock thread access */
840 mutex_pm_aware_unlock(&hi2c->mu);
841 } else {
842 FMSG("Interrupt access completed");
843 atomic_store_int(&hi2c->consumer_itr_lock, 0);
844 }
845 }
846
stm32_i2c_init(struct i2c_handle_s * hi2c,struct stm32_i2c_init_s * init_data)847 int stm32_i2c_init(struct i2c_handle_s *hi2c,
848 struct stm32_i2c_init_s *init_data)
849 {
850 int rc = 0;
851 uint32_t timing = 0;
852 vaddr_t base = 0;
853 uint32_t val = 0;
854
855 init_i2c_bus_access_lock(hi2c);
856
857 rc = i2c_setup_timing(hi2c, init_data, &timing);
858 if (rc)
859 return rc;
860
861 clk_enable(hi2c->clock);
862
863 base = get_base(hi2c);
864 hi2c->i2c_state = I2C_STATE_BUSY;
865
866 /* Disable the selected I2C peripheral */
867 io_clrbits32(base + I2C_CR1, I2C_CR1_PE);
868
869 /* Configure I2Cx: Frequency range */
870 io_write32(base + I2C_TIMINGR, timing & TIMINGR_CLEAR_MASK);
871
872 /* Disable Own Address1 before set the Own Address1 configuration */
873 io_write32(base + I2C_OAR1, 0);
874
875 /* Configure I2Cx: Own Address1 and ack own address1 mode */
876 if (init_data->addr_mode_10b_not_7b)
877 io_write32(base + I2C_OAR1,
878 I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE |
879 init_data->own_address1);
880 else
881 io_write32(base + I2C_OAR1,
882 I2C_OAR1_OA1EN | init_data->own_address1);
883
884 /* Configure I2Cx: Addressing Master mode */
885 io_write32(base + I2C_CR2, 0);
886 if (init_data->addr_mode_10b_not_7b)
887 io_setbits32(base + I2C_CR2, I2C_CR2_ADD10);
888
889 /*
890 * Enable the AUTOEND by default, and enable NACK
891 * (should be disabled only during Slave process).
892 */
893 io_setbits32(base + I2C_CR2, I2C_CR2_AUTOEND | I2C_CR2_NACK);
894
895 /* Disable Own Address2 before set the Own Address2 configuration */
896 io_write32(base + I2C_OAR2, 0);
897
898 /* Configure I2Cx: Dual mode and Own Address2 */
899 if (init_data->dual_address_mode)
900 io_write32(base + I2C_OAR2,
901 I2C_OAR2_OA2EN | init_data->own_address2 |
902 (init_data->own_address2_masks << 8));
903
904 /* Configure I2Cx: Generalcall and NoStretch mode */
905 val = 0;
906 if (init_data->general_call_mode)
907 val |= I2C_CR1_GCEN;
908 if (init_data->no_stretch_mode)
909 val |= I2C_CR1_NOSTRETCH;
910 io_write32(base + I2C_CR1, val);
911
912 /* Enable the selected I2C peripheral */
913 io_setbits32(base + I2C_CR1, I2C_CR1_PE);
914
915 hi2c->i2c_err = I2C_ERROR_NONE;
916 hi2c->i2c_state = I2C_STATE_READY;
917
918 i2c_config_analog_filter(hi2c, init_data->analog_filter);
919
920 clk_disable(hi2c->clock);
921
922 if (hi2c->pinctrl && pinctrl_apply_state(hi2c->pinctrl))
923 return -1;
924
925 return 0;
926 }
927
928 /* I2C transmit (TX) data register flush sequence */
i2c_flush_txdr(struct i2c_handle_s * hi2c)929 static void i2c_flush_txdr(struct i2c_handle_s *hi2c)
930 {
931 vaddr_t base = get_base(hi2c);
932
933 /*
934 * If a pending TXIS flag is set,
935 * write a dummy data in TXDR to clear it.
936 */
937 if (io_read32(base + I2C_ISR) & I2C_ISR_TXIS)
938 io_write32(base + I2C_TXDR, 0);
939
940 /* Flush TX register if not empty */
941 if ((io_read32(base + I2C_ISR) & I2C_ISR_TXE) == 0)
942 io_setbits32(base + I2C_ISR, I2C_ISR_TXE);
943 }
944
945 /*
946 * Wait for a single target I2C_ISR bit to reach an awaited value (0 or 1)
947 *
948 * @hi2c: I2C handle structure
949 * @bit_mask: Bit mask for the target single bit position to consider
950 * @awaited_value: Awaited value of the target bit in I2C_ISR, 0 or 1
951 * @timeout_ref: Expriation timeout reference
952 * Return 0 on success and a non-zero value on timeout
953 */
wait_isr_event(struct i2c_handle_s * hi2c,uint32_t bit_mask,unsigned int awaited_value,uint64_t timeout_ref)954 static int wait_isr_event(struct i2c_handle_s *hi2c, uint32_t bit_mask,
955 unsigned int awaited_value, uint64_t timeout_ref)
956 {
957 vaddr_t isr = get_base(hi2c) + I2C_ISR;
958
959 assert(IS_POWER_OF_TWO(bit_mask) && !(awaited_value & ~1U));
960
961 /* May timeout while TEE thread is suspended */
962 while (!timeout_elapsed(timeout_ref))
963 if (!!(io_read32(isr) & bit_mask) == awaited_value)
964 break;
965
966 if (!!(io_read32(isr) & bit_mask) == awaited_value)
967 return 0;
968
969 notif_i2c_timeout(hi2c);
970 return -1;
971 }
972
973 /* Handle Acknowledge-Failed sequence detection during an I2C Communication */
i2c_ack_failed(struct i2c_handle_s * hi2c,uint64_t timeout_ref)974 static int i2c_ack_failed(struct i2c_handle_s *hi2c, uint64_t timeout_ref)
975 {
976 vaddr_t base = get_base(hi2c);
977
978 if ((io_read32(base + I2C_ISR) & I2C_ISR_NACKF) == 0U)
979 return 0;
980
981 /*
982 * Wait until STOP Flag is reset. Use polling method.
983 * AutoEnd should be initiate after AF.
984 * Timeout may elpased while TEE thread is suspended.
985 */
986 while (!timeout_elapsed(timeout_ref))
987 if (io_read32(base + I2C_ISR) & I2C_ISR_STOPF)
988 break;
989
990 if ((io_read32(base + I2C_ISR) & I2C_ISR_STOPF) == 0) {
991 notif_i2c_timeout(hi2c);
992 return -1;
993 }
994
995 io_write32(base + I2C_ICR, I2C_ISR_NACKF);
996
997 io_write32(base + I2C_ICR, I2C_ISR_STOPF);
998
999 i2c_flush_txdr(hi2c);
1000
1001 io_clrbits32(base + I2C_CR2, CR2_RESET_MASK);
1002
1003 hi2c->i2c_err |= I2C_ERROR_ACKF;
1004 hi2c->i2c_state = I2C_STATE_READY;
1005
1006 return -1;
1007 }
1008
1009 /* Wait TXIS bit is 1 in I2C_ISR register */
i2c_wait_txis(struct i2c_handle_s * hi2c,uint64_t timeout_ref)1010 static int i2c_wait_txis(struct i2c_handle_s *hi2c, uint64_t timeout_ref)
1011 {
1012 while (!timeout_elapsed(timeout_ref)) {
1013 if (io_read32(get_base(hi2c) + I2C_ISR) & I2C_ISR_TXIS)
1014 break;
1015 if (i2c_ack_failed(hi2c, timeout_ref))
1016 return -1;
1017 }
1018
1019 if (io_read32(get_base(hi2c) + I2C_ISR) & I2C_ISR_TXIS)
1020 return 0;
1021
1022 if (i2c_ack_failed(hi2c, timeout_ref))
1023 return -1;
1024
1025 notif_i2c_timeout(hi2c);
1026 return -1;
1027 }
1028
1029 /* Wait STOPF bit is 1 in I2C_ISR register */
i2c_wait_stop(struct i2c_handle_s * hi2c,uint64_t timeout_ref)1030 static int i2c_wait_stop(struct i2c_handle_s *hi2c, uint64_t timeout_ref)
1031 {
1032 while (!timeout_elapsed(timeout_ref)) {
1033 if (io_read32(get_base(hi2c) + I2C_ISR) & I2C_ISR_STOPF)
1034 break;
1035
1036 if (i2c_ack_failed(hi2c, timeout_ref))
1037 return -1;
1038 }
1039
1040 if (io_read32(get_base(hi2c) + I2C_ISR) & I2C_ISR_STOPF)
1041 return 0;
1042
1043 if (i2c_ack_failed(hi2c, timeout_ref))
1044 return -1;
1045
1046 notif_i2c_timeout(hi2c);
1047 return -1;
1048 }
1049
1050 /*
1051 * Load I2C_CR2 register for a I2C transfer
1052 *
1053 * @hi2c: I2C handle structure
1054 * @dev_addr: Slave address to be transferred
1055 * @size: Number of bytes to be transferred
1056 * @i2c_mode: One of I2C_{RELOAD|AUTOEND|SOFTEND}_MODE: Enable Reload mode.
1057 * @startstop: One of I2C_NO_STARTSTOP, I2C_GENERATE_STOP,
1058 * I2C_GENERATE_START_{READ|WRITE}
1059 */
i2c_transfer_config(struct i2c_handle_s * hi2c,uint32_t dev_addr,uint32_t size,uint32_t i2c_mode,uint32_t startstop)1060 static void i2c_transfer_config(struct i2c_handle_s *hi2c, uint32_t dev_addr,
1061 uint32_t size, uint32_t i2c_mode,
1062 uint32_t startstop)
1063 {
1064 uint32_t clr_value = I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD |
1065 I2C_CR2_AUTOEND | I2C_CR2_START | I2C_CR2_STOP |
1066 (I2C_CR2_RD_WRN &
1067 (startstop >> (31U - I2C_CR2_RD_WRN_OFFSET)));
1068 uint32_t set_value = (dev_addr & I2C_CR2_SADD) |
1069 ((size << I2C_CR2_NBYTES_OFFSET) &
1070 I2C_CR2_NBYTES) |
1071 i2c_mode | startstop;
1072
1073 io_clrsetbits32(get_base(hi2c) + I2C_CR2, clr_value, set_value);
1074 }
1075
1076 /*
1077 * Master sends target device address followed by internal memory
1078 * address for a memory write request.
1079 * Function returns 0 on success or a negative value.
1080 */
i2c_request_mem_write(struct i2c_handle_s * hi2c,struct i2c_request * request,uint64_t timeout_ref)1081 static int i2c_request_mem_write(struct i2c_handle_s *hi2c,
1082 struct i2c_request *request,
1083 uint64_t timeout_ref)
1084 {
1085 vaddr_t base = get_base(hi2c);
1086
1087 i2c_transfer_config(hi2c, request->dev_addr, request->mem_addr_size,
1088 I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
1089
1090 if (i2c_wait_txis(hi2c, timeout_ref))
1091 return -1;
1092
1093 if (request->mem_addr_size == I2C_MEMADD_SIZE_8BIT) {
1094 /* Send memory address */
1095 io_write8(base + I2C_TXDR, request->mem_addr & 0x00FFU);
1096 } else {
1097 /* Send MSB of memory address */
1098 io_write8(base + I2C_TXDR, (request->mem_addr & 0xFF00U) >> 8);
1099
1100 if (i2c_wait_txis(hi2c, timeout_ref))
1101 return -1;
1102
1103 /* Send LSB of memory address */
1104 io_write8(base + I2C_TXDR, request->mem_addr & 0x00FFU);
1105 }
1106
1107 if (wait_isr_event(hi2c, I2C_ISR_TCR, 1, timeout_ref))
1108 return -1;
1109
1110 return 0;
1111 }
1112
1113 /*
1114 * Master sends target device address followed by internal memory
1115 * address to prepare a memory read request.
1116 * Function returns 0 on success or a negative value.
1117 */
i2c_request_mem_read(struct i2c_handle_s * hi2c,struct i2c_request * request,uint64_t timeout_ref)1118 static int i2c_request_mem_read(struct i2c_handle_s *hi2c,
1119 struct i2c_request *request,
1120 uint64_t timeout_ref)
1121 {
1122 vaddr_t base = get_base(hi2c);
1123
1124 i2c_transfer_config(hi2c, request->dev_addr, request->mem_addr_size,
1125 I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
1126
1127 if (i2c_wait_txis(hi2c, timeout_ref))
1128 return -1;
1129
1130 if (request->mem_addr_size == I2C_MEMADD_SIZE_8BIT) {
1131 /* Send memory address */
1132 io_write8(base + I2C_TXDR, request->mem_addr & 0x00FFU);
1133 } else {
1134 /* Send MSB of memory address */
1135 io_write8(base + I2C_TXDR, (request->mem_addr & 0xFF00U) >> 8);
1136
1137 if (i2c_wait_txis(hi2c, timeout_ref))
1138 return -1;
1139
1140 /* Send LSB of memory address */
1141 io_write8(base + I2C_TXDR, request->mem_addr & 0x00FFU);
1142 }
1143
1144 if (wait_isr_event(hi2c, I2C_ISR_TC, 1, timeout_ref))
1145 return -1;
1146
1147 return 0;
1148 }
1149
1150 /*
1151 * Write an amount of data in blocking mode
1152 *
1153 * @hi2c: Reference to struct i2c_handle_s
1154 * @request: I2C request parameters
1155 * @p_data: Pointer to data buffer
1156 * @size: Amount of data to be sent
1157 * Return 0 on success or a negative value
1158 */
do_write(struct i2c_handle_s * hi2c,struct i2c_request * request,uint8_t * p_data,uint16_t size)1159 static int do_write(struct i2c_handle_s *hi2c, struct i2c_request *request,
1160 uint8_t *p_data, uint16_t size)
1161 {
1162 uint64_t timeout_ref = 0;
1163 vaddr_t base = get_base(hi2c);
1164 int rc = -1;
1165 uint8_t *p_buff = p_data;
1166 size_t xfer_size = 0;
1167 size_t xfer_count = size;
1168
1169 if (request->mode != I2C_MODE_MASTER && request->mode != I2C_MODE_MEM)
1170 return -1;
1171
1172 if (!p_data || !size)
1173 return -1;
1174
1175 lock_i2c_bus_access(hi2c);
1176
1177 if (hi2c->i2c_state != I2C_STATE_READY) {
1178 unlock_i2c_bus_access(hi2c);
1179 return -1;
1180 }
1181
1182 clk_enable(hi2c->clock);
1183
1184 timeout_ref = timeout_init_us(I2C_TIMEOUT_BUSY_MS * 1000);
1185 if (wait_isr_event(hi2c, I2C_ISR_BUSY, 0, timeout_ref))
1186 goto bail;
1187
1188 hi2c->i2c_state = I2C_STATE_BUSY_TX;
1189 hi2c->i2c_err = I2C_ERROR_NONE;
1190 timeout_ref = timeout_init_us(request->timeout_ms * 1000);
1191
1192 if (request->mode == I2C_MODE_MEM) {
1193 /* In memory mode, send slave address and memory address */
1194 if (i2c_request_mem_write(hi2c, request, timeout_ref))
1195 goto bail;
1196
1197 if (xfer_count > MAX_NBYTE_SIZE) {
1198 xfer_size = MAX_NBYTE_SIZE;
1199 i2c_transfer_config(hi2c, request->dev_addr, xfer_size,
1200 I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
1201 } else {
1202 xfer_size = xfer_count;
1203 i2c_transfer_config(hi2c, request->dev_addr, xfer_size,
1204 I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
1205 }
1206 } else {
1207 /* In master mode, send slave address */
1208 if (xfer_count > MAX_NBYTE_SIZE) {
1209 xfer_size = MAX_NBYTE_SIZE;
1210 i2c_transfer_config(hi2c, request->dev_addr, xfer_size,
1211 I2C_RELOAD_MODE,
1212 I2C_GENERATE_START_WRITE);
1213 } else {
1214 xfer_size = xfer_count;
1215 i2c_transfer_config(hi2c, request->dev_addr, xfer_size,
1216 I2C_AUTOEND_MODE,
1217 I2C_GENERATE_START_WRITE);
1218 }
1219 }
1220
1221 do {
1222 if (i2c_wait_txis(hi2c, timeout_ref))
1223 goto bail;
1224
1225 io_write8(base + I2C_TXDR, *p_buff);
1226 p_buff++;
1227 xfer_count--;
1228 xfer_size--;
1229
1230 if (xfer_count && !xfer_size) {
1231 /* Wait until TCR flag is set */
1232 if (wait_isr_event(hi2c, I2C_ISR_TCR, 1, timeout_ref))
1233 goto bail;
1234
1235 if (xfer_count > MAX_NBYTE_SIZE) {
1236 xfer_size = MAX_NBYTE_SIZE;
1237 i2c_transfer_config(hi2c, request->dev_addr,
1238 xfer_size,
1239 I2C_RELOAD_MODE,
1240 I2C_NO_STARTSTOP);
1241 } else {
1242 xfer_size = xfer_count;
1243 i2c_transfer_config(hi2c, request->dev_addr,
1244 xfer_size,
1245 I2C_AUTOEND_MODE,
1246 I2C_NO_STARTSTOP);
1247 }
1248 }
1249
1250 } while (xfer_count > 0U);
1251
1252 /*
1253 * No need to Check TC flag, with AUTOEND mode the stop
1254 * is automatically generated.
1255 * Wait until STOPF flag is reset.
1256 */
1257 if (i2c_wait_stop(hi2c, timeout_ref))
1258 goto bail;
1259
1260 io_write32(base + I2C_ICR, I2C_ISR_STOPF);
1261
1262 io_clrbits32(base + I2C_CR2, CR2_RESET_MASK);
1263
1264 hi2c->i2c_state = I2C_STATE_READY;
1265
1266 rc = 0;
1267
1268 bail:
1269 clk_disable(hi2c->clock);
1270 unlock_i2c_bus_access(hi2c);
1271
1272 return rc;
1273 }
1274
stm32_i2c_mem_write(struct i2c_handle_s * hi2c,uint32_t dev_addr,uint32_t mem_addr,uint32_t mem_addr_size,uint8_t * p_data,size_t size,unsigned int timeout_ms)1275 int stm32_i2c_mem_write(struct i2c_handle_s *hi2c, uint32_t dev_addr,
1276 uint32_t mem_addr, uint32_t mem_addr_size,
1277 uint8_t *p_data, size_t size, unsigned int timeout_ms)
1278 {
1279 struct i2c_request request = {
1280 .dev_addr = dev_addr,
1281 .mode = I2C_MODE_MEM,
1282 .mem_addr = mem_addr,
1283 .mem_addr_size = mem_addr_size,
1284 .timeout_ms = timeout_ms,
1285 };
1286
1287 return do_write(hi2c, &request, p_data, size);
1288 }
1289
stm32_i2c_master_transmit(struct i2c_handle_s * hi2c,uint32_t dev_addr,uint8_t * p_data,size_t size,unsigned int timeout_ms)1290 int stm32_i2c_master_transmit(struct i2c_handle_s *hi2c, uint32_t dev_addr,
1291 uint8_t *p_data, size_t size,
1292 unsigned int timeout_ms)
1293 {
1294 struct i2c_request request = {
1295 .dev_addr = dev_addr,
1296 .mode = I2C_MODE_MASTER,
1297 .timeout_ms = timeout_ms,
1298 };
1299
1300 return do_write(hi2c, &request, p_data, size);
1301 }
1302
stm32_i2c_read_write_membyte(struct i2c_handle_s * hi2c,uint16_t dev_addr,unsigned int mem_addr,uint8_t * p_data,bool write)1303 int stm32_i2c_read_write_membyte(struct i2c_handle_s *hi2c, uint16_t dev_addr,
1304 unsigned int mem_addr, uint8_t *p_data,
1305 bool write)
1306 {
1307 uint64_t timeout_ref = 0;
1308 uintptr_t base = get_base(hi2c);
1309 int rc = -1;
1310 uint8_t *p_buff = p_data;
1311 uint32_t event_mask = 0;
1312
1313 lock_i2c_bus_access(hi2c);
1314
1315 if (hi2c->i2c_state != I2C_STATE_READY || !p_data) {
1316 unlock_i2c_bus_access(hi2c);
1317 return -1;
1318 }
1319
1320 clk_enable(hi2c->clock);
1321
1322 timeout_ref = timeout_init_us(I2C_TIMEOUT_BUSY_US);
1323 if (wait_isr_event(hi2c, I2C_ISR_BUSY, 0, timeout_ref))
1324 goto bail;
1325
1326 hi2c->i2c_state = write ? I2C_STATE_BUSY_TX : I2C_STATE_BUSY_RX;
1327 hi2c->i2c_err = I2C_ERROR_NONE;
1328
1329 i2c_transfer_config(hi2c, dev_addr, I2C_MEMADD_SIZE_8BIT,
1330 write ? I2C_RELOAD_MODE : I2C_SOFTEND_MODE,
1331 I2C_GENERATE_START_WRITE);
1332
1333 timeout_ref = timeout_init_us(I2C_TIMEOUT_BUSY_US);
1334 if (i2c_wait_txis(hi2c, timeout_ref))
1335 goto bail;
1336
1337 io_write8(base + I2C_TXDR, mem_addr);
1338
1339 if (write)
1340 event_mask = I2C_ISR_TCR;
1341 else
1342 event_mask = I2C_ISR_TC;
1343
1344 timeout_ref = timeout_init_us(I2C_TIMEOUT_BUSY_US);
1345 if (wait_isr_event(hi2c, event_mask, 1, timeout_ref))
1346 goto bail;
1347
1348 i2c_transfer_config(hi2c, dev_addr, I2C_MEMADD_SIZE_8BIT,
1349 I2C_AUTOEND_MODE,
1350 write ? I2C_NO_STARTSTOP : I2C_GENERATE_START_READ);
1351
1352 timeout_ref = timeout_init_us(I2C_TIMEOUT_BUSY_US);
1353 if (write) {
1354 if (i2c_wait_txis(hi2c, timeout_ref))
1355 goto bail;
1356
1357 io_write8(base + I2C_TXDR, *p_buff);
1358 } else {
1359 if (wait_isr_event(hi2c, I2C_ISR_RXNE, 1, timeout_ref))
1360 goto bail;
1361
1362 *p_buff = io_read8(base + I2C_RXDR);
1363 }
1364
1365 timeout_ref = timeout_init_us(I2C_TIMEOUT_BUSY_US);
1366 if (i2c_wait_stop(hi2c, timeout_ref))
1367 goto bail;
1368
1369 io_write32(base + I2C_ICR, I2C_ISR_STOPF);
1370 io_clrbits32(base + I2C_CR2, CR2_RESET_MASK);
1371
1372 hi2c->i2c_state = I2C_STATE_READY;
1373
1374 rc = 0;
1375
1376 bail:
1377 clk_disable(hi2c->clock);
1378 unlock_i2c_bus_access(hi2c);
1379
1380 return rc;
1381 }
1382
1383 /*
1384 * Read an amount of data in blocking mode
1385 *
1386 * @hi2c: Reference to struct i2c_handle_s
1387 * @request: I2C request parameters
1388 * @p_data: Pointer to data buffer
1389 * @size: Amount of data to be sent
1390 * Return 0 on success or a negative value
1391 */
do_read(struct i2c_handle_s * hi2c,struct i2c_request * request,uint8_t * p_data,uint32_t size)1392 static int do_read(struct i2c_handle_s *hi2c, struct i2c_request *request,
1393 uint8_t *p_data, uint32_t size)
1394 {
1395 vaddr_t base = get_base(hi2c);
1396 uint64_t timeout_ref = 0;
1397 int rc = -1;
1398 uint8_t *p_buff = p_data;
1399 size_t xfer_count = size;
1400 size_t xfer_size = 0;
1401
1402 if (request->mode != I2C_MODE_MASTER && request->mode != I2C_MODE_MEM)
1403 return -1;
1404
1405 if (!p_data || !size)
1406 return -1;
1407
1408 lock_i2c_bus_access(hi2c);
1409
1410 if (hi2c->i2c_state != I2C_STATE_READY) {
1411 unlock_i2c_bus_access(hi2c);
1412 return -1;
1413 }
1414
1415 clk_enable(hi2c->clock);
1416
1417 timeout_ref = timeout_init_us(I2C_TIMEOUT_BUSY_MS * 1000);
1418 if (wait_isr_event(hi2c, I2C_ISR_BUSY, 0, timeout_ref))
1419 goto bail;
1420
1421 hi2c->i2c_state = I2C_STATE_BUSY_RX;
1422 hi2c->i2c_err = I2C_ERROR_NONE;
1423 timeout_ref = timeout_init_us(request->timeout_ms * 1000);
1424
1425 if (request->mode == I2C_MODE_MEM) {
1426 /* Send memory address */
1427 if (i2c_request_mem_read(hi2c, request, timeout_ref))
1428 goto bail;
1429 }
1430
1431 /*
1432 * Send slave address.
1433 * Set NBYTES to write and reload if xfer_count > MAX_NBYTE_SIZE
1434 * and generate RESTART.
1435 */
1436 if (xfer_count > MAX_NBYTE_SIZE) {
1437 xfer_size = MAX_NBYTE_SIZE;
1438 i2c_transfer_config(hi2c, request->dev_addr, xfer_size,
1439 I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
1440 } else {
1441 xfer_size = xfer_count;
1442 i2c_transfer_config(hi2c, request->dev_addr, xfer_size,
1443 I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
1444 }
1445
1446 do {
1447 if (wait_isr_event(hi2c, I2C_ISR_RXNE, 1,
1448 timeout_init_us(I2C_TIMEOUT_RXNE_MS * 1000)))
1449 goto bail;
1450
1451 *p_buff = io_read8(base + I2C_RXDR);
1452 p_buff++;
1453 xfer_size--;
1454 xfer_count--;
1455
1456 if (xfer_count && !xfer_size) {
1457 if (wait_isr_event(hi2c, I2C_ISR_TCR, 1, timeout_ref))
1458 goto bail;
1459
1460 if (xfer_count > MAX_NBYTE_SIZE) {
1461 xfer_size = MAX_NBYTE_SIZE;
1462 i2c_transfer_config(hi2c, request->dev_addr,
1463 xfer_size,
1464 I2C_RELOAD_MODE,
1465 I2C_NO_STARTSTOP);
1466 } else {
1467 xfer_size = xfer_count;
1468 i2c_transfer_config(hi2c, request->dev_addr,
1469 xfer_size,
1470 I2C_AUTOEND_MODE,
1471 I2C_NO_STARTSTOP);
1472 }
1473 }
1474 } while (xfer_count > 0U);
1475
1476 /*
1477 * No need to Check TC flag, with AUTOEND mode the stop
1478 * is automatically generated.
1479 * Wait until STOPF flag is reset.
1480 */
1481 if (i2c_wait_stop(hi2c, timeout_ref))
1482 goto bail;
1483
1484 /* Clear the NACK generated at the end of the transfer */
1485 if ((io_read32(get_base(hi2c) + I2C_ISR) & I2C_ISR_NACKF))
1486 io_write32(get_base(hi2c) + I2C_ICR, I2C_ICR_NACKCF);
1487
1488 io_write32(base + I2C_ICR, I2C_ISR_STOPF);
1489
1490 io_clrbits32(base + I2C_CR2, CR2_RESET_MASK);
1491
1492 hi2c->i2c_state = I2C_STATE_READY;
1493
1494 rc = 0;
1495
1496 bail:
1497 clk_disable(hi2c->clock);
1498 unlock_i2c_bus_access(hi2c);
1499
1500 return rc;
1501 }
1502
stm32_i2c_mem_read(struct i2c_handle_s * hi2c,uint32_t dev_addr,uint32_t mem_addr,uint32_t mem_addr_size,uint8_t * p_data,size_t size,unsigned int timeout_ms)1503 int stm32_i2c_mem_read(struct i2c_handle_s *hi2c, uint32_t dev_addr,
1504 uint32_t mem_addr, uint32_t mem_addr_size,
1505 uint8_t *p_data, size_t size, unsigned int timeout_ms)
1506 {
1507 struct i2c_request request = {
1508 .dev_addr = dev_addr,
1509 .mode = I2C_MODE_MEM,
1510 .mem_addr = mem_addr,
1511 .mem_addr_size = mem_addr_size,
1512 .timeout_ms = timeout_ms,
1513 };
1514
1515 return do_read(hi2c, &request, p_data, size);
1516 }
1517
stm32_i2c_master_receive(struct i2c_handle_s * hi2c,uint32_t dev_addr,uint8_t * p_data,size_t size,unsigned int timeout_ms)1518 int stm32_i2c_master_receive(struct i2c_handle_s *hi2c, uint32_t dev_addr,
1519 uint8_t *p_data, size_t size,
1520 unsigned int timeout_ms)
1521 {
1522 struct i2c_request request = {
1523 .dev_addr = dev_addr,
1524 .mode = I2C_MODE_MASTER,
1525 .timeout_ms = timeout_ms,
1526 };
1527
1528 return do_read(hi2c, &request, p_data, size);
1529 }
1530
stm32_i2c_dev_to_handle(struct i2c_dev * i2c_dev)1531 static struct i2c_handle_s *stm32_i2c_dev_to_handle(struct i2c_dev *i2c_dev)
1532 {
1533 struct stm32_i2c_dev *dev = container_of(i2c_dev, struct stm32_i2c_dev,
1534 i2c_dev);
1535
1536 return dev->handle;
1537 }
1538
stm32_i2c_read_data(struct i2c_dev * i2c_dev,uint8_t * buf,size_t len)1539 static TEE_Result stm32_i2c_read_data(struct i2c_dev *i2c_dev, uint8_t *buf,
1540 size_t len)
1541 {
1542 struct i2c_handle_s *i2c_handle = stm32_i2c_dev_to_handle(i2c_dev);
1543 int rc = 0;
1544
1545 rc = stm32_i2c_master_receive(i2c_handle, i2c_dev->addr, buf, len,
1546 I2C_TIMEOUT_DEFAULT_MS);
1547 if (!rc)
1548 return TEE_SUCCESS;
1549 else
1550 return TEE_ERROR_GENERIC;
1551 }
1552
stm32_i2c_write_data(struct i2c_dev * i2c_dev,const uint8_t * buf,size_t len)1553 static TEE_Result stm32_i2c_write_data(struct i2c_dev *i2c_dev,
1554 const uint8_t *buf, size_t len)
1555 {
1556 struct i2c_handle_s *i2c_handle = stm32_i2c_dev_to_handle(i2c_dev);
1557 uint8_t *buf2 = (uint8_t *)buf;
1558 int rc = 0;
1559
1560 rc = stm32_i2c_master_transmit(i2c_handle, i2c_dev->addr, buf2, len,
1561 I2C_TIMEOUT_DEFAULT_MS);
1562 if (!rc)
1563 return TEE_SUCCESS;
1564 else
1565 return TEE_ERROR_GENERIC;
1566 }
1567
1568 static const struct i2c_ctrl_ops stm32_i2c_ops = {
1569 .read = stm32_i2c_read_data,
1570 .write = stm32_i2c_write_data,
1571 };
1572
stm32_i2c_is_device_ready(struct i2c_handle_s * hi2c,uint32_t dev_addr,unsigned int trials,unsigned int timeout_ms)1573 bool stm32_i2c_is_device_ready(struct i2c_handle_s *hi2c, uint32_t dev_addr,
1574 unsigned int trials, unsigned int timeout_ms)
1575 {
1576 vaddr_t base = get_base(hi2c);
1577 unsigned int i2c_trials = 0U;
1578 bool rc = false;
1579
1580 lock_i2c_bus_access(hi2c);
1581
1582 if (hi2c->i2c_state != I2C_STATE_READY) {
1583 unlock_i2c_bus_access(hi2c);
1584 return rc;
1585 }
1586
1587 clk_enable(hi2c->clock);
1588
1589 if (io_read32(base + I2C_ISR) & I2C_ISR_BUSY)
1590 goto bail;
1591
1592 hi2c->i2c_state = I2C_STATE_BUSY;
1593 hi2c->i2c_err = I2C_ERROR_NONE;
1594
1595 do {
1596 uint64_t timeout_ref = 0;
1597 vaddr_t isr = base + I2C_ISR;
1598
1599 /* Generate Start */
1600 if ((io_read32(base + I2C_OAR1) & I2C_OAR1_OA1MODE) == 0)
1601 io_write32(base + I2C_CR2,
1602 ((dev_addr & I2C_CR2_SADD) |
1603 I2C_CR2_START | I2C_CR2_AUTOEND) &
1604 ~I2C_CR2_RD_WRN);
1605 else
1606 io_write32(base + I2C_CR2,
1607 ((dev_addr & I2C_CR2_SADD) |
1608 I2C_CR2_START | I2C_CR2_ADD10) &
1609 ~I2C_CR2_RD_WRN);
1610
1611 /*
1612 * No need to Check TC flag, with AUTOEND mode the stop
1613 * is automatically generated.
1614 * Wait until STOPF flag is set or a NACK flag is set.
1615 */
1616 timeout_ref = timeout_init_us(timeout_ms * 1000);
1617 while (!timeout_elapsed(timeout_ref))
1618 if (io_read32(isr) & (I2C_ISR_STOPF | I2C_ISR_NACKF))
1619 break;
1620
1621 if ((io_read32(isr) & (I2C_ISR_STOPF | I2C_ISR_NACKF)) == 0) {
1622 notif_i2c_timeout(hi2c);
1623 goto bail;
1624 }
1625
1626 if ((io_read32(base + I2C_ISR) & I2C_ISR_NACKF) == 0U) {
1627 if (wait_isr_event(hi2c, I2C_ISR_STOPF, 1, timeout_ref))
1628 goto bail;
1629
1630 io_write32(base + I2C_ICR, I2C_ISR_STOPF);
1631
1632 hi2c->i2c_state = I2C_STATE_READY;
1633
1634 rc = true;
1635 goto bail;
1636 }
1637
1638 if (wait_isr_event(hi2c, I2C_ISR_STOPF, 1, timeout_ref))
1639 goto bail;
1640
1641 io_write32(base + I2C_ICR, I2C_ISR_NACKF);
1642 io_write32(base + I2C_ICR, I2C_ISR_STOPF);
1643
1644 if (i2c_trials == trials) {
1645 io_setbits32(base + I2C_CR2, I2C_CR2_STOP);
1646
1647 if (wait_isr_event(hi2c, I2C_ISR_STOPF, 1, timeout_ref))
1648 goto bail;
1649
1650 io_write32(base + I2C_ICR, I2C_ISR_STOPF);
1651 }
1652
1653 i2c_trials++;
1654 } while (i2c_trials < trials);
1655
1656 notif_i2c_timeout(hi2c);
1657
1658 bail:
1659 clk_disable(hi2c->clock);
1660 unlock_i2c_bus_access(hi2c);
1661
1662 return rc;
1663 }
1664
stm32_i2c_interrupt_access_lockdeps(struct i2c_handle_s * hi2c,struct itr_chip * itr_chip,size_t itr_num)1665 void stm32_i2c_interrupt_access_lockdeps(struct i2c_handle_s *hi2c,
1666 struct itr_chip *itr_chip,
1667 size_t itr_num)
1668 {
1669 struct stm32_itr_dep *itr_dep = NULL;
1670
1671 itr_dep = calloc(1, sizeof(*itr_dep));
1672 if (!itr_dep)
1673 panic();
1674
1675 itr_dep->chip = itr_chip;
1676 itr_dep->num = itr_num;
1677 SLIST_INSERT_HEAD(&hi2c->consumer_itr_head, itr_dep, link);
1678 }
1679
stm32_i2c_resume(struct i2c_handle_s * hi2c)1680 void stm32_i2c_resume(struct i2c_handle_s *hi2c)
1681 {
1682 if (hi2c->i2c_state == I2C_STATE_READY)
1683 return;
1684
1685 if ((hi2c->i2c_state != I2C_STATE_RESET) &&
1686 (hi2c->i2c_state != I2C_STATE_SUSPENDED))
1687 panic();
1688
1689 if (pinctrl_apply_state(hi2c->pinctrl))
1690 panic();
1691
1692 if (hi2c->i2c_state == I2C_STATE_RESET) {
1693 /* There is no valid I2C configuration to be loaded yet */
1694 return;
1695 }
1696
1697 restore_cfg(hi2c, &hi2c->sec_cfg);
1698
1699 hi2c->i2c_state = I2C_STATE_READY;
1700 }
1701
stm32_i2c_suspend(struct i2c_handle_s * hi2c)1702 void stm32_i2c_suspend(struct i2c_handle_s *hi2c)
1703 {
1704 if (hi2c->i2c_state == I2C_STATE_SUSPENDED)
1705 return;
1706
1707 if (hi2c->i2c_state != I2C_STATE_READY)
1708 panic();
1709
1710 save_cfg(hi2c, &hi2c->sec_cfg);
1711
1712 if (hi2c->pinctrl_sleep && pinctrl_apply_state(hi2c->pinctrl_sleep))
1713 panic();
1714
1715 hi2c->i2c_state = I2C_STATE_SUSPENDED;
1716 }
1717
stm32_get_i2c_dev(struct dt_pargs * args,void * data,struct i2c_dev ** out_device)1718 static TEE_Result stm32_get_i2c_dev(struct dt_pargs *args, void *data,
1719 struct i2c_dev **out_device)
1720 {
1721 struct stm32_i2c_dev *stm32_i2c_dev = NULL;
1722 paddr_t addr = 0;
1723
1724 addr = fdt_reg_base_address(args->fdt, args->consumer_node);
1725 if (addr == DT_INFO_INVALID_REG) {
1726 DMSG("Can't get device I2C address");
1727 return TEE_ERROR_GENERIC;
1728 }
1729
1730 stm32_i2c_dev = calloc(1, sizeof(*stm32_i2c_dev));
1731 if (!stm32_i2c_dev)
1732 return TEE_ERROR_OUT_OF_MEMORY;
1733
1734 stm32_i2c_dev->handle = data;
1735 stm32_i2c_dev->i2c_dev.addr = addr;
1736 stm32_i2c_dev->i2c_ctrl.ops = &stm32_i2c_ops;
1737 stm32_i2c_dev->i2c_dev.ctrl = &stm32_i2c_dev->i2c_ctrl;
1738
1739 *out_device = &stm32_i2c_dev->i2c_dev;
1740
1741 return TEE_SUCCESS;
1742 }
1743
stm32_i2c_probe(const void * fdt,int node,const void * compat_data)1744 static TEE_Result stm32_i2c_probe(const void *fdt, int node,
1745 const void *compat_data)
1746 {
1747 TEE_Result res = TEE_SUCCESS;
1748 int subnode = 0;
1749 struct i2c_handle_s *i2c_handle_p = NULL;
1750 struct stm32_i2c_init_s init_data = { };
1751 struct pinctrl_state *pinctrl_active = NULL;
1752 struct pinctrl_state *pinctrl_idle = NULL;
1753
1754 res = stm32_i2c_get_setup_from_fdt((void *)fdt, node, &init_data,
1755 &pinctrl_active, &pinctrl_idle);
1756 if (res)
1757 return res;
1758
1759 i2c_handle_p = calloc(1, sizeof(struct i2c_handle_s));
1760 if (!i2c_handle_p)
1761 return TEE_ERROR_OUT_OF_MEMORY;
1762
1763 i2c_handle_p->reg_size = init_data.reg_size;
1764 i2c_handle_p->clock = init_data.clock;
1765 i2c_handle_p->base.pa = init_data.pbase;
1766 i2c_handle_p->base.va = io_pa_or_va(&i2c_handle_p->base,
1767 init_data.reg_size);
1768 assert(i2c_handle_p->base.va);
1769 i2c_handle_p->clock = init_data.clock;
1770 i2c_handle_p->i2c_state = I2C_STATE_RESET;
1771 i2c_handle_p->pinctrl = pinctrl_active;
1772 i2c_handle_p->pinctrl_sleep = pinctrl_idle;
1773
1774 if (compat_data != &non_secure_bus)
1775 i2c_handle_p->i2c_secure = true;
1776
1777 init_data.analog_filter = true;
1778 init_data.digital_filter_coef = 0;
1779
1780 if (stm32_i2c_init(i2c_handle_p, &init_data))
1781 panic("Couldn't initialise I2C");
1782
1783 res = i2c_register_provider(fdt, node, stm32_get_i2c_dev, i2c_handle_p);
1784 if (res)
1785 panic("Couldn't register I2C provider");
1786
1787 fdt_for_each_subnode(subnode, fdt, node) {
1788 res = dt_driver_maybe_add_probe_node(fdt, subnode);
1789 if (res) {
1790 EMSG("Failed on node %s with %#"PRIx32,
1791 fdt_get_name(fdt, subnode, NULL), res);
1792 panic();
1793 }
1794 }
1795
1796 return res;
1797 }
1798
1799 static const struct dt_device_match stm32_i2c_match_table[] = {
1800 { .compatible = "st,stm32mp15-i2c" },
1801 { .compatible = "st,stm32mp13-i2c" },
1802 {
1803 .compatible = "st,stm32mp15-i2c-non-secure",
1804 .compat_data = &non_secure_bus,
1805 },
1806 { .compatible = "st,stm32mp25-i2c" },
1807 { }
1808 };
1809
1810 DEFINE_DT_DRIVER(stm32_i2c_dt_driver) = {
1811 .name = "stm32_i2c",
1812 .match_table = stm32_i2c_match_table,
1813 .probe = stm32_i2c_probe,
1814 .type = DT_DRIVER_I2C
1815 };
1816