1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2022 Rockchip Electronics Co. Ltd. 4 * 5 * it66353 HDMI 3 in 1 out driver. 6 * 7 * Author: Kenneth.Hung@ite.com.tw 8 * Wangqiang Guo <kay.guo@rock-chips.com> 9 * Version: IT66353_SAMPLE_1.08 10 * 11 */ 12 #ifndef _IT66353_DRV_H_ 13 #define _IT66353_DRV_H_ 14 15 #include "platform.h" 16 #include "it66353.h" 17 18 #define RX_PORT_0 0 19 #define RX_PORT_1 1 20 #define RX_PORT_2 2 21 #define RX_PORT_3 3 22 23 #define TRUE 1 24 #define FALSE 0 25 26 #define DDCWAITTIME 5 27 #define DDCWAITNUM 10 28 29 #define RX_PORT_COUNT 4 30 31 // for it66353_rx_term_power_down 32 #define CH0_OFF (0x10) 33 #define CH1_OFF (0x20) 34 #define CH2_OFF (0x40) 35 #define CLK_OFF (0x80) 36 #define ALLCH_OFF (0xF0) 37 #define ALLCH_ON (0x00) 38 39 /* =================================================== 40 * config: 41 * =================================================== 42 * 43 * RCLKFreqSel => 0: 20MHz, 1: 10MHz, 2: 5MHz, 3: 2.5MHz 44 */ 45 #define RCLKFreqSel 0 46 47 typedef enum { 48 RX_TOGGLE_HPD, 49 RX_PORT_CHANGE, 50 TX_OUTPUT, 51 TX_OUTPUT_PREPARE, 52 RX_CHECK_EQ, 53 SETUP_AFE, 54 RX_WAIT_CLOCK, 55 RX_HPD, 56 TX_GOT_HPD, 57 TX_WAIT_HPD, 58 TX_UNPLUG, 59 RX_UNPLUG, 60 IDLE, 61 } _SYS_FSM_STATE; 62 63 enum { 64 HDMI_MODE_AUTO, 65 HDMI_MODE_14, 66 HDMI_MODE_20, 67 }; 68 69 enum { 70 EQ_MODE_H14, 71 EQ_MODE_H20, 72 }; 73 74 75 typedef enum { 76 DEV_DEVICE_LOOP, 77 DEV_DEVICE_INIT, 78 DEV_WAIT_DEVICE_READY, 79 DEV_FW_VAR_INIT, 80 DEV_WAIT_RESET, 81 } _DEV_FSM_STATE; 82 83 typedef enum { 84 AEQ_OFF, 85 AEQ_START, 86 AEQ_CHECK_SAREQ_RESULT, 87 AEQ_APPLY_SAREQ, 88 AEQ_DONE, 89 AEQ_FAIL, 90 AEQ_MAX, 91 } _AEQ_FSM_STATE; 92 93 typedef enum { 94 EQRES_UNKNOWN, 95 EQRES_BUSY, 96 EQRES_SAREQ_DONE, 97 EQRES_SAREQ_FAIL, 98 EQRES_SAREQ_TIMEOUT, 99 EQRES_H14EQ_DONE, 100 EQRES_H14EQ_FAIL, 101 EQRES_H14EQ_TIMEOUT, 102 EQRES_DONE, 103 } _EQ_RESULT_TYPE; 104 105 typedef enum { 106 SysAEQ_OFF, 107 SysAEQ_RUN, 108 SysAEQ_DONE, 109 } _SYS_AEQ_TYPE; 110 111 enum { 112 EDID_SRC_EXT_SINK, 113 EDID_SRC_INTERNAL, 114 }; 115 116 enum { 117 TERM_LOW, 118 TERM_HIGH, 119 TERM_FOLLOW_TX, 120 TERM_FOLLOW_HPD, 121 }; 122 123 #define EDID_PORT_0 0x01 124 #define EDID_PORT_1 0x02 125 #define EDID_PORT_2 0x04 126 #define EDID_PORT_3 0x08 127 #define EDID_PORT_ALL (EDID_PORT_0 | EDID_PORT_1 | EDID_PORT_2 | EDID_PORT_3) 128 129 /* 130 * for it66353_get_port_info0() 131 */ 132 #define PI_5V (BIT(0)) 133 #define PI_HDMI_MODE (BIT(1)) 134 #define PI_CLK_DET (BIT(2)) 135 #define PI_CLK_VALID (BIT(3)) 136 #define PI_CLK_STABLE (BIT(4)) 137 #define PI_PLL_LOCK (BIT(5)) 138 // #define PI_XX (BIT(6)) 139 #define PI_SYM_LOCK (BIT(7)) 140 141 /* 142 * for it66353_get_port_info1() 143 */ 144 #define PI_PLL_HS1G 0x01 145 // #define PI_PLL_HS1G (BIT0) 146 147 typedef struct { 148 // TxSwap 149 u8 EnTxPNSwap; 150 u8 EnTxChSwap; 151 u8 EnTxVCLKInv; 152 u8 EnTxOutD1t; 153 154 u8 EnRxDDCBypass; 155 u8 EnRxPWR5VBypass; 156 u8 EnRxHPDBypass; 157 158 u8 EnCEC; 159 160 u8 EnableAutoEQ; 161 u8 ParseEDIDFromSink; 162 u8 NonActivePortReplyHPD; 163 u8 DisableEdidRam; 164 u8 TryFixedEQFirst; 165 u8 TurnOffTx5VWhenSwitchPort; 166 u8 FixIncorrectHdmiEnc; 167 168 } IT6635_DEVICE_OPTION_INT; 169 170 typedef struct { 171 u8 tag1; 172 u8 EnRxDDCBypass; 173 u8 EnRxPWR5VBypass; 174 u8 EnRxHPDBypass; 175 u8 TryFixedEQFirst; 176 u8 EnableAutoEQ; 177 u8 NonActivePortReplyHPD; 178 u8 DisableEdidRam; 179 u8 DefaultEQ[3]; 180 u8 FixIncorrectHdmiEnc; 181 u8 HPDOutputInverse; 182 u8 HPDTogglePeriod; 183 u8 TxOEAlignment; 184 u8 str_size; 185 186 } IT6635_RX_OPTIONS; 187 188 typedef struct { 189 u8 tag1; 190 // TxSwap 191 u8 EnTxPNSwap; 192 u8 EnTxChSwap; 193 u8 EnTxVCLKInv; 194 u8 EnTxOutD1t; 195 u8 CopyEDIDFromSink; 196 u8 ParsePhysicalAddr; 197 u8 TurnOffTx5VWhenSwitchPort; 198 u8 str_size; 199 200 } IT6635_TX_OPTIONS; 201 202 typedef struct { 203 u8 tag1; 204 u8 SwAddr; 205 u8 RxAddr; 206 u8 CecAddr; 207 u8 EdidAddr; 208 u8 ForceRxOn; 209 u8 RxAutoPowerDown; 210 u8 DoTxPowerDown; 211 u8 TxPowerDownWhileWaitingClock; 212 u8 str_size; 213 214 } IT6635_DEV_OPTION; 215 216 typedef struct { 217 IT6635_RX_OPTIONS *active_rx_opt; 218 IT6635_RX_OPTIONS *rx_opt[4]; 219 IT6635_TX_OPTIONS *tx_opt; 220 IT6635_DEV_OPTION *dev_opt; 221 222 } IT6635_DEV_OPTION_INTERNAL; 223 224 typedef struct { 225 struct { 226 u8 Rev; 227 u32 RCLK; 228 u8 RxHPDFlag[4]; 229 230 u8 VSDBOffset; // 0xFF; 231 232 u8 PhyAdr[4]; 233 u8 EdidChkSum[2]; 234 235 _SYS_FSM_STATE state_sys_fsm; 236 u8 state_dev_init; 237 u8 state_dev; 238 u8 fsm_return; 239 u8 Rx_active_port; 240 u8 Rx_new_port; 241 u8 Tx_current_5v; 242 u32 vclk; 243 u32 vclk_prev; 244 245 u16 RxCEDErr[3]; 246 u8 RxCEDErrValid; 247 u16 RxCEDErrRec[3][3]; 248 249 u8 count_unlock; 250 u8 count_symlock; 251 u8 count_symlock_lost; 252 u8 count_symlock_fail; 253 u8 count_symlock_unstable; 254 u8 count_fsm_err; 255 u8 count_eq_check; 256 u8 count_try_force_hdmi_mode; 257 u8 count_auto_eq_fail; 258 u8 count_wait_clock; 259 u8 clock_ratio; 260 u8 h2_scramble; 261 u8 edid_ready; 262 u8 prev_hpd_state; 263 264 u8 try_fixed_EQ; 265 u8 current_hdmi_mode; 266 u8 current_txoe; 267 u8 check_for_hpd_toggle; 268 u8 sdi_stable_count; 269 u8 check_for_sdi; 270 u8 force_hpd_state; 271 // u8 txoe_alignment; 272 u8 hpd_toggle_timeout; 273 u8 spmon; 274 275 __tick tick_set_afe; 276 __tick tick_hdcp; 277 // u8 en_count_hdcp; 278 u8 *default_edid[4]; 279 280 // tx 281 u8 hpd_wait_count; 282 u8 is_hdmi20_sink; 283 u8 rx_deskew_err; 284 } vars; 285 286 struct { 287 _SYS_AEQ_TYPE sys_aEQ; 288 u8 AutoEQ_state; 289 u8 AutoEQ_WaitTime; 290 u8 AutoEQ_Result; 291 u8 DFE_Valid; 292 u8 RS_Valid; 293 u16 RS_ValidMap[3]; 294 u8 EqHDMIMode; 295 u8 ManuEQ_state; 296 u8 DFE[14][3][3]; // [RS_value][channel012][NumABC] -> 0x34B...0x353 297 u8 CalcRS[3]; 298 299 u8 EQ_flag_14; 300 u8 EQ_flag_20; 301 u8 txoe_ready14; 302 u8 txoe_ready20; 303 u8 stored_RS_14[3]; 304 u8 stored_RS_20[3]; 305 u8 current_eq_mode; 306 307 // u8 FixedRsIndex[4]; 308 309 u8 meq_cur_idx; 310 311 u8 meq_adj_idx[3]; 312 u32 ced_err_avg[3]; 313 u32 ced_err_avg_prev[3]; 314 u8 ced_acc_count; 315 u8 manu_eq_fine_tune_count[3]; 316 u8 manu_eq_fine_tune_best_rs[3]; 317 318 } EQ; 319 320 // u8 edid_buf[128]; 321 322 IT6635_DEV_OPTION_INTERNAL opts; 323 324 } IT6635_DEVICE_DATA; 325 326 extern IT6635_DEVICE_DATA it66353_gdev; 327 extern const u8 it66353_rs_value[]; 328 extern IT6635_RX_OPTIONS it66353_s_RxOpts; 329 extern IT6635_TX_OPTIONS it66353_s_TxOpts; 330 extern IT6635_DEV_OPTION it66353_s_DevOpts; 331 extern u8 it66353_s_default_edid_port0[]; 332 333 334 #ifdef __cplusplus 335 extern "C" { 336 #endif 337 338 // -------------------------------- 339 extern u8 it66353_h2swwr(u8 offset, u8 wdata); 340 extern u8 it66353_h2swrd(u8 offset); 341 extern u8 it66353_h2swset(u8 offset, u8 mask, u8 wdata); 342 extern void it66353_h2swbrd(u8 offset, u8 length, u8 *rddata); 343 extern void it66353_h2swbwr(u8 offset, u8 length, u8 *rddata); 344 345 extern u8 it66353_h2rxwr(u8 offset, u8 wdata); 346 extern u8 it66353_h2rxrd(u8 offset); 347 extern u8 it66353_h2rxset(u8 offset, u8 mask, u8 dwata); 348 extern void it66353_h2rxbrd(u8 offset, u8 length, u8 *rddata); 349 extern void it66353_h2rxbwr(u8 offset, u8 length, u8 *rddata); 350 351 extern u8 it66353_cecwr(u8 offset, u8 wdata); 352 extern u8 it66353_cecrd(u8 offset); 353 extern u8 it66353_cecset(u8 offset, u8 mask, u8 wdata); 354 extern void it66353_cecbrd(u8 offset, u8 length, u8 *rddata); 355 extern void it66353_cecbwr(u8 offset, u8 length, u8 *rddata); 356 357 extern u8 it66353_h2rxedidwr(u8 offset, u8 *wrdata, u8 length); 358 359 extern void it66353_chgrxbank(u8 bankno); 360 extern void it66353_chgswbank(u8 bankno); 361 362 extern void it66353_rx_update_ced_err_from_hw(void); 363 extern void it66353_rx_get_ced_err(void); 364 extern void it66353_rx_clear_ced_err(void); 365 extern u8 it66353_rx_monitor_ced_err(void); 366 extern void it66353_rx_DFE_enable(u8 enable); 367 extern void it66353_rx_set_rs_3ch(u8 *rs_value); 368 extern void it66353_rx_set_rs(u8 ch, u8 rs_value); 369 370 extern u8 it66353_rx_is_all_ch_symlock(void); 371 extern u8 it66353_rx_is_ch_symlock(u8 ch); 372 extern u8 it66353_rx_is_clock_stable(void); 373 374 extern void it66353_rx_ovwr_hdmi_clk(u8 port, u8 ratio); 375 extern void it66353_rx_ovwr_h20_scrb(u8 port, u8 scrb); 376 377 extern void it66353_rx_auto_power_down_enable(u8 port, u8 enable); 378 extern void it66353_rx_term_power_down(u8 port, u8 channel); 379 extern void it66353_rx_handle_output_err(void); 380 381 extern void it66353_sw_enable_timer0(void); 382 extern void it66353_sw_disable_timer0(void); 383 extern u8 it66353_sw_get_timer0_interrupt(void); 384 385 extern void it66353_sw_clear_hdcp_status(void); 386 // -------------------------------- 387 extern void it66353_txoe(u8 enable); 388 extern void it66353_auto_detect_hdmi_encoding(void); 389 extern void it66353_fix_incorrect_hdmi_encoding(void); 390 391 extern u8 it66353_get_port_info1(u8 port, u8 info); 392 extern u8 it66353_get_port_info0(u8 port, u8 info); 393 394 extern void it66353_init_rclk(void); 395 extern void it66353_enable_tx_port(u8 enable); 396 // -------------- 397 extern void it66353_sys_state(u8 new_state); 398 extern void it66353_rx_reset(void); 399 extern void it66353_rx_caof_init(u8 port); 400 401 extern void it66353_eq_save_h20(void); 402 extern void it66353_eq_load_h20(void); 403 extern void it66353_eq_save_h14(void); 404 extern void it66353_eq_load_h14(void); 405 extern void it66353_eq_load_previous(void); 406 extern void it66353_eq_load_default(void); 407 408 extern void it66353_eq_reset_state(void); 409 extern void it66353_eq_set_state(u8 state); 410 extern u8 it66353_eq_get_state(void); 411 extern void it66353_eq_reset_txoe_ready(void); 412 extern void it66353_eq_set_txoe_ready(u8 ready); 413 extern u8 it66353_eq_get_txoe_ready(void); 414 415 extern void it66353_aeq_set_DFE2(u8 EQ0, u8 EQ1, u8 EQ2); 416 extern u8 it66353_rx_is_hdmi20(void); 417 extern void it66353_aeq_diable_eq_trigger(void); 418 extern u8 it66353_aeq_check_sareq_result(void); 419 420 #if DEBUG_FSM_CHANGE 421 #define it66353_fsm_chg(new_state) __it66353_fsm_chg(new_state, __LINE__) 422 #define it66353_fsm_chg_delayed(new_state) __it66353_fsm_chg2(new_state, __LINE__) 423 #else 424 extern void it66353_fsm_chg(u8 new_state); 425 extern void it66353_fsm_chg_delayed(u8 new_state); 426 #endif 427 428 extern void __it66353_fsm_chg(u8 new_state, int caller); 429 extern void __it66353_fsm_chg2(u8 new_state, int caller); 430 // void it66353_vars_init(void); 431 extern bool it66353_device_init(void); 432 extern bool it66353_device_init2(void); 433 434 extern bool it66353_read_edid(u8 block, u8 offset, int length, u8 *edid_buffer); 435 extern bool it66353_write_one_block_edid(u8 block, u8 *edid_buffer); 436 extern bool it66353_setup_edid_ram(u8 flag); 437 438 extern void it66353_force_hdmi20(void); 439 440 #ifdef __cplusplus 441 } 442 #endif 443 444 extern void it66353_rx_skew_adj(u8 ch); 445 #define _rx_edid_address_enable(port)\ 446 {it66353_h2swset(0x55 + port, 0x24, 0x20); } 447 #define _rx_edid_address_disable(port)\ 448 {it66353_h2swset(0x55 + port, 0x24, 0x04); } 449 #define _rx_edid_ram_enable(port)\ 450 {if (it66353_gdev.opts.rx_opt[port]->EnRxDDCBypass == 0) { it66353_h2swset(0x55 + port, 0x01, 0x00); }} 451 #define _rx_edid_ram_disable(port)\ 452 { it66353_h2swset(0x55 + port, 0x01, 0x01); } 453 #define _rx_edid_set_chksum(port, sum)\ 454 { it66353_h2swwr(0xe1 + port * 2, sum); } 455 #define _rx_edid_set_cec_phyaddr(port, phyAB, phyCD)\ 456 { it66353_h2swwr(0xd9 + port*2, phyAB); it66353_h2swwr(0xda + port*2, phyCD); } 457 458 #endif