1 /* 2 * rk_aiq_types_adpcc_ext.h 3 * 4 * Copyright (c) 2019 Rockchip Corporation 5 * 6 * Licensed under the Apache License, Version 2.0 (the "License"); 7 * you may not use this file except in compliance with the License. 8 * You may obtain a copy of the License at 9 * 10 * http://www.apache.org/licenses/LICENSE-2.0 11 * 12 * Unless required by applicable law or agreed to in writing, software 13 * distributed under the License is distributed on an "AS IS" BASIS, 14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 * See the License for the specific language governing permissions and 16 * limitations under the License. 17 * 18 */ 19 20 #ifndef __RK_AIQ_TYPES_ADPCC_EXT_H__ 21 #define __RK_AIQ_TYPES_ADPCC_EXT_H__ 22 23 #include "rk_aiq_comm.h" 24 25 #define CALIBDB_MAX_ISO_LEVEL 13 26 #define CALIBDB_NR_SHARP_MAX_ISO_LEVEL CALIBDB_MAX_ISO_LEVEL 27 #define CALIBDB_DPCC_MAX_ISO_LEVEL CALIBDB_MAX_ISO_LEVEL 28 #define CALIBDB_BLC_MAX_ISO_LEVEL CALIBDB_MAX_ISO_LEVEL 29 #define CALIBDB_NR_SHARP_SETTING_LEVEL 6 30 #define CALIBDB_MAX_MODE_NUM 5 31 #define CALIBDB_ZOOM_FOCUS_TBL_SIZE 256 32 #define CALIBDB_DEGAMMA_CRUVE_KNOTS 17 33 #define CALIBDB_ADPCC_KNOTS_NUM 13 34 #define CALIBDB_ADPCC_PDAF_KNOTS_NUM 16 35 #define DPCC_MAX_ISO_LEVEL CALIBDB_ADPCC_KNOTS_NUM 36 #define DPCC_PDAF_POINT_NUM (16) 37 38 #define CALIBDB_MAX_MODE_NAME_LENGTH (20) 39 #define CALIBDB_MAX_SCENE_NAME_LENGTH (10) 40 41 typedef enum AdpccOPMode_e { 42 ADPCC_OP_MODE_INVALID = 0, /**< initialization value */ 43 ADPCC_OP_MODE_AUTO = 1, /**< instance is created, but not initialized */ 44 ADPCC_OP_MODE_MANUAL = 2, /**< instance is confiured (ready to start) or stopped */ 45 ADPCC_OP_MODE_MAX /**< max */ 46 } AdpccOPMode_t; 47 48 typedef enum Adpcc_onfly_mode_e { 49 ADPCC_ONFLY_MODE_FAST = 0, /**< dpcc manual fast mode */ 50 ADPCC_ONFLY_MODE_EXPERT = 1, /**< dpcc manual expert mode */ 51 ADPCC_ONFLY_MODE_MAX /**< max */ 52 } Adpcc_onfly_mode_t; 53 54 typedef struct CalibDb_Dpcc_Sensor_s { 55 float en; 56 float max_level; 57 float iso[CALIBDB_DPCC_MAX_ISO_LEVEL]; 58 float level_single[CALIBDB_DPCC_MAX_ISO_LEVEL]; 59 float level_multiple[CALIBDB_DPCC_MAX_ISO_LEVEL]; 60 } CalibDb_Dpcc_Sensor_t; 61 62 typedef struct CalibDb_Dpcc_Fast_Mode_s { 63 int fast_mode_en; 64 int ISO[CALIBDB_DPCC_MAX_ISO_LEVEL]; 65 int fast_mode_single_en; 66 int fast_mode_single_level[CALIBDB_DPCC_MAX_ISO_LEVEL]; 67 int fast_mode_double_en; 68 int fast_mode_double_level[CALIBDB_DPCC_MAX_ISO_LEVEL]; 69 int fast_mode_triple_en; 70 int fast_mode_triple_level[CALIBDB_DPCC_MAX_ISO_LEVEL]; 71 } CalibDb_Dpcc_Fast_Mode_t; 72 73 typedef struct Adpcc_basic_params_select_s { 74 int iso; 75 // mode 0x0000 76 unsigned char stage1_enable; 77 unsigned char grayscale_mode; 78 unsigned char enable; 79 80 // output_mode 0x0004 81 unsigned char sw_rk_out_sel; 82 unsigned char sw_dpcc_output_sel; 83 unsigned char stage1_rb_3x3; 84 unsigned char stage1_g_3x3; 85 unsigned char stage1_incl_rb_center; 86 unsigned char stage1_incl_green_center; 87 88 // set_use 0x0008 89 unsigned char stage1_use_fix_set; 90 unsigned char stage1_use_set_3; 91 unsigned char stage1_use_set_2; 92 unsigned char stage1_use_set_1; 93 94 // methods_set_1 0x000c 95 unsigned char sw_rk_red_blue1_en; 96 unsigned char rg_red_blue1_enable; 97 unsigned char rnd_red_blue1_enable; 98 unsigned char ro_red_blue1_enable; 99 unsigned char lc_red_blue1_enable; 100 unsigned char pg_red_blue1_enable; 101 unsigned char sw_rk_green1_en; 102 unsigned char rg_green1_enable; 103 unsigned char rnd_green1_enable; 104 unsigned char ro_green1_enable; 105 unsigned char lc_green1_enable; 106 unsigned char pg_green1_enable; 107 108 // methods_set_2 0x0010 109 unsigned char sw_rk_red_blue2_en; 110 unsigned char rg_red_blue2_enable; 111 unsigned char rnd_red_blue2_enable; 112 unsigned char ro_red_blue2_enable; 113 unsigned char lc_red_blue2_enable; 114 unsigned char pg_red_blue2_enable; 115 unsigned char sw_rk_green2_en; 116 unsigned char rg_green2_enable; 117 unsigned char rnd_green2_enable; 118 unsigned char ro_green2_enable; 119 unsigned char lc_green2_enable; 120 unsigned char pg_green2_enable; 121 122 // methods_set_3 0x0014 123 unsigned char sw_rk_red_blue3_en; 124 unsigned char rg_red_blue3_enable; 125 unsigned char rnd_red_blue3_enable; 126 unsigned char ro_red_blue3_enable; 127 unsigned char lc_red_blue3_enable; 128 unsigned char pg_red_blue3_enable; 129 unsigned char sw_rk_green3_en; 130 unsigned char rg_green3_enable; 131 unsigned char rnd_green3_enable; 132 unsigned char ro_green3_enable; 133 unsigned char lc_green3_enable; 134 unsigned char pg_green3_enable; 135 136 // line_thresh_1 0x0018 137 unsigned char sw_mindis1_rb; 138 unsigned char sw_mindis1_g; 139 unsigned char line_thr_1_rb; 140 unsigned char line_thr_1_g; 141 142 // line_mad_fac_1 0x001c 143 unsigned char sw_dis_scale_min1; 144 unsigned char sw_dis_scale_max1; 145 unsigned char line_mad_fac_1_rb; 146 unsigned char line_mad_fac_1_g; 147 148 // pg_fac_1 0x0020 149 unsigned char pg_fac_1_rb; 150 unsigned char pg_fac_1_g; 151 152 // rnd_thresh_1 0x0024 153 unsigned char rnd_thr_1_rb; 154 unsigned char rnd_thr_1_g; 155 156 // rg_fac_1 0x0028 157 unsigned char rg_fac_1_rb; 158 unsigned char rg_fac_1_g; 159 160 // line_thresh_2 0x002c 161 unsigned char sw_mindis2_rb; 162 unsigned char sw_mindis2_g; 163 unsigned char line_thr_2_rb; 164 unsigned char line_thr_2_g; 165 166 // line_mad_fac_2 0x0030 167 unsigned char sw_dis_scale_min2; 168 unsigned char sw_dis_scale_max2; 169 unsigned char line_mad_fac_2_rb; 170 unsigned char line_mad_fac_2_g; 171 172 // pg_fac_2 0x0034 173 unsigned char pg_fac_2_rb; 174 unsigned char pg_fac_2_g; 175 176 // rnd_thresh_2 0x0038 177 unsigned char rnd_thr_2_rb; 178 unsigned char rnd_thr_2_g; 179 180 // rg_fac_2 0x003c 181 unsigned char rg_fac_2_rb; 182 unsigned char rg_fac_2_g; 183 184 // line_thresh_3 0x0040 185 unsigned char sw_mindis3_rb; 186 unsigned char sw_mindis3_g; 187 unsigned char line_thr_3_rb; 188 unsigned char line_thr_3_g; 189 190 // line_mad_fac_3 0x0044 191 unsigned char sw_dis_scale_min3; 192 unsigned char sw_dis_scale_max3; 193 unsigned char line_mad_fac_3_rb; 194 unsigned char line_mad_fac_3_g; 195 196 // pg_fac_3 0x0048 197 unsigned char pg_fac_3_rb; 198 unsigned char pg_fac_3_g; 199 200 // rnd_thresh_3 0x004c 201 unsigned char rnd_thr_3_rb; 202 unsigned char rnd_thr_3_g; 203 204 // rg_fac_3 0x0050 205 unsigned char rg_fac_3_rb; 206 unsigned char rg_fac_3_g; 207 208 // ro_limits 0x0054 209 unsigned char ro_lim_3_rb; 210 unsigned char ro_lim_3_g; 211 unsigned char ro_lim_2_rb; 212 unsigned char ro_lim_2_g; 213 unsigned char ro_lim_1_rb; 214 unsigned char ro_lim_1_g; 215 216 // rnd_offs 0x0058 217 unsigned char rnd_offs_3_rb; 218 unsigned char rnd_offs_3_g; 219 unsigned char rnd_offs_2_rb; 220 unsigned char rnd_offs_2_g; 221 unsigned char rnd_offs_1_rb; 222 unsigned char rnd_offs_1_g; 223 } Adpcc_basic_params_select_t; 224 225 typedef struct Adpcc_basic_params_s { 226 Adpcc_basic_params_select_t arBasic[DPCC_MAX_ISO_LEVEL]; 227 } Adpcc_basic_params_t; 228 229 typedef struct Adpcc_basic_cfg_params_s { 230 // mode 0x0000 231 // M4_NUMBER_DESC("stage1_enable", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 232 unsigned char stage1_enable; 233 // M4_NUMBER_DESC("grayscale_mode", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 234 unsigned char grayscale_mode; 235 // M4_NUMBER_DESC("enable", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 236 unsigned char enable; 237 238 // output_mode 0x0004 239 // M4_NUMBER_DESC("sw_rk_out_sel", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 240 unsigned char sw_rk_out_sel; 241 // M4_NUMBER_DESC("sw_dpcc_output_sel", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 242 unsigned char sw_dpcc_output_sel; 243 // M4_NUMBER_DESC("stage1_rb_3x3", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 244 unsigned char stage1_rb_3x3; 245 // M4_NUMBER_DESC("stage1_g_3x3", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 246 unsigned char stage1_g_3x3; 247 // M4_NUMBER_DESC("stage1_incl_rb_center", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 248 unsigned char stage1_incl_rb_center; 249 // M4_NUMBER_DESC("stage1_incl_green_center", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 250 unsigned char stage1_incl_green_center; 251 252 // set_use 0x0008 253 // M4_NUMBER_DESC("stage1_use_fix_set", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 254 unsigned char stage1_use_fix_set; 255 // M4_NUMBER_DESC("stage1_use_set_3", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 256 unsigned char stage1_use_set_3; 257 // M4_NUMBER_DESC("stage1_use_set_2", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 258 unsigned char stage1_use_set_2; 259 // M4_NUMBER_DESC("stage1_use_set_1", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 260 unsigned char stage1_use_set_1; 261 262 // methods_set_1 0x000c 263 // M4_NUMBER_DESC("sw_rk_red_blue1_en", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 264 unsigned char sw_rk_red_blue1_en; 265 // M4_NUMBER_DESC("rg_red_blue1_enable", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 266 unsigned char rg_red_blue1_enable; 267 // M4_NUMBER_DESC("rnd_red_blue1_enable", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 268 unsigned char rnd_red_blue1_enable; 269 // M4_NUMBER_DESC("ro_red_blue1_enable", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 270 unsigned char ro_red_blue1_enable; 271 // M4_NUMBER_DESC("lc_red_blue1_enable", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 272 unsigned char lc_red_blue1_enable; 273 // M4_NUMBER_DESC("pg_red_blue1_enable", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 274 unsigned char pg_red_blue1_enable; 275 // M4_NUMBER_DESC("sw_rk_green1_en", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 276 unsigned char sw_rk_green1_en; 277 // M4_NUMBER_DESC("rg_green1_enable", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 278 unsigned char rg_green1_enable; 279 // M4_NUMBER_DESC("rnd_green1_enable", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 280 unsigned char rnd_green1_enable; 281 // M4_NUMBER_DESC("ro_green1_enable", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 282 unsigned char ro_green1_enable; 283 // M4_NUMBER_DESC("lc_green1_enable", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 284 unsigned char lc_green1_enable; 285 // M4_NUMBER_DESC("pg_green1_enable", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 286 unsigned char pg_green1_enable; 287 288 // methods_set_2 0x0010 289 // M4_NUMBER_DESC("sw_rk_red_blue2_en", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 290 unsigned char sw_rk_red_blue2_en; 291 // M4_NUMBER_DESC("rg_red_blue2_enable", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 292 unsigned char rg_red_blue2_enable; 293 // M4_NUMBER_DESC("rnd_red_blue2_enable", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 294 unsigned char rnd_red_blue2_enable; 295 // M4_NUMBER_DESC("ro_red_blue2_enable", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 296 unsigned char ro_red_blue2_enable; 297 // M4_NUMBER_DESC("lc_red_blue2_enable", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 298 unsigned char lc_red_blue2_enable; 299 // M4_NUMBER_DESC("pg_red_blue2_enable", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 300 unsigned char pg_red_blue2_enable; 301 // M4_NUMBER_DESC("sw_rk_green2_en", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 302 unsigned char sw_rk_green2_en; 303 // M4_NUMBER_DESC("rg_green2_enable", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 304 unsigned char rg_green2_enable; 305 // M4_NUMBER_DESC("rnd_green2_enable", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 306 unsigned char rnd_green2_enable; 307 // M4_NUMBER_DESC("ro_green2_enable", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 308 unsigned char ro_green2_enable; 309 // M4_NUMBER_DESC("lc_green2_enable", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 310 unsigned char lc_green2_enable; 311 // M4_NUMBER_DESC("pg_green2_enable", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 312 unsigned char pg_green2_enable; 313 314 // methods_set_3 0x0014 315 // M4_NUMBER_DESC("sw_rk_red_blue3_en", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 316 unsigned char sw_rk_red_blue3_en; 317 // M4_NUMBER_DESC("rg_red_blue3_enable", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 318 unsigned char rg_red_blue3_enable; 319 // M4_NUMBER_DESC("rnd_red_blue3_enable", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 320 unsigned char rnd_red_blue3_enable; 321 // M4_NUMBER_DESC("ro_red_blue3_enable", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 322 unsigned char ro_red_blue3_enable; 323 // M4_NUMBER_DESC("lc_red_blue3_enable", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 324 unsigned char lc_red_blue3_enable; 325 // M4_NUMBER_DESC("pg_red_blue3_enable", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 326 unsigned char pg_red_blue3_enable; 327 // M4_NUMBER_DESC("sw_rk_green3_en", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 328 unsigned char sw_rk_green3_en; 329 // M4_NUMBER_DESC("rg_green3_enable", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 330 unsigned char rg_green3_enable; 331 // M4_NUMBER_DESC("rnd_green3_enable", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 332 unsigned char rnd_green3_enable; 333 // M4_NUMBER_DESC("ro_green3_enable", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 334 unsigned char ro_green3_enable; 335 // M4_NUMBER_DESC("lc_green3_enable", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 336 unsigned char lc_green3_enable; 337 // M4_NUMBER_DESC("pg_green3_enable", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 338 unsigned char pg_green3_enable; 339 340 // line_thresh_1 0x0018 341 // M4_NUMBER_DESC("sw_mindis1_rb", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 342 unsigned char sw_mindis1_rb; 343 // M4_NUMBER_DESC("sw_mindis1_g", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 344 unsigned char sw_mindis1_g; 345 // M4_NUMBER_DESC("line_thr_1_rb", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 346 unsigned char line_thr_1_rb; 347 // M4_NUMBER_DESC("line_thr_1_g", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 348 unsigned char line_thr_1_g; 349 350 // line_mad_fac_1 0x001c 351 // M4_NUMBER_DESC("sw_dis_scale_min1", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 352 unsigned char sw_dis_scale_min1; 353 // M4_NUMBER_DESC("sw_dis_scale_max1", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 354 unsigned char sw_dis_scale_max1; 355 // M4_NUMBER_DESC("line_mad_fac_1_rb", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 356 unsigned char line_mad_fac_1_rb; 357 // M4_NUMBER_DESC("line_mad_fac_1_g", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 358 unsigned char line_mad_fac_1_g; 359 360 // pg_fac_1 0x0020 361 // M4_NUMBER_DESC("pg_fac_1_rb", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 362 unsigned char pg_fac_1_rb; 363 // M4_NUMBER_DESC("pg_fac_1_g", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 364 unsigned char pg_fac_1_g; 365 366 // rnd_thresh_1 0x0024 367 // M4_NUMBER_DESC("rnd_thr_1_rb", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 368 unsigned char rnd_thr_1_rb; 369 // M4_NUMBER_DESC("rnd_thr_1_g", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 370 unsigned char rnd_thr_1_g; 371 372 // rg_fac_1 0x0028 373 // M4_NUMBER_DESC("rg_fac_1_rb", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 374 unsigned char rg_fac_1_rb; 375 // M4_NUMBER_DESC("rg_fac_1_g", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 376 unsigned char rg_fac_1_g; 377 378 // line_thresh_2 0x002c 379 // M4_NUMBER_DESC("sw_mindis2_rb", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 380 unsigned char sw_mindis2_rb; 381 // M4_NUMBER_DESC("sw_mindis2_g", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 382 unsigned char sw_mindis2_g; 383 // M4_NUMBER_DESC("line_thr_2_rb", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 384 unsigned char line_thr_2_rb; 385 // M4_NUMBER_DESC("line_thr_2_g", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 386 unsigned char line_thr_2_g; 387 388 // line_mad_fac_2 0x0030 389 // M4_NUMBER_DESC("sw_dis_scale_min2", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 390 unsigned char sw_dis_scale_min2; 391 // M4_NUMBER_DESC("sw_dis_scale_max2", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 392 unsigned char sw_dis_scale_max2; 393 // M4_NUMBER_DESC("line_mad_fac_2_rb", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 394 unsigned char line_mad_fac_2_rb; 395 // M4_NUMBER_DESC("line_mad_fac_2_g", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 396 unsigned char line_mad_fac_2_g; 397 398 // pg_fac_2 0x0034 399 // M4_NUMBER_DESC("pg_fac_2_rb", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 400 unsigned char pg_fac_2_rb; 401 // M4_NUMBER_DESC("pg_fac_2_g", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 402 unsigned char pg_fac_2_g; 403 404 // rnd_thresh_2 0x0038 405 // M4_NUMBER_DESC("rnd_thr_2_rb", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 406 unsigned char rnd_thr_2_rb; 407 // M4_NUMBER_DESC("rnd_thr_2_g", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 408 unsigned char rnd_thr_2_g; 409 410 // rg_fac_2 0x003c 411 // M4_NUMBER_DESC("rg_fac_2_rb", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 412 unsigned char rg_fac_2_rb; 413 // M4_NUMBER_DESC("rg_fac_2_g", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 414 unsigned char rg_fac_2_g; 415 416 // line_thresh_3 0x0040 417 // M4_NUMBER_DESC("sw_mindis3_rb", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 418 unsigned char sw_mindis3_rb; 419 // M4_NUMBER_DESC("sw_mindis3_g", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 420 unsigned char sw_mindis3_g; 421 // M4_NUMBER_DESC("line_thr_3_rb", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 422 unsigned char line_thr_3_rb; 423 // M4_NUMBER_DESC("line_thr_3_g", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 424 unsigned char line_thr_3_g; 425 426 // line_mad_fac_3 0x0044 427 // M4_NUMBER_DESC("sw_dis_scale_min3", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 428 unsigned char sw_dis_scale_min3; 429 // M4_NUMBER_DESC("sw_dis_scale_max3", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 430 unsigned char sw_dis_scale_max3; 431 // M4_NUMBER_DESC("line_mad_fac_3_rb", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 432 unsigned char line_mad_fac_3_rb; 433 // M4_NUMBER_DESC("line_mad_fac_3_g", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 434 unsigned char line_mad_fac_3_g; 435 436 // pg_fac_3 0x0048 437 // M4_NUMBER_DESC("pg_fac_3_rb", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 438 unsigned char pg_fac_3_rb; 439 // M4_NUMBER_DESC("pg_fac_3_g", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 440 unsigned char pg_fac_3_g; 441 442 // rnd_thresh_3 0x004c 443 // M4_NUMBER_DESC("rnd_thr_3_rb", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 444 unsigned char rnd_thr_3_rb; 445 // M4_NUMBER_DESC("rnd_thr_3_g", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 446 unsigned char rnd_thr_3_g; 447 448 // rg_fac_3 0x0050 449 // M4_NUMBER_DESC("rg_fac_3_rb", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 450 unsigned char rg_fac_3_rb; 451 // M4_NUMBER_DESC("rg_fac_3_g", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 452 unsigned char rg_fac_3_g; 453 454 // ro_limits 0x0054 455 // M4_NUMBER_DESC("ro_lim_3_rb", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 456 unsigned char ro_lim_3_rb; 457 // M4_NUMBER_DESC("ro_lim_3_g", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 458 unsigned char ro_lim_3_g; 459 // M4_NUMBER_DESC("ro_lim_2_rb", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 460 unsigned char ro_lim_2_rb; 461 // M4_NUMBER_DESC("ro_lim_2_g", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 462 unsigned char ro_lim_2_g; 463 // M4_NUMBER_DESC("ro_lim_1_rb", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 464 unsigned char ro_lim_1_rb; 465 // M4_NUMBER_DESC("ro_lim_1_g", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 466 unsigned char ro_lim_1_g; 467 468 // rnd_offs 0x0058 469 // M4_NUMBER_DESC("rnd_offs_3_rb", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 470 unsigned char rnd_offs_3_rb; 471 // M4_NUMBER_DESC("rnd_offs_3_g", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 472 unsigned char rnd_offs_3_g; 473 // M4_NUMBER_DESC("rnd_offs_2_rb", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 474 unsigned char rnd_offs_2_rb; 475 // M4_NUMBER_DESC("rnd_offs_2_g", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 476 unsigned char rnd_offs_2_g; 477 // M4_NUMBER_DESC("rnd_offs_1_rb", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 478 unsigned char rnd_offs_1_rb; 479 // M4_NUMBER_DESC("rnd_offs_1_g", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 480 unsigned char rnd_offs_1_g; 481 } Adpcc_basic_cfg_params_t; 482 483 typedef struct Adpcc_bpt_params_s { 484 // bpt_ctrl 0x005c 485 // M4_NUMBER_DESC("bpt_rb_3x3", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 486 unsigned char bpt_rb_3x3; 487 // M4_NUMBER_DESC("bpt_g_3x3", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 488 unsigned char bpt_g_3x3; 489 // M4_NUMBER_DESC("bpt_incl_rb_center", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 490 unsigned char bpt_incl_rb_center; 491 // M4_NUMBER_DESC("bpt_incl_green_center", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 492 unsigned char bpt_incl_green_center; 493 // M4_NUMBER_DESC("bpt_use_fix_set", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 494 unsigned char bpt_use_fix_set; 495 // M4_NUMBER_DESC("bpt_use_set_3", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 496 unsigned char bpt_use_set_3; 497 // M4_NUMBER_DESC("bpt_use_set_2", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 498 unsigned char bpt_use_set_2; 499 // M4_NUMBER_DESC("bpt_use_set_1", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 500 unsigned char bpt_use_set_1; 501 // M4_NUMBER_DESC("bpt_cor_en", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 502 unsigned char bpt_cor_en; 503 // M4_NUMBER_DESC("bpt_det_en", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 504 unsigned char bpt_det_en; 505 506 // bpt_number 0x0060 507 // M4_NUMBER_DESC("bp_number", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 508 uint16_t bp_number; 509 510 // bpt_addr 0x0064 511 // M4_NUMBER_DESC("bp_table_addr", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 512 uint16_t bp_table_addr; 513 514 // bpt_data 0x0068 515 // M4_NUMBER_DESC("bpt_v_addr", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 516 uint16_t bpt_v_addr; 517 // M4_NUMBER_DESC("bpt_h_addr", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 518 uint16_t bpt_h_addr; 519 520 // bp_cnt 0x006c 521 // M4_NUMBER_DESC("bp_cnt", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 522 unsigned int bp_cnt; 523 } Adpcc_bpt_params_t; 524 525 typedef struct dpcc_pdaf_point_s { 526 // M4_NUMBER_DESC("y", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 527 unsigned char y; 528 // M4_NUMBER_DESC("x", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 529 unsigned char x; 530 } dpcc_pdaf_point_t; 531 532 typedef struct Adpcc_pdaf_params_s { 533 // pdaf_en 0x0070 534 // M4_NUMBER_DESC("sw_pdaf_en", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 535 unsigned char sw_pdaf_en; 536 537 // pdaf_point_en 0x0074 538 // M4_ARRAY_DESC("pdaf_point_en", "u8", M4_SIZE(1,16), M4_RANGE(0,255), "0", M4_DIGIT(0), M4_DYNAMIC(0)) 539 unsigned char pdaf_point_en[DPCC_PDAF_POINT_NUM]; 540 541 // pdaf_offset 0x0078 542 // M4_NUMBER_DESC("pdaf_offsety", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 543 uint16_t pdaf_offsety; 544 // M4_NUMBER_DESC("pdaf_offsetx", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 545 uint16_t pdaf_offsetx; 546 547 // pdaf_wrap 0x007c 548 // M4_NUMBER_DESC("pdaf_wrapy", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 549 unsigned char pdaf_wrapy; 550 // M4_NUMBER_DESC("pdaf_wrapx", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 551 unsigned char pdaf_wrapx; 552 553 // pdaf_scope 0x0080 554 // M4_NUMBER_DESC("pdaf_wrapy_num", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 555 uint16_t pdaf_wrapy_num; 556 // M4_NUMBER_DESC("pdaf_wrapx_num", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 557 uint16_t pdaf_wrapx_num; 558 559 // pdaf_point_0 0x0084 560 // M4_STRUCT_LIST_DESC("point", M4_SIZE(1,16), "normal_ui_style") 561 dpcc_pdaf_point_t point[DPCC_PDAF_POINT_NUM]; 562 563 // pdaf_forward_med 0x00a4 564 // M4_NUMBER_DESC("pdaf_forward_med", "u8", M4_RANGE(0,255), "0", M4_DIGIT(0)) 565 unsigned char pdaf_forward_med; 566 } Adpcc_pdaf_params_t; 567 568 typedef struct Adpcc_Auto_Attr_s { 569 Adpcc_basic_params_t stBasicParams; 570 Adpcc_bpt_params_t stBptParams; 571 Adpcc_pdaf_params_t stPdafParams; 572 CalibDb_Dpcc_Fast_Mode_t stFastMode; 573 CalibDb_Dpcc_Sensor_t stSensorDpcc; 574 } Adpcc_Auto_Attr_t; 575 576 typedef struct Adpcc_fast_mode_attr_s { 577 // M4_BOOL_DESC("fast_mode_en", "0") 578 bool fast_mode_en; 579 // M4_BOOL_DESC("fast_mode_single_en", "0") 580 bool fast_mode_single_en; 581 // M4_NUMBER_DESC("fast_mode_single_level", "s32", M4_RANGE(0,255), "0", M4_DIGIT(0)) 582 int fast_mode_single_level; 583 // M4_BOOL_DESC("fast_mode_double_en", "0") 584 bool fast_mode_double_en; 585 // M4_NUMBER_DESC("fast_mode_double_level", "s32", M4_RANGE(0,255), "0", M4_DIGIT(0)) 586 int fast_mode_double_level; 587 // M4_BOOL_DESC("fast_mode_triple_en", "0") 588 bool fast_mode_triple_en; 589 // M4_NUMBER_DESC("fast_mode_triple_level", "f32", M4_RANGE(0,255), "0", M4_DIGIT(0)) 590 int fast_mode_triple_level; 591 } Adpcc_fast_mode_attr_t; 592 593 typedef struct Adpcc_onfly_cfg_s { 594 // M4_ENUM_DESC("mode", "Adpcc_onfly_mode_t", "ADPCC_ONFLY_MODE_FAST"); 595 Adpcc_onfly_mode_t mode; // expert or fast mode 596 // M4_STRUCT_DESC("fast_mode", "normal_ui_style") 597 Adpcc_fast_mode_attr_t fast_mode; 598 // M4_STRUCT_DESC("expert_mode", "normal_ui_style") 599 Adpcc_basic_cfg_params_t expert_mode; 600 } Adpcc_onfly_cfg_t; 601 602 typedef struct Adpcc_sensor_dpcc_attr_s { 603 // M4_BOOL_DESC("en", "0") 604 bool en; 605 // M4_NUMBER_DESC("max_level", "s16", M4_RANGE(0,32767), "0", M4_DIGIT(0)) 606 int max_level; 607 // M4_NUMBER_DESC("single_level", "s16", M4_RANGE(0,32767), "0", M4_DIGIT(0)) 608 int single_level; 609 // M4_NUMBER_DESC("double_level", "s16", M4_RANGE(0,32767), "0", M4_DIGIT(0)) 610 int double_level; 611 } Adpcc_sensor_dpcc_attr_t; 612 613 typedef struct Adpcc_Manual_Attr_s { 614 // M4_NUMBER_DESC("enable", "u8", M4_RANGE(0,1), "0", M4_DIGIT(0)) 615 unsigned char enable; 616 // M4_STRUCT_DESC("stOnfly", "normal_ui_style") 617 Adpcc_onfly_cfg_t stOnfly; 618 // M4_STRUCT_DESC("stBpt", "normal_ui_style") 619 Adpcc_bpt_params_t stBpt; 620 // M4_STRUCT_DESC("stPdaf", "normal_ui_style") 621 Adpcc_pdaf_params_t stPdaf; 622 // M4_STRUCT_DESC("stSensorDpcc", "normal_ui_style") 623 Adpcc_sensor_dpcc_attr_t stSensorDpcc; 624 } Adpcc_Manual_Attr_t; 625 626 typedef struct rk_aiq_dpcc_attrib_V20_s { 627 AdpccOPMode_t eMode; 628 Adpcc_Auto_Attr_t stAuto; 629 Adpcc_Manual_Attr_t stManual; 630 rk_aiq_uapi_sync_t sync; 631 } rk_aiq_dpcc_attrib_V20_t; 632 633 #endif /*__RK_AIQ_TYPES_ADPCC_EXT_H__*/ 634