1 /*
2 * Copyright (c) 2025, Mediatek Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <stddef.h>
8 #include <stdio.h>
9 #include <string.h>
10
11 #include <common/debug.h>
12 #include <lib/mmio.h>
13 #include <plat/common/platform.h>
14 #include <platform_def.h>
15
16 #include <drivers/spmi_api.h>
17 #include <lib/pm/mtk_pm.h>
18 #include <mt_plat_spm_setting.h>
19 #include <mt_spm.h>
20 #include <mt_spm_internal.h>
21 #include <mt_spm_reg.h>
22 #include <pmic_wrap/inc/mt_spm_pmic_wrap.h>
23
24 #define VCORE_BASE_UV 0
25 #ifdef MT8196_VCORE_SUPPORT
26 #define VCORE_STEP_UV 6250
27 #else
28 #define VCORE_STEP_UV 5000
29 #endif
30
31 #define VCORE_UV_TO_PMIC(uv) /* pmic >= uv */ \
32 ((((uv) - VCORE_BASE_UV) + (VCORE_STEP_UV - 1)) / VCORE_STEP_UV)
33 #define VCORE_PMIC_TO_UV(pmic) \
34 (((pmic) * VCORE_STEP_UV) + VCORE_BASE_UV)
35
36 #define VSRAM_BASE_UV 0
37 #define VSRAM_STEP_UV 6250
38
39 #define VSRAM_UV_TO_PMIC(uv) /* pmic >= uv */ \
40 ((((uv) - VSRAM_BASE_UV) + (VSRAM_STEP_UV - 1)) / VSRAM_STEP_UV)
41 #define VSRAM_PMIC_TO_UV(pmic) \
42 (((pmic) * VSRAM_STEP_UV) + VSRAM_BASE_UV)
43
44 static int spm_dvfs_init_done;
45
46 static struct pwr_ctrl vcorefs_ctrl = {
47 .wake_src = R12_CPU_WAKEUP,
48
49 /* default VCORE DVFS is disabled */
50 .pcm_flags = (SPM_FLAG_RUN_COMMON_SCENARIO |
51 SPM_FLAG_DISABLE_VCORE_DVS |
52 SPM_FLAG_DISABLE_DDR_DFS |
53 SPM_FLAG_DISABLE_EMI_DFS | SPM_FLAG_DISABLE_BUS_DFS),
54
55 /* SPM_SRC_REQ */
56 .reg_spm_adsp_mailbox_req = 0,
57 .reg_spm_apsrc_req = 0,
58 .reg_spm_ddren_req = 0,
59 .reg_spm_dvfs_req = 0,
60 .reg_spm_emi_req = 0,
61 .reg_spm_f26m_req = 0,
62 .reg_spm_infra_req = 0,
63 .reg_spm_pmic_req = 0,
64 .reg_spm_scp_mailbox_req = 0,
65 .reg_spm_sspm_mailbox_req = 0,
66 .reg_spm_sw_mailbox_req = 0,
67 .reg_spm_vcore_req = 1,
68 .reg_spm_vrf18_req = 0,
69 .adsp_mailbox_state = 0,
70 .apsrc_state = 0,
71 .ddren_state = 0,
72 .dvfs_state = 0,
73 .emi_state = 0,
74 .f26m_state = 0,
75 .infra_state = 0,
76 .pmic_state = 0,
77 .scp_mailbox_state = 0,
78 .sspm_mailbox_state = 0,
79 .sw_mailbox_state = 0,
80 .vcore_state = 0,
81 .vrf18_state = 0,
82
83 /* SPM_SRC_MASK_0 */
84 .reg_apifr_apsrc_rmb = 0,
85 .reg_apifr_ddren_rmb = 0,
86 .reg_apifr_emi_rmb = 0,
87 .reg_apifr_infra_rmb = 0,
88 .reg_apifr_pmic_rmb = 0,
89 .reg_apifr_srcclkena_mb = 0,
90 .reg_apifr_vcore_rmb = 0,
91 .reg_apifr_vrf18_rmb = 0,
92 .reg_apu_apsrc_rmb = 1,
93 .reg_apu_ddren_rmb = 0,
94 .reg_apu_emi_rmb = 1,
95 .reg_apu_infra_rmb = 1,
96 .reg_apu_pmic_rmb = 1,
97 .reg_apu_srcclkena_mb = 1,
98 .reg_apu_vcore_rmb = 1,
99 .reg_apu_vrf18_rmb = 1,
100 .reg_audio_apsrc_rmb = 1,
101 .reg_audio_ddren_rmb = 0,
102 .reg_audio_emi_rmb = 1,
103 .reg_audio_infra_rmb = 1,
104 .reg_audio_pmic_rmb = 1,
105 .reg_audio_srcclkena_mb = 1,
106 .reg_audio_vcore_rmb = 1,
107 .reg_audio_vrf18_rmb = 1,
108
109 /* SPM_SRC_MASK_1 */
110 .reg_audio_dsp_apsrc_rmb = 1,
111 .reg_audio_dsp_ddren_rmb = 0,
112 .reg_audio_dsp_emi_rmb = 1,
113 .reg_audio_dsp_infra_rmb = 1,
114 .reg_audio_dsp_pmic_rmb = 1,
115 .reg_audio_dsp_srcclkena_mb = 1,
116 .reg_audio_dsp_vcore_rmb = 1,
117 .reg_audio_dsp_vrf18_rmb = 1,
118 .reg_cam_apsrc_rmb = 0,
119 .reg_cam_ddren_rmb = 0,
120 .reg_cam_emi_rmb = 0,
121 .reg_cam_infra_rmb = 0,
122 .reg_cam_pmic_rmb = 0,
123 .reg_cam_srcclkena_mb = 0,
124 .reg_cam_vrf18_rmb = 0,
125 .reg_ccif_apsrc_rmb = 0xfff,
126
127 /* SPM_SRC_MASK_2 */
128 .reg_ccif_emi_rmb = 0xfff,
129 .reg_ccif_infra_rmb = 0xfff,
130
131 /* SPM_SRC_MASK_3 */
132 .reg_ccif_pmic_rmb = 0xfff,
133 .reg_ccif_srcclkena_mb = 0xfff,
134
135 /* SPM_SRC_MASK_4 */
136 .reg_ccif_vcore_rmb = 0xfff,
137 .reg_ccif_vrf18_rmb = 0xfff,
138 .reg_ccu_apsrc_rmb = 0,
139 .reg_ccu_ddren_rmb = 0,
140 .reg_ccu_emi_rmb = 0,
141 .reg_ccu_infra_rmb = 0,
142 .reg_ccu_pmic_rmb = 0,
143 .reg_ccu_srcclkena_mb = 0,
144 .reg_ccu_vrf18_rmb = 0,
145 .reg_cg_check_apsrc_rmb = 0,
146
147 /* SPM_SRC_MASK_5 */
148 .reg_cg_check_ddren_rmb = 0,
149 .reg_cg_check_emi_rmb = 0,
150 .reg_cg_check_infra_rmb = 0,
151 .reg_cg_check_pmic_rmb = 0,
152 .reg_cg_check_srcclkena_mb = 0,
153 .reg_cg_check_vcore_rmb = 1,
154 .reg_cg_check_vrf18_rmb = 0,
155 .reg_cksys_apsrc_rmb = 1,
156 .reg_cksys_ddren_rmb = 0,
157 .reg_cksys_emi_rmb = 1,
158 .reg_cksys_infra_rmb = 1,
159 .reg_cksys_pmic_rmb = 1,
160 .reg_cksys_srcclkena_mb = 1,
161 .reg_cksys_vcore_rmb = 1,
162 .reg_cksys_vrf18_rmb = 1,
163 .reg_cksys_1_apsrc_rmb = 1,
164 .reg_cksys_1_ddren_rmb = 0,
165 .reg_cksys_1_emi_rmb = 1,
166 .reg_cksys_1_infra_rmb = 1,
167 .reg_cksys_1_pmic_rmb = 1,
168 .reg_cksys_1_srcclkena_mb = 1,
169 .reg_cksys_1_vcore_rmb = 1,
170 .reg_cksys_1_vrf18_rmb = 1,
171
172 /* SPM_SRC_MASK_6 */
173 .reg_cksys_2_apsrc_rmb = 1,
174 .reg_cksys_2_ddren_rmb = 0,
175 .reg_cksys_2_emi_rmb = 1,
176 .reg_cksys_2_infra_rmb = 1,
177 .reg_cksys_2_pmic_rmb = 1,
178 .reg_cksys_2_srcclkena_mb = 1,
179 .reg_cksys_2_vcore_rmb = 1,
180 .reg_cksys_2_vrf18_rmb = 1,
181 .reg_conn_apsrc_rmb = 1,
182 .reg_conn_ddren_rmb = 0,
183 .reg_conn_emi_rmb = 1,
184 .reg_conn_infra_rmb = 1,
185 .reg_conn_pmic_rmb = 1,
186 .reg_conn_srcclkena_mb = 1,
187 .reg_conn_srcclkenb_mb = 1,
188 .reg_conn_vcore_rmb = 1,
189 .reg_conn_vrf18_rmb = 1,
190 .reg_corecfg_apsrc_rmb = 0,
191 .reg_corecfg_ddren_rmb = 0,
192 .reg_corecfg_emi_rmb = 0,
193 .reg_corecfg_infra_rmb = 0,
194 .reg_corecfg_pmic_rmb = 0,
195 .reg_corecfg_srcclkena_mb = 0,
196 .reg_corecfg_vcore_rmb = 0,
197 .reg_corecfg_vrf18_rmb = 0,
198
199 /* SPM_SRC_MASK_7 */
200 .reg_cpueb_apsrc_rmb = 1,
201 .reg_cpueb_ddren_rmb = 0,
202 .reg_cpueb_emi_rmb = 1,
203 .reg_cpueb_infra_rmb = 1,
204 .reg_cpueb_pmic_rmb = 1,
205 .reg_cpueb_srcclkena_mb = 1,
206 .reg_cpueb_vcore_rmb = 1,
207 .reg_cpueb_vrf18_rmb = 1,
208 .reg_disp0_apsrc_rmb = 0,
209 .reg_disp0_ddren_rmb = 0,
210 .reg_disp0_emi_rmb = 0,
211 .reg_disp0_infra_rmb = 0,
212 .reg_disp0_pmic_rmb = 0,
213 .reg_disp0_srcclkena_mb = 0,
214 .reg_disp0_vrf18_rmb = 0,
215 .reg_disp1_apsrc_rmb = 0,
216 .reg_disp1_ddren_rmb = 0,
217 .reg_disp1_emi_rmb = 0,
218 .reg_disp1_infra_rmb = 0,
219 .reg_disp1_pmic_rmb = 0,
220 .reg_disp1_srcclkena_mb = 0,
221 .reg_disp1_vrf18_rmb = 0,
222 .reg_dpm_apsrc_rmb = 0xf,
223 .reg_dpm_ddren_rmb = 0xf,
224
225 /* SPM_SRC_MASK_8 */
226 .reg_dpm_emi_rmb = 0xf,
227 .reg_dpm_infra_rmb = 0xf,
228 .reg_dpm_pmic_rmb = 0xf,
229 .reg_dpm_srcclkena_mb = 0xf,
230 .reg_dpm_vcore_rmb = 0xf,
231 .reg_dpm_vrf18_rmb = 0xf,
232 .reg_dpmaif_apsrc_rmb = 1,
233 .reg_dpmaif_ddren_rmb = 0,
234 .reg_dpmaif_emi_rmb = 1,
235 .reg_dpmaif_infra_rmb = 1,
236 .reg_dpmaif_pmic_rmb = 1,
237 .reg_dpmaif_srcclkena_mb = 1,
238 .reg_dpmaif_vcore_rmb = 1,
239 .reg_dpmaif_vrf18_rmb = 1,
240
241 /* SPM_SRC_MASK_9 */
242 .reg_dvfsrc_level_rmb = 1,
243 .reg_emisys_apsrc_rmb = 0,
244 .reg_emisys_ddren_rmb = 0,
245 .reg_emisys_emi_rmb = 0,
246 .reg_emisys_infra_rmb = 0,
247 .reg_emisys_pmic_rmb = 0,
248 .reg_emisys_srcclkena_mb = 0,
249 .reg_emisys_vcore_rmb = 0,
250 .reg_emisys_vrf18_rmb = 0,
251 .reg_gce_apsrc_rmb = 0,
252 .reg_gce_ddren_rmb = 0,
253 .reg_gce_emi_rmb = 0,
254 .reg_gce_infra_rmb = 0,
255 .reg_gce_pmic_rmb = 0,
256 .reg_gce_srcclkena_mb = 0,
257 .reg_gce_vcore_rmb = 0,
258 .reg_gce_vrf18_rmb = 0,
259 .reg_gpueb_apsrc_rmb = 1,
260 .reg_gpueb_ddren_rmb = 0,
261 .reg_gpueb_emi_rmb = 1,
262 .reg_gpueb_infra_rmb = 1,
263 .reg_gpueb_pmic_rmb = 1,
264 .reg_gpueb_srcclkena_mb = 1,
265 .reg_gpueb_vcore_rmb = 1,
266 .reg_gpueb_vrf18_rmb = 1,
267 .reg_hwccf_apsrc_rmb = 1,
268 .reg_hwccf_ddren_rmb = 0,
269 .reg_hwccf_emi_rmb = 1,
270 .reg_hwccf_infra_rmb = 1,
271 .reg_hwccf_pmic_rmb = 1,
272 .reg_hwccf_srcclkena_mb = 1,
273 .reg_hwccf_vcore_rmb = 1,
274
275 /* SPM_SRC_MASK_10 */
276 .reg_hwccf_vrf18_rmb = 1,
277 .reg_img_apsrc_rmb = 0,
278 .reg_img_ddren_rmb = 0,
279 .reg_img_emi_rmb = 0,
280 .reg_img_infra_rmb = 0,
281 .reg_img_pmic_rmb = 0,
282 .reg_img_srcclkena_mb = 0,
283 .reg_img_vrf18_rmb = 0,
284 .reg_infrasys_apsrc_rmb = 0,
285 .reg_infrasys_ddren_rmb = 0,
286 .reg_infrasys_emi_rmb = 0,
287 .reg_infrasys_infra_rmb = 0,
288 .reg_infrasys_pmic_rmb = 0,
289 .reg_infrasys_srcclkena_mb = 0,
290 .reg_infrasys_vcore_rmb = 0,
291 .reg_infrasys_vrf18_rmb = 0,
292 .reg_ipic_infra_rmb = 1,
293 .reg_ipic_vrf18_rmb = 1,
294 .reg_mcu_apsrc_rmb = 1,
295 .reg_mcu_ddren_rmb = 0,
296 .reg_mcu_emi_rmb = 1,
297 .reg_mcu_infra_rmb = 1,
298 .reg_mcu_pmic_rmb = 1,
299 .reg_mcu_srcclkena_mb = 1,
300 .reg_mcu_vcore_rmb = 1,
301 .reg_mcu_vrf18_rmb = 1,
302 .reg_md_apsrc_rmb = 1,
303 .reg_md_ddren_rmb = 0,
304 .reg_md_emi_rmb = 1,
305 .reg_md_infra_rmb = 1,
306 .reg_md_pmic_rmb = 1,
307 .reg_md_srcclkena_mb = 1,
308
309 /* SPM_SRC_MASK_11 */
310 .reg_md_srcclkena1_mb = 1,
311 .reg_md_vcore_rmb = 1,
312 .reg_md_vrf18_rmb = 1,
313 .reg_mm_proc_apsrc_rmb = 1,
314 .reg_mm_proc_ddren_rmb = 0,
315 .reg_mm_proc_emi_rmb = 1,
316 .reg_mm_proc_infra_rmb = 1,
317 .reg_mm_proc_pmic_rmb = 1,
318 .reg_mm_proc_srcclkena_mb = 1,
319 .reg_mm_proc_vcore_rmb = 1,
320 .reg_mm_proc_vrf18_rmb = 1,
321 .reg_mml0_apsrc_rmb = 0,
322 .reg_mml0_ddren_rmb = 0,
323 .reg_mml0_emi_rmb = 0,
324 .reg_mml0_infra_rmb = 0,
325 .reg_mml0_pmic_rmb = 0,
326 .reg_mml0_srcclkena_mb = 0,
327 .reg_mml0_vrf18_rmb = 0,
328 .reg_mml1_apsrc_rmb = 0,
329 .reg_mml1_ddren_rmb = 0,
330 .reg_mml1_emi_rmb = 0,
331 .reg_mml1_infra_rmb = 0,
332 .reg_mml1_pmic_rmb = 0,
333 .reg_mml1_srcclkena_mb = 0,
334 .reg_mml1_vrf18_rmb = 0,
335 .reg_ovl0_apsrc_rmb = 0,
336 .reg_ovl0_ddren_rmb = 0,
337 .reg_ovl0_emi_rmb = 0,
338 .reg_ovl0_infra_rmb = 0,
339 .reg_ovl0_pmic_rmb = 0,
340 .reg_ovl0_srcclkena_mb = 0,
341 .reg_ovl0_vrf18_rmb = 0,
342
343 /* SPM_SRC_MASK_12 */
344 .reg_ovl1_apsrc_rmb = 0,
345 .reg_ovl1_ddren_rmb = 0,
346 .reg_ovl1_emi_rmb = 0,
347 .reg_ovl1_infra_rmb = 0,
348 .reg_ovl1_pmic_rmb = 0,
349 .reg_ovl1_srcclkena_mb = 0,
350 .reg_ovl1_vrf18_rmb = 0,
351 .reg_pcie0_apsrc_rmb = 1,
352 .reg_pcie0_ddren_rmb = 0,
353 .reg_pcie0_emi_rmb = 1,
354 .reg_pcie0_infra_rmb = 1,
355 .reg_pcie0_pmic_rmb = 1,
356 .reg_pcie0_srcclkena_mb = 1,
357 .reg_pcie0_vcore_rmb = 1,
358 .reg_pcie0_vrf18_rmb = 1,
359 .reg_pcie1_apsrc_rmb = 1,
360 .reg_pcie1_ddren_rmb = 0,
361 .reg_pcie1_emi_rmb = 1,
362 .reg_pcie1_infra_rmb = 1,
363 .reg_pcie1_pmic_rmb = 1,
364 .reg_pcie1_srcclkena_mb = 1,
365 .reg_pcie1_vcore_rmb = 1,
366 .reg_pcie1_vrf18_rmb = 1,
367 .reg_perisys_apsrc_rmb = 1,
368 .reg_perisys_ddren_rmb = 0,
369 .reg_perisys_emi_rmb = 1,
370 .reg_perisys_infra_rmb = 1,
371 .reg_perisys_pmic_rmb = 1,
372 .reg_perisys_srcclkena_mb = 1,
373 .reg_perisys_vcore_rmb = 1,
374 .reg_perisys_vrf18_rmb = 1,
375 .reg_pmsr_apsrc_rmb = 1,
376
377 /* SPM_SRC_MASK_13 */
378 .reg_pmsr_ddren_rmb = 0,
379 .reg_pmsr_emi_rmb = 1,
380 .reg_pmsr_infra_rmb = 1,
381 .reg_pmsr_pmic_rmb = 1,
382 .reg_pmsr_srcclkena_mb = 1,
383 .reg_pmsr_vcore_rmb = 1,
384 .reg_pmsr_vrf18_rmb = 1,
385 .reg_scp_apsrc_rmb = 1,
386 .reg_scp_ddren_rmb = 0,
387 .reg_scp_emi_rmb = 1,
388 .reg_scp_infra_rmb = 1,
389 .reg_scp_pmic_rmb = 1,
390 .reg_scp_srcclkena_mb = 1,
391 .reg_scp_vcore_rmb = 1,
392 .reg_scp_vrf18_rmb = 1,
393 .reg_spu_hwr_apsrc_rmb = 1,
394 .reg_spu_hwr_ddren_rmb = 0,
395 .reg_spu_hwr_emi_rmb = 1,
396 .reg_spu_hwr_infra_rmb = 1,
397 .reg_spu_hwr_pmic_rmb = 1,
398 .reg_spu_hwr_srcclkena_mb = 1,
399 .reg_spu_hwr_vcore_rmb = 1,
400 .reg_spu_hwr_vrf18_rmb = 1,
401 .reg_spu_ise_apsrc_rmb = 1,
402 .reg_spu_ise_ddren_rmb = 0,
403 .reg_spu_ise_emi_rmb = 1,
404 .reg_spu_ise_infra_rmb = 1,
405 .reg_spu_ise_pmic_rmb = 1,
406 .reg_spu_ise_srcclkena_mb = 1,
407 .reg_spu_ise_vcore_rmb = 1,
408 .reg_spu_ise_vrf18_rmb = 1,
409
410 /* SPM_SRC_MASK_14 */
411 .reg_srcclkeni_infra_rmb = 0x3,
412 .reg_srcclkeni_pmic_rmb = 0x3,
413 .reg_srcclkeni_srcclkena_mb = 0x3,
414 .reg_srcclkeni_vcore_rmb = 0x3,
415 .reg_sspm_apsrc_rmb = 1,
416 .reg_sspm_ddren_rmb = 0,
417 .reg_sspm_emi_rmb = 1,
418 .reg_sspm_infra_rmb = 1,
419 .reg_sspm_pmic_rmb = 1,
420 .reg_sspm_srcclkena_mb = 1,
421 .reg_sspm_vrf18_rmb = 1,
422 .reg_ssrsys_apsrc_rmb = 1,
423 .reg_ssrsys_ddren_rmb = 0,
424 .reg_ssrsys_emi_rmb = 1,
425 .reg_ssrsys_infra_rmb = 1,
426 .reg_ssrsys_pmic_rmb = 1,
427 .reg_ssrsys_srcclkena_mb = 1,
428 .reg_ssrsys_vcore_rmb = 1,
429 .reg_ssrsys_vrf18_rmb = 1,
430 .reg_ssusb_apsrc_rmb = 1,
431 .reg_ssusb_ddren_rmb = 0,
432 .reg_ssusb_emi_rmb = 1,
433 .reg_ssusb_infra_rmb = 1,
434 .reg_ssusb_pmic_rmb = 1,
435 .reg_ssusb_srcclkena_mb = 1,
436 .reg_ssusb_vcore_rmb = 1,
437 .reg_ssusb_vrf18_rmb = 1,
438 .reg_uart_hub_infra_rmb = 1,
439
440 /* SPM_SRC_MASK_15 */
441 .reg_uart_hub_pmic_rmb = 1,
442 .reg_uart_hub_srcclkena_mb = 1,
443 .reg_uart_hub_vcore_rmb = 1,
444 .reg_uart_hub_vrf18_rmb = 1,
445 .reg_ufs_apsrc_rmb = 1,
446 .reg_ufs_ddren_rmb = 0,
447 .reg_ufs_emi_rmb = 1,
448 .reg_ufs_infra_rmb = 1,
449 .reg_ufs_pmic_rmb = 1,
450 .reg_ufs_srcclkena_mb = 1,
451 .reg_ufs_vcore_rmb = 1,
452 .reg_ufs_vrf18_rmb = 1,
453 .reg_vdec_apsrc_rmb = 0,
454 .reg_vdec_ddren_rmb = 0,
455 .reg_vdec_emi_rmb = 0,
456 .reg_vdec_infra_rmb = 0,
457 .reg_vdec_pmic_rmb = 0,
458 .reg_vdec_srcclkena_mb = 0,
459 .reg_vdec_vrf18_rmb = 0,
460 .reg_venc_apsrc_rmb = 0,
461 .reg_venc_ddren_rmb = 0,
462 .reg_venc_emi_rmb = 0,
463 .reg_venc_infra_rmb = 0,
464 .reg_venc_pmic_rmb = 0,
465 .reg_venc_srcclkena_mb = 0,
466 .reg_venc_vrf18_rmb = 0,
467 .reg_vlpcfg_apsrc_rmb = 1,
468 .reg_vlpcfg_ddren_rmb = 0,
469 .reg_vlpcfg_emi_rmb = 1,
470 .reg_vlpcfg_infra_rmb = 1,
471 .reg_vlpcfg_pmic_rmb = 1,
472 .reg_vlpcfg_srcclkena_mb = 1,
473
474 /* SPM_SRC_MASK_16 */
475 .reg_vlpcfg_vcore_rmb = 1,
476 .reg_vlpcfg_vrf18_rmb = 1,
477 .reg_vlpcfg1_apsrc_rmb = 1,
478 .reg_vlpcfg1_ddren_rmb = 0,
479 .reg_vlpcfg1_emi_rmb = 1,
480 .reg_vlpcfg1_infra_rmb = 1,
481 .reg_vlpcfg1_pmic_rmb = 1,
482 .reg_vlpcfg1_srcclkena_mb = 1,
483 .reg_vlpcfg1_vcore_rmb = 1,
484 .reg_vlpcfg1_vrf18_rmb = 1,
485
486 /* SPM_EVENT_CON_MISC */
487 .reg_srcclken_fast_resp = 0,
488 .reg_csyspwrup_ack_mask = 1,
489
490 /* SPM_SRC_MASK_17 */
491 /* SPM D7X WA for wakeup source */
492 .reg_spm_sw_vcore_rmb = 0x3,
493 .reg_spm_sw_pmic_rmb = 0,
494
495 /* SPM_SRC_MASK_18 */
496 .reg_spm_sw_srcclkena_mb = 0,
497
498 /* SPM_WAKE_MASK*/
499 #ifdef MT_SPM_COMMON_SODI_SUPPORT
500 #if defined(CFG_MICROTRUST_TEE_SUPPORT)
501 .reg_wake_mask = 0x81302012,
502 #else
503 .reg_wake_mask = 0x89302012,
504 #endif
505 #else
506 .reg_wake_mask = 0xEFFFFFF7,
507 #endif
508
509 .reg_ext_wake_mask = 0xFFFFFFFF,
510 };
511
512 struct spm_lp_scen __spm_vcorefs = {
513 .pwrctrl = &vcorefs_ctrl,
514 };
515
get_vsram_pmic_voltage(void)516 static int get_vsram_pmic_voltage(void)
517 {
518 uint8_t vsram_pmic = 0x78;
519 int spmi_ret = 0;
520 #ifdef CONFIG_MTK_SPMI
521 struct spmi_device *spmi_dev;
522
523 spmi_dev = get_spmi_device(SPMI_MASTER_1, SPMI_SLAVE_4);
524 if (spmi_dev == NULL)
525 return vsram_pmic;
526
527 spmi_ret = spmi_ext_register_readl(spmi_dev, 0x250, &vsram_pmic, 1);
528 #endif
529 if (spmi_ret != 0)
530 vsram_pmic = 0x78;
531
532 return vsram_pmic;
533 }
534
get_vcore_pmic_voltage(void)535 static int get_vcore_pmic_voltage(void)
536 {
537 uint8_t vcore_pmic = 0x91;
538 int spmi_ret = 0;
539 #ifdef CONFIG_MTK_SPMI
540 struct spmi_device *spmi_dev;
541 uint16_t vcore_addr;
542
543 vcore_addr = (uint16_t)((mmio_read_32(SPM_PWRAP_CMD0) >> 16) & 0xFFFF);
544 spmi_dev = get_spmi_device(SPMI_MASTER_P_1, SPMI_SLAVE_8);
545 if (spmi_dev == NULL)
546 return vcore_pmic;
547
548 spmi_ret = spmi_ext_register_readl(spmi_dev, vcore_addr, &vcore_pmic, 1);
549 #endif
550 if (spmi_ret != 0)
551 vcore_pmic = 0x91;
552
553 return vcore_pmic;
554 }
555
spm_dvfsfw_init(uint64_t boot_up_opp,uint64_t dram_issue)556 void spm_dvfsfw_init(uint64_t boot_up_opp, uint64_t dram_issue)
557 {
558 uint32_t pmic_val;
559
560 pmic_val = get_vsram_pmic_voltage();
561 pmic_val = VCORE_UV_TO_PMIC(VSRAM_PMIC_TO_UV(pmic_val));
562 mt_spm_pmic_wrap_set_cmd(PMIC_WRAP_PHASE_ALLINONE, CMD_17, pmic_val);
563 pmic_val = get_vcore_pmic_voltage();
564 mmio_write_32(PCM_WDT_LATCH_SPARE_5, pmic_val);
565
566 if (spm_dvfs_init_done)
567 return;
568
569 mmio_clrsetbits_32(SPM_DVFS_CON, SPM_DVFS_FORCE_ENABLE_LSB, SPM_DVFSRC_ENABLE_LSB);
570
571 mmio_write_32(SPM_SW_RSV_3, 0x08000000);
572 mmio_write_32(SPM_DVS_DFS_LEVEL, 0x10080080);
573 mmio_write_32(PCM_WDT_LATCH_SPARE_4, 0x08008002);
574
575 spm_dvfs_init_done = 1;
576 }
577
__spm_sync_vcore_dvfs_pcm_flags(uint32_t * dest_pcm_flags,const uint32_t * src_pcm_flags)578 void __spm_sync_vcore_dvfs_pcm_flags(uint32_t *dest_pcm_flags,
579 const uint32_t *src_pcm_flags)
580 {
581 uint32_t dvfs_mask = SPM_FLAG_DISABLE_VCORE_DVS |
582 SPM_FLAG_DISABLE_DDR_DFS |
583 SPM_FLAG_DISABLE_EMI_DFS |
584 SPM_FLAG_DISABLE_BUS_DFS;
585
586 *dest_pcm_flags = (*dest_pcm_flags & (~dvfs_mask)) |
587 (*src_pcm_flags & dvfs_mask);
588 }
589
__spm_sync_vcore_dvfs_power_control(struct pwr_ctrl * dest_pwr_ctrl,const struct pwr_ctrl * src_pwr_ctrl)590 void __spm_sync_vcore_dvfs_power_control(struct pwr_ctrl *dest_pwr_ctrl,
591 const struct pwr_ctrl *src_pwr_ctrl)
592 {
593
594 __spm_sync_vcore_dvfs_pcm_flags(&dest_pwr_ctrl->pcm_flags,
595 &src_pwr_ctrl->pcm_flags);
596
597 if (dest_pwr_ctrl->pcm_flags_cust)
598 __spm_sync_vcore_dvfs_pcm_flags(&dest_pwr_ctrl->pcm_flags_cust,
599 &src_pwr_ctrl->pcm_flags);
600 }
601
spm_go_to_vcorefs(uint64_t spm_flags)602 void spm_go_to_vcorefs(uint64_t spm_flags)
603 {
604 set_pwrctrl_pcm_flags(__spm_vcorefs.pwrctrl, spm_flags);
605 __spm_set_power_control(__spm_vcorefs.pwrctrl, 0);
606 __spm_set_wakeup_event(__spm_vcorefs.pwrctrl);
607 __spm_set_pcm_flags(__spm_vcorefs.pwrctrl);
608 __spm_send_cpu_wakeup_event();
609 }
610