1 /* SPDX-License-Identifier: GPL-2.0 */
2
3 //#include <linux/kernel.h>
4 #include <linux/memory.h>
5 #include <linux/kernel.h>
6 #include <linux/init.h>
7 #include <linux/module.h>
8 #include <linux/platform_device.h>
9 #include <linux/sched.h>
10 #include <linux/mutex.h>
11 #include <linux/err.h>
12 #include <linux/clk.h>
13 #include <asm/delay.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/delay.h>
16 #include <asm/io.h>
17 #include <linux/irq.h>
18 #include <linux/interrupt.h>
19 //#include <mach/io.h>
20 //#include <mach/irqs.h>
21 #include <linux/fs.h>
22 #include <linux/uaccess.h>
23 #include <linux/miscdevice.h>
24 #include <linux/poll.h>
25 #include <linux/delay.h>
26 #include <linux/wait.h>
27 #include <linux/syscalls.h>
28 #include <linux/timer.h>
29 #include <linux/time.h>
30 #include <asm/cacheflush.h>
31 #include <linux/slab.h>
32 #include <linux/fb.h>
33 #include <linux/wakelock.h>
34 #include <linux/version.h>
35
36 #include "rga_reg_info.h"
37 #include "rga_rop.h"
38 #include "rga.h"
39
40
41 /*************************************************************
42 Func:
43 RGA_pixel_width_init
44 Description:
45 select pixel_width form data format
46 Author:
47 ZhangShengqin
48 Date:
49 20012-2-2 10:59:25
50 **************************************************************/
51 unsigned char
RGA_pixel_width_init(unsigned int format)52 RGA_pixel_width_init(unsigned int format)
53 {
54 unsigned char pixel_width;
55
56 pixel_width = 0;
57
58 switch(format)
59 {
60 /* RGB FORMAT */
61 case RK_FORMAT_RGBA_8888 : pixel_width = 4; break;
62 case RK_FORMAT_RGBX_8888 : pixel_width = 4; break;
63 case RK_FORMAT_RGB_888 : pixel_width = 3; break;
64 case RK_FORMAT_BGRA_8888 : pixel_width = 4; break;
65 case RK_FORMAT_RGB_565 : pixel_width = 2; break;
66 case RK_FORMAT_RGBA_5551 : pixel_width = 2; break;
67 case RK_FORMAT_RGBA_4444 : pixel_width = 2; break;
68 case RK_FORMAT_BGR_888 : pixel_width = 3; break;
69
70 /* YUV FORMAT */
71 case RK_FORMAT_YCbCr_422_SP : pixel_width = 1; break;
72 case RK_FORMAT_YCbCr_422_P : pixel_width = 1; break;
73 case RK_FORMAT_YCbCr_420_SP : pixel_width = 1; break;
74 case RK_FORMAT_YCbCr_420_P : pixel_width = 1; break;
75 case RK_FORMAT_YCrCb_422_SP : pixel_width = 1; break;
76 case RK_FORMAT_YCrCb_422_P : pixel_width = 1; break;
77 case RK_FORMAT_YCrCb_420_SP : pixel_width = 1; break;
78 case RK_FORMAT_YCrCb_420_P : pixel_width = 1; break;
79 //case default : pixel_width = 0; break;
80 }
81
82 return pixel_width;
83 }
84
85 /*************************************************************
86 Func:
87 dst_ctrl_cal
88 Description:
89 calculate dst act window position / width / height
90 and set the tile struct
91 Author:
92 ZhangShengqin
93 Date:
94 20012-2-2 10:59:25
95 **************************************************************/
96 static void
dst_ctrl_cal(const struct rga_req * msg,TILE_INFO * tile)97 dst_ctrl_cal(const struct rga_req *msg, TILE_INFO *tile)
98 {
99 u32 width = msg->dst.act_w;
100 u32 height = msg->dst.act_h;
101 s32 xoff = msg->dst.x_offset;
102 s32 yoff = msg->dst.y_offset;
103
104 s32 x0, y0, x1, y1, x2, y2;
105 s32 x00,y00,x10,y10,x20,y20;
106 s32 xx, xy, yx, yy;
107 s32 pos[8];
108
109 s32 xmax, xmin, ymax, ymin;
110
111 s32 sina = msg->sina; /* 16.16 */
112 s32 cosa = msg->cosa; /* 16.16 */
113
114 xmax = xmin = ymax = ymin = 0;
115
116 if((msg->rotate_mode == 0)||(msg->rotate_mode == 2)||(msg->rotate_mode == 3))
117 {
118 pos[0] = xoff;
119 pos[1] = yoff;
120
121 pos[2] = xoff;
122 pos[3] = yoff + height - 1;
123
124 pos[4] = xoff + width - 1;
125 pos[5] = yoff + height - 1;
126
127 pos[6] = xoff + width - 1;
128 pos[7] = yoff;
129
130 xmax = MIN(MAX(MAX(MAX(pos[0], pos[2]), pos[4]), pos[6]), msg->clip.xmax);
131 xmin = MAX(MIN(MIN(MIN(pos[0], pos[2]), pos[4]), pos[6]), msg->clip.xmin);
132
133 ymax = MIN(MAX(MAX(MAX(pos[1], pos[3]), pos[5]), pos[7]), msg->clip.ymax);
134 ymin = MAX(MIN(MIN(MIN(pos[1], pos[3]), pos[5]), pos[7]), msg->clip.ymin);
135
136 //printk("xmax = %d, xmin = %d, ymin = %d, ymax = %d\n", xmax, xmin, ymin, ymax);
137 }
138 else if(msg->rotate_mode == 1)
139 {
140 if((sina == 0) || (cosa == 0))
141 {
142 if((sina == 0) && (cosa == -65536))
143 {
144 /* 180 */
145 pos[0] = xoff - width + 1;
146 pos[1] = yoff - height + 1;
147
148 pos[2] = xoff - width + 1;
149 pos[3] = yoff;
150
151 pos[4] = xoff;
152 pos[5] = yoff;
153
154 pos[6] = xoff;
155 pos[7] = yoff - height + 1;
156 }
157 else if((cosa == 0)&&(sina == 65536))
158 {
159 /* 90 */
160 pos[0] = xoff - height + 1;
161 pos[1] = yoff;
162
163 pos[2] = xoff - height + 1;
164 pos[3] = yoff + width - 1;
165
166 pos[4] = xoff;
167 pos[5] = yoff + width - 1;
168
169 pos[6] = xoff;
170 pos[7] = yoff;
171 }
172 else if((cosa == 0)&&(sina == -65536))
173 {
174 /* 270 */
175 pos[0] = xoff;
176 pos[1] = yoff - width + 1;
177
178 pos[2] = xoff;
179 pos[3] = yoff;
180
181 pos[4] = xoff + height - 1;
182 pos[5] = yoff;
183
184 pos[6] = xoff + height - 1;
185 pos[7] = yoff - width + 1;
186 }
187 else
188 {
189 /* 0 */
190 pos[0] = xoff;
191 pos[1] = yoff;
192
193 pos[2] = xoff;
194 pos[3] = yoff + height - 1;
195
196 pos[4] = xoff + width - 1;
197 pos[5] = yoff + height - 1;
198
199 pos[6] = xoff + width - 1;
200 pos[7] = yoff;
201 }
202
203 xmax = MIN(MAX(MAX(MAX(pos[0], pos[2]), pos[4]), pos[6]), msg->clip.xmax);
204 xmin = MAX(MIN(MIN(MIN(pos[0], pos[2]), pos[4]), pos[6]), msg->clip.xmin);
205
206 ymax = MIN(MAX(MAX(MAX(pos[1], pos[3]), pos[5]), pos[7]), msg->clip.ymax);
207 ymin = MAX(MIN(MIN(MIN(pos[1], pos[3]), pos[5]), pos[7]), msg->clip.ymin);
208 }
209 else
210 {
211 xx = msg->cosa;
212 xy = msg->sina;
213 yx = xy;
214 yy = xx;
215
216 x0 = width + xoff;
217 y0 = yoff;
218
219 x1 = xoff;
220 y1 = height + yoff;
221
222 x2 = width + xoff;
223 y2 = height + yoff;
224
225 pos[0] = xoff;
226 pos[1] = yoff;
227
228 pos[2] = x00 = (((x0 - xoff)*xx - (y0 - yoff)*xy)>>16) + xoff;
229 pos[3] = y00 = (((x0 - xoff)*yx + (y0 - yoff)*yy)>>16) + yoff;
230
231 pos[4] = x10 = (((x1 - xoff)*xx - (y1 - yoff)*xy)>>16) + xoff;
232 pos[5] = y10 = (((x1 - xoff)*yx + (y1 - yoff)*yy)>>16) + yoff;
233
234 pos[6] = x20 = (((x2 - xoff)*xx - (y2 - yoff)*xy)>>16) + xoff;
235 pos[7] = y20 = (((x2 - xoff)*yx + (y2 - yoff)*yy)>>16) + yoff;
236
237 xmax = MAX(MAX(MAX(x00, xoff), x10), x20) + 2;
238 xmin = MIN(MIN(MIN(x00, xoff), x10), x20) - 1;
239
240 ymax = MAX(MAX(MAX(y00, yoff), y10), y20) + 2;
241 ymin = MIN(MIN(MIN(y00, yoff), y10), y20) - 1;
242
243 xmax = MIN(xmax, msg->clip.xmax);
244 xmin = MAX(xmin, msg->clip.xmin);
245
246 ymax = MIN(ymax, msg->clip.ymax);
247 ymin = MAX(ymin, msg->clip.ymin);
248
249 //printk("xmin = %d, xmax = %d, ymin = %d, ymax = %d\n", xmin, xmax, ymin, ymax);
250 }
251 }
252
253 if ((xmax < xmin) || (ymax < ymin)) {
254 xmin = xmax;
255 ymin = ymax;
256 }
257
258 if ((xmin >= msg->dst.vir_w)||(xmax < 0)||(ymin >= msg->dst.vir_h)||(ymax < 0)) {
259 xmin = xmax = ymin = ymax = 0;
260 }
261
262 //printk("xmin = %d, xmax = %d, ymin = %d, ymax = %d\n", xmin, xmax, ymin, ymax);
263
264 tile->dst_ctrl.w = (xmax - xmin);
265 tile->dst_ctrl.h = (ymax - ymin);
266 tile->dst_ctrl.x_off = xmin;
267 tile->dst_ctrl.y_off = ymin;
268
269 //printk("tile->dst_ctrl.w = %x, tile->dst_ctrl.h = %x\n", tile->dst_ctrl.w, tile->dst_ctrl.h);
270
271 tile->tile_x_num = (xmax - xmin + 1 + 7)>>3;
272 tile->tile_y_num = (ymax - ymin + 1 + 7)>>3;
273
274 tile->dst_x_tmp = xmin - msg->dst.x_offset;
275 tile->dst_y_tmp = ymin - msg->dst.y_offset;
276 }
277
278 /*************************************************************
279 Func:
280 src_tile_info_cal
281 Description:
282 calculate src remap window position / width / height
283 and set the tile struct
284 Author:
285 ZhangShengqin
286 Date:
287 20012-2-2 10:59:25
288 **************************************************************/
289
290 static void
src_tile_info_cal(const struct rga_req * msg,TILE_INFO * tile)291 src_tile_info_cal(const struct rga_req *msg, TILE_INFO *tile)
292 {
293 s32 x0, x1, x2, x3, y0, y1, y2, y3;
294
295 int64_t xx, xy, yx, yy;
296
297 int64_t pos[8];
298 int64_t epos[8];
299
300 int64_t x_dx, x_dy, y_dx, y_dy;
301 int64_t x_temp_start, y_temp_start;
302 int64_t xmax, xmin, ymax, ymin;
303
304 int64_t t_xoff, t_yoff;
305
306 xx = tile->matrix[0]; /* 32.32 */
307 xy = tile->matrix[1]; /* 32.32 */
308 yx = tile->matrix[2]; /* 32.32 */
309 yy = tile->matrix[3]; /* 32.32 */
310
311 if(msg->rotate_mode == 1)
312 {
313 x0 = tile->dst_x_tmp;
314 y0 = tile->dst_y_tmp;
315
316 x1 = x0;
317 y1 = y0 + 8;
318
319 x2 = x0 + 8;
320 y2 = y0 + 8;
321
322 x3 = x0 + 8;
323 y3 = y0;
324
325 pos[0] = (x0*xx + y0*yx);
326 pos[1] = (x0*xy + y0*yy);
327
328 pos[2] = (x1*xx + y1*yx);
329 pos[3] = (x1*xy + y1*yy);
330
331 pos[4] = (x2*xx + y2*yx);
332 pos[5] = (x2*xy + y2*yy);
333
334 pos[6] = (x3*xx + y3*yx);
335 pos[7] = (x3*xy + y3*yy);
336
337 y1 = y0 + 7;
338 x2 = x0 + 7;
339 y2 = y0 + 7;
340 x3 = x0 + 7;
341
342 epos[0] = pos[0];
343 epos[1] = pos[1];
344
345 epos[2] = (x1*xx + y1*yx);
346 epos[3] = (x1*xy + y1*yy);
347
348 epos[4] = (x2*xx + y2*yx);
349 epos[5] = (x2*xy + y2*yy);
350
351 epos[6] = (x3*xx + y3*yx);
352 epos[7] = (x3*xy + y3*yy);
353
354 x_dx = pos[6] - pos[0];
355 x_dy = pos[7] - pos[1];
356
357 y_dx = pos[2] - pos[0];
358 y_dy = pos[3] - pos[1];
359
360 tile->x_dx = (s32)(x_dx >> 22 );
361 tile->x_dy = (s32)(x_dy >> 22 );
362 tile->y_dx = (s32)(y_dx >> 22 );
363 tile->y_dy = (s32)(y_dy >> 22 );
364
365 x_temp_start = x0*xx + y0*yx;
366 y_temp_start = x0*xy + y0*yy;
367
368 xmax = (MAX(MAX(MAX(epos[0], epos[2]), epos[4]), epos[6]));
369 xmin = (MIN(MIN(MIN(epos[0], epos[2]), epos[4]), epos[6]));
370
371 ymax = (MAX(MAX(MAX(epos[1], epos[3]), epos[5]), epos[7]));
372 ymin = (MIN(MIN(MIN(epos[1], epos[3]), epos[5]), epos[7]));
373
374 t_xoff = (x_temp_start - xmin)>>18;
375 t_yoff = (y_temp_start - ymin)>>18;
376
377 tile->tile_xoff = (s32)t_xoff;
378 tile->tile_yoff = (s32)t_yoff;
379
380 tile->tile_w = (u16)((xmax - xmin)>>21); //.11
381 tile->tile_h = (u16)((ymax - ymin)>>21); //.11
382
383 tile->tile_start_x_coor = (s16)(xmin>>29); //.3
384 tile->tile_start_y_coor = (s16)(ymin>>29); //.3
385 }
386 else if (msg->rotate_mode == 2)
387 {
388 tile->x_dx = (s32)((8*xx)>>22);
389 tile->x_dy = 0;
390 tile->y_dx = 0;
391 tile->y_dy = (s32)((8*yy)>>22);
392
393 tile->tile_w = ABS((s32)((7*xx)>>21));
394 tile->tile_h = ABS((s32)((7*yy)>>21));
395
396 tile->tile_xoff = ABS((s32)((7*xx)>>18));
397 tile->tile_yoff = 0;
398
399 tile->tile_start_x_coor = (((msg->src.act_w - 1)<<11) - (tile->tile_w))>>8;
400 tile->tile_start_y_coor = 0;
401 }
402 else if (msg->rotate_mode == 3)
403 {
404 tile->x_dx = (s32)((8*xx)>>22);
405 tile->x_dy = 0;
406 tile->y_dx = 0;
407 tile->y_dy = (s32)((8*yy)>>22);
408
409 tile->tile_w = ABS((s32)((7*xx)>>21));
410 tile->tile_h = ABS((s32)((7*yy)>>21));
411
412 tile->tile_xoff = 0;
413 tile->tile_yoff = ABS((s32)((7*yy)>>18));
414
415 tile->tile_start_x_coor = 0;
416 tile->tile_start_y_coor = (((msg->src.act_h - 1)<<11) - (tile->tile_h))>>8;
417 }
418
419 if ((msg->scale_mode == 2)||(msg->alpha_rop_flag >> 7))
420 {
421 tile->tile_start_x_coor -= (1<<3);
422 tile->tile_start_y_coor -= (1<<3);
423 tile->tile_w += (2 << 11);
424 tile->tile_h += (2 << 11);
425 tile->tile_xoff += (1<<14);
426 tile->tile_yoff += (1<<14);
427 }
428 }
429
430
431 /*************************************************************
432 Func:
433 RGA_set_mode_ctrl
434 Description:
435 fill mode ctrl reg info
436 Author:
437 ZhangShengqin
438 Date:
439 20012-2-2 10:59:25
440 **************************************************************/
441
442 static void
RGA_set_mode_ctrl(u8 * base,const struct rga_req * msg)443 RGA_set_mode_ctrl(u8 *base, const struct rga_req *msg)
444 {
445 u32 *bRGA_MODE_CTL;
446 u32 reg = 0;
447
448 u8 src_rgb_pack = 0;
449 u8 src_format = 0;
450 u8 src_rb_swp = 0;
451 u8 src_a_swp = 0;
452 u8 src_cbcr_swp = 0;
453
454 u8 dst_rgb_pack = 0;
455 u8 dst_format = 0;
456 u8 dst_rb_swp = 0;
457 u8 dst_a_swp = 0;
458
459 bRGA_MODE_CTL = (u32 *)(base + RGA_MODE_CTRL_OFFSET);
460
461 reg = ((reg & (~m_RGA_MODE_CTRL_2D_RENDER_MODE)) | (s_RGA_MODE_CTRL_2D_RENDER_MODE(msg->render_mode)));
462
463 /* src info set */
464
465 if (msg->render_mode == color_palette_mode || msg->render_mode == update_palette_table_mode)
466 {
467 src_format = 0x10 | (msg->palette_mode & 3);
468 }
469 else
470 {
471 switch (msg->src.format)
472 {
473 case RK_FORMAT_RGBA_8888 : src_format = 0x0; break;
474 case RK_FORMAT_RGBA_4444 : src_format = 0x3; break;
475 case RK_FORMAT_RGBA_5551 : src_format = 0x2; break;
476 case RK_FORMAT_BGRA_8888 : src_format = 0x0; src_rb_swp = 0x1; break;
477 case RK_FORMAT_RGBX_8888 : src_format = 0x0; break;
478 case RK_FORMAT_RGB_565 : src_format = 0x1; break;
479 case RK_FORMAT_RGB_888 : src_format = 0x0; src_rgb_pack = 1; break;
480 case RK_FORMAT_BGR_888 : src_format = 0x0; src_rgb_pack = 1; src_rb_swp = 1; break;
481
482 case RK_FORMAT_YCbCr_422_SP : src_format = 0x4; break;
483 case RK_FORMAT_YCbCr_422_P : src_format = 0x5; break;
484 case RK_FORMAT_YCbCr_420_SP : src_format = 0x6; break;
485 case RK_FORMAT_YCbCr_420_P : src_format = 0x7; break;
486
487 case RK_FORMAT_YCrCb_422_SP : src_format = 0x4; src_cbcr_swp = 1; break;
488 case RK_FORMAT_YCrCb_422_P : src_format = 0x5; src_cbcr_swp = 1; break;
489 case RK_FORMAT_YCrCb_420_SP : src_format = 0x6; src_cbcr_swp = 1; break;
490 case RK_FORMAT_YCrCb_420_P : src_format = 0x7; src_cbcr_swp = 1; break;
491 }
492 }
493
494 src_a_swp = msg->src.alpha_swap & 1;
495
496 reg = ((reg & (~m_RGA_MODE_CTRL_SRC_RGB_PACK)) | (s_RGA_MODE_CTRL_SRC_RGB_PACK(src_rgb_pack)));
497 reg = ((reg & (~m_RGA_MODE_CTRL_SRC_FORMAT)) | (s_RGA_MODE_CTRL_SRC_FORMAT(src_format)));
498 reg = ((reg & (~m_RGA_MODE_CTRL_SRC_RB_SWAP)) | (s_RGA_MODE_CTRL_SRC_RB_SWAP(src_rb_swp)));
499 reg = ((reg & (~m_RGA_MODE_CTRL_SRC_ALPHA_SWAP)) | (s_RGA_MODE_CTRL_SRC_ALPHA_SWAP(src_a_swp)));
500 reg = ((reg & (~m_RGA_MODE_CTRL_SRC_UV_SWAP_MODE )) | (s_RGA_MODE_CTRL_SRC_UV_SWAP_MODE (src_cbcr_swp)));
501
502
503 /* YUV2RGB MODE */
504 reg = ((reg & (~m_RGA_MODE_CTRL_YUV2RGB_CON_MODE)) | (s_RGA_MODE_CTRL_YUV2RGB_CON_MODE(msg->yuv2rgb_mode)));
505
506 /* ROTATE MODE */
507 reg = ((reg & (~m_RGA_MODE_CTRL_ROTATE_MODE)) | (s_RGA_MODE_CTRL_ROTATE_MODE(msg->rotate_mode)));
508
509 /* SCALE MODE */
510 reg = ((reg & (~m_RGA_MODE_CTRL_SCALE_MODE)) | (s_RGA_MODE_CTRL_SCALE_MODE(msg->scale_mode)));
511
512 /* COLOR FILL MODE */
513 reg = ((reg & (~m_RGA_MODE_CTRL_PAT_SEL)) | (s_RGA_MODE_CTRL_PAT_SEL(msg->color_fill_mode)));
514
515
516 if ((msg->render_mode == update_palette_table_mode)||(msg->render_mode == update_patten_buff_mode))
517 {
518 dst_format = msg->pat.format;
519 }
520 else
521 {
522 dst_format = (u8)msg->dst.format;
523 }
524
525 /* dst info set */
526 switch (dst_format)
527 {
528 case RK_FORMAT_BGRA_8888 : dst_format = 0x0; dst_rb_swp = 0x1; break;
529 case RK_FORMAT_RGBA_4444 : dst_format = 0x3; break;
530 case RK_FORMAT_RGBA_5551 : dst_format = 0x2; break;
531 case RK_FORMAT_RGBA_8888 : dst_format = 0x0; break;
532 case RK_FORMAT_RGB_565 : dst_format = 0x1; break;
533 case RK_FORMAT_RGB_888 : dst_format = 0x0; dst_rgb_pack = 0x1; break;
534 case RK_FORMAT_BGR_888 : dst_format = 0x0; dst_rgb_pack = 0x1; dst_rb_swp = 1; break;
535 case RK_FORMAT_RGBX_8888 : dst_format = 0x0; break;
536 }
537
538 dst_a_swp = msg->dst.alpha_swap & 1;
539
540 reg = ((reg & (~m_RGA_MODE_CTRL_DST_FORMAT)) | (s_RGA_MODE_CTRL_DST_FORMAT(dst_format)));
541 reg = ((reg & (~m_RGA_MODE_CTRL_DST_RGB_PACK)) | (s_RGA_MODE_CTRL_DST_RGB_PACK(dst_rgb_pack)));
542 reg = ((reg & (~m_RGA_MODE_CTRL_DST_RB_SWAP)) | (s_RGA_MODE_CTRL_DST_RB_SWAP(dst_rb_swp)));
543 reg = ((reg & (~m_RGA_MODE_CTRL_DST_ALPHA_SWAP)) | (s_RGA_MODE_CTRL_DST_ALPHA_SWAP(dst_a_swp)));
544 reg = ((reg & (~m_RGA_MODE_CTRL_LUT_ENDIAN_MODE)) | (s_RGA_MODE_CTRL_LUT_ENDIAN_MODE(msg->endian_mode & 1)));
545 reg = ((reg & (~m_RGA_MODE_CTRL_SRC_TRANS_MODE)) | (s_RGA_MODE_CTRL_SRC_TRANS_MODE(msg->src_trans_mode)));
546 reg = ((reg & (~m_RGA_MODE_CTRL_ZERO_MODE_ENABLE)) | (s_RGA_MODE_CTRL_ZERO_MODE_ENABLE(msg->alpha_rop_mode >> 4)));
547 reg = ((reg & (~m_RGA_MODE_CTRL_DST_ALPHA_ENABLE)) | (s_RGA_MODE_CTRL_DST_ALPHA_ENABLE(msg->alpha_rop_mode >> 5)));
548
549 *bRGA_MODE_CTL = reg;
550
551 }
552
553
554
555 /*************************************************************
556 Func:
557 RGA_set_src
558 Description:
559 fill src relate reg info
560 Author:
561 ZhangShengqin
562 Date:
563 20012-2-2 10:59:25
564 **************************************************************/
565
566 static void
RGA_set_src(u8 * base,const struct rga_req * msg)567 RGA_set_src(u8 *base, const struct rga_req *msg)
568 {
569 u32 *bRGA_SRC_VIR_INFO;
570 u32 *bRGA_SRC_ACT_INFO;
571 u32 *bRGA_SRC_Y_MST;
572 u32 *bRGA_SRC_CB_MST;
573 u32 *bRGA_SRC_CR_MST;
574
575 s16 x_off, y_off, stride;
576 s16 uv_x_off, uv_y_off, uv_stride;
577 u32 pixel_width;
578
579 uv_x_off = uv_y_off = uv_stride = 0;
580
581 bRGA_SRC_Y_MST = (u32 *)(base + RGA_SRC_Y_MST_OFFSET);
582 bRGA_SRC_CB_MST = (u32 *)(base + RGA_SRC_CB_MST_OFFSET);
583 bRGA_SRC_CR_MST = (u32 *)(base + RGA_SRC_CR_MST_OFFSET);
584 bRGA_SRC_VIR_INFO = (u32 *)(base + RGA_SRC_VIR_INFO_OFFSET);
585 bRGA_SRC_ACT_INFO = (u32 *)(base + RGA_SRC_ACT_INFO_OFFSET);
586
587 x_off = msg->src.x_offset;
588 y_off = msg->src.y_offset;
589
590 pixel_width = RGA_pixel_width_init(msg->src.format);
591
592 stride = ((msg->src.vir_w * pixel_width) + 3) & (~3);
593
594 switch(msg->src.format)
595 {
596 case RK_FORMAT_YCbCr_422_SP :
597 uv_stride = stride;
598 uv_x_off = x_off;
599 uv_y_off = y_off;
600 break;
601 case RK_FORMAT_YCbCr_422_P :
602 uv_stride = stride >> 1;
603 uv_x_off = x_off >> 1;
604 uv_y_off = y_off;
605 break;
606 case RK_FORMAT_YCbCr_420_SP :
607 uv_stride = stride;
608 uv_x_off = x_off;
609 uv_y_off = y_off >> 1;
610 break;
611 case RK_FORMAT_YCbCr_420_P :
612 uv_stride = stride >> 1;
613 uv_x_off = x_off >> 1;
614 uv_y_off = y_off >> 1;
615 break;
616 case RK_FORMAT_YCrCb_422_SP :
617 uv_stride = stride;
618 uv_x_off = x_off;
619 uv_y_off = y_off;
620 break;
621 case RK_FORMAT_YCrCb_422_P :
622 uv_stride = stride >> 1;
623 uv_x_off = x_off >> 1;
624 uv_y_off = y_off;
625 break;
626 case RK_FORMAT_YCrCb_420_SP :
627 uv_stride = stride;
628 uv_x_off = x_off;
629 uv_y_off = y_off >> 1;
630 break;
631 case RK_FORMAT_YCrCb_420_P :
632 uv_stride = stride >> 1;
633 uv_x_off = x_off >> 1;
634 uv_y_off = y_off >> 1;
635 break;
636 }
637
638
639 /* src addr set */
640 *bRGA_SRC_Y_MST = msg->src.yrgb_addr + (y_off * stride) + (x_off * pixel_width);
641 *bRGA_SRC_CB_MST = msg->src.uv_addr + uv_y_off * uv_stride + uv_x_off;
642 *bRGA_SRC_CR_MST = msg->src.v_addr + uv_y_off * uv_stride + uv_x_off;
643
644 if((msg->alpha_rop_flag >> 1) & 1)
645 *bRGA_SRC_CB_MST = (u32)msg->rop_mask_addr;
646
647 if (msg->render_mode == color_palette_mode)
648 {
649 u8 shift;
650 u16 sw, byte_num;
651 shift = 3 - (msg->palette_mode & 3);
652 sw = msg->src.vir_w;
653
654 byte_num = sw >> shift;
655 stride = (byte_num + 3) & (~3);
656 }
657
658 /* src act window / vir window set */
659 *bRGA_SRC_VIR_INFO = ((stride >> 2) | (msg->src.vir_h)<<16);
660 *bRGA_SRC_ACT_INFO = ((msg->src.act_w-1) | (msg->src.act_h-1)<<16);
661 }
662
663
664 /*************************************************************
665 Func:
666 RGA_set_dst
667 Description:
668 fill dst relate reg info
669 Author:
670 ZhangShengqin
671 Date:
672 20012-2-2 10:59:25
673 **************************************************************/
674
RGA_set_dst(u8 * base,const struct rga_req * msg)675 static s32 RGA_set_dst(u8 *base, const struct rga_req *msg)
676 {
677 u32 *bRGA_DST_MST;
678 u32 *bRGA_DST_UV_MST;
679 u32 *bRGA_DST_VIR_INFO;
680 u32 *bRGA_DST_CTR_INFO;
681 u32 *bRGA_PRESCL_CB_MST;
682 u32 *bRGA_PRESCL_CR_MST;
683 u32 *bRGA_YUV_OUT_CFG;
684
685 u32 reg = 0;
686
687 u8 pw;
688 s16 x_off = msg->dst.x_offset;
689 s16 y_off = msg->dst.y_offset;
690 u16 stride, rop_mask_stride;
691
692 bRGA_DST_MST = (u32 *)(base + RGA_DST_MST_OFFSET);
693 bRGA_DST_UV_MST = (u32 *)(base + RGA_DST_UV_MST_OFFSET);
694 bRGA_DST_VIR_INFO = (u32 *)(base + RGA_DST_VIR_INFO_OFFSET);
695 bRGA_DST_CTR_INFO = (u32 *)(base + RGA_DST_CTR_INFO_OFFSET);
696 bRGA_PRESCL_CB_MST = (u32 *)(base + RGA_PRESCL_CB_MST_OFFSET);
697 bRGA_PRESCL_CR_MST = (u32 *)(base + RGA_PRESCL_CR_MST_OFFSET);
698 bRGA_YUV_OUT_CFG = (u32 *)(base + RGA_YUV_OUT_CFG_OFFSET);
699
700 pw = RGA_pixel_width_init(msg->dst.format);
701
702 stride = (msg->dst.vir_w * pw + 3) & (~3);
703
704 *bRGA_DST_MST = (u32)msg->dst.yrgb_addr + (y_off * stride) + (x_off * pw);
705
706 *bRGA_DST_UV_MST = 0;
707 *bRGA_YUV_OUT_CFG = 0;
708 if (msg->rotate_mode == 1) {
709 if (msg->sina == 65536 && msg->cosa == 0) {
710 /* rotate 90 */
711 x_off = msg->dst.x_offset - msg->dst.act_h + 1;
712 } else if (msg->sina == 0 && msg->cosa == -65536) {
713 /* rotate 180 */
714 x_off = msg->dst.x_offset - msg->dst.act_w + 1;
715 y_off = msg->dst.y_offset - msg->dst.act_h + 1;
716 } else if (msg->sina == -65536 && msg->cosa == 0) {
717 /* totate 270 */
718 y_off = msg->dst.y_offset - msg->dst.act_w + 1;
719 }
720 }
721
722 switch(msg->dst.format)
723 {
724 case RK_FORMAT_YCbCr_422_SP :
725 *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off) * stride) + ((x_off) * pw);
726 *bRGA_DST_UV_MST = (u32)msg->dst.uv_addr + (y_off * stride) + x_off;
727 *bRGA_YUV_OUT_CFG |= (((msg->yuv2rgb_mode >> 2) & 3) << 4) | (0 << 3) | (0 << 1) | 1;
728 break;
729 case RK_FORMAT_YCbCr_422_P :
730 *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off) * stride) + ((x_off>>1) * pw);
731 *bRGA_PRESCL_CR_MST = (u32)msg->dst.v_addr + ((y_off) * stride) + ((x_off>>1) * pw);
732 break;
733 case RK_FORMAT_YCbCr_420_SP :
734 *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off>>1) * stride) + ((x_off) * pw);
735 *bRGA_DST_UV_MST = (u32)msg->dst.uv_addr + ((y_off>>1) * stride) + x_off;
736 *bRGA_YUV_OUT_CFG |= (((msg->yuv2rgb_mode >> 2) & 3) << 4) | (0 << 3) | (1 << 1) | 1;
737 break;
738 case RK_FORMAT_YCbCr_420_P :
739 *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off>>1) * stride) + ((x_off>>1) * pw);
740 *bRGA_PRESCL_CR_MST = (u32)msg->dst.v_addr + ((y_off>>1) * stride) + ((x_off>>1) * pw);
741 break;
742 case RK_FORMAT_YCrCb_422_SP :
743 *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off) * stride) + ((x_off) * pw);
744 *bRGA_DST_UV_MST = (u32)msg->dst.uv_addr + (y_off * stride) + x_off;
745 *bRGA_YUV_OUT_CFG |= (((msg->yuv2rgb_mode >> 2) & 3) << 4) | (1 << 3) | (0 << 1) | 1;
746 break;
747 case RK_FORMAT_YCrCb_422_P :
748 *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off) * stride) + ((x_off>>1) * pw);
749 *bRGA_PRESCL_CR_MST = (u32)msg->dst.v_addr + ((y_off) * stride) + ((x_off>>1) * pw);
750 break;
751 case RK_FORMAT_YCrCb_420_SP :
752 *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off>>1) * stride) + ((x_off) * pw);
753 *bRGA_DST_UV_MST = (u32)msg->dst.uv_addr + ((y_off>>1) * stride) + x_off;
754 *bRGA_YUV_OUT_CFG |= (((msg->yuv2rgb_mode >> 2) & 3) << 4) | (1 << 3) | (1 << 1) | 1;
755 break;
756 case RK_FORMAT_YCrCb_420_P :
757 *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off>>1) * stride) + ((x_off>>1) * pw);
758 *bRGA_PRESCL_CR_MST = (u32)msg->dst.v_addr + ((y_off>>1) * stride) + ((x_off>>1) * pw);
759 break;
760 }
761
762 rop_mask_stride = (((msg->src.vir_w + 7)>>3) + 3) & (~3);//not dst_vir.w,hxx,2011.7.21
763
764 reg = (stride >> 2) & 0xffff;
765 reg = reg | ((rop_mask_stride>>2) << 16);
766
767 #if defined(CONFIG_ARCH_RK2928) || defined(CONFIG_ARCH_RK3188)
768 //reg = reg | ((msg->alpha_rop_mode & 3) << 28);
769 reg = reg | (1 << 28);
770 #endif
771
772 if (msg->render_mode == line_point_drawing_mode)
773 {
774 reg &= 0xffff;
775 reg = reg | (msg->dst.vir_h << 16);
776 }
777
778 *bRGA_DST_VIR_INFO = reg;
779 *bRGA_DST_CTR_INFO = (msg->dst.act_w - 1) | ((msg->dst.act_h - 1) << 16);
780 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 1, 0))
781 if (msg->render_mode == pre_scaling_mode) {
782 *bRGA_YUV_OUT_CFG &= 0xfffffffe;
783 }
784 #endif
785 return 0;
786 }
787
788
789 /*************************************************************
790 Func:
791 RGA_set_alpha_rop
792 Description:
793 fill alpha rop some relate reg bit
794 Author:
795 ZhangShengqin
796 Date:
797 20012-2-2 10:59:25
798 **************************************************************/
799 static void
RGA_set_alpha_rop(u8 * base,const struct rga_req * msg)800 RGA_set_alpha_rop(u8 *base, const struct rga_req *msg)
801 {
802 u32 *bRGA_ALPHA_CON;
803 u32 *bRGA_ROP_CON0;
804 u32 *bRGA_ROP_CON1;
805 u32 reg = 0;
806 u32 rop_con0, rop_con1;
807
808 u8 rop_mode = (msg->alpha_rop_mode) & 3;
809 u8 alpha_mode = msg->alpha_rop_mode & 3;
810
811 rop_con0 = rop_con1 = 0;
812
813 bRGA_ALPHA_CON = (u32 *)(base + RGA_ALPHA_CON_OFFSET);
814
815 reg = ((reg & (~m_RGA_ALPHA_CON_ENABLE) )| (s_RGA_ALPHA_CON_ENABLE(msg->alpha_rop_flag & 1)));
816 reg = ((reg & (~m_RGA_ALPHA_CON_A_OR_R_SEL)) | (s_RGA_ALPHA_CON_A_OR_R_SEL((msg->alpha_rop_flag >> 1) & 1)));
817 reg = ((reg & (~m_RGA_ALPHA_CON_ALPHA_MODE)) | (s_RGA_ALPHA_CON_ALPHA_MODE(alpha_mode)));
818 reg = ((reg & (~m_RGA_ALPHA_CON_PD_MODE)) | (s_RGA_ALPHA_CON_PD_MODE(msg->PD_mode)));
819 reg = ((reg & (~m_RGA_ALPHA_CON_SET_CONSTANT_VALUE)) | (s_RGA_ALPHA_CON_SET_CONSTANT_VALUE(msg->alpha_global_value)));
820 reg = ((reg & (~m_RGA_ALPHA_CON_PD_M_SEL)) | (s_RGA_ALPHA_CON_PD_M_SEL(msg->alpha_rop_flag >> 3)));
821 reg = ((reg & (~m_RGA_ALPHA_CON_FADING_ENABLE)) | (s_RGA_ALPHA_CON_FADING_ENABLE(msg->alpha_rop_flag >> 2)));
822 reg = ((reg & (~m_RGA_ALPHA_CON_ROP_MODE_SEL)) | (s_RGA_ALPHA_CON_ROP_MODE_SEL(rop_mode)));
823 reg = ((reg & (~m_RGA_ALPHA_CON_CAL_MODE_SEL)) | (s_RGA_ALPHA_CON_CAL_MODE_SEL(msg->alpha_rop_flag >> 4)));
824 reg = ((reg & (~m_RGA_ALPHA_CON_DITHER_ENABLE)) | (s_RGA_ALPHA_CON_DITHER_ENABLE(msg->alpha_rop_flag >> 5)));
825 reg = ((reg & (~m_RGA_ALPHA_CON_GRADIENT_CAL_MODE)) | (s_RGA_ALPHA_CON_GRADIENT_CAL_MODE(msg->alpha_rop_flag >> 6)));
826 reg = ((reg & (~m_RGA_ALPHA_CON_AA_SEL)) | (s_RGA_ALPHA_CON_AA_SEL(msg->alpha_rop_flag >> 7)));
827
828 *bRGA_ALPHA_CON = reg;
829
830 if(rop_mode == 0) {
831 rop_con0 = ROP3_code[(msg->rop_code & 0xff)];
832 }
833 else if(rop_mode == 1) {
834 rop_con0 = ROP3_code[(msg->rop_code & 0xff)];
835 }
836 else if(rop_mode == 2) {
837 rop_con0 = ROP3_code[(msg->rop_code & 0xff)];
838 rop_con1 = ROP3_code[(msg->rop_code & 0xff00)>>8];
839 }
840
841 bRGA_ROP_CON0 = (u32 *)(base + RGA_ROP_CON0_OFFSET);
842 bRGA_ROP_CON1 = (u32 *)(base + RGA_ROP_CON1_OFFSET);
843
844 *bRGA_ROP_CON0 = (u32)rop_con0;
845 *bRGA_ROP_CON1 = (u32)rop_con1;
846 }
847
848
849 /*************************************************************
850 Func:
851 RGA_set_color
852 Description:
853 fill color some relate reg bit
854 bg_color/fg_color
855 Author:
856 ZhangShengqin
857 Date:
858 20012-2-2 10:59:25
859 **************************************************************/
860
861 static void
RGA_set_color(u8 * base,const struct rga_req * msg)862 RGA_set_color(u8 *base, const struct rga_req *msg)
863 {
864 u32 *bRGA_SRC_TR_COLOR0;
865 u32 *bRGA_SRC_TR_COLOR1;
866 u32 *bRGA_SRC_BG_COLOR;
867 u32 *bRGA_SRC_FG_COLOR;
868
869
870 bRGA_SRC_BG_COLOR = (u32 *)(base + RGA_SRC_BG_COLOR_OFFSET);
871 bRGA_SRC_FG_COLOR = (u32 *)(base + RGA_SRC_FG_COLOR_OFFSET);
872
873 *bRGA_SRC_BG_COLOR = msg->bg_color; /* 1bpp 0 */
874 *bRGA_SRC_FG_COLOR = msg->fg_color; /* 1bpp 1 */
875
876 bRGA_SRC_TR_COLOR0 = (u32 *)(base + RGA_SRC_TR_COLOR0_OFFSET);
877 bRGA_SRC_TR_COLOR1 = (u32 *)(base + RGA_SRC_TR_COLOR1_OFFSET);
878
879 *bRGA_SRC_TR_COLOR0 = msg->color_key_min;
880 *bRGA_SRC_TR_COLOR1 = msg->color_key_max;
881 }
882
883
884 /*************************************************************
885 Func:
886 RGA_set_fading
887 Description:
888 fill fading some relate reg bit
889 Author:
890 ZhangShengqin
891 Date:
892 20012-2-2 10:59:25
893 **************************************************************/
894
895 static s32
RGA_set_fading(u8 * base,const struct rga_req * msg)896 RGA_set_fading(u8 *base, const struct rga_req *msg)
897 {
898 u32 *bRGA_FADING_CON;
899 u8 r, g, b;
900 u32 reg = 0;
901
902 bRGA_FADING_CON = (u32 *)(base + RGA_FADING_CON_OFFSET);
903
904 b = msg->fading.b;
905 g = msg->fading.g;
906 r = msg->fading.r;
907
908 reg = (r<<8) | (g<<16) | (b<<24) | reg;
909
910 *bRGA_FADING_CON = reg;
911
912 return 0;
913 }
914
915
916 /*************************************************************
917 Func:
918 RGA_set_pat
919 Description:
920 fill patten some relate reg bit
921 Author:
922 ZhangShengqin
923 Date:
924 20012-2-2 10:59:25
925 **************************************************************/
926
927 static s32
RGA_set_pat(u8 * base,const struct rga_req * msg)928 RGA_set_pat(u8 *base, const struct rga_req *msg)
929 {
930 u32 *bRGA_PAT_CON;
931 u32 *bRGA_PAT_START_POINT;
932 u32 reg = 0;
933
934 bRGA_PAT_START_POINT = (u32 *)(base + RGA_PAT_START_POINT_OFFSET);
935
936 bRGA_PAT_CON = (u32 *)(base + RGA_PAT_CON_OFFSET);
937
938 *bRGA_PAT_START_POINT = (msg->pat.act_w * msg->pat.y_offset) + msg->pat.x_offset;
939
940 reg = (msg->pat.act_w - 1) | ((msg->pat.act_h - 1) << 8) | (msg->pat.x_offset << 16) | (msg->pat.y_offset << 24);
941 *bRGA_PAT_CON = reg;
942
943 return 0;
944 }
945
946
947
948
949 /*************************************************************
950 Func:
951 RGA_set_bitblt_reg_info
952 Description:
953 fill bitblt mode relate ren info
954 Author:
955 ZhangShengqin
956 Date:
957 20012-2-2 10:59:25
958 **************************************************************/
959
960 static void
RGA_set_bitblt_reg_info(u8 * base,const struct rga_req * msg,TILE_INFO * tile)961 RGA_set_bitblt_reg_info(u8 *base, const struct rga_req * msg, TILE_INFO *tile)
962 {
963 u32 *bRGA_SRC_Y_MST;
964 u32 *bRGA_SRC_CB_MST;
965 u32 *bRGA_SRC_CR_MST;
966 u32 *bRGA_SRC_X_PARA;
967 u32 *bRGA_SRC_Y_PARA;
968 u32 *bRGA_SRC_TILE_XINFO;
969 u32 *bRGA_SRC_TILE_YINFO;
970 u32 *bRGA_SRC_TILE_H_INCR;
971 u32 *bRGA_SRC_TILE_V_INCR;
972 u32 *bRGA_SRC_TILE_OFFSETX;
973 u32 *bRGA_SRC_TILE_OFFSETY;
974
975 u32 *bRGA_DST_MST;
976 u32 *bRGA_DST_CTR_INFO;
977
978 s32 m0, m1, m2, m3;
979 s32 pos[8];
980 //s32 x_dx, x_dy, y_dx, y_dy;
981 s32 xmin, xmax, ymin, ymax;
982 s32 xp, yp;
983 u32 y_addr, u_addr, v_addr;
984 u32 pixel_width, stride;
985
986 u_addr = v_addr = 0;
987
988 /* src info */
989
990 bRGA_SRC_Y_MST = (u32 *)(base + RGA_SRC_Y_MST_OFFSET);
991 bRGA_SRC_CB_MST = (u32 *)(base + RGA_SRC_CB_MST_OFFSET);
992 bRGA_SRC_CR_MST = (u32 *)(base + RGA_SRC_CR_MST_OFFSET);
993
994 bRGA_SRC_X_PARA = (u32 *)(base + RGA_SRC_X_PARA_OFFSET);
995 bRGA_SRC_Y_PARA = (u32 *)(base + RGA_SRC_Y_PARA_OFFSET);
996
997 bRGA_SRC_TILE_XINFO = (u32 *)(base + RGA_SRC_TILE_XINFO_OFFSET);
998 bRGA_SRC_TILE_YINFO = (u32 *)(base + RGA_SRC_TILE_YINFO_OFFSET);
999 bRGA_SRC_TILE_H_INCR = (u32 *)(base + RGA_SRC_TILE_H_INCR_OFFSET);
1000 bRGA_SRC_TILE_V_INCR = (u32 *)(base + RGA_SRC_TILE_V_INCR_OFFSET);
1001 bRGA_SRC_TILE_OFFSETX = (u32 *)(base + RGA_SRC_TILE_OFFSETX_OFFSET);
1002 bRGA_SRC_TILE_OFFSETY = (u32 *)(base + RGA_SRC_TILE_OFFSETY_OFFSET);
1003
1004 bRGA_DST_MST = (u32 *)(base + RGA_DST_MST_OFFSET);
1005 bRGA_DST_CTR_INFO = (u32 *)(base + RGA_DST_CTR_INFO_OFFSET);
1006
1007 /* Matrix reg fill */
1008 m0 = (s32)(tile->matrix[0] >> 18);
1009 m1 = (s32)(tile->matrix[1] >> 18);
1010 m2 = (s32)(tile->matrix[2] >> 18);
1011 m3 = (s32)(tile->matrix[3] >> 18);
1012
1013 *bRGA_SRC_X_PARA = (m0 & 0xffff) | (m2 << 16);
1014 *bRGA_SRC_Y_PARA = (m1 & 0xffff) | (m3 << 16);
1015
1016 /* src tile information setting */
1017 if(msg->rotate_mode != 0)//add by hxx,2011.7.12,for rtl0707,when line scanning ,do not calc src tile info
1018 {
1019 *bRGA_SRC_TILE_XINFO = (tile->tile_start_x_coor & 0xffff) | (tile->tile_w << 16);
1020 *bRGA_SRC_TILE_YINFO = (tile->tile_start_y_coor & 0xffff) | (tile->tile_h << 16);
1021
1022 *bRGA_SRC_TILE_H_INCR = ((tile->x_dx) & 0xffff) | ((tile->x_dy) << 16);
1023 *bRGA_SRC_TILE_V_INCR = ((tile->y_dx) & 0xffff) | ((tile->y_dy) << 16);
1024
1025 *bRGA_SRC_TILE_OFFSETX = tile->tile_xoff;
1026 *bRGA_SRC_TILE_OFFSETY = tile->tile_yoff;
1027 }
1028
1029 pixel_width = RGA_pixel_width_init(msg->src.format);
1030
1031 stride = ((msg->src.vir_w * pixel_width) + 3) & (~3);
1032
1033 if ((msg->rotate_mode == 1)||(msg->rotate_mode == 2)||(msg->rotate_mode == 3))
1034 {
1035 pos[0] = tile->tile_start_x_coor<<8;
1036 pos[1] = tile->tile_start_y_coor<<8;
1037
1038 pos[2] = pos[0];
1039 pos[3] = pos[1] + tile->tile_h;
1040
1041 pos[4] = pos[0] + tile->tile_w;
1042 pos[5] = pos[1] + tile->tile_h;
1043
1044 pos[6] = pos[0] + tile->tile_w;
1045 pos[7] = pos[1];
1046
1047 pos[0] >>= 11;
1048 pos[1] >>= 11;
1049
1050 pos[2] >>= 11;
1051 pos[3] >>= 11;
1052
1053 pos[4] >>= 11;
1054 pos[5] >>= 11;
1055
1056 pos[6] >>= 11;
1057 pos[7] >>= 11;
1058
1059 xmax = (MAX(MAX(MAX(pos[0], pos[2]), pos[4]), pos[6]) + 1);
1060 xmin = (MIN(MIN(MIN(pos[0], pos[2]), pos[4]), pos[6]));
1061
1062 ymax = (MAX(MAX(MAX(pos[1], pos[3]), pos[5]), pos[7]) + 1);
1063 ymin = (MIN(MIN(MIN(pos[1], pos[3]), pos[5]), pos[7]));
1064
1065 xp = xmin + msg->src.x_offset;
1066 yp = ymin + msg->src.y_offset;
1067
1068 if (!((xmax < 0)||(xmin > msg->src.act_w - 1)||(ymax < 0)||(ymin > msg->src.act_h - 1)))
1069 {
1070 xp = CLIP(xp, msg->src.x_offset, msg->src.x_offset + msg->src.act_w - 1);
1071 yp = CLIP(yp, msg->src.y_offset, msg->src.y_offset + msg->src.act_h - 1);
1072 }
1073
1074 switch(msg->src.format)
1075 {
1076 case RK_FORMAT_YCbCr_420_P :
1077 y_addr = msg->src.yrgb_addr + yp*stride + xp;
1078 u_addr = msg->src.uv_addr + (yp>>1)*(stride>>1) + (xp>>1);
1079 v_addr = msg->src.v_addr + (yp>>1)*(stride>>1) + (xp>>1);
1080 break;
1081 case RK_FORMAT_YCbCr_420_SP :
1082 y_addr = msg->src.yrgb_addr + yp*stride + xp;
1083 u_addr = msg->src.uv_addr + (yp>>1)*stride + ((xp>>1)<<1);
1084 break;
1085 case RK_FORMAT_YCbCr_422_P :
1086 y_addr = msg->src.yrgb_addr + yp*stride + xp;
1087 u_addr = msg->src.uv_addr + (yp)*(stride>>1) + (xp>>1);
1088 v_addr = msg->src.v_addr + (yp)*(stride>>1) + (xp>>1);
1089 break;
1090 case RK_FORMAT_YCbCr_422_SP:
1091 y_addr = msg->src.yrgb_addr + yp*stride + xp;
1092 u_addr = msg->src.uv_addr + yp*stride + ((xp>>1)<<1);
1093 break;
1094 case RK_FORMAT_YCrCb_420_P :
1095 y_addr = msg->src.yrgb_addr + yp*stride + xp;
1096 u_addr = msg->src.uv_addr + (yp>>1)*(stride>>1) + (xp>>1);
1097 v_addr = msg->src.v_addr + (yp>>1)*(stride>>1) + (xp>>1);
1098 break;
1099 case RK_FORMAT_YCrCb_420_SP :
1100 y_addr = msg->src.yrgb_addr + yp*stride + xp;
1101 u_addr = msg->src.uv_addr + (yp>>1)*stride + ((xp>>1)<<1);
1102 break;
1103 case RK_FORMAT_YCrCb_422_P :
1104 y_addr = msg->src.yrgb_addr + yp*stride + xp;
1105 u_addr = msg->src.uv_addr + (yp)*(stride>>1) + (xp>>1);
1106 v_addr = msg->src.v_addr + (yp)*(stride>>1) + (xp>>1);
1107 break;
1108 case RK_FORMAT_YCrCb_422_SP:
1109 y_addr = msg->src.yrgb_addr + yp*stride + xp;
1110 u_addr = msg->src.uv_addr + yp*stride + ((xp>>1)<<1);
1111 break;
1112 default :
1113 y_addr = msg->src.yrgb_addr + yp*stride + xp*pixel_width;
1114 break;
1115 }
1116
1117 *bRGA_SRC_Y_MST = y_addr;
1118 *bRGA_SRC_CB_MST = u_addr;
1119 *bRGA_SRC_CR_MST = v_addr;
1120 }
1121
1122 /*dst info*/
1123 pixel_width = RGA_pixel_width_init(msg->dst.format);
1124 stride = (msg->dst.vir_w * pixel_width + 3) & (~3);
1125 *bRGA_DST_MST = (u32)msg->dst.yrgb_addr + (tile->dst_ctrl.y_off * stride) + (tile->dst_ctrl.x_off * pixel_width);
1126 *bRGA_DST_CTR_INFO = (tile->dst_ctrl.w) | ((tile->dst_ctrl.h) << 16);
1127
1128 *bRGA_DST_CTR_INFO |= ((1<<29) | (1<<28));
1129 }
1130
1131
1132
1133
1134 /*************************************************************
1135 Func:
1136 RGA_set_color_palette_reg_info
1137 Description:
1138 fill color palette process some relate reg bit
1139 Author:
1140 ZhangShengqin
1141 Date:
1142 20012-2-2 10:59:25
1143 **************************************************************/
1144
1145 static void
RGA_set_color_palette_reg_info(u8 * base,const struct rga_req * msg)1146 RGA_set_color_palette_reg_info(u8 *base, const struct rga_req *msg)
1147 {
1148 u32 *bRGA_SRC_Y_MST;
1149 u32 p;
1150 s16 x_off, y_off;
1151 u16 src_stride;
1152 u8 shift;
1153 u16 sw, byte_num;
1154
1155 x_off = msg->src.x_offset;
1156 y_off = msg->src.y_offset;
1157
1158 sw = msg->src.vir_w;
1159 shift = 3 - (msg->palette_mode & 3);
1160 byte_num = sw >> shift;
1161 src_stride = (byte_num + 3) & (~3);
1162
1163 p = msg->src.yrgb_addr;
1164 p = p + (x_off>>shift) + y_off*src_stride;
1165
1166 bRGA_SRC_Y_MST = (u32 *)(base + RGA_SRC_Y_MST_OFFSET);
1167 *bRGA_SRC_Y_MST = (u32)p;
1168 }
1169
1170
1171 /*************************************************************
1172 Func:
1173 RGA_set_color_fill_reg_info
1174 Description:
1175 fill color fill process some relate reg bit
1176 Author:
1177 ZhangShengqin
1178 Date:
1179 20012-2-2 10:59:25
1180 **************************************************************/
1181 static void
RGA_set_color_fill_reg_info(u8 * base,const struct rga_req * msg)1182 RGA_set_color_fill_reg_info(u8 *base, const struct rga_req *msg)
1183 {
1184
1185 u32 *bRGA_CP_GR_A;
1186 u32 *bRGA_CP_GR_B;
1187 u32 *bRGA_CP_GR_G;
1188 u32 *bRGA_CP_GR_R;
1189
1190 u32 *bRGA_PAT_CON;
1191
1192 bRGA_CP_GR_A = (u32 *)(base + RGA_CP_GR_A_OFFSET);
1193 bRGA_CP_GR_B = (u32 *)(base + RGA_CP_GR_B_OFFSET);
1194 bRGA_CP_GR_G = (u32 *)(base + RGA_CP_GR_G_OFFSET);
1195 bRGA_CP_GR_R = (u32 *)(base + RGA_CP_GR_R_OFFSET);
1196
1197 bRGA_PAT_CON = (u32 *)(base + RGA_PAT_CON_OFFSET);
1198
1199 *bRGA_CP_GR_A = (msg->gr_color.gr_x_a & 0xffff) | (msg->gr_color.gr_y_a << 16);
1200 *bRGA_CP_GR_B = (msg->gr_color.gr_x_b & 0xffff) | (msg->gr_color.gr_y_b << 16);
1201 *bRGA_CP_GR_G = (msg->gr_color.gr_x_g & 0xffff) | (msg->gr_color.gr_y_g << 16);
1202 *bRGA_CP_GR_R = (msg->gr_color.gr_x_r & 0xffff) | (msg->gr_color.gr_y_r << 16);
1203
1204 *bRGA_PAT_CON = (msg->pat.vir_w-1) | ((msg->pat.vir_h-1) << 8) | (msg->pat.x_offset << 16) | (msg->pat.y_offset << 24);
1205
1206 }
1207
1208
1209 /*************************************************************
1210 Func:
1211 RGA_set_line_drawing_reg_info
1212 Description:
1213 fill line drawing process some relate reg bit
1214 Author:
1215 ZhangShengqin
1216 Date:
1217 20012-2-2 10:59:25
1218 **************************************************************/
1219
RGA_set_line_drawing_reg_info(u8 * base,const struct rga_req * msg)1220 static s32 RGA_set_line_drawing_reg_info(u8 *base, const struct rga_req *msg)
1221 {
1222 u32 *bRGA_LINE_DRAW;
1223 u32 *bRGA_DST_VIR_INFO;
1224 u32 *bRGA_LINE_DRAW_XY_INFO;
1225 u32 *bRGA_LINE_DRAW_WIDTH;
1226 u32 *bRGA_LINE_DRAWING_COLOR;
1227 u32 *bRGA_LINE_DRAWING_MST;
1228
1229 u32 reg = 0;
1230
1231 s16 x_width, y_width;
1232 u16 abs_x, abs_y, delta;
1233 u16 stride;
1234 u8 pw;
1235 u32 start_addr;
1236 u8 line_dir, dir_major, dir_semi_major;
1237 u16 major_width;
1238
1239 bRGA_LINE_DRAW = (u32 *)(base + RGA_LINE_DRAW_OFFSET);
1240 bRGA_DST_VIR_INFO = (u32 *)(base + RGA_DST_VIR_INFO_OFFSET);
1241 bRGA_LINE_DRAW_XY_INFO = (u32 *)(base + RGA_LINE_DRAW_XY_INFO_OFFSET);
1242 bRGA_LINE_DRAW_WIDTH = (u32 *)(base + RGA_LINE_DRAWING_WIDTH_OFFSET);
1243 bRGA_LINE_DRAWING_COLOR = (u32 *)(base + RGA_LINE_DRAWING_COLOR_OFFSET);
1244 bRGA_LINE_DRAWING_MST = (u32 *)(base + RGA_LINE_DRAWING_MST_OFFSET);
1245
1246 pw = RGA_pixel_width_init(msg->dst.format);
1247
1248 stride = (msg->dst.vir_w * pw + 3) & (~3);
1249
1250 start_addr = msg->dst.yrgb_addr
1251 + (msg->line_draw_info.start_point.y * stride)
1252 + (msg->line_draw_info.start_point.x * pw);
1253
1254 x_width = msg->line_draw_info.start_point.x - msg->line_draw_info.end_point.x;
1255 y_width = msg->line_draw_info.start_point.y - msg->line_draw_info.end_point.y;
1256
1257 abs_x = abs(x_width);
1258 abs_y = abs(y_width);
1259
1260 if (abs_x >= abs_y)
1261 {
1262 if (y_width > 0)
1263 dir_semi_major = 1;
1264 else
1265 dir_semi_major = 0;
1266
1267 if (x_width > 0)
1268 dir_major = 1;
1269 else
1270 dir_major = 0;
1271
1272 if((abs_x == 0)||(abs_y == 0))
1273 delta = 0;
1274 else
1275 delta = (abs_y<<12)/abs_x;
1276
1277 if (delta >> 12)
1278 delta -= 1;
1279
1280 major_width = abs_x;
1281 line_dir = 0;
1282 }
1283 else
1284 {
1285 if (x_width > 0)
1286 dir_semi_major = 1;
1287 else
1288 dir_semi_major = 0;
1289
1290 if (y_width > 0)
1291 dir_major = 1;
1292 else
1293 dir_major = 0;
1294
1295 delta = (abs_x<<12)/abs_y;
1296 major_width = abs_y;
1297 line_dir = 1;
1298 }
1299
1300 reg = (reg & (~m_RGA_LINE_DRAW_MAJOR_WIDTH)) | (s_RGA_LINE_DRAW_MAJOR_WIDTH(major_width));
1301 reg = (reg & (~m_RGA_LINE_DRAW_LINE_DIRECTION)) | (s_RGA_LINE_DRAW_LINE_DIRECTION(line_dir));
1302 reg = (reg & (~m_RGA_LINE_DRAW_LINE_WIDTH)) | (s_RGA_LINE_DRAW_LINE_WIDTH(msg->line_draw_info.line_width - 1));
1303 reg = (reg & (~m_RGA_LINE_DRAW_INCR_VALUE)) | (s_RGA_LINE_DRAW_INCR_VALUE(delta));
1304 reg = (reg & (~m_RGA_LINE_DRAW_DIR_SEMI_MAJOR)) | (s_RGA_LINE_DRAW_DIR_SEMI_MAJOR(dir_semi_major));
1305 reg = (reg & (~m_RGA_LINE_DRAW_DIR_MAJOR)) | (s_RGA_LINE_DRAW_DIR_MAJOR(dir_major));
1306 reg = (reg & (~m_RGA_LINE_DRAW_LAST_POINT)) | (s_RGA_LINE_DRAW_LAST_POINT(msg->line_draw_info.flag >> 1));
1307 reg = (reg & (~m_RGA_LINE_DRAW_ANTI_ALISING)) | (s_RGA_LINE_DRAW_ANTI_ALISING(msg->line_draw_info.flag));
1308
1309 *bRGA_LINE_DRAW = reg;
1310
1311 reg = (msg->line_draw_info.start_point.x & 0xfff) | ((msg->line_draw_info.start_point.y & 0xfff) << 16);
1312 *bRGA_LINE_DRAW_XY_INFO = reg;
1313
1314 *bRGA_LINE_DRAW_WIDTH = msg->dst.vir_w;
1315
1316 *bRGA_LINE_DRAWING_COLOR = msg->line_draw_info.color;
1317
1318 *bRGA_LINE_DRAWING_MST = (u32)start_addr;
1319
1320 return 0;
1321 }
1322
1323
1324 /*full*/
1325 static s32
RGA_set_filter_reg_info(u8 * base,const struct rga_req * msg)1326 RGA_set_filter_reg_info(u8 *base, const struct rga_req *msg)
1327 {
1328 u32 *bRGA_BLUR_SHARP_INFO;
1329 u32 reg = 0;
1330
1331 bRGA_BLUR_SHARP_INFO = (u32 *)(base + RGA_ALPHA_CON_OFFSET);
1332
1333 reg = *bRGA_BLUR_SHARP_INFO;
1334
1335 reg = ((reg & (~m_RGA_BLUR_SHARP_FILTER_TYPE)) | (s_RGA_BLUR_SHARP_FILTER_TYPE(msg->bsfilter_flag & 3)));
1336 reg = ((reg & (~m_RGA_BLUR_SHARP_FILTER_MODE)) | (s_RGA_BLUR_SHARP_FILTER_MODE(msg->bsfilter_flag >>2)));
1337
1338 *bRGA_BLUR_SHARP_INFO = reg;
1339
1340 return 0;
1341 }
1342
1343
1344 /*full*/
1345 static s32
RGA_set_pre_scale_reg_info(u8 * base,const struct rga_req * msg)1346 RGA_set_pre_scale_reg_info(u8 *base, const struct rga_req *msg)
1347 {
1348 u32 *bRGA_PRE_SCALE_INFO;
1349 u32 reg = 0;
1350 u32 h_ratio = 0;
1351 u32 v_ratio = 0;
1352 u32 ps_yuv_flag = 0;
1353 u32 src_width, src_height;
1354 u32 dst_width, dst_height;
1355
1356 src_width = msg->src.act_w;
1357 src_height = msg->src.act_h;
1358
1359 dst_width = msg->dst.act_w;
1360 dst_height = msg->dst.act_h;
1361
1362 if((dst_width == 0) || (dst_height == 0))
1363 {
1364 printk("pre scale reg info error ratio is divide zero\n");
1365 return -EINVAL;
1366 }
1367
1368 h_ratio = (src_width <<16) / dst_width;
1369 v_ratio = (src_height<<16) / dst_height;
1370
1371 if (h_ratio <= (1<<16))
1372 h_ratio = 0;
1373 else if (h_ratio <= (2<<16))
1374 h_ratio = 1;
1375 else if (h_ratio <= (4<<16))
1376 h_ratio = 2;
1377 else if (h_ratio <= (8<<16))
1378 h_ratio = 3;
1379
1380 if (v_ratio <= (1<<16))
1381 v_ratio = 0;
1382 else if (v_ratio <= (2<<16))
1383 v_ratio = 1;
1384 else if (v_ratio <= (4<<16))
1385 v_ratio = 2;
1386 else if (v_ratio <= (8<<16))
1387 v_ratio = 3;
1388
1389 if(msg->src.format == msg->dst.format)
1390 ps_yuv_flag = 0;
1391 else
1392 ps_yuv_flag = 1;
1393
1394 bRGA_PRE_SCALE_INFO = (u32 *)(base + RGA_ALPHA_CON_OFFSET);
1395
1396 reg = *bRGA_PRE_SCALE_INFO;
1397 reg = ((reg & (~m_RGA_PRE_SCALE_HOR_RATIO)) | (s_RGA_PRE_SCALE_HOR_RATIO((u8)h_ratio)));
1398 reg = ((reg & (~m_RGA_PRE_SCALE_VER_RATIO)) | (s_RGA_PRE_SCALE_VER_RATIO((u8)v_ratio)));
1399 reg = ((reg & (~m_RGA_PRE_SCALE_OUTPUT_FORMAT)) | (s_RGA_PRE_SCALE_OUTPUT_FORMAT(ps_yuv_flag)));
1400
1401 *bRGA_PRE_SCALE_INFO = reg;
1402
1403 return 0;
1404 }
1405
1406
1407
1408 /*full*/
1409 static int
RGA_set_update_palette_table_reg_info(u8 * base,const struct rga_req * msg)1410 RGA_set_update_palette_table_reg_info(u8 *base, const struct rga_req *msg)
1411 {
1412 u32 *bRGA_LUT_MST;
1413
1414 if (!msg->LUT_addr) {
1415 return -1;
1416 }
1417
1418 bRGA_LUT_MST = (u32 *)(base + RGA_LUT_MST_OFFSET);
1419
1420 *bRGA_LUT_MST = (u32)msg->LUT_addr;
1421
1422 return 0;
1423 }
1424
1425
1426
1427 /*full*/
1428 static int
RGA_set_update_patten_buff_reg_info(u8 * base,const struct rga_req * msg)1429 RGA_set_update_patten_buff_reg_info(u8 *base, const struct rga_req *msg)
1430 {
1431 u32 *bRGA_PAT_MST;
1432 u32 *bRGA_PAT_CON;
1433 u32 *bRGA_PAT_START_POINT;
1434 u32 reg = 0;
1435 rga_img_info_t *pat;
1436
1437 pat = (rga_img_info_t *)&msg->pat;
1438
1439 bRGA_PAT_START_POINT = (u32 *)(base + RGA_PAT_START_POINT_OFFSET);
1440 bRGA_PAT_MST = (u32 *)(base + RGA_PAT_MST_OFFSET);
1441 bRGA_PAT_CON = (u32 *)(base + RGA_PAT_CON_OFFSET);
1442
1443 if ( !pat->yrgb_addr ) {
1444 return -1;
1445 }
1446 *bRGA_PAT_MST = (u32)pat->yrgb_addr;
1447
1448 if ((pat->vir_w > 256)||(pat->x_offset > 256)||(pat->y_offset > 256)) {
1449 return -1;
1450 }
1451 *bRGA_PAT_START_POINT = (pat->vir_w * pat->y_offset) + pat->x_offset;
1452
1453 reg = (pat->vir_w-1) | ((pat->vir_h-1) << 8) | (pat->x_offset << 16) | (pat->y_offset << 24);
1454 *bRGA_PAT_CON = reg;
1455
1456 return 0;
1457 }
1458
1459
1460 /*************************************************************
1461 Func:
1462 RGA_set_mmu_ctrl_reg_info
1463 Description:
1464 fill mmu relate some reg info
1465 Author:
1466 ZhangShengqin
1467 Date:
1468 20012-2-2 10:59:25
1469 **************************************************************/
1470
1471 static s32
RGA_set_mmu_ctrl_reg_info(u8 * base,const struct rga_req * msg)1472 RGA_set_mmu_ctrl_reg_info(u8 *base, const struct rga_req *msg)
1473 {
1474 u32 *RGA_MMU_TLB, *RGA_MMU_CTRL_ADDR;
1475 u32 mmu_addr;
1476 u8 TLB_size, mmu_enable, src_flag, dst_flag, CMD_flag;
1477 u32 reg = 0;
1478
1479 mmu_addr = (u32)msg->mmu_info.base_addr;
1480 TLB_size = (msg->mmu_info.mmu_flag >> 4) & 0x3;
1481 mmu_enable = msg->mmu_info.mmu_flag & 0x1;
1482
1483 src_flag = (msg->mmu_info.mmu_flag >> 1) & 0x1;
1484 dst_flag = (msg->mmu_info.mmu_flag >> 2) & 0x1;
1485 CMD_flag = (msg->mmu_info.mmu_flag >> 3) & 0x1;
1486
1487 RGA_MMU_TLB = (u32 *)(base + RGA_MMU_TLB_OFFSET);
1488 RGA_MMU_CTRL_ADDR = (u32 *)(base + RGA_FADING_CON_OFFSET);
1489
1490 reg = ((reg & (~m_RGA_MMU_CTRL_TLB_ADDR)) | s_RGA_MMU_CTRL_TLB_ADDR(mmu_addr));
1491 *RGA_MMU_TLB = reg;
1492
1493 reg = *RGA_MMU_CTRL_ADDR;
1494 reg = ((reg & (~m_RGA_MMU_CTRL_PAGE_TABLE_SIZE)) | s_RGA_MMU_CTRL_PAGE_TABLE_SIZE(TLB_size));
1495 reg = ((reg & (~m_RGA_MMU_CTRL_MMU_ENABLE)) | s_RGA_MMU_CTRL_MMU_ENABLE(mmu_enable));
1496 reg = ((reg & (~m_RGA_MMU_CTRL_SRC_FLUSH)) | s_RGA_MMU_CTRL_SRC_FLUSH(1));
1497 reg = ((reg & (~m_RGA_MMU_CTRL_DST_FLUSH)) | s_RGA_MMU_CTRL_DST_FLUSH(1));
1498 reg = ((reg & (~m_RGA_MMU_CTRL_CMD_CHAN_FLUSH)) | s_RGA_MMU_CTRL_CMD_CHAN_FLUSH(1));
1499 *RGA_MMU_CTRL_ADDR = reg;
1500
1501 return 0;
1502 }
1503
1504
1505
1506 /*************************************************************
1507 Func:
1508 RGA_gen_reg_info
1509 Description:
1510 Generate RGA command reg list from rga_req struct.
1511 Author:
1512 ZhangShengqin
1513 Date:
1514 20012-2-2 10:59:25
1515 **************************************************************/
1516 int
RGA_gen_reg_info(const struct rga_req * msg,unsigned char * base)1517 RGA_gen_reg_info(const struct rga_req *msg, unsigned char *base)
1518 {
1519 TILE_INFO tile;
1520
1521 memset(base, 0x0, 28*4);
1522 RGA_set_mode_ctrl(base, msg);
1523
1524 switch(msg->render_mode)
1525 {
1526 case bitblt_mode :
1527 RGA_set_alpha_rop(base, msg);
1528 RGA_set_src(base, msg);
1529 RGA_set_dst(base, msg);
1530 RGA_set_color(base, msg);
1531 RGA_set_fading(base, msg);
1532 RGA_set_pat(base, msg);
1533 matrix_cal(msg, &tile);
1534 dst_ctrl_cal(msg, &tile);
1535 src_tile_info_cal(msg, &tile);
1536 RGA_set_bitblt_reg_info(base, msg, &tile);
1537 break;
1538 case color_palette_mode :
1539 RGA_set_src(base, msg);
1540 RGA_set_dst(base, msg);
1541 RGA_set_color(base, msg);
1542 RGA_set_color_palette_reg_info(base, msg);
1543 break;
1544 case color_fill_mode :
1545 RGA_set_alpha_rop(base, msg);
1546 RGA_set_dst(base, msg);
1547 RGA_set_color(base, msg);
1548 RGA_set_pat(base, msg);
1549 RGA_set_color_fill_reg_info(base, msg);
1550 break;
1551 case line_point_drawing_mode :
1552 RGA_set_alpha_rop(base, msg);
1553 RGA_set_dst(base, msg);
1554 RGA_set_color(base, msg);
1555 RGA_set_line_drawing_reg_info(base, msg);
1556 break;
1557 case blur_sharp_filter_mode :
1558 RGA_set_src(base, msg);
1559 RGA_set_dst(base, msg);
1560 RGA_set_filter_reg_info(base, msg);
1561 break;
1562 case pre_scaling_mode :
1563 RGA_set_src(base, msg);
1564 RGA_set_dst(base, msg);
1565 if(RGA_set_pre_scale_reg_info(base, msg) == -EINVAL)
1566 return -1;
1567 break;
1568 case update_palette_table_mode :
1569 if (RGA_set_update_palette_table_reg_info(base, msg)) {
1570 return -1;
1571 }
1572 break;
1573 case update_patten_buff_mode:
1574 if (RGA_set_update_patten_buff_reg_info(base, msg)){
1575 return -1;
1576 }
1577
1578 break;
1579 }
1580
1581 RGA_set_mmu_ctrl_reg_info(base, msg);
1582
1583 return 0;
1584 }
1585
1586
1587
1588