1 /*
2 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
3 *
4 * SPDX-License-Identifier: GPL-2.0
5 */
6 #include <linux/compat.h>
7 #include <linux/delay.h>
8 #include <linux/kernel.h>
9 #include <linux/string.h>
10
11 #include "rkflash_debug.h"
12 #include "sfc_nor.h"
13
14 static struct flash_info spi_flash_tbl[] = {
15 /* GD25Q40B */
16 { 0xc84013, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x05, 10, 9, 0 },
17 /* GD25Q32B */
18 { 0xc84016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 13, 9, 0 },
19 /* GD25Q64B/C/E */
20 { 0xc84017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 },
21 /* GD25Q127C and GD25Q128C/E */
22 { 0xc84018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 },
23 /* GD25Q256B/C/D/E */
24 { 0xc84019, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1C, 16, 6, 0 },
25 /* GD25Q512MC */
26 { 0xc84020, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1C, 17, 6, 0 },
27 /* GD25LQ64C */
28 { 0xc86017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 9, 0 },
29 /* GD25LQ128 */
30 { 0xc86018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 15, 9, 0 },
31 /* GD25LQ32E */
32 { 0xc86016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 13, 9, 0 },
33 /* GD25B512MEYIG */
34 { 0xc8471A, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x1C, 17, 0, 0 },
35 /* GD55B01GE */
36 { 0xc8471B, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x1C, 18, 0, 0 },
37 /* GD25LQ255E and GD25LQ256C */
38 { 0xc86019, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x1D, 16, 9, 0 },
39 /* GD25LB512MEYIG */
40 { 0xc8671A, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x1C, 17, 0, 0 },
41 /* GD55LB01GEFIRR */
42 { 0xc8671B, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x1C, 18, 0, 0 },
43 /* GD55LT01GEFIRT */
44 { 0xc8661B, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x1C, 18, 0, 0 },
45 /* GD25LB256EYIGR */
46 { 0xc86719, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x1C, 16, 0, 0 },
47
48 /* W25Q32JV */
49 { 0xef4016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 9, 0 },
50 /* W25Q64JVSSIQ */
51 { 0xef4017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 },
52 /* W25Q128FV and W25Q128JV*/
53 { 0xef4018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 },
54 /* W25Q256F/J */
55 { 0xef4019, 128, 8, 0x13, 0x02, 0x6C, 0x32, 0x20, 0xD8, 0x3C, 16, 9, 0 },
56 /* W25Q32JW */
57 { 0xef6016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 9, 0 },
58 /* W25Q64FWSSIG */
59 { 0xef6017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 },
60 /* W25Q128JWSQ */
61 { 0xef6018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 },
62 /* W25Q256JWEQ*/
63 { 0xef6019, 128, 8, 0x13, 0x02, 0x6C, 0x32, 0x20, 0xD8, 0x3C, 16, 9, 0 },
64 /* W25Q128JVSIM */
65 { 0xef7018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 },
66 /* W25Q256JVEM */
67 { 0xef7019, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x3C, 16, 9, 0 },
68
69 /* MX25L3233FM2I-08G */
70 { 0xc22016, 128, 8, 0x03, 0x02, 0x6B, 0x38, 0x20, 0xD8, 0x0E, 13, 6, 0 },
71 /* MX25L6433F */
72 { 0xc22017, 128, 8, 0x03, 0x02, 0x6B, 0x38, 0x20, 0xD8, 0x0E, 14, 6, 0 },
73 /* MX25L12835E/F MX25L12833FMI-10G */
74 { 0xc22018, 128, 8, 0x03, 0x02, 0x6B, 0x38, 0x20, 0xD8, 0x0E, 15, 6, 0 },
75 /* MX25L25635E/F MX25L25645G MX25L25645GMI-08G */
76 { 0xc22019, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1E, 16, 6, 0 },
77 /* MX25L51245GMI */
78 { 0xc2201a, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1E, 17, 6, 0 },
79 /* MX25U51245G */
80 { 0xc2253a, 128, 8, 0x0C, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1E, 17, 6, 0 },
81 /* MX25U3232F */
82 { 0xc22536, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0E, 13, 6, 0 },
83 /* MX25U6432F */
84 { 0xc22537, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0E, 14, 6, 0 },
85 /* MX25U12832F */
86 { 0xc22538, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0E, 15, 6, 0 },
87 /* MX25U25645GZ4I-00 */
88 { 0xc22539, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1E, 16, 6, 0 },
89
90 /* XM25QH32C */
91 { 0x204016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 9, 0 },
92 /* XM25QH64C */
93 { 0x204017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 },
94 /* XM25QH128C */
95 { 0x204018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x05, 15, 9, 0 },
96 /* XM25QH256C */
97 { 0x204019, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x1C, 16, 9, 0 },
98 /* XM25QH64B */
99 { 0x206017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 6, 0 },
100 /* XM25QH128B */
101 { 0x206018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 15, 6, 0 },
102 /* XM25QH(QU)256B */
103 { 0x206019, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1D, 16, 6, 0 },
104 /* XM25QH64A */
105 { 0x207017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 0, 0 },
106 /* XM25QU128C */
107 { 0x204118, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 },
108 /* XM25QU64C */
109 { 0x204117, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 },
110
111 /* XT25F128A XM25QH128A */
112 { 0x207018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 0, 0 },
113 /* XT25F64BSSIGU-5 XT25F64F */
114 { 0x0b4017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 9, 0 },
115 /* XT25F128BSSIGU */
116 { 0x0b4018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 15, 9, 0 },
117 /* XT25F256BSFIGU */
118 { 0x0b4019, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x1C, 16, 9, 0 },
119 /* XT25F32BS XT25F32F */
120 { 0x0b4016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 13, 9, 0 },
121 /* XT25F16BS */
122 { 0x0b4015, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 12, 9, 0 },
123 /* XT25Q64D */
124 { 0x0b6017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 },
125 /* XT25Q128D */
126 { 0x0b6018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 },
127
128 /* EN25QH64A */
129 { 0x1c7017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 0, 0 },
130 /* EN25QH128A */
131 { 0x1c7018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 0, 0 },
132 /* EN25QH32B */
133 { 0x1c7016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 0, 0 },
134 /* EN25S32A */
135 { 0x1c3816, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 0, 0 },
136 /* EN25S64A */
137 { 0x1c3817, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 0, 0 },
138 /* EN25QH256A */
139 { 0x1c7019, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x1C, 16, 0, 0 },
140 /* EN25QX256A */
141 { 0x1c7119, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x1C, 16, 9, 0 },
142 /* EN25QX128A */
143 { 0x1c7118, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 },
144
145 /* P25Q64H */
146 { 0x856017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 },
147 /* P25Q128H */
148 { 0x856018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 },
149 /* P25Q16H-SUH-IT */
150 { 0x856015, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 12, 9, 0 },
151 /* P25Q32SL P25Q32SH-SSH-IT */
152 { 0x856016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 9, 0 },
153 /* PY25Q64HA */
154 { 0x852017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 },
155 /* PY25Q128H */
156 { 0x852018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 },
157 /* PY25Q256H */
158 { 0x852019, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x1C, 16, 9, 0 },
159 /* PY25Q128LA */
160 { 0x856518, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 },
161
162 /* ZB25VQ64 */
163 { 0x5e4017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 },
164 /* ZB25VQ128 */
165 { 0x5e4018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 },
166 /* ZB25LQ128 */
167 { 0x5e5018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 },
168
169 /* BH25Q128AS, BY25Q128AS */
170 { 0x684018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 },
171 /* BH25Q64BS */
172 { 0x684017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 },
173
174 /* FM25Q128A */
175 { 0xA14018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 },
176 /* FM25Q64-SOB-T-G */
177 { 0xA14017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 },
178 /* FM25Q256I3 */
179 { 0xA14019, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x1C, 16, 9, 0 },
180
181 /* FM25Q64A */
182 { 0xf83217, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 9, 0 },
183 /* FM25M4AA */
184 { 0xf84218, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 15, 9, 0 },
185 /* FM25M64C */
186 { 0xf84317, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 9, 0 },
187
188 /* DS25M4AB-1AIB4 */
189 { 0xe54218, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 },
190
191 /* GM25Q128A */
192 { 0x1c4018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 },
193
194 /* IS25LP512M */
195 { 0x9D601A, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x3C, 17, 6, 0 },
196 /* IS25WP512M */
197 { 0x9D701A, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x3C, 17, 6, 0 },
198
199 /* BY25Q256FSEIG */
200 { 0x684919, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x1C, 16, 9, 0 },
201
202 /* NM25Q128EVB */
203 { 0x522118, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 10, 0 },
204
205 /* GT25Q40D */
206 { 0xc44013, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 10, 9, 0 },
207 };
208
snor_write_en(void)209 static int snor_write_en(void)
210 {
211 int ret;
212 struct rk_sfc_op op;
213
214 op.sfcmd.d32 = 0;
215 op.sfcmd.b.cmd = CMD_WRITE_EN;
216
217 op.sfctrl.d32 = 0;
218
219 ret = sfc_request(&op, 0, NULL, 0);
220
221 return ret;
222 }
223
snor_reset_device(void)224 int snor_reset_device(void)
225 {
226 struct rk_sfc_op op;
227
228 op.sfcmd.d32 = 0;
229 op.sfcmd.b.cmd = CMD_ENABLE_RESER;
230
231 op.sfctrl.d32 = 0;
232 sfc_request(&op, 0, NULL, 0);
233
234 op.sfcmd.d32 = 0;
235 op.sfcmd.b.cmd = CMD_RESET_DEVICE;
236
237 op.sfctrl.d32 = 0;
238 sfc_request(&op, 0, NULL, 0);
239 /* tRST=30us , delay 1ms here */
240 sfc_delay(1000);
241
242 return SFC_OK;
243 }
244
snor_enter_4byte_mode(void)245 static int snor_enter_4byte_mode(void)
246 {
247 int ret;
248 struct rk_sfc_op op;
249
250 op.sfcmd.d32 = 0;
251 op.sfcmd.b.cmd = CMD_ENTER_4BYTE_MODE;
252
253 op.sfctrl.d32 = 0;
254
255 ret = sfc_request(&op, 0, NULL, 0);
256 return ret;
257 }
258
snor_read_status(u32 reg_index,u8 * status)259 static int snor_read_status(u32 reg_index, u8 *status)
260 {
261 int ret;
262 struct rk_sfc_op op;
263 u8 read_stat_cmd[] = {CMD_READ_STATUS,
264 CMD_READ_STATUS2, CMD_READ_STATUS3};
265 op.sfcmd.d32 = 0;
266 op.sfcmd.b.cmd = read_stat_cmd[reg_index];
267
268 op.sfctrl.d32 = 0;
269 ret = sfc_request(&op, 0, status, 1);
270
271 return ret;
272 }
273
snor_wait_busy(int timeout)274 static int snor_wait_busy(int timeout)
275 {
276 int ret;
277 struct rk_sfc_op op;
278 int i;
279 u32 status;
280
281 op.sfcmd.d32 = 0;
282 op.sfcmd.b.cmd = CMD_READ_STATUS;
283
284 op.sfctrl.d32 = 0;
285
286 for (i = 0; i < timeout; i++) {
287 ret = sfc_request(&op, 0, &status, 1);
288 if (ret != SFC_OK)
289 return ret;
290
291 if ((status & 0x01) == 0)
292 return SFC_OK;
293
294 sfc_delay(1);
295 }
296 rkflash_print_error("%s error %x\n", __func__, timeout);
297
298 return SFC_BUSY_TIMEOUT;
299 }
300
snor_write_status2(u32 reg_index,u8 status)301 static int snor_write_status2(u32 reg_index, u8 status)
302 {
303 int ret;
304 struct rk_sfc_op op;
305 u8 status2[2];
306
307 status2[reg_index] = status;
308 if (reg_index == 0)
309 ret = snor_read_status(2, &status2[1]);
310 else
311 ret = snor_read_status(0, &status2[0]);
312 if (ret != SFC_OK)
313 return ret;
314
315 snor_write_en();
316
317 op.sfcmd.d32 = 0;
318 op.sfcmd.b.cmd = CMD_WRITE_STATUS;
319 op.sfcmd.b.rw = SFC_WRITE;
320
321 op.sfctrl.d32 = 0;
322
323 ret = sfc_request(&op, 0, &status2[0], 2);
324 if (ret != SFC_OK)
325 return ret;
326
327 ret = snor_wait_busy(10000); /* 10ms */
328
329 return ret;
330 }
331
snor_write_status1(u32 reg_index,u8 status)332 static int snor_write_status1(u32 reg_index, u8 status)
333 {
334 int ret;
335 struct rk_sfc_op op;
336 u8 status2[2];
337 u8 read_index;
338
339 status2[reg_index] = status;
340 read_index = (reg_index == 0) ? 1 : 0;
341 ret = snor_read_status(read_index, &status2[read_index]);
342 if (ret != SFC_OK)
343 return ret;
344
345 snor_write_en();
346
347 op.sfcmd.d32 = 0;
348 op.sfcmd.b.cmd = CMD_WRITE_STATUS;
349 op.sfcmd.b.rw = SFC_WRITE;
350
351 op.sfctrl.d32 = 0;
352
353 ret = sfc_request(&op, 0, &status2[0], 2);
354 if (ret != SFC_OK)
355 return ret;
356
357 ret = snor_wait_busy(10000); /* 10ms */
358
359 return ret;
360 }
361
snor_write_status(u32 reg_index,u8 status)362 static int snor_write_status(u32 reg_index, u8 status)
363 {
364 int ret;
365 struct rk_sfc_op op;
366 u8 write_stat_cmd[] = {CMD_WRITE_STATUS,
367 CMD_WRITE_STATUS2, CMD_WRITE_STATUS3};
368 snor_write_en();
369 op.sfcmd.d32 = 0;
370 op.sfcmd.b.cmd = write_stat_cmd[reg_index];
371 op.sfcmd.b.rw = SFC_WRITE;
372
373 op.sfctrl.d32 = 0;
374
375 ret = sfc_request(&op, 0, &status, 1);
376 if (ret != SFC_OK)
377 return ret;
378
379 ret = snor_wait_busy(10000); /* 10ms */
380
381 return ret;
382 }
383
snor_erase(struct SFNOR_DEV * p_dev,u32 addr,enum NOR_ERASE_TYPE erase_type)384 int snor_erase(struct SFNOR_DEV *p_dev,
385 u32 addr,
386 enum NOR_ERASE_TYPE erase_type)
387 {
388 int ret;
389 struct rk_sfc_op op;
390 int timeout[] = {400, 2000, 40000}; /* ms */
391
392 rkflash_print_dio("%s %x %x\n", __func__, addr, erase_type);
393
394 if (erase_type > ERASE_CHIP)
395 return SFC_PARAM_ERR;
396
397 op.sfcmd.d32 = 0;
398 if (erase_type == ERASE_BLOCK64K)
399 op.sfcmd.b.cmd = p_dev->blk_erase_cmd;
400 else if (erase_type == ERASE_SECTOR)
401 op.sfcmd.b.cmd = p_dev->sec_erase_cmd;
402 else
403 op.sfcmd.b.cmd = CMD_CHIP_ERASE;
404
405 op.sfcmd.b.addrbits = (erase_type != ERASE_CHIP) ?
406 SFC_ADDR_24BITS : SFC_ADDR_0BITS;
407 if (p_dev->addr_mode == ADDR_MODE_4BYTE && erase_type != ERASE_CHIP)
408 op.sfcmd.b.addrbits = SFC_ADDR_32BITS;
409 op.sfcmd.b.rw = SFC_WRITE;
410
411 op.sfctrl.d32 = 0;
412
413 snor_write_en();
414
415 ret = sfc_request(&op, addr, NULL, 0);
416 if (ret != SFC_OK)
417 return ret;
418
419 ret = snor_wait_busy(timeout[erase_type] * 1000);
420 return ret;
421 }
422
snor_prog_page(struct SFNOR_DEV * p_dev,u32 addr,void * p_data,u32 size)423 int snor_prog_page(struct SFNOR_DEV *p_dev,
424 u32 addr,
425 void *p_data,
426 u32 size)
427 {
428 int ret;
429 struct rk_sfc_op op;
430
431 rkflash_print_dio("%s %x %x\n", __func__, addr, *(u32 *)(p_data));
432
433 op.sfcmd.d32 = 0;
434 op.sfcmd.b.cmd = p_dev->prog_cmd;
435 op.sfcmd.b.addrbits = SFC_ADDR_24BITS;
436 op.sfcmd.b.rw = SFC_WRITE;
437
438 op.sfctrl.d32 = 0;
439 op.sfctrl.b.datalines = p_dev->prog_lines;
440 op.sfctrl.b.enbledma = 1;
441 op.sfctrl.b.addrlines = p_dev->prog_addr_lines;
442
443 if (p_dev->addr_mode == ADDR_MODE_4BYTE)
444 op.sfcmd.b.addrbits = SFC_ADDR_32BITS;
445
446 snor_write_en();
447
448 ret = sfc_request(&op, addr, p_data, size);
449 if (ret != SFC_OK)
450 return ret;
451
452 ret = snor_wait_busy(10000);
453
454 return ret;
455 }
456
snor_prog(struct SFNOR_DEV * p_dev,u32 addr,void * p_data,u32 size)457 static int snor_prog(struct SFNOR_DEV *p_dev, u32 addr, void *p_data, u32 size)
458 {
459 int ret = SFC_OK;
460 u32 page_size, len;
461 u8 *p_buf = (u8 *)p_data;
462
463 page_size = NOR_PAGE_SIZE;
464 while (size) {
465 len = page_size < size ? page_size : size;
466 ret = snor_prog_page(p_dev, addr, p_buf, len);
467 if (ret != SFC_OK)
468 return ret;
469
470 size -= len;
471 addr += len;
472 p_buf += len;
473 }
474
475 return ret;
476 }
477
snor_enable_QE(struct SFNOR_DEV * p_dev)478 static int snor_enable_QE(struct SFNOR_DEV *p_dev)
479 {
480 int ret = SFC_OK;
481 int reg_index;
482 int bit_offset;
483 u8 status;
484
485 reg_index = p_dev->QE_bits >> 3;
486 bit_offset = p_dev->QE_bits & 0x7;
487 ret = snor_read_status(reg_index, &status);
488 if (ret != SFC_OK)
489 return ret;
490
491 if (status & (1 << bit_offset)) /* is QE bit set */
492 return SFC_OK;
493
494 status |= (1 << bit_offset);
495
496 return p_dev->write_status(reg_index, status);
497 }
498
snor_disable_QE(struct SFNOR_DEV * p_dev)499 int snor_disable_QE(struct SFNOR_DEV *p_dev)
500 {
501 int ret = SFC_OK;
502 int reg_index;
503 int bit_offset;
504 u8 status;
505
506 reg_index = p_dev->QE_bits >> 3;
507 bit_offset = p_dev->QE_bits & 0x7;
508 ret = snor_read_status(reg_index, &status);
509 if (ret != SFC_OK)
510 return ret;
511
512 if (!(status & (1 << bit_offset)))
513 return SFC_OK;
514
515 status &= ~(1 << bit_offset);
516
517 return p_dev->write_status(reg_index, status);
518 }
519
snor_read_data(struct SFNOR_DEV * p_dev,u32 addr,void * p_data,u32 size)520 int snor_read_data(struct SFNOR_DEV *p_dev,
521 u32 addr,
522 void *p_data,
523 u32 size)
524 {
525 int ret;
526 struct rk_sfc_op op;
527
528 op.sfcmd.d32 = 0;
529 op.sfcmd.b.cmd = p_dev->read_cmd;
530 op.sfcmd.b.addrbits = SFC_ADDR_24BITS;
531
532 op.sfctrl.d32 = 0;
533 op.sfctrl.b.datalines = p_dev->read_lines;
534 if (!(size & 0x3) && size >= 4)
535 op.sfctrl.b.enbledma = 1;
536
537 if (p_dev->read_cmd == CMD_FAST_READ_X1 ||
538 p_dev->read_cmd == CMD_PAGE_FASTREAD4B ||
539 p_dev->read_cmd == CMD_FAST_READ_X4 ||
540 p_dev->read_cmd == CMD_FAST_READ_X2 ||
541 p_dev->read_cmd == CMD_FAST_4READ_X4) {
542 op.sfcmd.b.dummybits = 8;
543 } else if (p_dev->read_cmd == CMD_FAST_READ_A4) {
544 op.sfcmd.b.addrbits = SFC_ADDR_32BITS;
545 addr = (addr << 8) | 0xFF; /* Set M[7:0] = 0xFF */
546 op.sfcmd.b.dummybits = 4;
547 op.sfctrl.b.addrlines = SFC_4BITS_LINE;
548 }
549
550 if (p_dev->addr_mode == ADDR_MODE_4BYTE)
551 op.sfcmd.b.addrbits = SFC_ADDR_32BITS;
552
553 ret = sfc_request(&op, addr, p_data, size);
554 rkflash_print_dio("%s %x %x\n", __func__, addr, *(u32 *)(p_data));
555
556 return ret;
557 }
558
snor_read(struct SFNOR_DEV * p_dev,u32 sec,u32 n_sec,void * p_data)559 int snor_read(struct SFNOR_DEV *p_dev, u32 sec, u32 n_sec, void *p_data)
560 {
561 int ret = SFC_OK;
562 u32 addr, size, len;
563 u8 *p_buf = (u8 *)p_data;
564
565 rkflash_print_dio("%s %x %x\n", __func__, sec, n_sec);
566
567 if ((sec + n_sec) > p_dev->capacity)
568 return SFC_PARAM_ERR;
569
570 addr = sec << 9;
571 size = n_sec << 9;
572 while (size) {
573 len = size < p_dev->max_iosize ? size : p_dev->max_iosize;
574 ret = snor_read_data(p_dev, addr, p_buf, len);
575 if (ret != SFC_OK) {
576 rkflash_print_error("snor_read_data %x ret= %x\n",
577 addr >> 9, ret);
578 goto out;
579 }
580
581 size -= len;
582 addr += len;
583 p_buf += len;
584 }
585 out:
586 if (!ret)
587 ret = n_sec;
588
589 return ret;
590 }
591
snor_write(struct SFNOR_DEV * p_dev,u32 sec,u32 n_sec,void * p_data)592 int snor_write(struct SFNOR_DEV *p_dev, u32 sec, u32 n_sec, void *p_data)
593 {
594 int ret = SFC_OK;
595 u32 len, blk_size, offset;
596 u8 *p_buf = (u8 *)p_data;
597 u32 total_sec = n_sec;
598
599 rkflash_print_dio("%s %x %x\n", __func__, sec, n_sec);
600
601 if ((sec + n_sec) > p_dev->capacity)
602 return SFC_PARAM_ERR;
603
604 while (n_sec) {
605 if (sec < 512 || sec >= p_dev->capacity - 512)
606 blk_size = 8;
607 else
608 blk_size = p_dev->blk_size;
609
610 offset = (sec & (blk_size - 1));
611 if (!offset) {
612 ret = snor_erase(p_dev, sec << 9, (blk_size == 8) ?
613 ERASE_SECTOR : ERASE_BLOCK64K);
614 if (ret != SFC_OK) {
615 rkflash_print_error("snor_erase %x ret= %x\n",
616 sec, ret);
617 goto out;
618 }
619 }
620 len = (blk_size - offset) < n_sec ?
621 (blk_size - offset) : n_sec;
622 ret = snor_prog(p_dev, sec << 9, p_buf, len << 9);
623 if (ret != SFC_OK) {
624 rkflash_print_error("snor_prog %x ret= %x\n", sec, ret);
625 goto out;
626 }
627 n_sec -= len;
628 sec += len;
629 p_buf += len << 9;
630 }
631 out:
632 if (!ret)
633 ret = total_sec;
634
635 return ret;
636 }
637
snor_read_id(u8 * data)638 int snor_read_id(u8 *data)
639 {
640 int ret;
641 struct rk_sfc_op op;
642
643 op.sfcmd.d32 = 0;
644 op.sfcmd.b.cmd = CMD_READ_JEDECID;
645
646 op.sfctrl.d32 = 0;
647
648 ret = sfc_request(&op, 0, data, 3);
649
650 return ret;
651 }
652
snor_read_parameter(u32 addr,u8 * data)653 static int snor_read_parameter(u32 addr, u8 *data)
654 {
655 int ret;
656 struct rk_sfc_op op;
657
658 op.sfcmd.d32 = 0;
659 op.sfcmd.b.cmd = CMD_READ_PARAMETER;
660 op.sfcmd.b.addrbits = SFC_ADDR_24BITS;
661 op.sfcmd.b.dummybits = 8;
662
663 op.sfctrl.d32 = 0;
664
665 ret = sfc_request(&op, addr, data, 1);
666
667 return ret;
668 }
669
snor_get_capacity(struct SFNOR_DEV * p_dev)670 u32 snor_get_capacity(struct SFNOR_DEV *p_dev)
671 {
672 return p_dev->capacity;
673 }
674
snor_get_flash_info(u8 * flash_id)675 static struct flash_info *snor_get_flash_info(u8 *flash_id)
676 {
677 u32 i;
678 u32 id = (flash_id[0] << 16) | (flash_id[1] << 8) | (flash_id[2] << 0);
679
680 for (i = 0; i < ARRAY_SIZE(spi_flash_tbl); i++) {
681 if (spi_flash_tbl[i].id == id)
682 return &spi_flash_tbl[i];
683 }
684 return NULL;
685 }
686
687 /* Adjust flash info in ram base on parameter */
snor_flash_info_adjust(struct flash_info * spi_flash_info)688 static void *snor_flash_info_adjust(struct flash_info *spi_flash_info)
689 {
690 u32 addr;
691 u8 para_version;
692
693 if (spi_flash_info->id == 0xc84019) {
694 addr = 0x09;
695 snor_read_parameter(addr, ¶_version);
696 if (para_version == 0x06) {
697 spi_flash_info->QE_bits = 9;
698 spi_flash_info->prog_cmd_4 = 0x34;
699 }
700 }
701 return 0;
702 }
703
snor_parse_flash_table(struct SFNOR_DEV * p_dev,struct flash_info * g_spi_flash_info)704 static int snor_parse_flash_table(struct SFNOR_DEV *p_dev,
705 struct flash_info *g_spi_flash_info)
706 {
707 int i, ret;
708
709 if (g_spi_flash_info) {
710 snor_flash_info_adjust(g_spi_flash_info);
711 p_dev->manufacturer = (g_spi_flash_info->id >> 16) & 0xFF;
712 p_dev->mem_type = (g_spi_flash_info->id >> 8) & 0xFF;
713 p_dev->capacity = 1 << g_spi_flash_info->density;
714 p_dev->blk_size = g_spi_flash_info->block_size;
715 p_dev->page_size = NOR_SECS_PAGE;
716 p_dev->read_cmd = g_spi_flash_info->read_cmd;
717 p_dev->prog_cmd = g_spi_flash_info->prog_cmd;
718 p_dev->sec_erase_cmd = g_spi_flash_info->sector_erase_cmd;
719 p_dev->blk_erase_cmd = g_spi_flash_info->block_erase_cmd;
720 p_dev->prog_lines = DATA_LINES_X1;
721 p_dev->read_lines = DATA_LINES_X1;
722 p_dev->QE_bits = g_spi_flash_info->QE_bits;
723 p_dev->addr_mode = ADDR_MODE_3BYTE;
724
725 i = g_spi_flash_info->feature & FEA_READ_STATUE_MASK;
726 if (i == 0)
727 p_dev->write_status = snor_write_status;
728 else if (i == 1)
729 p_dev->write_status = snor_write_status1;
730 else if (i == 2)
731 p_dev->write_status = snor_write_status2;
732
733 if (g_spi_flash_info->feature & FEA_4BIT_READ) {
734 ret = SFC_OK;
735 if (g_spi_flash_info->QE_bits)
736 ret = snor_enable_QE(p_dev);
737 if (ret == SFC_OK) {
738 p_dev->read_lines = DATA_LINES_X4;
739 p_dev->read_cmd = g_spi_flash_info->read_cmd_4;
740 }
741 }
742 if (g_spi_flash_info->feature & FEA_4BIT_PROG &&
743 p_dev->read_lines == DATA_LINES_X4) {
744 p_dev->prog_lines = DATA_LINES_X4;
745 p_dev->prog_cmd = g_spi_flash_info->prog_cmd_4;
746 if ((p_dev->manufacturer == MID_MACRONIX) &&
747 (p_dev->prog_cmd == CMD_PAGE_PROG_A4 ||
748 p_dev->prog_cmd == CMD_PAGE_PROG_4PP))
749 p_dev->prog_addr_lines = DATA_LINES_X4;
750 }
751
752 if (g_spi_flash_info->feature & FEA_4BYTE_ADDR)
753 p_dev->addr_mode = ADDR_MODE_4BYTE;
754
755 if ((g_spi_flash_info->feature & FEA_4BYTE_ADDR_MODE))
756 snor_enter_4byte_mode();
757 }
758
759 return SFC_OK;
760 }
761
snor_init(struct SFNOR_DEV * p_dev)762 int snor_init(struct SFNOR_DEV *p_dev)
763 {
764 struct flash_info *g_spi_flash_info;
765 u8 id_byte[5];
766
767 if (!p_dev)
768 return SFC_PARAM_ERR;
769
770 memset((void *)p_dev, 0, sizeof(struct SFNOR_DEV));
771 p_dev->max_iosize = sfc_get_max_iosize();
772
773 snor_read_id(id_byte);
774 rkflash_print_error("sfc nor id: %x %x %x\n",
775 id_byte[0], id_byte[1], id_byte[2]);
776 if (0xFF == id_byte[0] || 0x00 == id_byte[0] || 0xFF == id_byte[1] || 0x00 == id_byte[1])
777 return SFC_ERROR;
778
779 g_spi_flash_info = snor_get_flash_info(id_byte);
780 if (g_spi_flash_info) {
781 snor_parse_flash_table(p_dev, g_spi_flash_info);
782 } else {
783 pr_err("The device not support yet!\n");
784
785 p_dev->manufacturer = id_byte[0];
786 p_dev->mem_type = id_byte[1];
787 p_dev->capacity = 1 << (id_byte[2] - 9);
788 p_dev->QE_bits = 0;
789 p_dev->blk_size = NOR_SECS_BLK;
790 p_dev->page_size = NOR_SECS_PAGE;
791 p_dev->read_cmd = CMD_READ_DATA;
792 p_dev->prog_cmd = CMD_PAGE_PROG;
793 p_dev->sec_erase_cmd = CMD_SECTOR_ERASE;
794 p_dev->blk_erase_cmd = CMD_BLOCK_ERASE;
795 p_dev->prog_lines = DATA_LINES_X1;
796 p_dev->prog_addr_lines = DATA_LINES_X1;
797 p_dev->read_lines = DATA_LINES_X1;
798 p_dev->write_status = snor_write_status;
799 snor_reset_device();
800 }
801
802 rkflash_print_info("addr_mode: %x\n", p_dev->addr_mode);
803 rkflash_print_info("read_lines: %x\n", p_dev->read_lines);
804 rkflash_print_info("prog_lines: %x\n", p_dev->prog_lines);
805 rkflash_print_info("read_cmd: %x\n", p_dev->read_cmd);
806 rkflash_print_info("prog_cmd: %x\n", p_dev->prog_cmd);
807 rkflash_print_info("blk_erase_cmd: %x\n", p_dev->blk_erase_cmd);
808 rkflash_print_info("sec_erase_cmd: %x\n", p_dev->sec_erase_cmd);
809 rkflash_print_info("capacity: %x\n", p_dev->capacity);
810
811 return SFC_OK;
812 }
813
snor_reinit_from_table_packet(struct SFNOR_DEV * p_dev,struct snor_info_packet * packet)814 int snor_reinit_from_table_packet(struct SFNOR_DEV *p_dev,
815 struct snor_info_packet *packet)
816 {
817 struct flash_info g_spi_flash_info;
818 u8 id_byte[5];
819 int ret;
820
821 if (!p_dev || packet->id != SNOR_INFO_PACKET_ID)
822 return SFC_PARAM_ERR;
823
824 snor_read_id(id_byte);
825 if (0xFF == id_byte[0] || 0x00 == id_byte[0])
826 return SFC_ERROR;
827
828 g_spi_flash_info.id = id_byte[0] << 16 | id_byte[1] << 8 | id_byte[2];
829 g_spi_flash_info.block_size = NOR_SECS_BLK;
830 g_spi_flash_info.sector_size = NOR_SECS_PAGE;
831 g_spi_flash_info.read_cmd = packet->read_cmd;
832 g_spi_flash_info.prog_cmd = packet->prog_cmd;
833 g_spi_flash_info.read_cmd_4 = packet->read_cmd_4;
834 g_spi_flash_info.prog_cmd_4 = packet->prog_cmd_4;
835 if (id_byte[2] >= 0x19)
836 g_spi_flash_info.read_cmd_4 = CMD_FAST_4READ_X4;
837 g_spi_flash_info.sector_erase_cmd = packet->sector_erase_cmd;
838 g_spi_flash_info.block_erase_cmd = packet->block_erase_cmd;
839 g_spi_flash_info.feature = packet->feature;
840 g_spi_flash_info.density = id_byte[2] - 9;
841 g_spi_flash_info.QE_bits = packet->QE_bits;
842
843 ret = snor_parse_flash_table(p_dev, &g_spi_flash_info);
844
845 return ret;
846 }
847
848