1 /*
2 * Copyright 2016 Rockchip Electronics Co. LTD
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17 #define MODULE_TAG "rc_model_v2_smt"
18
19 #include <string.h>
20 #include <math.h>
21
22 #include "mpp_env.h"
23 #include "mpp_mem.h"
24 #include "mpp_common.h"
25
26 #include "rc_base.h"
27 #include "rc_debug.h"
28 #include "rc_model_v2_smt.h"
29 #include "mpp_rc.h"
30
31 #define LOW_QP 34
32 #define LOW_LOW_QP 35
33
34 typedef struct RcModelV2SmtCtx_t {
35 RcCfg usr_cfg;
36 RK_U32 frame_type;
37 RK_U32 last_frame_type;
38 RK_U32 first_frm_flg;
39 RK_S64 frm_num;
40 RK_S32 qp_min;
41 RK_S32 qp_max;
42 MppEncGopMode gop_mode;
43 RK_S64 acc_intra_count;
44 RK_S64 acc_inter_count;
45 RK_S32 last_fps_bits;
46 RK_S32 pre_gop_left_bit;
47 MppData *qp_p;
48 MppDataV2 *motion_level;
49 MppDataV2 *complex_level;
50 MppDataV2 *stat_bits;
51 MppDataV2 *rt_bits; /* real time bits */
52 MppPIDCtx pid_fps;
53 RK_S64 count_real_bit;
54 RK_S64 count_pred_bit;
55 RK_S64 count_frame;
56 RK_S64 fixed_i_pred_bit;
57 RK_S64 fixed_p_pred_bit;
58 RK_S32 change_bit_flag;
59
60 RK_S32 bits_tgt_lower; /* bits target lower limit */
61 RK_S32 bits_tgt_upper; /* bits target upper limit */
62 RK_S32 bits_per_lower_i; /* bits per intra frame in low rate */
63 RK_S32 bits_per_upper_i; /* bits per intra frame in high rate */
64 RK_S32 bits_per_lower_p; /* bits per P frame in low rate */
65 RK_S32 bits_per_upper_p; /* bits per P frame in high rate */
66
67 RK_S32 pre_diff_bit_lower;
68 RK_S32 pre_diff_bit_upper;
69 RK_S32 igop;
70 MppPIDCtx pid_lower_i;
71 MppPIDCtx pid_upper_i;
72 MppPIDCtx pid_lower_all;
73 MppPIDCtx pid_upper_all;
74 MppDataV2 *pid_lower_p;
75 MppDataV2 *pid_upper_p;
76 RK_S32 qp_out;
77 RK_S32 qp_prev_out;
78 RK_S32 pre_real_bit_i; /* real bit of last intra frame */
79 RK_S32 pre_qp_i; /* qp of last intra frame */
80 RK_S32 gop_qp_sum;
81 RK_S32 gop_frm_cnt;
82 RK_S32 pre_iblk4_prop;
83 RK_S32 reenc_cnt;
84 RK_U32 drop_cnt;
85 RK_S32 on_drop;
86 RK_S32 on_pskip;
87 } RcModelV2SmtCtx;
88
89 // rc_container_bitrate_thd2
90 static RK_S32 rc_ctnr_qp_thd1[6] = { 51, 42, 42, 51, 38, 38 };
91 static RK_S32 rc_ctnr_qp_thd2[6] = { 51, 44, 44, 51, 40, 40 };
92 static RK_S32 rc_ctnr_br_thd1[6] = { 100, 110, 110, 100, 110, 110 };
93 static RK_S32 rc_ctnr_br_thd2[6] = { 100, 120, 120, 100, 125, 125 };
94
bits_model_smt_deinit(RcModelV2SmtCtx * ctx)95 MPP_RET bits_model_smt_deinit(RcModelV2SmtCtx *ctx)
96 {
97 rc_dbg_func("enter %p\n", ctx);
98
99 if (ctx->qp_p) {
100 mpp_data_deinit(ctx->qp_p);
101 ctx->qp_p = NULL;
102 }
103
104 if (ctx->motion_level != NULL) {
105 mpp_data_deinit_v2(ctx->motion_level);
106 ctx->motion_level = NULL;
107 }
108
109 if (ctx->complex_level != NULL) {
110 mpp_data_deinit_v2(ctx->complex_level);
111 ctx->complex_level = NULL;
112 }
113
114 if (ctx->stat_bits != NULL) {
115 mpp_data_deinit_v2(ctx->stat_bits);
116 ctx->stat_bits = NULL;
117 }
118
119 if (ctx->rt_bits != NULL) {
120 mpp_data_deinit_v2(ctx->rt_bits);
121 ctx->rt_bits = NULL;
122 }
123
124 if (ctx->pid_lower_p != NULL) {
125 mpp_data_deinit_v2(ctx->pid_lower_p);
126 ctx->pid_lower_p = NULL;
127 }
128
129 if (ctx->pid_upper_p != NULL) {
130 mpp_data_deinit_v2(ctx->pid_upper_p);
131 ctx->pid_upper_p = NULL;
132 }
133
134 rc_dbg_func("leave %p\n", ctx);
135 return MPP_OK;
136 }
137
bits_model_smt_init(RcModelV2SmtCtx * ctx)138 MPP_RET bits_model_smt_init(RcModelV2SmtCtx *ctx)
139 {
140 RK_S32 gop_len = ctx->usr_cfg.igop;
141 RcFpsCfg *fps = &ctx->usr_cfg.fps;
142 RK_S32 mad_len = 10;
143 RK_S32 ave_bits_lower = 0, ave_bits_uppper = 0;
144 RK_S32 bits_lower_i, bits_upper_i;
145 RK_S32 bits_lower_p, bits_upper_p;
146 RK_S32 bit_ratio[5] = { 7, 8, 9, 10, 11 };
147 RK_S32 nfps = fps->fps_out_num / fps->fps_out_denom;
148 RK_S32 win_len = mpp_clip(MPP_MAX3(gop_len, nfps, 10), 1, nfps);
149 RK_S32 rt_stat_len = fps->fps_out_num / fps->fps_out_denom; /* real time stat len */
150 RK_S32 stat_len = fps->fps_out_num * ctx->usr_cfg.stats_time / fps->fps_out_denom;
151 stat_len = stat_len ? stat_len : (fps->fps_out_num * 8 / fps->fps_out_denom);
152
153 rc_dbg_func("enter %p\n", ctx);
154 ctx->frm_num = 0;
155 ctx->first_frm_flg = 1;
156 ctx->gop_frm_cnt = 0;
157 ctx->gop_qp_sum = 0;
158
159 // smt
160 ctx->igop = gop_len;
161 ctx->qp_min = 10;
162 ctx->qp_max = 51;
163
164 if (ctx->motion_level)
165 mpp_data_deinit_v2(ctx->motion_level);
166 mpp_data_init_v2(&ctx->motion_level, mad_len, 0);
167
168 if (ctx->complex_level)
169 mpp_data_deinit_v2(ctx->complex_level);
170 mpp_data_init_v2(&ctx->complex_level, mad_len, 0);
171
172 if (ctx->pid_lower_p)
173 mpp_data_deinit_v2(ctx->pid_lower_p);
174 mpp_data_init_v2(&ctx->pid_lower_p, stat_len, 0);
175
176 if (ctx->pid_upper_p)
177 mpp_data_deinit_v2(ctx->pid_upper_p);
178 mpp_data_init_v2(&ctx->pid_upper_p, stat_len, 0);
179
180 mpp_pid_reset(&ctx->pid_fps);
181 mpp_pid_reset(&ctx->pid_lower_i);
182 mpp_pid_reset(&ctx->pid_upper_i);
183 mpp_pid_reset(&ctx->pid_lower_all);
184 mpp_pid_reset(&ctx->pid_upper_all);
185
186 mpp_pid_set_param(&ctx->pid_fps, 4, 6, 0, 90, win_len);
187 mpp_pid_set_param(&ctx->pid_lower_i, 4, 6, 0, 100, win_len);
188 mpp_pid_set_param(&ctx->pid_upper_i, 4, 6, 0, 100, win_len);
189 mpp_pid_set_param(&ctx->pid_lower_all, 4, 6, 0, 100, gop_len);
190 mpp_pid_set_param(&ctx->pid_upper_all, 4, 6, 0, 100, gop_len);
191
192 ave_bits_lower = (RK_S64)ctx->usr_cfg.bps_min * fps->fps_out_denom / fps->fps_out_num;
193 ave_bits_uppper = (RK_S64)ctx->usr_cfg.bps_max * fps->fps_out_denom / fps->fps_out_num;
194
195 ctx->acc_intra_count = 0;
196 ctx->acc_inter_count = 0;
197 ctx->last_fps_bits = 0;
198
199 if (gop_len == 0) {
200 ctx->gop_mode = MPP_GOP_ALL_INTER;
201 bits_lower_p = ave_bits_lower;
202 bits_lower_i = ave_bits_lower * 10;
203 bits_upper_p = ave_bits_uppper;
204 bits_upper_i = ave_bits_uppper * 10;
205 } else if (gop_len == 1) {
206 ctx->gop_mode = MPP_GOP_ALL_INTRA;
207 bits_lower_p = 0;
208 bits_lower_i = ave_bits_lower;
209 bits_upper_p = 0;
210 bits_upper_i = ave_bits_uppper;
211 /* disable debreath on all intra case */
212 if (ctx->usr_cfg.debreath_cfg.enable)
213 ctx->usr_cfg.debreath_cfg.enable = 0;
214 } else if (gop_len < win_len) {
215 ctx->gop_mode = MPP_GOP_SMALL;
216 bits_lower_p = ave_bits_lower >> 1;
217 bits_lower_i = bits_lower_p * (gop_len + 1);
218 bits_upper_p = ave_bits_uppper >> 1;
219 bits_upper_i = bits_upper_p * (gop_len + 1);
220 } else {
221 RK_S32 g = gop_len;
222 RK_S32 idx = g <= 50 ? 0 : (g <= 100 ? 1 : (g <= 200 ? 2 : (g <= 300 ? 3 : 4)));
223
224 ctx->gop_mode = MPP_GOP_LARGE;
225 bits_lower_i = ave_bits_lower * bit_ratio[idx] / 2;
226 bits_upper_i = ave_bits_uppper * bit_ratio[idx] / 2;
227 bits_lower_p = ave_bits_lower - bits_lower_i / (nfps - 1);
228 bits_upper_p = ave_bits_uppper - bits_upper_i / (nfps - 1);
229 ctx->fixed_i_pred_bit = (ctx->usr_cfg.bps_max / nfps * 8) / 8;
230 ctx->fixed_p_pred_bit = ((ctx->usr_cfg.bps_max * g / nfps - ctx->fixed_i_pred_bit) / (g - 1)) / 8;
231 }
232
233 ctx->bits_per_lower_i = bits_lower_i;
234 ctx->bits_per_upper_i = bits_upper_i;
235 ctx->bits_per_lower_p = bits_lower_p;
236 ctx->bits_per_upper_p = bits_upper_p;
237
238 rc_dbg_rc("bits_per_lower_i %d, bits_per_upper_i %d, "
239 "bits_per_lower_p %d, bits_per_upper_p %d\n",
240 bits_lower_i, bits_upper_i, bits_lower_p, bits_upper_p);
241
242 if (ctx->stat_bits)
243 mpp_data_deinit_v2(ctx->stat_bits);
244 mpp_data_init_v2(&ctx->stat_bits, stat_len, bits_upper_p);
245
246 if (ctx->rt_bits)
247 mpp_data_deinit_v2(ctx->rt_bits);
248 mpp_data_init_v2(&ctx->rt_bits, rt_stat_len, bits_upper_p);
249
250 rc_dbg_func("leave %p\n", ctx);
251 return MPP_OK;
252 }
253
bits_model_update_smt(RcModelV2SmtCtx * ctx,RK_S32 real_bit)254 MPP_RET bits_model_update_smt(RcModelV2SmtCtx *ctx, RK_S32 real_bit)
255 {
256 rc_dbg_func("enter %p\n", ctx);
257 RcFpsCfg *fps = &ctx->usr_cfg.fps;
258 RK_S32 bps_target_tmp = 0;
259 RK_S32 mod = 0;
260
261 rc_dbg_func("enter %p\n", ctx);
262
263 mpp_data_update_v2(ctx->stat_bits, real_bit);
264 ctx->pre_diff_bit_lower = ctx->bits_tgt_lower - real_bit;
265 ctx->pre_diff_bit_upper = ctx->bits_tgt_upper - real_bit;
266
267 ctx->count_real_bit = ctx->count_real_bit + real_bit / 8;
268 if (ctx->frame_type == INTRA_FRAME) {
269 ctx->count_pred_bit = ctx->count_pred_bit + ctx->fixed_i_pred_bit;
270 } else {
271 ctx->count_pred_bit = ctx->count_pred_bit + ctx->fixed_p_pred_bit;
272 }
273 ctx->count_frame ++;
274 if (ctx->count_real_bit > 72057594037927935 || ctx->count_pred_bit > 72057594037927935) {
275 ctx->count_real_bit = 0;
276 ctx->count_pred_bit = 0;
277 }
278
279 if (ctx->change_bit_flag == 1) {
280 real_bit = real_bit * 8 / 10;
281 }
282
283 if (ctx->frame_type == INTRA_FRAME) {
284 ctx->acc_intra_count++;
285 mpp_pid_update(&ctx->pid_lower_i, real_bit - ctx->bits_tgt_lower, 1);
286 mpp_pid_update(&ctx->pid_upper_i, real_bit - ctx->bits_tgt_upper, 1);
287 } else {
288 ctx->acc_inter_count++;
289 mpp_data_update_v2(ctx->pid_lower_p, real_bit - ctx->bits_tgt_lower);
290 mpp_data_update_v2(ctx->pid_upper_p, real_bit - ctx->bits_tgt_upper);
291 }
292 mpp_pid_update(&ctx->pid_lower_all, real_bit - ctx->bits_tgt_lower, 1);
293 mpp_pid_update(&ctx->pid_upper_all, real_bit - ctx->bits_tgt_upper, 1);
294
295 ctx->last_fps_bits += real_bit;
296 /* new fps start */
297 mod = ctx->acc_intra_count + ctx->acc_inter_count;
298 mod = mod % (fps->fps_out_num / fps->fps_out_denom);
299 if (0 == mod) {
300 bps_target_tmp = (ctx->usr_cfg.bps_min + ctx->usr_cfg.bps_max) >> 1;
301 if (bps_target_tmp * 3 > (ctx->last_fps_bits * 2))
302 mpp_pid_update(&ctx->pid_fps, bps_target_tmp - ctx->last_fps_bits, 0);
303 else {
304 bps_target_tmp = ctx->usr_cfg.bps_min * 4 / 10 + ctx->usr_cfg.bps_max * 6 / 10;
305 mpp_pid_update(&ctx->pid_fps, bps_target_tmp - ctx->last_fps_bits, 0);
306 }
307 ctx->last_fps_bits = 0;
308 }
309
310 /* new frame start */
311 ctx->qp_prev_out = ctx->qp_out;
312
313 rc_dbg_func("leave %p\n", ctx);
314
315 return MPP_OK;
316 }
317
rc_model_v2_smt_h265_init(void * ctx,RcCfg * cfg)318 MPP_RET rc_model_v2_smt_h265_init(void *ctx, RcCfg *cfg)
319 {
320 RcModelV2SmtCtx *p = (RcModelV2SmtCtx*)ctx;
321
322 rc_dbg_func("enter %p\n", ctx);
323
324 memcpy(&p->usr_cfg, cfg, sizeof(RcCfg));
325 bits_model_smt_init(p);
326
327 rc_dbg_func("leave %p\n", ctx);
328 return MPP_OK;
329 }
330
rc_model_v2_smt_h264_init(void * ctx,RcCfg * cfg)331 MPP_RET rc_model_v2_smt_h264_init(void *ctx, RcCfg *cfg)
332 {
333 RcModelV2SmtCtx *p = (RcModelV2SmtCtx*)ctx;
334
335 rc_dbg_func("enter %p\n", ctx);
336
337 memcpy(&p->usr_cfg, cfg, sizeof(RcCfg));
338 bits_model_smt_init(p);
339
340 rc_dbg_func("leave %p\n", ctx);
341 return MPP_OK;
342 }
343
344
rc_model_v2_smt_deinit(void * ctx)345 MPP_RET rc_model_v2_smt_deinit(void *ctx)
346 {
347 RcModelV2SmtCtx *p = (RcModelV2SmtCtx *)ctx;
348 rc_dbg_func("enter %p\n", ctx);
349 bits_model_smt_deinit(p);
350 rc_dbg_func("leave %p\n", ctx);
351 return MPP_OK;
352 }
353
set_coef(void * ctx,RK_S32 * coef,RK_S32 val)354 static void set_coef(void *ctx, RK_S32 *coef, RK_S32 val)
355 {
356 RcModelV2SmtCtx *p = (RcModelV2SmtCtx*)ctx;
357 RK_S32 cplx_lvl_0 = mpp_data_get_pre_val_v2(p->complex_level, 0);
358 RK_S32 cplx_lvl_1 = mpp_data_get_pre_val_v2(p->complex_level, 1);
359 RK_S32 cplx_lvl_sum = mpp_data_sum_v2(p->complex_level);
360
361 if (cplx_lvl_sum == 0)
362 *coef = val + 0;
363 else if (cplx_lvl_sum == 1) {
364 if (cplx_lvl_0 == 0)
365 *coef = val + 10;
366 else
367 *coef = val + 25;
368 } else if (cplx_lvl_sum == 2) {
369 if (cplx_lvl_0 == 0)
370 *coef = val + 25;
371 else
372 *coef = val + 35;
373 } else if (cplx_lvl_sum == 3) {
374 if (cplx_lvl_0 == 0)
375 *coef = val + 35;
376 else
377 *coef = val + 51;
378 } else if (cplx_lvl_sum >= 4 && cplx_lvl_sum <= 6) {
379 if (cplx_lvl_0 == 0) {
380 if (cplx_lvl_1 == 0)
381 *coef = val + 35;
382 else
383 *coef = val + 51;
384 } else
385 *coef = val + 64;
386 } else if (cplx_lvl_sum >= 7 && cplx_lvl_sum <= 9) {
387 if (cplx_lvl_0 == 0) {
388 if (cplx_lvl_1 == 0)
389 *coef = val + 64;
390 else
391 *coef = val + 72;
392 } else
393 *coef = val + 72;
394 } else
395 *coef = val + 80;
396 }
397
398 static RK_U32 mb_num[9] = {
399 0, 200, 700, 1200, 2000, 4000, 8000, 16000, 20000
400 };
401
402 static RK_U32 tab_bit[9] = {
403 3780, 3570, 3150, 2940, 2730, 3780, 2100, 1680, 2100
404 };
405
406 static RK_U8 qscale2qp[96] = {
407 15, 15, 15, 15, 15, 16, 18, 20, 21, 22, 23,
408 24, 25, 25, 26, 27, 28, 28, 29, 29, 30, 30,
409 30, 31, 31, 32, 32, 33, 33, 33, 34, 34, 34,
410 34, 35, 35, 35, 36, 36, 36, 36, 36, 37, 37,
411 37, 37, 38, 38, 38, 38, 38, 39, 39, 39, 39,
412 39, 39, 40, 40, 40, 40, 41, 41, 41, 41, 41,
413 41, 41, 42, 42, 42, 42, 42, 42, 42, 42, 43,
414 43, 43, 43, 43, 43, 43, 43, 44, 44, 44, 44,
415 44, 44, 44, 44, 45, 45, 45, 45,
416 };
417
418 static RK_U8 inter_pqp0[52] = {
419 1, 1, 1, 1, 1, 2, 3, 4,
420 5, 6, 7, 8, 9, 10, 11, 12,
421 13, 14, 15, 17, 18, 19, 20, 21,
422 21, 21, 22, 23, 24, 25, 26, 26,
423 27, 28, 28, 29, 29, 29, 30, 31,
424 31, 32, 32, 33, 33, 34, 35, 35,
425 35, 36, 36, 36
426 };
427
428 static RK_U8 inter_pqp1[52] = {
429 1, 1, 2, 3, 4, 5, 6, 7,
430 8, 9, 10, 11, 12, 13, 14, 15,
431 16, 17, 18, 19, 20, 20, 21, 22,
432 23, 24, 25, 26, 26, 27, 28, 29,
433 29, 30, 31, 31, 32, 33, 34, 35,
434 36, 37, 38, 39, 40, 41, 42, 42,
435 42, 43, 43, 44
436 };
437
438 static RK_U8 intra_pqp0[3][52] = {
439 {
440 1, 1, 1, 2, 3, 4, 5, 6,
441 7, 8, 9, 10, 11, 12, 13, 14,
442 15, 16, 17, 18, 19, 20, 21, 22,
443 23, 23, 24, 25, 26, 27, 27, 28,
444 28, 29, 30, 31, 32, 32, 33, 34,
445 34, 34, 35, 35, 36, 36, 36, 36,
446 37, 37, 37, 38
447 },
448
449 {
450 1, 1, 1, 2, 3, 4, 5, 6,
451 7, 8, 9, 10, 11, 12, 13, 14,
452 15, 16, 17, 17, 18, 18, 19, 19,
453 20, 21, 22, 23, 24, 25, 26, 27,
454 28, 29, 30, 31, 32, 32, 33, 34,
455 34, 34, 35, 35, 36, 36, 36, 36,
456 37, 37, 37, 38
457 },
458
459 {
460 1, 1, 1, 2, 3, 4, 5, 6,
461 7, 8, 9, 10, 11, 12, 13, 14,
462 14, 15, 15, 16, 16, 17, 17, 18,
463 16, 16, 16, 17, 18, 19, 20, 21,
464 23, 24, 26, 28, 30, 31, 32, 33,
465 34, 34, 35, 35, 36, 36, 36, 36,
466 37, 37, 37, 38
467 },
468 };
469
470 static RK_U8 intra_pqp1[52] = {
471 2, 3, 4, 5, 6, 7, 8, 9,
472 10, 11, 12, 13, 14, 15, 16, 17,
473 18, 19, 20, 22, 23, 24, 25, 26,
474 27, 28, 29, 30, 31, 32, 33, 34,
475 35, 36, 37, 38, 39, 40, 41, 42,
476 43, 44, 45, 46, 47, 48, 49, 50,
477 51, 51, 51, 51
478 };
479
cal_smt_first_i_start_qp(RK_S32 target_bit,RK_U32 total_mb)480 static RK_S32 cal_smt_first_i_start_qp(RK_S32 target_bit, RK_U32 total_mb)
481 {
482 RK_S32 cnt = 0;
483 RK_S32 index;
484 RK_S32 i;
485
486 for (i = 0; i < 8; i++) {
487 if (mb_num[i] > total_mb)
488 break;
489 cnt++;
490 }
491
492 index = (total_mb * tab_bit[cnt] - 350) / target_bit; // qscale
493 index = mpp_clip(index, 4, 95);
494
495 return qscale2qp[index];
496 }
497
calc_smt_debreath_qp(RcModelV2SmtCtx * ctx)498 static MPP_RET calc_smt_debreath_qp(RcModelV2SmtCtx * ctx)
499 {
500 RK_S32 fm_qp_sum = 0;
501 RK_S32 new_fm_qp = 0;
502 RcDebreathCfg *debreath_cfg = &ctx->usr_cfg.debreath_cfg;
503 RK_S32 dealt_qp = 0;
504 RK_S32 gop_qp_sum = ctx->gop_qp_sum;
505 RK_S32 gop_frm_cnt = ctx->gop_frm_cnt;
506 static RK_S8 intra_qp_map[8] = {
507 0, 0, 1, 1, 2, 2, 2, 2,
508 };
509 RK_U8 idx2 = MPP_MIN(ctx->pre_iblk4_prop >> 5, (RK_S32)sizeof(intra_qp_map) - 1);
510
511 static RK_S8 strength_map[36] = {
512 0, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4,
513 5, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8,
514 9, 9, 9, 10, 10, 10, 11, 11, 11, 12, 12, 12
515 };
516
517 rc_dbg_func("enter %p\n", ctx);
518
519 fm_qp_sum = MPP_MIN(gop_qp_sum / gop_frm_cnt, (RK_S32)sizeof(strength_map) - 1);
520
521 rc_dbg_qp("i qp_out %d, qp_start_sum = %d, intra_lv4_prop %d",
522 ctx->qp_out, fm_qp_sum, ctx->pre_iblk4_prop);
523
524 dealt_qp = strength_map[debreath_cfg->strength] - intra_qp_map[idx2];
525 if (fm_qp_sum > dealt_qp)
526 new_fm_qp = fm_qp_sum - dealt_qp;
527 else
528 new_fm_qp = fm_qp_sum;
529
530 ctx->qp_out = mpp_clip(new_fm_qp, ctx->usr_cfg.min_i_quality, ctx->usr_cfg.max_i_quality);
531 ctx->gop_frm_cnt = 0;
532 ctx->gop_qp_sum = 0;
533 rc_dbg_func("leave %p\n", ctx);
534 return MPP_OK;
535 }
536
smt_start_prepare(void * ctx,EncRcTask * task)537 static MPP_RET smt_start_prepare(void *ctx, EncRcTask *task)
538 {
539 EncFrmStatus *frm = &task->frm;
540 RcModelV2SmtCtx *p = (RcModelV2SmtCtx *) ctx;
541 EncRcTaskInfo *info = &task->info;
542 RcFpsCfg *fps = &p->usr_cfg.fps;
543 RK_S32 fps_out = fps->fps_out_num / fps->fps_out_denom;
544 RK_S32 b_min = p->usr_cfg.bps_min;
545 RK_S32 b_max = p->usr_cfg.bps_max;
546 RK_S32 bits_lower, bits_upper;
547
548 p->frame_type = frm->is_intra ? INTRA_FRAME : INTER_P_FRAME;
549 if (frm->ref_mode == REF_TO_PREV_INTRA)
550 p->frame_type = info->frame_type = INTER_VI_FRAME;
551
552 switch (p->gop_mode) {
553 case MPP_GOP_ALL_INTER: {
554 if (p->frame_type == INTRA_FRAME) {
555 bits_lower = p->bits_per_lower_i;
556 bits_upper = p->bits_per_upper_i;
557 } else {
558 bits_lower = p->bits_per_lower_p - mpp_data_mean_v2(p->pid_lower_p);
559 bits_upper = p->bits_per_upper_p - mpp_data_mean_v2(p->pid_upper_p);
560 }
561 } break;
562 case MPP_GOP_ALL_INTRA: {
563 bits_lower = p->bits_per_lower_i - mpp_pid_calc(&p->pid_lower_i);
564 bits_upper = p->bits_per_upper_i - mpp_pid_calc(&p->pid_upper_i);
565 } break;
566 default: {
567 if (p->frame_type == INTRA_FRAME) {
568 RK_S32 diff_bit = mpp_pid_calc(&p->pid_fps);
569
570 p->pre_gop_left_bit = p->pid_fps.i - diff_bit;
571 mpp_pid_reset(&p->pid_fps);
572 if (p->acc_intra_count) {
573 bits_lower = (p->bits_per_lower_i + diff_bit);
574 bits_upper = (p->bits_per_upper_i + diff_bit);
575 } else {
576 bits_lower = p->bits_per_lower_i - mpp_pid_calc(&p->pid_lower_i);
577 bits_upper = p->bits_per_upper_i - mpp_pid_calc(&p->pid_upper_i);
578 }
579 } else {
580 if (p->last_frame_type == INTRA_FRAME) {
581 RK_S32 bits_prev_i = p->pre_real_bit_i;
582
583 bits_lower = p->bits_per_lower_p
584 = ((RK_S64)b_min * p->igop / fps_out - bits_prev_i +
585 p->pre_gop_left_bit) / (p->igop - 1);
586
587 bits_upper = p->bits_per_upper_p
588 = ((RK_S64)b_max * p->igop / fps_out - bits_prev_i +
589 p->pre_gop_left_bit) / (p->igop - 1);
590
591 } else {
592 RK_S32 diff_bit_lr = mpp_data_mean_v2(p->pid_lower_p);
593 RK_S32 diff_bit_hr = mpp_data_mean_v2(p->pid_upper_p);
594 RK_S32 lr = (RK_S64)b_min * fps->fps_out_denom / fps->fps_out_num;
595 RK_S32 hr = (RK_S64)b_max * fps->fps_out_denom / fps->fps_out_num;
596
597 bits_lower = p->bits_per_lower_p - diff_bit_lr;
598 if (bits_lower > 2 * lr)
599 bits_lower = 2 * lr;
600
601 bits_upper = p->bits_per_upper_p - diff_bit_hr;
602 if (bits_upper > 2 * hr)
603 bits_upper = 2 * hr;
604 }
605
606 }
607 } break;
608 }
609
610 p->bits_tgt_lower = bits_lower;
611 p->bits_tgt_upper = bits_upper;
612 info->bit_max = (bits_lower + bits_upper) / 2;
613 if (info->bit_max < 100)
614 info->bit_max = 100;
615
616 if (NULL == p->qp_p) {
617 RK_S32 nfps = fps_out < 15 ? 4 * fps_out : (fps_out < 25 ? 3 * fps_out : 2 * fps_out);
618 mpp_data_init(&p->qp_p, mpp_clip(MPP_MAX(p->igop, nfps), 20, 50));
619 }
620
621 rc_dbg_rc("bits_tgt_lower %d, bits_tgt_upper %d, bit_max %d, qp_out %d",
622 p->bits_tgt_lower, p->bits_tgt_upper, info->bit_max, p->qp_out);
623
624 return MPP_OK;
625 }
626
smt_calc_coef(void * ctx)627 static RK_S32 smt_calc_coef(void *ctx)
628 {
629 RcModelV2SmtCtx *p = (RcModelV2SmtCtx *) ctx;
630 RK_S32 coef = 1024;
631 RK_S32 coef2 = 512;
632 RK_S32 md_lvl_sum = mpp_data_sum_v2(p->motion_level);
633 RK_S32 md_lvl_0 = mpp_data_get_pre_val_v2(p->motion_level, 0);
634 RK_S32 md_lvl_1 = mpp_data_get_pre_val_v2(p->motion_level, 1);
635
636 if (md_lvl_sum < 100)
637 set_coef(ctx, &coef, 0);
638 else if (md_lvl_sum < 200) {
639 if (md_lvl_0 < 100)
640 set_coef(ctx, &coef, 102);
641 else
642 set_coef(ctx, &coef, 154);
643 } else if (md_lvl_sum < 300) {
644 if (md_lvl_0 < 100)
645 set_coef(ctx, &coef, 154);
646 else if (md_lvl_0 == 100) {
647 if (md_lvl_1 < 100)
648 set_coef(ctx, &coef, 205);
649 else if (md_lvl_1 == 100)
650 set_coef(ctx, &coef, 256);
651 else
652 set_coef(ctx, &coef, 307);
653 } else
654 set_coef(ctx, &coef, 307);
655 } else if (md_lvl_sum < 600) {
656 if (md_lvl_0 < 100) {
657 if (md_lvl_1 < 100)
658 set_coef(ctx, &coef, 307);
659 else if (md_lvl_1 == 100)
660 set_coef(ctx, &coef, 358);
661 else
662 set_coef(ctx, &coef, 410);
663 } else if (md_lvl_0 == 100) {
664 if (md_lvl_1 < 100)
665 set_coef(ctx, &coef, 358);
666 else if (md_lvl_1 == 100)
667 set_coef(ctx, &coef, 410);
668 else
669 set_coef(ctx, &coef, 461);
670 } else
671 set_coef(ctx, &coef, 461);
672 } else if (md_lvl_sum < 900) {
673 if (md_lvl_0 < 100) {
674 if (md_lvl_1 < 100)
675 set_coef(ctx, &coef, 410);
676 else if (md_lvl_1 == 100)
677 set_coef(ctx, &coef, 461);
678 else
679 set_coef(ctx, &coef, 512);
680 } else if (md_lvl_0 == 100) {
681 if (md_lvl_1 < 100)
682 set_coef(ctx, &coef, 512);
683 else if (md_lvl_1 == 100)
684 set_coef(ctx, &coef, 563);
685 else
686 set_coef(ctx, &coef, 614);
687 } else
688 set_coef(ctx, &coef, 614);
689 } else if (md_lvl_sum < 1500)
690 set_coef(ctx, &coef, 666);
691 else if (md_lvl_sum < 1900)
692 set_coef(ctx, &coef, 768);
693 else
694 set_coef(ctx, &coef, 900);
695
696 if (coef > 1024)
697 coef = 1024;
698
699 if (coef >= 900)
700 coef2 = 1024;
701 else if (coef >= 307) // 0.7~0.3 --> 1.0~0.5
702 coef2 = 512 + (coef - 307) * (1024 - 512) / (717 - 307);
703 else // 0.3~0.0 --> 0.5~0.0
704 coef2 = 0 + coef * (512 - 0) / (307 - 0);
705 if (coef2 >= 1024)
706 coef2 = 1024;
707
708 return coef2;
709 }
710
711 /* bit_target_use: average of bits_tgt_lower and bits_tgt_upper */
derive_iframe_qp_by_bitrate(RcModelV2SmtCtx * p,RK_S32 bit_target_use)712 static RK_S32 derive_iframe_qp_by_bitrate(RcModelV2SmtCtx *p, RK_S32 bit_target_use)
713 {
714 RcFpsCfg *fps = &p->usr_cfg.fps;
715 RK_S32 avg_bps = (p->usr_cfg.bps_min + p->usr_cfg.bps_max) / 2;
716 RK_S32 fps_out = fps->fps_out_num / fps->fps_out_denom;
717 RK_S32 avg_pqp = mpp_data_avg(p->qp_p, -1, 1, 1);
718 RK_S32 avg_qp = mpp_clip(avg_pqp, p->qp_min, p->qp_max);
719 RK_S32 prev_iqp = p->pre_qp_i;
720 RK_S32 prev_pqp = p->qp_prev_out;
721 RK_S32 pre_bits_i = p->pre_real_bit_i;
722 RK_S32 qp_out_i = 0;
723
724 if (bit_target_use <= pre_bits_i) {
725 qp_out_i = (bit_target_use * 5 < pre_bits_i) ? prev_iqp + 3 :
726 (bit_target_use * 2 < pre_bits_i) ? prev_iqp + 2 :
727 (bit_target_use * 3 < pre_bits_i * 2) ? prev_iqp + 1 : prev_iqp;
728 } else {
729 qp_out_i = (pre_bits_i * 3 < bit_target_use) ? prev_iqp - 3 :
730 (pre_bits_i * 2 < bit_target_use) ? prev_iqp - 2 :
731 (pre_bits_i * 3 < bit_target_use * 2) ? prev_iqp - 1 : prev_iqp;
732 }
733 rc_dbg_rc("frame %lld bit_target_use %d pre_bits_i %d prev_iqp %d qp_out_i %d\n",
734 p->frm_num, bit_target_use, pre_bits_i, prev_iqp, qp_out_i);
735
736 //FIX: may be invalid(2025.01.06)
737 if (!p->reenc_cnt && p->usr_cfg.debreath_cfg.enable)
738 calc_smt_debreath_qp(p);
739
740 qp_out_i = mpp_clip(qp_out_i, inter_pqp0[avg_qp], inter_pqp1[avg_qp]);
741 qp_out_i = mpp_clip(qp_out_i, inter_pqp0[prev_pqp], inter_pqp1[prev_pqp]);
742 if (qp_out_i > 27)
743 qp_out_i = mpp_clip(qp_out_i, intra_pqp0[0][prev_iqp], intra_pqp1[prev_iqp]);
744 else if (qp_out_i > 22)
745 qp_out_i = mpp_clip(qp_out_i, intra_pqp0[1][prev_iqp], intra_pqp1[prev_iqp]);
746 else
747 qp_out_i = mpp_clip(qp_out_i, intra_pqp0[2][prev_iqp], intra_pqp1[prev_iqp]);
748
749 rc_dbg_rc("frame %lld qp_out_i %d avg_qp %d prev_pqp %d prev_iqp %d qp_out_i %d\n",
750 p->frm_num, qp_out_i, avg_qp, prev_pqp, prev_iqp, qp_out_i);
751
752 if (p->pre_gop_left_bit < 0) {
753 if (abs(p->pre_gop_left_bit) * 5 > avg_bps * (p->igop / fps_out))
754 qp_out_i = mpp_clip(qp_out_i, 20, 51);
755 else if (abs(p->pre_gop_left_bit) * 20 > avg_bps * (p->igop / fps_out))
756 qp_out_i = mpp_clip(qp_out_i, 15, 51);
757
758 rc_dbg_rc("frame %lld pre_gop_left_bit %d avg_bps %d qp_out_i %d\n",
759 p->frm_num, p->pre_gop_left_bit, avg_bps, qp_out_i);
760 }
761
762 return qp_out_i;
763 }
764
derive_pframe_qp_by_bitrate(RcModelV2SmtCtx * p)765 static RK_S32 derive_pframe_qp_by_bitrate(RcModelV2SmtCtx *p)
766 {
767 RcFpsCfg *fps = &p->usr_cfg.fps;
768 RK_S32 avg_bps = (p->usr_cfg.bps_min + p->usr_cfg.bps_max) / 2;
769 RK_S32 fps_out = fps->fps_out_num / fps->fps_out_denom;
770 RK_S32 bits_target_use = 0;
771 RK_S32 pre_diff_bit_use = 0;
772 RK_S32 coef = smt_calc_coef(p);
773 RK_S32 m_tbr = p->bits_tgt_upper - p->bits_tgt_lower;
774 RK_S32 m_dbr = p->pre_diff_bit_upper - p->pre_diff_bit_lower;
775 RK_S32 diff_bit = (p->pid_lower_all.i + p->pid_upper_all.i) >> 1;
776 RK_S32 prev_pqp = p->qp_prev_out;
777 RK_S32 qp_out = p->qp_out;
778 RK_S32 qp_add = 0, qp_minus = 0;
779
780 bits_target_use = ((RK_S64)m_tbr * coef + (RK_S64)p->bits_tgt_lower * 1024) >> 10;
781 pre_diff_bit_use = ((RK_S64)m_dbr * coef + (RK_S64)p->pre_diff_bit_lower * 1024) >> 10;
782
783 if (bits_target_use < 100)
784 bits_target_use = 100;
785
786 rc_dbg_rc("frame %lld bits_target_use %d m_tbr %d coef %d bits_tgt_lower %d\n"
787 "pre_diff_bit_use %d m_dbr %d pre_diff_bit_lower %d "
788 "bits_tgt_upper %d pre_diff_bit_upper %d qp_out_0 %d\n",
789 p->frm_num, bits_target_use, m_tbr, coef, p->bits_tgt_lower,
790 pre_diff_bit_use, m_dbr, p->pre_diff_bit_lower,
791 p->bits_tgt_upper, p->pre_diff_bit_upper, qp_out);
792
793 if (abs(pre_diff_bit_use) * 100 <= bits_target_use * 3)
794 qp_out = prev_pqp - 1;
795 else if (pre_diff_bit_use * 100 > bits_target_use * 3) {
796 if (pre_diff_bit_use >= bits_target_use)
797 qp_out = qp_out >= 30 ? prev_pqp - 4 : prev_pqp - 3;
798 else if (pre_diff_bit_use * 4 >= bits_target_use * 1)
799 qp_out = qp_out >= 30 ? prev_pqp - 3 : prev_pqp - 2;
800 else if (pre_diff_bit_use * 10 > bits_target_use * 1)
801 qp_out = prev_pqp - 2;
802 else
803 qp_out = prev_pqp - 1;
804 } else {
805 RK_S32 qp_add_tmp = (prev_pqp >= 36) ? 0 : 1;
806 pre_diff_bit_use = abs(pre_diff_bit_use);
807 qp_out = (pre_diff_bit_use >= 2 * bits_target_use) ? prev_pqp + 2 + qp_add_tmp :
808 (pre_diff_bit_use * 3 >= bits_target_use * 2) ? prev_pqp + 1 + qp_add_tmp :
809 (pre_diff_bit_use * 5 > bits_target_use) ? prev_pqp + 1 : prev_pqp;
810 }
811 rc_dbg_rc("frame %lld prev_pqp %d qp_out_1 %d\n", p->frm_num, prev_pqp, qp_out);
812
813 qp_out = mpp_clip(qp_out, p->qp_min, p->qp_max);
814 if (qp_out > LOW_QP) {
815 pre_diff_bit_use = ((RK_S64)m_dbr * coef + (RK_S64)p->pre_diff_bit_lower * 1024) >> 10;
816 bits_target_use = avg_bps / fps_out;
817 bits_target_use = -bits_target_use / 5;
818 coef += pre_diff_bit_use <= 2 * bits_target_use ? 205 :
819 ((pre_diff_bit_use <= bits_target_use) ? 102 : 51);
820
821 if (coef >= 1024 || qp_out > LOW_LOW_QP)
822 coef = 1024;
823 rc_dbg_rc("frame %lld pre_diff_bit_use %d bits_target_use %d coef %d\n",
824 p->frm_num, pre_diff_bit_use, bits_target_use, coef);
825
826 pre_diff_bit_use = ((RK_S64)m_dbr * coef + (RK_S64)p->pre_diff_bit_lower * 1024) >> 10;
827 bits_target_use = ((RK_S64)m_tbr * coef + (RK_S64)p->bits_tgt_lower * 1024) >> 10;
828 if (bits_target_use < 100)
829 bits_target_use = 100;
830
831 if (abs(pre_diff_bit_use) * 100 <= bits_target_use * 3)
832 qp_out = prev_pqp;
833 else if (pre_diff_bit_use * 100 > bits_target_use * 3) {
834 if (pre_diff_bit_use >= bits_target_use)
835 qp_out = qp_out >= 30 ? prev_pqp - 3 : prev_pqp - 2;
836 else if (pre_diff_bit_use * 4 >= bits_target_use * 1)
837 qp_out = qp_out >= 30 ? prev_pqp - 2 : prev_pqp - 1;
838 else if (pre_diff_bit_use * 10 > bits_target_use * 1)
839 qp_out = prev_pqp - 1;
840 else
841 qp_out = prev_pqp;
842 } else {
843 pre_diff_bit_use = abs(pre_diff_bit_use);
844 qp_out = prev_pqp + (pre_diff_bit_use * 3 >= bits_target_use * 2 ? 1 : 0);
845 }
846 rc_dbg_rc("frame %lld pre_diff_bit_use %d bits_target_use %d prev_pqp %d qp_out_2 %d\n",
847 p->frm_num, pre_diff_bit_use, bits_target_use, prev_pqp, qp_out);
848 }
849
850 qp_out = mpp_clip(qp_out, p->qp_min, p->qp_max);
851
852 //Add rc_container
853 p->change_bit_flag = 0;
854 if (p->usr_cfg.rc_container) {
855 RK_S32 cnt = p->usr_cfg.scene_mode * 3 + p->usr_cfg.rc_container;
856 if (p->count_real_bit < p->count_pred_bit * rc_ctnr_br_thd1[cnt] / 100) {
857 if (qp_out > rc_ctnr_qp_thd1[cnt]) {
858 p->change_bit_flag = 1;
859 }
860
861 qp_out = mpp_clip(qp_out, 10, rc_ctnr_qp_thd1[cnt]);
862 } else if (p->count_real_bit < p->count_pred_bit * rc_ctnr_br_thd2[cnt] / 100) {
863 if (qp_out > rc_ctnr_qp_thd2[cnt]) {
864 p->change_bit_flag = 1;
865 }
866 qp_out = mpp_clip(qp_out, 10, rc_ctnr_qp_thd2[cnt]);
867 }
868 }
869
870 qp_add = qp_out > 36 ? 1 : (qp_out > 33 ? 2 : (qp_out > 30 ? 3 : 4));
871 qp_minus = qp_out > 40 ? 4 : (qp_out > 36 ? 3 : (qp_out > 33 ? 2 : 1));
872 qp_out = mpp_clip(qp_out, prev_pqp - qp_minus, prev_pqp + qp_add);
873 rc_dbg_rc("frame %lld qp_out_3 %d qp_add %d qp_minus %d\n",
874 p->frm_num, qp_out, qp_add, qp_minus);
875
876 if (diff_bit > 0) {
877 if (avg_bps * 5 > avg_bps) //FIXME: avg_bps is typo error?(2025.01.06)
878 qp_out = mpp_clip(qp_out, 25, 51);
879 else if (avg_bps * 20 > avg_bps)
880 qp_out = mpp_clip(qp_out, 21, 51);
881 rc_dbg_rc("frame %lld avg_bps %d qp_out_4 %d\n", p->frm_num, avg_bps, qp_out);
882 }
883
884 return qp_out;
885 }
886
revise_qp_by_complexity(RcModelV2SmtCtx * p,RK_S32 fm_min_iqp,RK_S32 fm_min_pqp,RK_S32 fm_max_iqp,RK_S32 fm_max_pqp)887 static RK_S32 revise_qp_by_complexity(RcModelV2SmtCtx *p, RK_S32 fm_min_iqp,
888 RK_S32 fm_min_pqp, RK_S32 fm_max_iqp, RK_S32 fm_max_pqp)
889 {
890 RK_S32 md_lvl_sum = mpp_data_sum_v2(p->motion_level);
891 RK_S32 md_lvl_0 = mpp_data_get_pre_val_v2(p->motion_level, 0);
892 RK_S32 cplx_lvl_sum = mpp_data_sum_v2(p->complex_level);
893 RK_S32 qp_add = 0, qp_add_p = 0;
894 RK_S32 qp_final = p->qp_out;
895
896 qp_add = 4;
897 qp_add_p = 4;
898 if (md_lvl_sum >= 700 || md_lvl_0 == 200) {
899 qp_add = 6;
900 qp_add_p = 6;
901 } else if (md_lvl_sum >= 400 || md_lvl_0 == 100) {
902 qp_add = 5;
903 qp_add_p = 5;
904 }
905 if (cplx_lvl_sum >= 12) {
906 qp_add++;
907 qp_add_p++;
908 }
909
910 rc_dbg_rc("frame %lld md_lvl_sum %d md_lvl_0 %d cplx_lvl_sum %d "
911 "qp_add_cplx %d qp_add_p %d qp_final_0 %d\n",
912 p->frm_num, md_lvl_sum, md_lvl_0, cplx_lvl_sum,
913 qp_add, qp_add_p, qp_final);
914
915 if (p->frame_type == INTRA_FRAME)
916 qp_final = mpp_clip(qp_final, fm_min_iqp + qp_add, fm_max_iqp);
917 else if (p->frame_type == INTER_VI_FRAME) {
918 RK_S32 vi_max_qp = (fm_max_pqp > 42) ? (fm_max_pqp - 5) :
919 (fm_max_pqp > 39) ? (fm_max_pqp - 3) :
920 (fm_max_pqp > 35) ? (fm_max_pqp - 2) : fm_max_pqp;
921 qp_final -= 1;
922 qp_final = mpp_clip(qp_final, fm_min_pqp + qp_add - 1, fm_max_pqp);
923 qp_final = mpp_clip(qp_final, qp_final, vi_max_qp);
924 } else
925 qp_final = mpp_clip(qp_final, fm_min_pqp + qp_add_p, fm_max_pqp);
926
927 qp_final = mpp_clip(qp_final, p->qp_min, p->qp_max);
928 rc_dbg_rc("frame %lld frm_type %d frm_qp %d:%d:%d:%d blk_qp %d:%d qp_final_1 %d\n",
929 p->frm_num, p->frame_type, fm_min_iqp, fm_max_iqp,
930 fm_min_pqp, fm_max_pqp, p->qp_min, p->qp_max, qp_final);
931
932 return qp_final;
933 }
934
rc_model_v2_smt_start(void * ctx,EncRcTask * task)935 MPP_RET rc_model_v2_smt_start(void *ctx, EncRcTask * task)
936 {
937 RcModelV2SmtCtx *p = (RcModelV2SmtCtx *) ctx;
938 EncFrmStatus *frm = &task->frm;
939 EncRcTaskInfo *info = &task->info;
940 RcFpsCfg *fps = &p->usr_cfg.fps;
941 RK_S32 fps_out = fps->fps_out_num / fps->fps_out_denom;
942 RK_S32 avg_pqp = 0;
943 RK_S32 fm_min_iqp = p->usr_cfg.fqp_min_i;
944 RK_S32 fm_min_pqp = p->usr_cfg.fqp_min_p;
945 RK_S32 fm_max_iqp = p->usr_cfg.fqp_max_i;
946 RK_S32 fm_max_pqp = p->usr_cfg.fqp_max_p;
947
948 if (frm->reencode)
949 return MPP_OK;
950
951 smt_start_prepare(ctx, task);
952 avg_pqp = mpp_data_avg(p->qp_p, -1, 1, 1);
953
954 if (p->frm_num == 0) {
955 RK_S32 mb_w = MPP_ALIGN(p->usr_cfg.width, 16) / 16;
956 RK_S32 mb_h = MPP_ALIGN(p->usr_cfg.height, 16) / 16;
957 RK_S32 ratio = mpp_clip(fps_out / 10 + 1, 1, 3);
958 RK_S32 qp_out_f0 = 0;
959 if (p->usr_cfg.init_quality < 0) {
960 qp_out_f0 = cal_smt_first_i_start_qp(p->bits_tgt_upper * ratio, mb_w * mb_h);
961 qp_out_f0 = (fm_min_iqp > 31) ? mpp_clip(qp_out_f0, fm_min_iqp, p->qp_max) :
962 mpp_clip(qp_out_f0, 31, p->qp_max);
963 } else
964 qp_out_f0 = p->usr_cfg.init_quality;
965
966 p->qp_out = qp_out_f0;
967 p->count_real_bit = 0;
968 p->count_pred_bit = 0;
969 p->count_frame = 0;
970 rc_dbg_rc("first frame init_quality %d bits_tgt_upper %d "
971 "mb_w %d mb_h %d ratio %d qp_out %d\n",
972 p->usr_cfg.init_quality, p->bits_tgt_upper,
973 mb_w, mb_h, ratio, p->qp_out);
974 } else if (p->frame_type == INTRA_FRAME) {
975 // if (p->frm_num > 0)
976 p->qp_out = derive_iframe_qp_by_bitrate(p, info->bit_max);
977 } else {
978 if (p->last_frame_type == INTRA_FRAME) {
979 RK_S32 prev_qp = p->qp_prev_out;
980 p->qp_out = prev_qp + (prev_qp < 33 ? 3 : (prev_qp < 35 ? 2 : 1));
981 } else
982 p->qp_out = derive_pframe_qp_by_bitrate(p);
983 }
984
985 p->qp_out = revise_qp_by_complexity(p, fm_min_iqp, fm_min_pqp, fm_max_iqp, fm_max_pqp);
986
987 info->quality_target = p->qp_out;
988 info->complex_scene = 0;
989 if (p->frame_type == INTER_P_FRAME && avg_pqp >= fm_max_pqp - 1 &&
990 p->qp_out == fm_max_pqp && p->qp_prev_out == fm_max_pqp)
991 info->complex_scene = 1;
992
993 info->quality_max = p->usr_cfg.max_quality;
994 info->quality_min = p->usr_cfg.min_quality;
995
996 rc_dbg_rc("frame %lld quality [%d : %d : %d] complex_scene %d\n",
997 p->frm_num, info->quality_min, info->quality_target,
998 info->quality_max, info->complex_scene);
999
1000 p->frm_num++;
1001 p->reenc_cnt = 0;
1002 rc_dbg_func("leave %p\n", ctx);
1003 return MPP_OK;
1004 }
1005
check_super_frame_smt(RcModelV2SmtCtx * ctx,EncRcTaskInfo * cfg)1006 MPP_RET check_super_frame_smt(RcModelV2SmtCtx *ctx, EncRcTaskInfo *cfg)
1007 {
1008 MPP_RET ret = MPP_OK;
1009 RK_S32 frame_type = ctx->frame_type;
1010 RK_U32 bits_thr = 0;
1011 RcCfg *usr_cfg = &ctx->usr_cfg;
1012
1013 rc_dbg_func("enter %p\n", ctx);
1014 if (usr_cfg->super_cfg.super_mode) {
1015 bits_thr = usr_cfg->super_cfg.super_p_thd;
1016 if (frame_type == INTRA_FRAME)
1017 bits_thr = usr_cfg->super_cfg.super_i_thd;
1018
1019 if ((RK_U32)cfg->bit_real >= bits_thr) {
1020 if (usr_cfg->super_cfg.super_mode == MPP_ENC_RC_SUPER_FRM_DROP) {
1021 rc_dbg_rc("super frame drop current frame");
1022 usr_cfg->drop_mode = MPP_ENC_RC_DROP_FRM_NORMAL;
1023 usr_cfg->drop_gap = 0;
1024 }
1025 ret = MPP_NOK;
1026 }
1027 }
1028 rc_dbg_func("leave %p\n", ctx);
1029 return ret;
1030 }
1031
check_re_enc_smt(RcModelV2SmtCtx * ctx,EncRcTaskInfo * cfg)1032 MPP_RET check_re_enc_smt(RcModelV2SmtCtx *ctx, EncRcTaskInfo *cfg)
1033 {
1034 RcCfg *usr_cfg = &ctx->usr_cfg;
1035 RK_S32 frame_type = ctx->frame_type;
1036 RK_S32 bit_thr = 0;
1037 RK_S32 stat_time = usr_cfg->stats_time;
1038 RK_S32 last_ins_bps = mpp_data_sum_v2(ctx->stat_bits) / stat_time;
1039 RK_S32 ins_bps = (last_ins_bps * stat_time - mpp_data_get_pre_val_v2(ctx->stat_bits, -1)
1040 + cfg->bit_real) / stat_time;
1041 RK_S32 bps;
1042 RK_S32 ret = MPP_OK;
1043
1044 rc_dbg_func("enter %p\n", ctx);
1045 rc_dbg_rc("reenc check target_bps %d last_ins_bps %d ins_bps %d",
1046 usr_cfg->bps_target, last_ins_bps, ins_bps);
1047
1048 if (ctx->reenc_cnt >= usr_cfg->max_reencode_times)
1049 return MPP_OK;
1050
1051 if (check_super_frame_smt(ctx, cfg))
1052 return MPP_NOK;
1053
1054 if (usr_cfg->debreath_cfg.enable && !ctx->first_frm_flg)
1055 return MPP_OK;
1056
1057 rc_dbg_drop("drop mode %d frame_type %d\n", usr_cfg->drop_mode, frame_type);
1058 if (usr_cfg->drop_mode && frame_type == INTER_P_FRAME) {
1059 bit_thr = (RK_S32)(usr_cfg->bps_max * (100 + usr_cfg->drop_thd) / (float)100);
1060 rc_dbg_drop("drop mode %d check max_bps %d bit_thr %d ins_bps %d",
1061 usr_cfg->drop_mode, usr_cfg->bps_target, bit_thr, ins_bps);
1062 return (ins_bps > bit_thr) ? MPP_NOK : MPP_OK;
1063 }
1064
1065 switch (frame_type) {
1066 case INTRA_FRAME:
1067 bit_thr = 3 * cfg->bit_max / 2;
1068 break;
1069 case INTER_P_FRAME:
1070 bit_thr = 3 * cfg->bit_max;
1071 break;
1072 default:
1073 break;
1074 }
1075
1076 if (cfg->bit_real > bit_thr) {
1077 bps = usr_cfg->bps_max;
1078 if ((bps - (bps >> 3) < ins_bps) && (bps / 20 < ins_bps - last_ins_bps))
1079 ret = MPP_NOK;
1080 }
1081
1082 rc_dbg_func("leave %p ret %d\n", ctx, ret);
1083 return ret;
1084 }
1085
rc_model_v2_smt_check_reenc(void * ctx,EncRcTask * task)1086 MPP_RET rc_model_v2_smt_check_reenc(void *ctx, EncRcTask *task)
1087 {
1088 RcModelV2SmtCtx *p = (RcModelV2SmtCtx *)ctx;
1089 EncRcTaskInfo *cfg = (EncRcTaskInfo *)&task->info;
1090 EncFrmStatus *frm = &task->frm;
1091 RcCfg *usr_cfg = &p->usr_cfg;
1092
1093 rc_dbg_func("enter ctx %p cfg %p\n", ctx, cfg);
1094
1095 frm->reencode = 0;
1096
1097 if ((usr_cfg->mode == RC_FIXQP) ||
1098 (task->force.force_flag & ENC_RC_FORCE_QP) ||
1099 p->on_drop || p->on_pskip)
1100 return MPP_OK;
1101
1102 if (check_re_enc_smt(p, cfg)) {
1103 MppEncRcDropFrmMode drop_mode = usr_cfg->drop_mode;
1104
1105 if (frm->is_intra)
1106 drop_mode = MPP_ENC_RC_DROP_FRM_DISABLED;
1107
1108 if (usr_cfg->drop_gap && p->drop_cnt >= usr_cfg->drop_gap)
1109 drop_mode = MPP_ENC_RC_DROP_FRM_DISABLED;
1110
1111 rc_dbg_drop("reenc drop_mode %d drop_cnt %d\n", drop_mode, p->drop_cnt);
1112
1113 switch (drop_mode) {
1114 case MPP_ENC_RC_DROP_FRM_NORMAL : {
1115 frm->drop = 1;
1116 frm->reencode = 1;
1117 p->on_drop = 1;
1118 p->drop_cnt++;
1119 rc_dbg_drop("drop\n");
1120 } break;
1121 case MPP_ENC_RC_DROP_FRM_PSKIP : {
1122 frm->force_pskip = 1;
1123 frm->reencode = 1;
1124 p->on_pskip = 1;
1125 p->drop_cnt++;
1126 rc_dbg_drop("force_pskip\n");
1127 } break;
1128 case MPP_ENC_RC_DROP_FRM_DISABLED :
1129 default : {
1130 RK_S32 bits_thr = usr_cfg->super_cfg.super_p_thd;
1131 if (p->frame_type == INTRA_FRAME)
1132 bits_thr = usr_cfg->super_cfg.super_i_thd;
1133
1134 if (cfg->bit_real > bits_thr * 2)
1135 cfg->quality_target += 3;
1136 else if (cfg->bit_real > bits_thr * 3 / 2)
1137 cfg->quality_target += 2;
1138 else if (cfg->bit_real > bits_thr)
1139 cfg->quality_target ++;
1140
1141 if (cfg->quality_target < cfg->quality_max) {
1142 p->reenc_cnt++;
1143 frm->reencode = 1;
1144 }
1145 p->drop_cnt = 0;
1146 } break;
1147 }
1148 }
1149
1150 return MPP_OK;
1151 }
1152
rc_model_v2_smt_end(void * ctx,EncRcTask * task)1153 MPP_RET rc_model_v2_smt_end(void *ctx, EncRcTask * task)
1154 {
1155 RcModelV2SmtCtx *p = (RcModelV2SmtCtx *) ctx;
1156 EncRcTaskInfo *cfg = (EncRcTaskInfo *) & task->info;
1157 RK_S32 bit_real = cfg->bit_real;
1158
1159 rc_dbg_func("enter ctx %p cfg %p\n", ctx, cfg);
1160 rc_dbg_rc("motion_level %u, complex_level %u\n", cfg->motion_level, cfg->complex_level);
1161
1162 mpp_data_update_v2(p->rt_bits, bit_real);
1163 cfg->rt_bits = mpp_data_sum_v2(p->rt_bits);
1164 rc_dbg_rc("frame %lld real_bit %d real time bits %d\n",
1165 p->frm_num - 1, bit_real, cfg->rt_bits);
1166
1167 mpp_data_update_v2(p->motion_level, cfg->motion_level);
1168 mpp_data_update_v2(p->complex_level, cfg->complex_level);
1169 p->first_frm_flg = 0;
1170
1171 if (p->frame_type == INTER_P_FRAME || p->gop_mode == MPP_GOP_ALL_INTRA)
1172 mpp_data_update(p->qp_p, p->qp_out);
1173 else {
1174 p->pre_qp_i = p->qp_out;
1175 p->pre_real_bit_i = bit_real;
1176 }
1177
1178 bits_model_update_smt(p, bit_real);
1179 p->qp_prev_out = p->qp_out;
1180 p->last_frame_type = p->frame_type;
1181 p->pre_iblk4_prop = cfg->iblk4_prop;
1182 p->gop_frm_cnt++;
1183 p->gop_qp_sum += p->qp_out;
1184
1185 rc_dbg_func("leave %p\n", ctx);
1186 return MPP_OK;
1187 }
1188
rc_model_v2_smt_hal_start(void * ctx,EncRcTask * task)1189 MPP_RET rc_model_v2_smt_hal_start(void *ctx, EncRcTask *task)
1190 {
1191 rc_dbg_func("smt_hal_start enter ctx %p task %p\n", ctx, task);
1192 return MPP_OK;
1193 }
1194
rc_model_v2_smt_hal_end(void * ctx,EncRcTask * task)1195 MPP_RET rc_model_v2_smt_hal_end(void *ctx, EncRcTask *task)
1196 {
1197 rc_dbg_func("smt_hal_end enter ctx %p task %p\n", ctx, task);
1198 rc_dbg_func("leave %p\n", ctx);
1199 return MPP_OK;
1200 }
1201
1202 const RcImplApi smt_h264e = {
1203 "smart",
1204 MPP_VIDEO_CodingAVC,
1205 sizeof(RcModelV2SmtCtx),
1206 rc_model_v2_smt_h264_init,
1207 rc_model_v2_smt_deinit,
1208 NULL,
1209 rc_model_v2_smt_check_reenc,
1210 rc_model_v2_smt_start,
1211 rc_model_v2_smt_end,
1212 rc_model_v2_smt_hal_start,
1213 rc_model_v2_smt_hal_end,
1214 };
1215
1216 const RcImplApi smt_h265e = {
1217 "smart",
1218 MPP_VIDEO_CodingHEVC,
1219 sizeof(RcModelV2SmtCtx),
1220 rc_model_v2_smt_h265_init,
1221 rc_model_v2_smt_deinit,
1222 NULL,
1223 rc_model_v2_smt_check_reenc,
1224 rc_model_v2_smt_start,
1225 rc_model_v2_smt_end,
1226 rc_model_v2_smt_hal_start,
1227 rc_model_v2_smt_hal_end,
1228 };
1229