1 /* 2 * Copyright 2017 Rockchip Electronics Co. LTD 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef __HAL_H264E_VEPU_V2_H__ 18 #define __HAL_H264E_VEPU_V2_H__ 19 20 #include "mpp_enc_cfg.h" 21 #include "mpp_rc.h" 22 #include "vepu_common.h" 23 24 #define H264E_HAL_SET_REG(reg, addr, val) \ 25 do { \ 26 reg[(addr)>>2] = (RK_U32)(val); \ 27 if (hal_h264e_debug & 0/*H264E_HAL_LOG_INFO*/) \ 28 mpp_log("line(%d) set reg[%03d/%03x]: %08x", __LINE__, (addr)>>2, addr, val); \ 29 } while (0) 30 31 typedef enum H264eVpuFrameType_t { 32 H264E_VPU_FRAME_P = 0, 33 H264E_VPU_FRAME_I = 1 34 } H264eVpuFrameType; 35 36 #define VEPU_CTRL_LEVELS 7 37 #define VEPU_CHECK_POINTS_MAX 10 38 39 typedef struct HalH264eVepuInput_t { 40 /* Hardware config format */ 41 RK_S32 src_fmt; 42 RK_S32 src_w; 43 RK_S32 src_h; 44 45 VepuStrideCfg stride_cfg; 46 RK_S32 pixel_stride; 47 48 size_t size_y; 49 size_t size_c; 50 51 RK_U32 offset_cb; 52 RK_U32 offset_cr; 53 54 RK_U8 r_mask_msb; 55 RK_U8 g_mask_msb; 56 RK_U8 b_mask_msb; 57 RK_U8 swap_8_in; 58 RK_U8 swap_16_in; 59 RK_U8 swap_32_in; 60 61 RK_U32 color_conversion_coeff_a; 62 RK_U32 color_conversion_coeff_b; 63 RK_U32 color_conversion_coeff_c; 64 RK_U32 color_conversion_coeff_e; 65 RK_U32 color_conversion_coeff_f; 66 67 RK_U32 rotation; 68 } HalH264eVepuPrep; 69 70 typedef struct HalH264eVepuFrmAddr_t { 71 // original frame Y/Cb/Cr/RGB address 72 RK_U32 orig[3]; 73 // reconstruction frame 74 RK_U32 recn[2]; 75 RK_U32 refr[2]; 76 } HalH264eVepuAddr; 77 78 /* 79 * Vepu buffer allocater 80 * There are three internal buffer for Vepu encoder: 81 * 1. cabac table input buffer 82 * 2. nal size table output buffer 83 * 3. recon / refer frame buffer 84 */ 85 typedef struct HalH264eVepuBufs_t { 86 MppBufferGroup group; 87 88 /* cabac table buffer */ 89 RK_S32 cabac_init_idc; 90 MppBuffer cabac_table; 91 92 /* 93 * nal size table buffer 94 * table size must be 64-bit multiple, space for zero at the end of table 95 * Atleast 1 macroblock row in every slice 96 */ 97 RK_S32 mb_h; 98 RK_S32 nal_tab_size; 99 MppBuffer nal_size_table; 100 101 /* 102 * recon / refer frame buffer 103 * sync with encoder using slot index 104 */ 105 size_t frm_size; 106 size_t yuv_size; 107 RK_S32 frm_cnt; 108 MppBuffer frm_buf[H264E_MAX_REFS_CNT + 1]; 109 } HalH264eVepuBufs; 110 111 typedef struct HalH264eVepuMbRc_t { 112 /* VEPU MB rate control parameter for config to hardware */ 113 RK_S32 qp_init; 114 RK_S32 qp_min; 115 RK_S32 qp_max; 116 117 /* 118 * VEPU MB can have max 10 check points (cp). 119 * 120 * On each check point hardware will check the target bit and 121 * error bits and change qp according to delta qp step 122 * 123 * cp_distance_mbs check point distance in mbs (0 = disabled) 124 * cp_target bitrate target at each check point 125 * cp_error error bit level step for each delta qp 126 * cp_delta_qp delta qp applied on when on bit rate error amount 127 */ 128 RK_S32 cp_distance_mbs; 129 RK_S32 cp_target[VEPU_CHECK_POINTS_MAX]; 130 RK_S32 cp_error[VEPU_CTRL_LEVELS]; 131 RK_S32 cp_delta_qp[VEPU_CTRL_LEVELS]; 132 133 /* 134 * MAD based QP adjustment 135 * mad_qp_change [-8..7] 136 * mad_threshold MAD threshold div256 137 */ 138 RK_S32 mad_qp_change; 139 RK_S32 mad_threshold; 140 141 /* slice split by mb row (0 = one slice) */ 142 RK_S32 slice_size_mb_rows; 143 144 /* favor and penalty for mode decision */ 145 146 /* 147 * VEPU MB rate control parameter which is read from hardware 148 * out_strm_size output stream size (bits) 149 * qp_sum QP Sum div2 output 150 * rlc_count RLC codeword count div4 output max 255*255*384/4 151 */ 152 RK_U32 hdr_strm_size; 153 RK_U32 hdr_free_size; 154 RK_U32 out_strm_size; 155 RK_S32 qp_sum; 156 RK_S32 rlc_count; 157 158 RK_S32 cp_usage[VEPU_CHECK_POINTS_MAX]; 159 /* Macroblock count with MAD value under threshold output */ 160 RK_S32 less_mad_count; 161 /* MB count output */ 162 RK_S32 mb_count; 163 164 /* hardware encoding status 0 - corret 1 - error */ 165 RK_U32 hw_status; 166 } HalH264eVepuMbRc; 167 168 typedef void *HalH264eVepuMbRcCtx; 169 170 171 172 #ifdef __cplusplus 173 extern "C" { 174 #endif 175 176 RK_S32 exp_golomb_signed(RK_S32 val); 177 178 /* buffer management function */ 179 MPP_RET h264e_vepu_buf_init(HalH264eVepuBufs *bufs); 180 MPP_RET h264e_vepu_buf_deinit(HalH264eVepuBufs *bufs); 181 182 MPP_RET h264e_vepu_buf_set_cabac_idc(HalH264eVepuBufs *bufs, RK_S32 idc); 183 MPP_RET h264e_vepu_buf_set_frame_size(HalH264eVepuBufs *bufs, RK_S32 w, RK_S32 h); 184 185 MppBuffer h264e_vepu_buf_get_nal_size_table(HalH264eVepuBufs *bufs); 186 MppBuffer h264e_vepu_buf_get_frame_buffer(HalH264eVepuBufs *bufs, RK_S32 index); 187 188 /* preprocess setup function */ 189 MPP_RET h264e_vepu_prep_setup(HalH264eVepuPrep *prep, MppEncPrepCfg *cfg); 190 MPP_RET h264e_vepu_prep_get_addr(HalH264eVepuPrep *prep, MppBuffer buffer, 191 RK_U32 (*addr)[3]); 192 193 /* macroblock bitrate control function */ 194 MPP_RET h264e_vepu_mbrc_init(HalH264eVepuMbRcCtx *ctx, HalH264eVepuMbRc *mbrc); 195 MPP_RET h264e_vepu_mbrc_deinit(HalH264eVepuMbRcCtx ctx); 196 197 MPP_RET h264e_vepu_mbrc_setup(HalH264eVepuMbRcCtx ctx, MppEncCfgSet *cfg); 198 MPP_RET h264e_vepu_slice_split_cfg(H264eSlice *slice, HalH264eVepuMbRc *mbrc, 199 EncRcTask *rc_task, MppEncCfgSet *set_cfg); 200 201 /* 202 * generate hardware MB rc config by: 203 * 1 - HalH264eVepuMbRcCtx ctx 204 * The previous frame encoding status 205 * 2 - RcSyntax 206 * Provide current frame target bitrate related info 207 * 3 - EncFrmStatus 208 * Provide dpb related info like I / P frame, temporal id, refer distance 209 * 210 * Then output the HalH264eVepuMbRc for register generation 211 */ 212 MPP_RET h264e_vepu_mbrc_prepare(HalH264eVepuMbRcCtx ctx, HalH264eVepuMbRc *mbrc, 213 EncRcTask *rc_task); 214 MPP_RET h264e_vepu_mbrc_update(HalH264eVepuMbRcCtx ctx, HalH264eVepuMbRc *mbrc); 215 216 #ifdef __cplusplus 217 } 218 #endif 219 220 #endif 221