1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #define SWSMU_CODE_LAYER_L2
25
26 #include <linux/firmware.h>
27 #include <linux/pci.h>
28 #include <linux/i2c.h>
29 #include "amdgpu.h"
30 #include "amdgpu_smu.h"
31 #include "atomfirmware.h"
32 #include "amdgpu_atomfirmware.h"
33 #include "amdgpu_atombios.h"
34 #include "smu_v11_0.h"
35 #include "smu11_driver_if_sienna_cichlid.h"
36 #include "soc15_common.h"
37 #include "atom.h"
38 #include "sienna_cichlid_ppt.h"
39 #include "smu_v11_0_7_pptable.h"
40 #include "smu_v11_0_7_ppsmc.h"
41 #include "nbio/nbio_2_3_offset.h"
42 #include "nbio/nbio_2_3_sh_mask.h"
43 #include "thm/thm_11_0_2_offset.h"
44 #include "thm/thm_11_0_2_sh_mask.h"
45 #include "mp/mp_11_0_offset.h"
46 #include "mp/mp_11_0_sh_mask.h"
47
48 #include "asic_reg/mp/mp_11_0_sh_mask.h"
49 #include "smu_cmn.h"
50
51 /*
52 * DO NOT use these for err/warn/info/debug messages.
53 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
54 * They are more MGPU friendly.
55 */
56 #undef pr_err
57 #undef pr_warn
58 #undef pr_info
59 #undef pr_debug
60
61 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
62
63 #define FEATURE_MASK(feature) (1ULL << feature)
64 #define SMC_DPM_FEATURE ( \
65 FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
66 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \
67 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \
68 FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \
69 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \
70 FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \
71 FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT) | \
72 FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT))
73
74 #define SMU_11_0_7_GFX_BUSY_THRESHOLD 15
75
76 static struct cmn2asic_msg_mapping sienna_cichlid_message_map[SMU_MSG_MAX_COUNT] = {
77 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1),
78 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
79 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
80 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow, 0),
81 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 0),
82 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0),
83 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0),
84 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 1),
85 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 1),
86 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 1),
87 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 1),
88 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetRunningSmuFeaturesLow, 1),
89 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetRunningSmuFeaturesHigh, 1),
90 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1),
91 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0),
92 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 0),
93 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 0),
94 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0),
95 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0),
96 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 0),
97 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0),
98 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0),
99 MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0),
100 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0),
101 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 0),
102 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 0),
103 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 1),
104 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0),
105 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1),
106 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1),
107 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1),
108 MSG_MAP(SetGeminiMode, PPSMC_MSG_SetGeminiMode, 0),
109 MSG_MAP(SetGeminiApertureHigh, PPSMC_MSG_SetGeminiApertureHigh, 0),
110 MSG_MAP(SetGeminiApertureLow, PPSMC_MSG_SetGeminiApertureLow, 0),
111 MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters, 0),
112 MSG_MAP(ReenableAcDcInterrupt, PPSMC_MSG_ReenableAcDcInterrupt, 0),
113 MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource, 0),
114 MSG_MAP(SetUclkFastSwitch, PPSMC_MSG_SetUclkFastSwitch, 0),
115 MSG_MAP(SetVideoFps, PPSMC_MSG_SetVideoFps, 0),
116 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 1),
117 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0),
118 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0),
119 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0),
120 MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq, 1),
121 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco, 0),
122 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0),
123 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0),
124 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0),
125 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0),
126 MSG_MAP(BacoAudioD3PME, PPSMC_MSG_BacoAudioD3PME, 0),
127 MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0),
128 MSG_MAP(Mode1Reset, PPSMC_MSG_Mode1Reset, 0),
129 MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0),
130 };
131
132 static struct cmn2asic_mapping sienna_cichlid_clk_map[SMU_CLK_COUNT] = {
133 CLK_MAP(GFXCLK, PPCLK_GFXCLK),
134 CLK_MAP(SCLK, PPCLK_GFXCLK),
135 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
136 CLK_MAP(FCLK, PPCLK_FCLK),
137 CLK_MAP(UCLK, PPCLK_UCLK),
138 CLK_MAP(MCLK, PPCLK_UCLK),
139 CLK_MAP(DCLK, PPCLK_DCLK_0),
140 CLK_MAP(DCLK1, PPCLK_DCLK_1),
141 CLK_MAP(VCLK, PPCLK_VCLK_0),
142 CLK_MAP(VCLK1, PPCLK_VCLK_1),
143 CLK_MAP(DCEFCLK, PPCLK_DCEFCLK),
144 CLK_MAP(DISPCLK, PPCLK_DISPCLK),
145 CLK_MAP(PIXCLK, PPCLK_PIXCLK),
146 CLK_MAP(PHYCLK, PPCLK_PHYCLK),
147 };
148
149 static struct cmn2asic_mapping sienna_cichlid_feature_mask_map[SMU_FEATURE_COUNT] = {
150 FEA_MAP(DPM_PREFETCHER),
151 FEA_MAP(DPM_GFXCLK),
152 FEA_MAP(DPM_GFX_GPO),
153 FEA_MAP(DPM_UCLK),
154 FEA_MAP(DPM_FCLK),
155 FEA_MAP(DPM_SOCCLK),
156 FEA_MAP(DPM_MP0CLK),
157 FEA_MAP(DPM_LINK),
158 FEA_MAP(DPM_DCEFCLK),
159 FEA_MAP(DPM_XGMI),
160 FEA_MAP(MEM_VDDCI_SCALING),
161 FEA_MAP(MEM_MVDD_SCALING),
162 FEA_MAP(DS_GFXCLK),
163 FEA_MAP(DS_SOCCLK),
164 FEA_MAP(DS_FCLK),
165 FEA_MAP(DS_LCLK),
166 FEA_MAP(DS_DCEFCLK),
167 FEA_MAP(DS_UCLK),
168 FEA_MAP(GFX_ULV),
169 FEA_MAP(FW_DSTATE),
170 FEA_MAP(GFXOFF),
171 FEA_MAP(BACO),
172 FEA_MAP(MM_DPM_PG),
173 FEA_MAP(RSMU_SMN_CG),
174 FEA_MAP(PPT),
175 FEA_MAP(TDC),
176 FEA_MAP(APCC_PLUS),
177 FEA_MAP(GTHR),
178 FEA_MAP(ACDC),
179 FEA_MAP(VR0HOT),
180 FEA_MAP(VR1HOT),
181 FEA_MAP(FW_CTF),
182 FEA_MAP(FAN_CONTROL),
183 FEA_MAP(THERMAL),
184 FEA_MAP(GFX_DCS),
185 FEA_MAP(RM),
186 FEA_MAP(LED_DISPLAY),
187 FEA_MAP(GFX_SS),
188 FEA_MAP(OUT_OF_BAND_MONITOR),
189 FEA_MAP(TEMP_DEPENDENT_VMIN),
190 FEA_MAP(MMHUB_PG),
191 FEA_MAP(ATHUB_PG),
192 FEA_MAP(APCC_DFLL),
193 };
194
195 static struct cmn2asic_mapping sienna_cichlid_table_map[SMU_TABLE_COUNT] = {
196 TAB_MAP(PPTABLE),
197 TAB_MAP(WATERMARKS),
198 TAB_MAP(AVFS_PSM_DEBUG),
199 TAB_MAP(AVFS_FUSE_OVERRIDE),
200 TAB_MAP(PMSTATUSLOG),
201 TAB_MAP(SMU_METRICS),
202 TAB_MAP(DRIVER_SMU_CONFIG),
203 TAB_MAP(ACTIVITY_MONITOR_COEFF),
204 TAB_MAP(OVERDRIVE),
205 TAB_MAP(I2C_COMMANDS),
206 TAB_MAP(PACE),
207 };
208
209 static struct cmn2asic_mapping sienna_cichlid_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
210 PWR_MAP(AC),
211 PWR_MAP(DC),
212 };
213
214 static struct cmn2asic_mapping sienna_cichlid_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
215 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT),
216 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
217 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT),
218 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
219 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
220 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT),
221 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
222 };
223
224 static int
sienna_cichlid_get_allowed_feature_mask(struct smu_context * smu,uint32_t * feature_mask,uint32_t num)225 sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
226 uint32_t *feature_mask, uint32_t num)
227 {
228 struct amdgpu_device *adev = smu->adev;
229
230 if (num > 2)
231 return -EINVAL;
232
233 memset(feature_mask, 0, sizeof(uint32_t) * num);
234
235 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
236 | FEATURE_MASK(FEATURE_DPM_FCLK_BIT)
237 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
238 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
239 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
240 | FEATURE_MASK(FEATURE_DS_FCLK_BIT)
241 | FEATURE_MASK(FEATURE_DS_UCLK_BIT)
242 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
243 | FEATURE_MASK(FEATURE_DF_CSTATE_BIT)
244 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
245 | FEATURE_MASK(FEATURE_GFX_SS_BIT)
246 | FEATURE_MASK(FEATURE_VR0HOT_BIT)
247 | FEATURE_MASK(FEATURE_PPT_BIT)
248 | FEATURE_MASK(FEATURE_TDC_BIT)
249 | FEATURE_MASK(FEATURE_BACO_BIT)
250 | FEATURE_MASK(FEATURE_APCC_DFLL_BIT)
251 | FEATURE_MASK(FEATURE_FW_CTF_BIT)
252 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
253 | FEATURE_MASK(FEATURE_THERMAL_BIT)
254 | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT);
255
256 if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) {
257 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
258 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT);
259 }
260
261 if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
262 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
263 | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
264 | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
265
266 if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
267 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
268
269 if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
270 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
271
272 if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
273 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
274
275 if (adev->pm.pp_feature & PP_ULV_MASK)
276 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
277
278 if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
279 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
280
281 if (adev->pm.pp_feature & PP_GFXOFF_MASK)
282 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
283
284 if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)
285 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
286
287 if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
288 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
289
290 if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN ||
291 smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG)
292 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_PG_BIT);
293
294 return 0;
295 }
296
sienna_cichlid_check_bxco_support(struct smu_context * smu)297 static void sienna_cichlid_check_bxco_support(struct smu_context *smu)
298 {
299 struct smu_table_context *table_context = &smu->smu_table;
300 struct smu_11_0_7_powerplay_table *powerplay_table =
301 table_context->power_play_table;
302 struct smu_baco_context *smu_baco = &smu->smu_baco;
303 struct amdgpu_device *adev = smu->adev;
304 uint32_t val;
305
306 if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_BACO ||
307 powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_MACO) {
308 val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
309 smu_baco->platform_support =
310 (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true :
311 false;
312
313 /*
314 * Disable BACO entry/exit completely on below SKUs to
315 * avoid hardware intermittent failures.
316 */
317 if (((adev->pdev->device == 0x73A1) &&
318 (adev->pdev->revision == 0x00)) ||
319 ((adev->pdev->device == 0x73BF) &&
320 (adev->pdev->revision == 0xCF)) ||
321 ((adev->pdev->device == 0x7422) &&
322 (adev->pdev->revision == 0x00)))
323 smu_baco->platform_support = false;
324
325 }
326 }
327
sienna_cichlid_check_powerplay_table(struct smu_context * smu)328 static int sienna_cichlid_check_powerplay_table(struct smu_context *smu)
329 {
330 struct smu_table_context *table_context = &smu->smu_table;
331 struct smu_11_0_7_powerplay_table *powerplay_table =
332 table_context->power_play_table;
333
334 if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_HARDWAREDC)
335 smu->dc_controlled_by_gpio = true;
336
337 sienna_cichlid_check_bxco_support(smu);
338
339 table_context->thermal_controller_type =
340 powerplay_table->thermal_controller_type;
341
342 return 0;
343 }
344
sienna_cichlid_append_powerplay_table(struct smu_context * smu)345 static int sienna_cichlid_append_powerplay_table(struct smu_context *smu)
346 {
347 struct smu_table_context *table_context = &smu->smu_table;
348 PPTable_t *smc_pptable = table_context->driver_pptable;
349 struct atom_smc_dpm_info_v4_9 *smc_dpm_table;
350 int index, ret;
351
352 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
353 smc_dpm_info);
354
355 ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
356 (uint8_t **)&smc_dpm_table);
357 if (ret)
358 return ret;
359
360 memcpy(smc_pptable->I2cControllers, smc_dpm_table->I2cControllers,
361 sizeof(*smc_dpm_table) - sizeof(smc_dpm_table->table_header));
362
363 return 0;
364 }
365
sienna_cichlid_store_powerplay_table(struct smu_context * smu)366 static int sienna_cichlid_store_powerplay_table(struct smu_context *smu)
367 {
368 struct smu_table_context *table_context = &smu->smu_table;
369 struct smu_11_0_7_powerplay_table *powerplay_table =
370 table_context->power_play_table;
371
372 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
373 sizeof(PPTable_t));
374
375 return 0;
376 }
377
sienna_cichlid_setup_pptable(struct smu_context * smu)378 static int sienna_cichlid_setup_pptable(struct smu_context *smu)
379 {
380 int ret = 0;
381
382 ret = smu_v11_0_setup_pptable(smu);
383 if (ret)
384 return ret;
385
386 ret = sienna_cichlid_store_powerplay_table(smu);
387 if (ret)
388 return ret;
389
390 ret = sienna_cichlid_append_powerplay_table(smu);
391 if (ret)
392 return ret;
393
394 ret = sienna_cichlid_check_powerplay_table(smu);
395 if (ret)
396 return ret;
397
398 return ret;
399 }
400
sienna_cichlid_tables_init(struct smu_context * smu)401 static int sienna_cichlid_tables_init(struct smu_context *smu)
402 {
403 struct smu_table_context *smu_table = &smu->smu_table;
404 struct smu_table *tables = smu_table->tables;
405
406 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
407 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
408 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
409 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
410 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
411 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
412 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
413 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
414 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
415 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
416 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
417 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
418 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
419 sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
420 AMDGPU_GEM_DOMAIN_VRAM);
421
422 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
423 if (!smu_table->metrics_table)
424 goto err0_out;
425 smu_table->metrics_time = 0;
426
427 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_0);
428 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
429 if (!smu_table->gpu_metrics_table)
430 goto err1_out;
431
432 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
433 if (!smu_table->watermarks_table)
434 goto err2_out;
435
436 return 0;
437
438 err2_out:
439 kfree(smu_table->gpu_metrics_table);
440 err1_out:
441 kfree(smu_table->metrics_table);
442 err0_out:
443 return -ENOMEM;
444 }
445
sienna_cichlid_get_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)446 static int sienna_cichlid_get_smu_metrics_data(struct smu_context *smu,
447 MetricsMember_t member,
448 uint32_t *value)
449 {
450 struct smu_table_context *smu_table= &smu->smu_table;
451 SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
452 int ret = 0;
453
454 mutex_lock(&smu->metrics_lock);
455
456 ret = smu_cmn_get_metrics_table_locked(smu,
457 NULL,
458 false);
459 if (ret) {
460 mutex_unlock(&smu->metrics_lock);
461 return ret;
462 }
463
464 switch (member) {
465 case METRICS_CURR_GFXCLK:
466 *value = metrics->CurrClock[PPCLK_GFXCLK];
467 break;
468 case METRICS_CURR_SOCCLK:
469 *value = metrics->CurrClock[PPCLK_SOCCLK];
470 break;
471 case METRICS_CURR_UCLK:
472 *value = metrics->CurrClock[PPCLK_UCLK];
473 break;
474 case METRICS_CURR_VCLK:
475 *value = metrics->CurrClock[PPCLK_VCLK_0];
476 break;
477 case METRICS_CURR_VCLK1:
478 *value = metrics->CurrClock[PPCLK_VCLK_1];
479 break;
480 case METRICS_CURR_DCLK:
481 *value = metrics->CurrClock[PPCLK_DCLK_0];
482 break;
483 case METRICS_CURR_DCLK1:
484 *value = metrics->CurrClock[PPCLK_DCLK_1];
485 break;
486 case METRICS_CURR_DCEFCLK:
487 *value = metrics->CurrClock[PPCLK_DCEFCLK];
488 break;
489 case METRICS_CURR_FCLK:
490 *value = metrics->CurrClock[PPCLK_FCLK];
491 break;
492 case METRICS_AVERAGE_GFXCLK:
493 if (metrics->AverageGfxActivity <= SMU_11_0_7_GFX_BUSY_THRESHOLD)
494 *value = metrics->AverageGfxclkFrequencyPostDs;
495 else
496 *value = metrics->AverageGfxclkFrequencyPreDs;
497 break;
498 case METRICS_AVERAGE_FCLK:
499 *value = metrics->AverageFclkFrequencyPostDs;
500 break;
501 case METRICS_AVERAGE_UCLK:
502 *value = metrics->AverageUclkFrequencyPostDs;
503 break;
504 case METRICS_AVERAGE_GFXACTIVITY:
505 *value = metrics->AverageGfxActivity;
506 break;
507 case METRICS_AVERAGE_MEMACTIVITY:
508 *value = metrics->AverageUclkActivity;
509 break;
510 case METRICS_AVERAGE_SOCKETPOWER:
511 *value = metrics->AverageSocketPower << 8;
512 break;
513 case METRICS_TEMPERATURE_EDGE:
514 *value = metrics->TemperatureEdge *
515 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
516 break;
517 case METRICS_TEMPERATURE_HOTSPOT:
518 *value = metrics->TemperatureHotspot *
519 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
520 break;
521 case METRICS_TEMPERATURE_MEM:
522 *value = metrics->TemperatureMem *
523 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
524 break;
525 case METRICS_TEMPERATURE_VRGFX:
526 *value = metrics->TemperatureVrGfx *
527 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
528 break;
529 case METRICS_TEMPERATURE_VRSOC:
530 *value = metrics->TemperatureVrSoc *
531 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
532 break;
533 case METRICS_THROTTLER_STATUS:
534 *value = metrics->ThrottlerStatus;
535 break;
536 case METRICS_CURR_FANSPEED:
537 *value = metrics->CurrFanSpeed;
538 break;
539 default:
540 *value = UINT_MAX;
541 break;
542 }
543
544 mutex_unlock(&smu->metrics_lock);
545
546 return ret;
547
548 }
549
sienna_cichlid_allocate_dpm_context(struct smu_context * smu)550 static int sienna_cichlid_allocate_dpm_context(struct smu_context *smu)
551 {
552 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
553
554 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
555 GFP_KERNEL);
556 if (!smu_dpm->dpm_context)
557 return -ENOMEM;
558
559 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
560
561 return 0;
562 }
563
sienna_cichlid_init_smc_tables(struct smu_context * smu)564 static int sienna_cichlid_init_smc_tables(struct smu_context *smu)
565 {
566 int ret = 0;
567
568 ret = sienna_cichlid_tables_init(smu);
569 if (ret)
570 return ret;
571
572 ret = sienna_cichlid_allocate_dpm_context(smu);
573 if (ret)
574 return ret;
575
576 return smu_v11_0_init_smc_tables(smu);
577 }
578
sienna_cichlid_set_default_dpm_table(struct smu_context * smu)579 static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
580 {
581 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
582 PPTable_t *driver_ppt = smu->smu_table.driver_pptable;
583 struct smu_11_0_dpm_table *dpm_table;
584 struct amdgpu_device *adev = smu->adev;
585 int ret = 0;
586
587 /* socclk dpm table setup */
588 dpm_table = &dpm_context->dpm_tables.soc_table;
589 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
590 ret = smu_v11_0_set_single_dpm_table(smu,
591 SMU_SOCCLK,
592 dpm_table);
593 if (ret)
594 return ret;
595 dpm_table->is_fine_grained =
596 !driver_ppt->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete;
597 } else {
598 dpm_table->count = 1;
599 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
600 dpm_table->dpm_levels[0].enabled = true;
601 dpm_table->min = dpm_table->dpm_levels[0].value;
602 dpm_table->max = dpm_table->dpm_levels[0].value;
603 }
604
605 /* gfxclk dpm table setup */
606 dpm_table = &dpm_context->dpm_tables.gfx_table;
607 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
608 ret = smu_v11_0_set_single_dpm_table(smu,
609 SMU_GFXCLK,
610 dpm_table);
611 if (ret)
612 return ret;
613 dpm_table->is_fine_grained =
614 !driver_ppt->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete;
615 } else {
616 dpm_table->count = 1;
617 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
618 dpm_table->dpm_levels[0].enabled = true;
619 dpm_table->min = dpm_table->dpm_levels[0].value;
620 dpm_table->max = dpm_table->dpm_levels[0].value;
621 }
622
623 /* uclk dpm table setup */
624 dpm_table = &dpm_context->dpm_tables.uclk_table;
625 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
626 ret = smu_v11_0_set_single_dpm_table(smu,
627 SMU_UCLK,
628 dpm_table);
629 if (ret)
630 return ret;
631 dpm_table->is_fine_grained =
632 !driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete;
633 } else {
634 dpm_table->count = 1;
635 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
636 dpm_table->dpm_levels[0].enabled = true;
637 dpm_table->min = dpm_table->dpm_levels[0].value;
638 dpm_table->max = dpm_table->dpm_levels[0].value;
639 }
640
641 /* fclk dpm table setup */
642 dpm_table = &dpm_context->dpm_tables.fclk_table;
643 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
644 ret = smu_v11_0_set_single_dpm_table(smu,
645 SMU_FCLK,
646 dpm_table);
647 if (ret)
648 return ret;
649 dpm_table->is_fine_grained =
650 !driver_ppt->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete;
651 } else {
652 dpm_table->count = 1;
653 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
654 dpm_table->dpm_levels[0].enabled = true;
655 dpm_table->min = dpm_table->dpm_levels[0].value;
656 dpm_table->max = dpm_table->dpm_levels[0].value;
657 }
658
659 /* vclk0 dpm table setup */
660 dpm_table = &dpm_context->dpm_tables.vclk_table;
661 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
662 ret = smu_v11_0_set_single_dpm_table(smu,
663 SMU_VCLK,
664 dpm_table);
665 if (ret)
666 return ret;
667 dpm_table->is_fine_grained =
668 !driver_ppt->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete;
669 } else {
670 dpm_table->count = 1;
671 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
672 dpm_table->dpm_levels[0].enabled = true;
673 dpm_table->min = dpm_table->dpm_levels[0].value;
674 dpm_table->max = dpm_table->dpm_levels[0].value;
675 }
676
677 /* vclk1 dpm table setup */
678 if (adev->vcn.num_vcn_inst > 1) {
679 dpm_table = &dpm_context->dpm_tables.vclk1_table;
680 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
681 ret = smu_v11_0_set_single_dpm_table(smu,
682 SMU_VCLK1,
683 dpm_table);
684 if (ret)
685 return ret;
686 dpm_table->is_fine_grained =
687 !driver_ppt->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete;
688 } else {
689 dpm_table->count = 1;
690 dpm_table->dpm_levels[0].value =
691 smu->smu_table.boot_values.vclk / 100;
692 dpm_table->dpm_levels[0].enabled = true;
693 dpm_table->min = dpm_table->dpm_levels[0].value;
694 dpm_table->max = dpm_table->dpm_levels[0].value;
695 }
696 }
697
698 /* dclk0 dpm table setup */
699 dpm_table = &dpm_context->dpm_tables.dclk_table;
700 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
701 ret = smu_v11_0_set_single_dpm_table(smu,
702 SMU_DCLK,
703 dpm_table);
704 if (ret)
705 return ret;
706 dpm_table->is_fine_grained =
707 !driver_ppt->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete;
708 } else {
709 dpm_table->count = 1;
710 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
711 dpm_table->dpm_levels[0].enabled = true;
712 dpm_table->min = dpm_table->dpm_levels[0].value;
713 dpm_table->max = dpm_table->dpm_levels[0].value;
714 }
715
716 /* dclk1 dpm table setup */
717 if (adev->vcn.num_vcn_inst > 1) {
718 dpm_table = &dpm_context->dpm_tables.dclk1_table;
719 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
720 ret = smu_v11_0_set_single_dpm_table(smu,
721 SMU_DCLK1,
722 dpm_table);
723 if (ret)
724 return ret;
725 dpm_table->is_fine_grained =
726 !driver_ppt->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete;
727 } else {
728 dpm_table->count = 1;
729 dpm_table->dpm_levels[0].value =
730 smu->smu_table.boot_values.dclk / 100;
731 dpm_table->dpm_levels[0].enabled = true;
732 dpm_table->min = dpm_table->dpm_levels[0].value;
733 dpm_table->max = dpm_table->dpm_levels[0].value;
734 }
735 }
736
737 /* dcefclk dpm table setup */
738 dpm_table = &dpm_context->dpm_tables.dcef_table;
739 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
740 ret = smu_v11_0_set_single_dpm_table(smu,
741 SMU_DCEFCLK,
742 dpm_table);
743 if (ret)
744 return ret;
745 dpm_table->is_fine_grained =
746 !driver_ppt->DpmDescriptor[PPCLK_DCEFCLK].SnapToDiscrete;
747 } else {
748 dpm_table->count = 1;
749 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
750 dpm_table->dpm_levels[0].enabled = true;
751 dpm_table->min = dpm_table->dpm_levels[0].value;
752 dpm_table->max = dpm_table->dpm_levels[0].value;
753 }
754
755 /* pixelclk dpm table setup */
756 dpm_table = &dpm_context->dpm_tables.pixel_table;
757 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
758 ret = smu_v11_0_set_single_dpm_table(smu,
759 SMU_PIXCLK,
760 dpm_table);
761 if (ret)
762 return ret;
763 dpm_table->is_fine_grained =
764 !driver_ppt->DpmDescriptor[PPCLK_PIXCLK].SnapToDiscrete;
765 } else {
766 dpm_table->count = 1;
767 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
768 dpm_table->dpm_levels[0].enabled = true;
769 dpm_table->min = dpm_table->dpm_levels[0].value;
770 dpm_table->max = dpm_table->dpm_levels[0].value;
771 }
772
773 /* displayclk dpm table setup */
774 dpm_table = &dpm_context->dpm_tables.display_table;
775 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
776 ret = smu_v11_0_set_single_dpm_table(smu,
777 SMU_DISPCLK,
778 dpm_table);
779 if (ret)
780 return ret;
781 dpm_table->is_fine_grained =
782 !driver_ppt->DpmDescriptor[PPCLK_DISPCLK].SnapToDiscrete;
783 } else {
784 dpm_table->count = 1;
785 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
786 dpm_table->dpm_levels[0].enabled = true;
787 dpm_table->min = dpm_table->dpm_levels[0].value;
788 dpm_table->max = dpm_table->dpm_levels[0].value;
789 }
790
791 /* phyclk dpm table setup */
792 dpm_table = &dpm_context->dpm_tables.phy_table;
793 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
794 ret = smu_v11_0_set_single_dpm_table(smu,
795 SMU_PHYCLK,
796 dpm_table);
797 if (ret)
798 return ret;
799 dpm_table->is_fine_grained =
800 !driver_ppt->DpmDescriptor[PPCLK_PHYCLK].SnapToDiscrete;
801 } else {
802 dpm_table->count = 1;
803 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
804 dpm_table->dpm_levels[0].enabled = true;
805 dpm_table->min = dpm_table->dpm_levels[0].value;
806 dpm_table->max = dpm_table->dpm_levels[0].value;
807 }
808
809 return 0;
810 }
811
sienna_cichlid_dpm_set_vcn_enable(struct smu_context * smu,bool enable)812 static int sienna_cichlid_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
813 {
814 struct amdgpu_device *adev = smu->adev;
815 int ret = 0;
816
817 if (enable) {
818 /* vcn dpm on is a prerequisite for vcn power gate messages */
819 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
820 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL);
821 if (ret)
822 return ret;
823 if (adev->vcn.num_vcn_inst > 1) {
824 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn,
825 0x10000, NULL);
826 if (ret)
827 return ret;
828 }
829 }
830 } else {
831 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
832 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn, 0, NULL);
833 if (ret)
834 return ret;
835 if (adev->vcn.num_vcn_inst > 1) {
836 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn,
837 0x10000, NULL);
838 if (ret)
839 return ret;
840 }
841 }
842 }
843
844 return ret;
845 }
846
sienna_cichlid_dpm_set_jpeg_enable(struct smu_context * smu,bool enable)847 static int sienna_cichlid_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
848 {
849 int ret = 0;
850
851 if (enable) {
852 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
853 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL);
854 if (ret)
855 return ret;
856 }
857 } else {
858 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
859 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL);
860 if (ret)
861 return ret;
862 }
863 }
864
865 return ret;
866 }
867
sienna_cichlid_get_current_clk_freq_by_table(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * value)868 static int sienna_cichlid_get_current_clk_freq_by_table(struct smu_context *smu,
869 enum smu_clk_type clk_type,
870 uint32_t *value)
871 {
872 MetricsMember_t member_type;
873 int clk_id = 0;
874
875 clk_id = smu_cmn_to_asic_specific_index(smu,
876 CMN2ASIC_MAPPING_CLK,
877 clk_type);
878 if (clk_id < 0)
879 return clk_id;
880
881 switch (clk_id) {
882 case PPCLK_GFXCLK:
883 member_type = METRICS_CURR_GFXCLK;
884 break;
885 case PPCLK_UCLK:
886 member_type = METRICS_CURR_UCLK;
887 break;
888 case PPCLK_SOCCLK:
889 member_type = METRICS_CURR_SOCCLK;
890 break;
891 case PPCLK_FCLK:
892 member_type = METRICS_CURR_FCLK;
893 break;
894 case PPCLK_VCLK_0:
895 member_type = METRICS_CURR_VCLK;
896 break;
897 case PPCLK_VCLK_1:
898 member_type = METRICS_CURR_VCLK1;
899 break;
900 case PPCLK_DCLK_0:
901 member_type = METRICS_CURR_DCLK;
902 break;
903 case PPCLK_DCLK_1:
904 member_type = METRICS_CURR_DCLK1;
905 break;
906 case PPCLK_DCEFCLK:
907 member_type = METRICS_CURR_DCEFCLK;
908 break;
909 default:
910 return -EINVAL;
911 }
912
913 return sienna_cichlid_get_smu_metrics_data(smu,
914 member_type,
915 value);
916
917 }
918
sienna_cichlid_is_support_fine_grained_dpm(struct smu_context * smu,enum smu_clk_type clk_type)919 static bool sienna_cichlid_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
920 {
921 PPTable_t *pptable = smu->smu_table.driver_pptable;
922 DpmDescriptor_t *dpm_desc = NULL;
923 uint32_t clk_index = 0;
924
925 clk_index = smu_cmn_to_asic_specific_index(smu,
926 CMN2ASIC_MAPPING_CLK,
927 clk_type);
928 dpm_desc = &pptable->DpmDescriptor[clk_index];
929
930 /* 0 - Fine grained DPM, 1 - Discrete DPM */
931 return dpm_desc->SnapToDiscrete == 0 ? true : false;
932 }
933
sienna_cichlid_print_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,char * buf)934 static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
935 enum smu_clk_type clk_type, char *buf)
936 {
937 struct amdgpu_device *adev = smu->adev;
938 struct smu_table_context *table_context = &smu->smu_table;
939 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
940 struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
941 PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable;
942 int i, size = 0, ret = 0;
943 uint32_t cur_value = 0, value = 0, count = 0;
944 uint32_t freq_values[3] = {0};
945 uint32_t mark_index = 0;
946 uint32_t gen_speed, lane_width;
947
948 switch (clk_type) {
949 case SMU_GFXCLK:
950 case SMU_SCLK:
951 case SMU_SOCCLK:
952 case SMU_MCLK:
953 case SMU_UCLK:
954 case SMU_FCLK:
955 case SMU_DCEFCLK:
956 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, clk_type, &cur_value);
957 if (ret)
958 goto print_clk_out;
959
960 /* no need to disable gfxoff when retrieving the current gfxclk */
961 if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
962 amdgpu_gfx_off_ctrl(adev, false);
963
964 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count);
965 if (ret)
966 goto print_clk_out;
967
968 if (!sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
969 for (i = 0; i < count; i++) {
970 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value);
971 if (ret)
972 goto print_clk_out;
973
974 size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
975 cur_value == value ? "*" : "");
976 }
977 } else {
978 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
979 if (ret)
980 goto print_clk_out;
981 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]);
982 if (ret)
983 goto print_clk_out;
984
985 freq_values[1] = cur_value;
986 mark_index = cur_value == freq_values[0] ? 0 :
987 cur_value == freq_values[2] ? 2 : 1;
988
989 count = 3;
990 if (mark_index != 1) {
991 count = 2;
992 freq_values[1] = freq_values[2];
993 }
994
995 for (i = 0; i < count; i++) {
996 size += sprintf(buf + size, "%d: %uMhz %s\n", i, freq_values[i],
997 cur_value == freq_values[i] ? "*" : "");
998 }
999
1000 }
1001 break;
1002 case SMU_PCIE:
1003 gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu);
1004 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
1005 for (i = 0; i < NUM_LINK_LEVELS; i++)
1006 size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i,
1007 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
1008 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," :
1009 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," :
1010 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "",
1011 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" :
1012 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" :
1013 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" :
1014 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" :
1015 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" :
1016 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "",
1017 pptable->LclkFreq[i],
1018 (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) &&
1019 (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
1020 "*" : "");
1021 break;
1022 default:
1023 break;
1024 }
1025
1026 print_clk_out:
1027 if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
1028 amdgpu_gfx_off_ctrl(adev, true);
1029
1030 return size;
1031 }
1032
sienna_cichlid_force_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t mask)1033 static int sienna_cichlid_force_clk_levels(struct smu_context *smu,
1034 enum smu_clk_type clk_type, uint32_t mask)
1035 {
1036 struct amdgpu_device *adev = smu->adev;
1037 int ret = 0, size = 0;
1038 uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
1039
1040 soft_min_level = mask ? (ffs(mask) - 1) : 0;
1041 soft_max_level = mask ? (fls(mask) - 1) : 0;
1042
1043 if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
1044 amdgpu_gfx_off_ctrl(adev, false);
1045
1046 switch (clk_type) {
1047 case SMU_GFXCLK:
1048 case SMU_SCLK:
1049 case SMU_SOCCLK:
1050 case SMU_MCLK:
1051 case SMU_UCLK:
1052 case SMU_FCLK:
1053 /* There is only 2 levels for fine grained DPM */
1054 if (sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
1055 soft_max_level = (soft_max_level >= 1 ? 1 : 0);
1056 soft_min_level = (soft_min_level >= 1 ? 1 : 0);
1057 }
1058
1059 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
1060 if (ret)
1061 goto forec_level_out;
1062
1063 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
1064 if (ret)
1065 goto forec_level_out;
1066
1067 ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
1068 if (ret)
1069 goto forec_level_out;
1070 break;
1071 case SMU_DCEFCLK:
1072 dev_info(smu->adev->dev,"Setting DCEFCLK min/max dpm level is not supported!\n");
1073 break;
1074 default:
1075 break;
1076 }
1077
1078 forec_level_out:
1079 if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
1080 amdgpu_gfx_off_ctrl(adev, true);
1081
1082 return size;
1083 }
1084
sienna_cichlid_populate_umd_state_clk(struct smu_context * smu)1085 static int sienna_cichlid_populate_umd_state_clk(struct smu_context *smu)
1086 {
1087 struct smu_11_0_dpm_context *dpm_context =
1088 smu->smu_dpm.dpm_context;
1089 struct smu_11_0_dpm_table *gfx_table =
1090 &dpm_context->dpm_tables.gfx_table;
1091 struct smu_11_0_dpm_table *mem_table =
1092 &dpm_context->dpm_tables.uclk_table;
1093 struct smu_11_0_dpm_table *soc_table =
1094 &dpm_context->dpm_tables.soc_table;
1095 struct smu_umd_pstate_table *pstate_table =
1096 &smu->pstate_table;
1097
1098 pstate_table->gfxclk_pstate.min = gfx_table->min;
1099 pstate_table->gfxclk_pstate.peak = gfx_table->max;
1100
1101 pstate_table->uclk_pstate.min = mem_table->min;
1102 pstate_table->uclk_pstate.peak = mem_table->max;
1103
1104 pstate_table->socclk_pstate.min = soc_table->min;
1105 pstate_table->socclk_pstate.peak = soc_table->max;
1106
1107 return 0;
1108 }
1109
sienna_cichlid_pre_display_config_changed(struct smu_context * smu)1110 static int sienna_cichlid_pre_display_config_changed(struct smu_context *smu)
1111 {
1112 int ret = 0;
1113 uint32_t max_freq = 0;
1114
1115 /* Sienna_Cichlid do not support to change display num currently */
1116 return 0;
1117 #if 0
1118 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL);
1119 if (ret)
1120 return ret;
1121 #endif
1122
1123 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1124 ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &max_freq);
1125 if (ret)
1126 return ret;
1127 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq);
1128 if (ret)
1129 return ret;
1130 }
1131
1132 return ret;
1133 }
1134
sienna_cichlid_display_config_changed(struct smu_context * smu)1135 static int sienna_cichlid_display_config_changed(struct smu_context *smu)
1136 {
1137 int ret = 0;
1138
1139 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1140 smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1141 smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1142 #if 0
1143 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
1144 smu->display_config->num_display,
1145 NULL);
1146 #endif
1147 if (ret)
1148 return ret;
1149 }
1150
1151 return ret;
1152 }
1153
sienna_cichlid_get_gpu_power(struct smu_context * smu,uint32_t * value)1154 static int sienna_cichlid_get_gpu_power(struct smu_context *smu, uint32_t *value)
1155 {
1156 if (!value)
1157 return -EINVAL;
1158
1159 return sienna_cichlid_get_smu_metrics_data(smu,
1160 METRICS_AVERAGE_SOCKETPOWER,
1161 value);
1162 }
1163
sienna_cichlid_get_current_activity_percent(struct smu_context * smu,enum amd_pp_sensors sensor,uint32_t * value)1164 static int sienna_cichlid_get_current_activity_percent(struct smu_context *smu,
1165 enum amd_pp_sensors sensor,
1166 uint32_t *value)
1167 {
1168 int ret = 0;
1169
1170 if (!value)
1171 return -EINVAL;
1172
1173 switch (sensor) {
1174 case AMDGPU_PP_SENSOR_GPU_LOAD:
1175 ret = sienna_cichlid_get_smu_metrics_data(smu,
1176 METRICS_AVERAGE_GFXACTIVITY,
1177 value);
1178 break;
1179 case AMDGPU_PP_SENSOR_MEM_LOAD:
1180 ret = sienna_cichlid_get_smu_metrics_data(smu,
1181 METRICS_AVERAGE_MEMACTIVITY,
1182 value);
1183 break;
1184 default:
1185 dev_err(smu->adev->dev, "Invalid sensor for retrieving clock activity\n");
1186 return -EINVAL;
1187 }
1188
1189 return ret;
1190 }
1191
sienna_cichlid_is_dpm_running(struct smu_context * smu)1192 static bool sienna_cichlid_is_dpm_running(struct smu_context *smu)
1193 {
1194 int ret = 0;
1195 uint32_t feature_mask[2];
1196 uint64_t feature_enabled;
1197
1198 ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
1199 if (ret)
1200 return false;
1201
1202 feature_enabled = (uint64_t)feature_mask[1] << 32 | feature_mask[0];
1203
1204 return !!(feature_enabled & SMC_DPM_FEATURE);
1205 }
1206
sienna_cichlid_get_fan_speed_rpm(struct smu_context * smu,uint32_t * speed)1207 static int sienna_cichlid_get_fan_speed_rpm(struct smu_context *smu,
1208 uint32_t *speed)
1209 {
1210 if (!speed)
1211 return -EINVAL;
1212
1213 return sienna_cichlid_get_smu_metrics_data(smu,
1214 METRICS_CURR_FANSPEED,
1215 speed);
1216 }
1217
sienna_cichlid_get_fan_parameters(struct smu_context * smu)1218 static int sienna_cichlid_get_fan_parameters(struct smu_context *smu)
1219 {
1220 PPTable_t *pptable = smu->smu_table.driver_pptable;
1221
1222 smu->fan_max_rpm = pptable->FanMaximumRpm;
1223
1224 return 0;
1225 }
1226
sienna_cichlid_get_power_profile_mode(struct smu_context * smu,char * buf)1227 static int sienna_cichlid_get_power_profile_mode(struct smu_context *smu, char *buf)
1228 {
1229 DpmActivityMonitorCoeffInt_t activity_monitor;
1230 uint32_t i, size = 0;
1231 int16_t workload_type = 0;
1232 static const char *profile_name[] = {
1233 "BOOTUP_DEFAULT",
1234 "3D_FULL_SCREEN",
1235 "POWER_SAVING",
1236 "VIDEO",
1237 "VR",
1238 "COMPUTE",
1239 "CUSTOM"};
1240 static const char *title[] = {
1241 "PROFILE_INDEX(NAME)",
1242 "CLOCK_TYPE(NAME)",
1243 "FPS",
1244 "MinFreqType",
1245 "MinActiveFreqType",
1246 "MinActiveFreq",
1247 "BoosterFreqType",
1248 "BoosterFreq",
1249 "PD_Data_limit_c",
1250 "PD_Data_error_coeff",
1251 "PD_Data_error_rate_coeff"};
1252 int result = 0;
1253
1254 if (!buf)
1255 return -EINVAL;
1256
1257 size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1258 title[0], title[1], title[2], title[3], title[4], title[5],
1259 title[6], title[7], title[8], title[9], title[10]);
1260
1261 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1262 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1263 workload_type = smu_cmn_to_asic_specific_index(smu,
1264 CMN2ASIC_MAPPING_WORKLOAD,
1265 i);
1266 if (workload_type < 0)
1267 return -EINVAL;
1268
1269 result = smu_cmn_update_table(smu,
1270 SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
1271 (void *)(&activity_monitor), false);
1272 if (result) {
1273 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1274 return result;
1275 }
1276
1277 size += sprintf(buf + size, "%2d %14s%s:\n",
1278 i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1279
1280 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1281 " ",
1282 0,
1283 "GFXCLK",
1284 activity_monitor.Gfx_FPS,
1285 activity_monitor.Gfx_MinFreqStep,
1286 activity_monitor.Gfx_MinActiveFreqType,
1287 activity_monitor.Gfx_MinActiveFreq,
1288 activity_monitor.Gfx_BoosterFreqType,
1289 activity_monitor.Gfx_BoosterFreq,
1290 activity_monitor.Gfx_PD_Data_limit_c,
1291 activity_monitor.Gfx_PD_Data_error_coeff,
1292 activity_monitor.Gfx_PD_Data_error_rate_coeff);
1293
1294 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1295 " ",
1296 1,
1297 "SOCCLK",
1298 activity_monitor.Fclk_FPS,
1299 activity_monitor.Fclk_MinFreqStep,
1300 activity_monitor.Fclk_MinActiveFreqType,
1301 activity_monitor.Fclk_MinActiveFreq,
1302 activity_monitor.Fclk_BoosterFreqType,
1303 activity_monitor.Fclk_BoosterFreq,
1304 activity_monitor.Fclk_PD_Data_limit_c,
1305 activity_monitor.Fclk_PD_Data_error_coeff,
1306 activity_monitor.Fclk_PD_Data_error_rate_coeff);
1307
1308 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1309 " ",
1310 2,
1311 "MEMLK",
1312 activity_monitor.Mem_FPS,
1313 activity_monitor.Mem_MinFreqStep,
1314 activity_monitor.Mem_MinActiveFreqType,
1315 activity_monitor.Mem_MinActiveFreq,
1316 activity_monitor.Mem_BoosterFreqType,
1317 activity_monitor.Mem_BoosterFreq,
1318 activity_monitor.Mem_PD_Data_limit_c,
1319 activity_monitor.Mem_PD_Data_error_coeff,
1320 activity_monitor.Mem_PD_Data_error_rate_coeff);
1321 }
1322
1323 return size;
1324 }
1325
sienna_cichlid_set_power_profile_mode(struct smu_context * smu,long * input,uint32_t size)1326 static int sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1327 {
1328 DpmActivityMonitorCoeffInt_t activity_monitor;
1329 int workload_type, ret = 0;
1330
1331 smu->power_profile_mode = input[size];
1332
1333 if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1334 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode);
1335 return -EINVAL;
1336 }
1337
1338 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1339
1340 ret = smu_cmn_update_table(smu,
1341 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1342 (void *)(&activity_monitor), false);
1343 if (ret) {
1344 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1345 return ret;
1346 }
1347
1348 switch (input[0]) {
1349 case 0: /* Gfxclk */
1350 activity_monitor.Gfx_FPS = input[1];
1351 activity_monitor.Gfx_MinFreqStep = input[2];
1352 activity_monitor.Gfx_MinActiveFreqType = input[3];
1353 activity_monitor.Gfx_MinActiveFreq = input[4];
1354 activity_monitor.Gfx_BoosterFreqType = input[5];
1355 activity_monitor.Gfx_BoosterFreq = input[6];
1356 activity_monitor.Gfx_PD_Data_limit_c = input[7];
1357 activity_monitor.Gfx_PD_Data_error_coeff = input[8];
1358 activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
1359 break;
1360 case 1: /* Socclk */
1361 activity_monitor.Fclk_FPS = input[1];
1362 activity_monitor.Fclk_MinFreqStep = input[2];
1363 activity_monitor.Fclk_MinActiveFreqType = input[3];
1364 activity_monitor.Fclk_MinActiveFreq = input[4];
1365 activity_monitor.Fclk_BoosterFreqType = input[5];
1366 activity_monitor.Fclk_BoosterFreq = input[6];
1367 activity_monitor.Fclk_PD_Data_limit_c = input[7];
1368 activity_monitor.Fclk_PD_Data_error_coeff = input[8];
1369 activity_monitor.Fclk_PD_Data_error_rate_coeff = input[9];
1370 break;
1371 case 2: /* Memlk */
1372 activity_monitor.Mem_FPS = input[1];
1373 activity_monitor.Mem_MinFreqStep = input[2];
1374 activity_monitor.Mem_MinActiveFreqType = input[3];
1375 activity_monitor.Mem_MinActiveFreq = input[4];
1376 activity_monitor.Mem_BoosterFreqType = input[5];
1377 activity_monitor.Mem_BoosterFreq = input[6];
1378 activity_monitor.Mem_PD_Data_limit_c = input[7];
1379 activity_monitor.Mem_PD_Data_error_coeff = input[8];
1380 activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
1381 break;
1382 }
1383
1384 ret = smu_cmn_update_table(smu,
1385 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1386 (void *)(&activity_monitor), true);
1387 if (ret) {
1388 dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
1389 return ret;
1390 }
1391 }
1392
1393 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1394 workload_type = smu_cmn_to_asic_specific_index(smu,
1395 CMN2ASIC_MAPPING_WORKLOAD,
1396 smu->power_profile_mode);
1397 if (workload_type < 0)
1398 return -EINVAL;
1399 smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1400 1 << workload_type, NULL);
1401
1402 return ret;
1403 }
1404
sienna_cichlid_notify_smc_display_config(struct smu_context * smu)1405 static int sienna_cichlid_notify_smc_display_config(struct smu_context *smu)
1406 {
1407 struct smu_clocks min_clocks = {0};
1408 struct pp_display_clock_request clock_req;
1409 int ret = 0;
1410
1411 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
1412 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
1413 min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
1414
1415 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1416 clock_req.clock_type = amd_pp_dcef_clock;
1417 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
1418
1419 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);
1420 if (!ret) {
1421 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
1422 ret = smu_cmn_send_smc_msg_with_param(smu,
1423 SMU_MSG_SetMinDeepSleepDcefclk,
1424 min_clocks.dcef_clock_in_sr/100,
1425 NULL);
1426 if (ret) {
1427 dev_err(smu->adev->dev, "Attempt to set divider for DCEFCLK Failed!");
1428 return ret;
1429 }
1430 }
1431 } else {
1432 dev_info(smu->adev->dev, "Attempt to set Hard Min for DCEFCLK Failed!");
1433 }
1434 }
1435
1436 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1437 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
1438 if (ret) {
1439 dev_err(smu->adev->dev, "[%s] Set hard min uclk failed!", __func__);
1440 return ret;
1441 }
1442 }
1443
1444 return 0;
1445 }
1446
sienna_cichlid_set_watermarks_table(struct smu_context * smu,struct pp_smu_wm_range_sets * clock_ranges)1447 static int sienna_cichlid_set_watermarks_table(struct smu_context *smu,
1448 struct pp_smu_wm_range_sets *clock_ranges)
1449 {
1450 Watermarks_t *table = smu->smu_table.watermarks_table;
1451 int ret = 0;
1452 int i;
1453
1454 if (clock_ranges) {
1455 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
1456 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
1457 return -EINVAL;
1458
1459 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
1460 table->WatermarkRow[WM_DCEFCLK][i].MinClock =
1461 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
1462 table->WatermarkRow[WM_DCEFCLK][i].MaxClock =
1463 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
1464 table->WatermarkRow[WM_DCEFCLK][i].MinUclk =
1465 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
1466 table->WatermarkRow[WM_DCEFCLK][i].MaxUclk =
1467 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
1468
1469 table->WatermarkRow[WM_DCEFCLK][i].WmSetting =
1470 clock_ranges->reader_wm_sets[i].wm_inst;
1471 }
1472
1473 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
1474 table->WatermarkRow[WM_SOCCLK][i].MinClock =
1475 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
1476 table->WatermarkRow[WM_SOCCLK][i].MaxClock =
1477 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
1478 table->WatermarkRow[WM_SOCCLK][i].MinUclk =
1479 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
1480 table->WatermarkRow[WM_SOCCLK][i].MaxUclk =
1481 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
1482
1483 table->WatermarkRow[WM_SOCCLK][i].WmSetting =
1484 clock_ranges->writer_wm_sets[i].wm_inst;
1485 }
1486
1487 smu->watermarks_bitmap |= WATERMARKS_EXIST;
1488 }
1489
1490 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1491 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
1492 ret = smu_cmn_write_watermarks_table(smu);
1493 if (ret) {
1494 dev_err(smu->adev->dev, "Failed to update WMTABLE!");
1495 return ret;
1496 }
1497 smu->watermarks_bitmap |= WATERMARKS_LOADED;
1498 }
1499
1500 return 0;
1501 }
1502
sienna_cichlid_thermal_get_temperature(struct smu_context * smu,enum amd_pp_sensors sensor,uint32_t * value)1503 static int sienna_cichlid_thermal_get_temperature(struct smu_context *smu,
1504 enum amd_pp_sensors sensor,
1505 uint32_t *value)
1506 {
1507 int ret = 0;
1508
1509 if (!value)
1510 return -EINVAL;
1511
1512 switch (sensor) {
1513 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1514 ret = sienna_cichlid_get_smu_metrics_data(smu,
1515 METRICS_TEMPERATURE_HOTSPOT,
1516 value);
1517 break;
1518 case AMDGPU_PP_SENSOR_EDGE_TEMP:
1519 ret = sienna_cichlid_get_smu_metrics_data(smu,
1520 METRICS_TEMPERATURE_EDGE,
1521 value);
1522 break;
1523 case AMDGPU_PP_SENSOR_MEM_TEMP:
1524 ret = sienna_cichlid_get_smu_metrics_data(smu,
1525 METRICS_TEMPERATURE_MEM,
1526 value);
1527 break;
1528 default:
1529 dev_err(smu->adev->dev, "Invalid sensor for retrieving temp\n");
1530 return -EINVAL;
1531 }
1532
1533 return ret;
1534 }
1535
sienna_cichlid_read_sensor(struct smu_context * smu,enum amd_pp_sensors sensor,void * data,uint32_t * size)1536 static int sienna_cichlid_read_sensor(struct smu_context *smu,
1537 enum amd_pp_sensors sensor,
1538 void *data, uint32_t *size)
1539 {
1540 int ret = 0;
1541 struct smu_table_context *table_context = &smu->smu_table;
1542 PPTable_t *pptable = table_context->driver_pptable;
1543
1544 if(!data || !size)
1545 return -EINVAL;
1546
1547 mutex_lock(&smu->sensor_lock);
1548 switch (sensor) {
1549 case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1550 *(uint32_t *)data = pptable->FanMaximumRpm;
1551 *size = 4;
1552 break;
1553 case AMDGPU_PP_SENSOR_MEM_LOAD:
1554 case AMDGPU_PP_SENSOR_GPU_LOAD:
1555 ret = sienna_cichlid_get_current_activity_percent(smu, sensor, (uint32_t *)data);
1556 *size = 4;
1557 break;
1558 case AMDGPU_PP_SENSOR_GPU_POWER:
1559 ret = sienna_cichlid_get_gpu_power(smu, (uint32_t *)data);
1560 *size = 4;
1561 break;
1562 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1563 case AMDGPU_PP_SENSOR_EDGE_TEMP:
1564 case AMDGPU_PP_SENSOR_MEM_TEMP:
1565 ret = sienna_cichlid_thermal_get_temperature(smu, sensor, (uint32_t *)data);
1566 *size = 4;
1567 break;
1568 case AMDGPU_PP_SENSOR_GFX_MCLK:
1569 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);
1570 *(uint32_t *)data *= 100;
1571 *size = 4;
1572 break;
1573 case AMDGPU_PP_SENSOR_GFX_SCLK:
1574 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data);
1575 *(uint32_t *)data *= 100;
1576 *size = 4;
1577 break;
1578 case AMDGPU_PP_SENSOR_VDDGFX:
1579 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
1580 *size = 4;
1581 break;
1582 default:
1583 ret = -EOPNOTSUPP;
1584 break;
1585 }
1586 mutex_unlock(&smu->sensor_lock);
1587
1588 return ret;
1589 }
1590
sienna_cichlid_get_uclk_dpm_states(struct smu_context * smu,uint32_t * clocks_in_khz,uint32_t * num_states)1591 static int sienna_cichlid_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
1592 {
1593 uint32_t num_discrete_levels = 0;
1594 uint16_t *dpm_levels = NULL;
1595 uint16_t i = 0;
1596 struct smu_table_context *table_context = &smu->smu_table;
1597 PPTable_t *driver_ppt = NULL;
1598
1599 if (!clocks_in_khz || !num_states || !table_context->driver_pptable)
1600 return -EINVAL;
1601
1602 driver_ppt = table_context->driver_pptable;
1603 num_discrete_levels = driver_ppt->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels;
1604 dpm_levels = driver_ppt->FreqTableUclk;
1605
1606 if (num_discrete_levels == 0 || dpm_levels == NULL)
1607 return -EINVAL;
1608
1609 *num_states = num_discrete_levels;
1610 for (i = 0; i < num_discrete_levels; i++) {
1611 /* convert to khz */
1612 *clocks_in_khz = (*dpm_levels) * 1000;
1613 clocks_in_khz++;
1614 dpm_levels++;
1615 }
1616
1617 return 0;
1618 }
1619
sienna_cichlid_get_thermal_temperature_range(struct smu_context * smu,struct smu_temperature_range * range)1620 static int sienna_cichlid_get_thermal_temperature_range(struct smu_context *smu,
1621 struct smu_temperature_range *range)
1622 {
1623 struct smu_table_context *table_context = &smu->smu_table;
1624 struct smu_11_0_7_powerplay_table *powerplay_table =
1625 table_context->power_play_table;
1626 PPTable_t *pptable = smu->smu_table.driver_pptable;
1627
1628 if (!range)
1629 return -EINVAL;
1630
1631 memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
1632
1633 range->max = pptable->TemperatureLimit[TEMP_EDGE] *
1634 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1635 range->edge_emergency_max = (pptable->TemperatureLimit[TEMP_EDGE] + CTF_OFFSET_EDGE) *
1636 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1637 range->hotspot_crit_max = pptable->TemperatureLimit[TEMP_HOTSPOT] *
1638 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1639 range->hotspot_emergency_max = (pptable->TemperatureLimit[TEMP_HOTSPOT] + CTF_OFFSET_HOTSPOT) *
1640 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1641 range->mem_crit_max = pptable->TemperatureLimit[TEMP_MEM] *
1642 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1643 range->mem_emergency_max = (pptable->TemperatureLimit[TEMP_MEM] + CTF_OFFSET_MEM)*
1644 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1645 range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
1646
1647 return 0;
1648 }
1649
sienna_cichlid_display_disable_memory_clock_switch(struct smu_context * smu,bool disable_memory_clock_switch)1650 static int sienna_cichlid_display_disable_memory_clock_switch(struct smu_context *smu,
1651 bool disable_memory_clock_switch)
1652 {
1653 int ret = 0;
1654 struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
1655 (struct smu_11_0_max_sustainable_clocks *)
1656 smu->smu_table.max_sustainable_clocks;
1657 uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;
1658 uint32_t max_memory_clock = max_sustainable_clocks->uclock;
1659
1660 if(smu->disable_uclk_switch == disable_memory_clock_switch)
1661 return 0;
1662
1663 if(disable_memory_clock_switch)
1664 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, max_memory_clock, 0);
1665 else
1666 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_memory_clock, 0);
1667
1668 if(!ret)
1669 smu->disable_uclk_switch = disable_memory_clock_switch;
1670
1671 return ret;
1672 }
1673
sienna_cichlid_get_power_limit(struct smu_context * smu)1674 static int sienna_cichlid_get_power_limit(struct smu_context *smu)
1675 {
1676 struct smu_11_0_7_powerplay_table *powerplay_table =
1677 (struct smu_11_0_7_powerplay_table *)smu->smu_table.power_play_table;
1678 PPTable_t *pptable = smu->smu_table.driver_pptable;
1679 uint32_t power_limit, od_percent;
1680
1681 if (smu_v11_0_get_current_power_limit(smu, &power_limit)) {
1682 /* the last hope to figure out the ppt limit */
1683 if (!pptable) {
1684 dev_err(smu->adev->dev, "Cannot get PPT limit due to pptable missing!");
1685 return -EINVAL;
1686 }
1687 power_limit =
1688 pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
1689 }
1690 smu->current_power_limit = power_limit;
1691
1692 if (smu->od_enabled) {
1693 od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_7_ODSETTING_POWERPERCENTAGE]);
1694
1695 dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit);
1696
1697 power_limit *= (100 + od_percent);
1698 power_limit /= 100;
1699 }
1700 smu->max_power_limit = power_limit;
1701
1702 return 0;
1703 }
1704
sienna_cichlid_update_pcie_parameters(struct smu_context * smu,uint32_t pcie_gen_cap,uint32_t pcie_width_cap)1705 static int sienna_cichlid_update_pcie_parameters(struct smu_context *smu,
1706 uint32_t pcie_gen_cap,
1707 uint32_t pcie_width_cap)
1708 {
1709 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
1710 PPTable_t *pptable = smu->smu_table.driver_pptable;
1711 uint32_t smu_pcie_arg;
1712 int ret, i;
1713
1714 /* lclk dpm table setup */
1715 for (i = 0; i < MAX_PCIE_CONF; i++) {
1716 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pptable->PcieGenSpeed[i];
1717 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pptable->PcieLaneCount[i];
1718 }
1719
1720 for (i = 0; i < NUM_LINK_LEVELS; i++) {
1721 smu_pcie_arg = (i << 16) |
1722 ((pptable->PcieGenSpeed[i] <= pcie_gen_cap) ?
1723 (pptable->PcieGenSpeed[i] << 8) :
1724 (pcie_gen_cap << 8)) |
1725 ((pptable->PcieLaneCount[i] <= pcie_width_cap) ?
1726 pptable->PcieLaneCount[i] :
1727 pcie_width_cap);
1728
1729 ret = smu_cmn_send_smc_msg_with_param(smu,
1730 SMU_MSG_OverridePcieParameters,
1731 smu_pcie_arg,
1732 NULL);
1733
1734 if (ret)
1735 return ret;
1736
1737 if (pptable->PcieGenSpeed[i] > pcie_gen_cap)
1738 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap;
1739 if (pptable->PcieLaneCount[i] > pcie_width_cap)
1740 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap;
1741 }
1742
1743 return 0;
1744 }
1745
sienna_cichlid_get_dpm_ultimate_freq(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min,uint32_t * max)1746 static int sienna_cichlid_get_dpm_ultimate_freq(struct smu_context *smu,
1747 enum smu_clk_type clk_type,
1748 uint32_t *min, uint32_t *max)
1749 {
1750 struct amdgpu_device *adev = smu->adev;
1751 int ret;
1752
1753 if (clk_type == SMU_GFXCLK)
1754 amdgpu_gfx_off_ctrl(adev, false);
1755 ret = smu_v11_0_get_dpm_ultimate_freq(smu, clk_type, min, max);
1756 if (clk_type == SMU_GFXCLK)
1757 amdgpu_gfx_off_ctrl(adev, true);
1758
1759 return ret;
1760 }
1761
sienna_cichlid_run_btc(struct smu_context * smu)1762 static int sienna_cichlid_run_btc(struct smu_context *smu)
1763 {
1764 return smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
1765 }
1766
sienna_cichlid_is_baco_supported(struct smu_context * smu)1767 static bool sienna_cichlid_is_baco_supported(struct smu_context *smu)
1768 {
1769 struct amdgpu_device *adev = smu->adev;
1770
1771 if (amdgpu_sriov_vf(adev) || (!smu_v11_0_baco_is_support(smu)))
1772 return false;
1773
1774 return true;
1775 }
1776
sienna_cichlid_is_mode1_reset_supported(struct smu_context * smu)1777 static bool sienna_cichlid_is_mode1_reset_supported(struct smu_context *smu)
1778 {
1779 struct amdgpu_device *adev = smu->adev;
1780 uint32_t val;
1781 u32 smu_version;
1782
1783 /**
1784 * SRIOV env will not support SMU mode1 reset
1785 * PM FW support mode1 reset from 58.26
1786 */
1787 smu_cmn_get_smc_version(smu, NULL, &smu_version);
1788 if (amdgpu_sriov_vf(adev) || (smu_version < 0x003a1a00))
1789 return false;
1790
1791 /**
1792 * mode1 reset relies on PSP, so we should check if
1793 * PSP is alive.
1794 */
1795 val = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
1796 return val != 0x0;
1797 }
1798
sienna_cichlid_dump_pptable(struct smu_context * smu)1799 static void sienna_cichlid_dump_pptable(struct smu_context *smu)
1800 {
1801 struct smu_table_context *table_context = &smu->smu_table;
1802 PPTable_t *pptable = table_context->driver_pptable;
1803 int i;
1804
1805 dev_info(smu->adev->dev, "Dumped PPTable:\n");
1806
1807 dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
1808 dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
1809 dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
1810
1811 for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
1812 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]);
1813 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]);
1814 dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]);
1815 dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]);
1816 }
1817
1818 for (i = 0; i < TDC_THROTTLER_COUNT; i++) {
1819 dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]);
1820 dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]);
1821 }
1822
1823 for (i = 0; i < TEMP_COUNT; i++) {
1824 dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]);
1825 }
1826
1827 dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit);
1828 dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig);
1829 dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]);
1830 dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]);
1831 dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]);
1832
1833 dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit);
1834 for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) {
1835 dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]);
1836 dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]);
1837 }
1838 dev_info(smu->adev->dev, "PaddingAPCC[0] = 0x%x\n", pptable->PaddingAPCC[0]);
1839 dev_info(smu->adev->dev, "PaddingAPCC[1] = 0x%x\n", pptable->PaddingAPCC[1]);
1840 dev_info(smu->adev->dev, "PaddingAPCC[2] = 0x%x\n", pptable->PaddingAPCC[2]);
1841 dev_info(smu->adev->dev, "PaddingAPCC[3] = 0x%x\n", pptable->PaddingAPCC[3]);
1842
1843 dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask);
1844
1845 dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask);
1846
1847 dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc);
1848 dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx);
1849 dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx);
1850 dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc);
1851
1852 dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin);
1853 dev_info(smu->adev->dev, "PaddingLIVmin = 0x%x\n", pptable->PaddingLIVmin);
1854
1855 dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold);
1856 dev_info(smu->adev->dev, "paddingRlcUlvParams[0] = 0x%x\n", pptable->paddingRlcUlvParams[0]);
1857 dev_info(smu->adev->dev, "paddingRlcUlvParams[1] = 0x%x\n", pptable->paddingRlcUlvParams[1]);
1858 dev_info(smu->adev->dev, "paddingRlcUlvParams[2] = 0x%x\n", pptable->paddingRlcUlvParams[2]);
1859
1860 dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx);
1861 dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc);
1862 dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx);
1863 dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc);
1864
1865 dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx);
1866 dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc);
1867
1868 dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin);
1869 dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin);
1870 dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp);
1871 dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp);
1872 dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp);
1873 dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp);
1874 dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis);
1875 dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis);
1876
1877 dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"
1878 " .VoltageMode = 0x%02x\n"
1879 " .SnapToDiscrete = 0x%02x\n"
1880 " .NumDiscreteLevels = 0x%02x\n"
1881 " .padding = 0x%02x\n"
1882 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1883 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1884 " .SsFmin = 0x%04x\n"
1885 " .Padding_16 = 0x%04x\n",
1886 pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
1887 pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
1888 pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
1889 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding,
1890 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
1891 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
1892 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
1893 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
1894 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
1895 pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
1896 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
1897
1898 dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"
1899 " .VoltageMode = 0x%02x\n"
1900 " .SnapToDiscrete = 0x%02x\n"
1901 " .NumDiscreteLevels = 0x%02x\n"
1902 " .padding = 0x%02x\n"
1903 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1904 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1905 " .SsFmin = 0x%04x\n"
1906 " .Padding_16 = 0x%04x\n",
1907 pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
1908 pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
1909 pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
1910 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding,
1911 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
1912 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
1913 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
1914 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
1915 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
1916 pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
1917 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
1918
1919 dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"
1920 " .VoltageMode = 0x%02x\n"
1921 " .SnapToDiscrete = 0x%02x\n"
1922 " .NumDiscreteLevels = 0x%02x\n"
1923 " .padding = 0x%02x\n"
1924 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1925 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1926 " .SsFmin = 0x%04x\n"
1927 " .Padding_16 = 0x%04x\n",
1928 pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
1929 pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
1930 pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
1931 pptable->DpmDescriptor[PPCLK_UCLK].Padding,
1932 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
1933 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
1934 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
1935 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
1936 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
1937 pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
1938 pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
1939
1940 dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"
1941 " .VoltageMode = 0x%02x\n"
1942 " .SnapToDiscrete = 0x%02x\n"
1943 " .NumDiscreteLevels = 0x%02x\n"
1944 " .padding = 0x%02x\n"
1945 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1946 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1947 " .SsFmin = 0x%04x\n"
1948 " .Padding_16 = 0x%04x\n",
1949 pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
1950 pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
1951 pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
1952 pptable->DpmDescriptor[PPCLK_FCLK].Padding,
1953 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
1954 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
1955 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
1956 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
1957 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
1958 pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
1959 pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
1960
1961 dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n"
1962 " .VoltageMode = 0x%02x\n"
1963 " .SnapToDiscrete = 0x%02x\n"
1964 " .NumDiscreteLevels = 0x%02x\n"
1965 " .padding = 0x%02x\n"
1966 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1967 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1968 " .SsFmin = 0x%04x\n"
1969 " .Padding_16 = 0x%04x\n",
1970 pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode,
1971 pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete,
1972 pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels,
1973 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding,
1974 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m,
1975 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b,
1976 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a,
1977 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b,
1978 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c,
1979 pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin,
1980 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16);
1981
1982 dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n"
1983 " .VoltageMode = 0x%02x\n"
1984 " .SnapToDiscrete = 0x%02x\n"
1985 " .NumDiscreteLevels = 0x%02x\n"
1986 " .padding = 0x%02x\n"
1987 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1988 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1989 " .SsFmin = 0x%04x\n"
1990 " .Padding_16 = 0x%04x\n",
1991 pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode,
1992 pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete,
1993 pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels,
1994 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding,
1995 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m,
1996 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b,
1997 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a,
1998 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b,
1999 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c,
2000 pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin,
2001 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16);
2002
2003 dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n"
2004 " .VoltageMode = 0x%02x\n"
2005 " .SnapToDiscrete = 0x%02x\n"
2006 " .NumDiscreteLevels = 0x%02x\n"
2007 " .padding = 0x%02x\n"
2008 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2009 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2010 " .SsFmin = 0x%04x\n"
2011 " .Padding_16 = 0x%04x\n",
2012 pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode,
2013 pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete,
2014 pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels,
2015 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding,
2016 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m,
2017 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b,
2018 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a,
2019 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b,
2020 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c,
2021 pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin,
2022 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16);
2023
2024 dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n"
2025 " .VoltageMode = 0x%02x\n"
2026 " .SnapToDiscrete = 0x%02x\n"
2027 " .NumDiscreteLevels = 0x%02x\n"
2028 " .padding = 0x%02x\n"
2029 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2030 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2031 " .SsFmin = 0x%04x\n"
2032 " .Padding_16 = 0x%04x\n",
2033 pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode,
2034 pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete,
2035 pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels,
2036 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding,
2037 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m,
2038 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b,
2039 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a,
2040 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b,
2041 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c,
2042 pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin,
2043 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16);
2044
2045 dev_info(smu->adev->dev, "FreqTableGfx\n");
2046 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
2047 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]);
2048
2049 dev_info(smu->adev->dev, "FreqTableVclk\n");
2050 for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
2051 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]);
2052
2053 dev_info(smu->adev->dev, "FreqTableDclk\n");
2054 for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
2055 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]);
2056
2057 dev_info(smu->adev->dev, "FreqTableSocclk\n");
2058 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
2059 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]);
2060
2061 dev_info(smu->adev->dev, "FreqTableUclk\n");
2062 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2063 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]);
2064
2065 dev_info(smu->adev->dev, "FreqTableFclk\n");
2066 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
2067 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]);
2068
2069 dev_info(smu->adev->dev, "Paddingclks[0] = 0x%x\n", pptable->Paddingclks[0]);
2070 dev_info(smu->adev->dev, "Paddingclks[1] = 0x%x\n", pptable->Paddingclks[1]);
2071 dev_info(smu->adev->dev, "Paddingclks[2] = 0x%x\n", pptable->Paddingclks[2]);
2072 dev_info(smu->adev->dev, "Paddingclks[3] = 0x%x\n", pptable->Paddingclks[3]);
2073 dev_info(smu->adev->dev, "Paddingclks[4] = 0x%x\n", pptable->Paddingclks[4]);
2074 dev_info(smu->adev->dev, "Paddingclks[5] = 0x%x\n", pptable->Paddingclks[5]);
2075 dev_info(smu->adev->dev, "Paddingclks[6] = 0x%x\n", pptable->Paddingclks[6]);
2076 dev_info(smu->adev->dev, "Paddingclks[7] = 0x%x\n", pptable->Paddingclks[7]);
2077 dev_info(smu->adev->dev, "Paddingclks[8] = 0x%x\n", pptable->Paddingclks[8]);
2078 dev_info(smu->adev->dev, "Paddingclks[9] = 0x%x\n", pptable->Paddingclks[9]);
2079 dev_info(smu->adev->dev, "Paddingclks[10] = 0x%x\n", pptable->Paddingclks[10]);
2080 dev_info(smu->adev->dev, "Paddingclks[11] = 0x%x\n", pptable->Paddingclks[11]);
2081 dev_info(smu->adev->dev, "Paddingclks[12] = 0x%x\n", pptable->Paddingclks[12]);
2082 dev_info(smu->adev->dev, "Paddingclks[13] = 0x%x\n", pptable->Paddingclks[13]);
2083 dev_info(smu->adev->dev, "Paddingclks[14] = 0x%x\n", pptable->Paddingclks[14]);
2084 dev_info(smu->adev->dev, "Paddingclks[15] = 0x%x\n", pptable->Paddingclks[15]);
2085
2086 dev_info(smu->adev->dev, "DcModeMaxFreq\n");
2087 dev_info(smu->adev->dev, " .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);
2088 dev_info(smu->adev->dev, " .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]);
2089 dev_info(smu->adev->dev, " .PPCLK_UCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]);
2090 dev_info(smu->adev->dev, " .PPCLK_FCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]);
2091 dev_info(smu->adev->dev, " .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]);
2092 dev_info(smu->adev->dev, " .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]);
2093 dev_info(smu->adev->dev, " .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]);
2094 dev_info(smu->adev->dev, " .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]);
2095
2096 dev_info(smu->adev->dev, "FreqTableUclkDiv\n");
2097 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2098 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]);
2099
2100 dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq);
2101 dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding);
2102
2103 dev_info(smu->adev->dev, "Mp0clkFreq\n");
2104 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
2105 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]);
2106
2107 dev_info(smu->adev->dev, "Mp0DpmVoltage\n");
2108 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
2109 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]);
2110
2111 dev_info(smu->adev->dev, "MemVddciVoltage\n");
2112 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2113 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]);
2114
2115 dev_info(smu->adev->dev, "MemMvddVoltage\n");
2116 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2117 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]);
2118
2119 dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry);
2120 dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit);
2121 dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
2122 dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource);
2123 dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding);
2124
2125 dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask);
2126
2127 dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask);
2128 dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask);
2129 dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]);
2130 dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow);
2131 dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]);
2132 dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]);
2133 dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]);
2134 dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]);
2135 dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt);
2136 dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt);
2137 dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt);
2138
2139 dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage);
2140 dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime);
2141 dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime);
2142 dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum);
2143 dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis);
2144 dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout);
2145
2146 dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]);
2147 dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]);
2148 dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]);
2149 dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]);
2150 dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]);
2151
2152 dev_info(smu->adev->dev, "FlopsPerByteTable\n");
2153 for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++)
2154 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]);
2155
2156 dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv);
2157 dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]);
2158 dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]);
2159 dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]);
2160
2161 dev_info(smu->adev->dev, "UclkDpmPstates\n");
2162 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2163 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]);
2164
2165 dev_info(smu->adev->dev, "UclkDpmSrcFreqRange\n");
2166 dev_info(smu->adev->dev, " .Fmin = 0x%x\n",
2167 pptable->UclkDpmSrcFreqRange.Fmin);
2168 dev_info(smu->adev->dev, " .Fmax = 0x%x\n",
2169 pptable->UclkDpmSrcFreqRange.Fmax);
2170 dev_info(smu->adev->dev, "UclkDpmTargFreqRange\n");
2171 dev_info(smu->adev->dev, " .Fmin = 0x%x\n",
2172 pptable->UclkDpmTargFreqRange.Fmin);
2173 dev_info(smu->adev->dev, " .Fmax = 0x%x\n",
2174 pptable->UclkDpmTargFreqRange.Fmax);
2175 dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq);
2176 dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding);
2177
2178 dev_info(smu->adev->dev, "PcieGenSpeed\n");
2179 for (i = 0; i < NUM_LINK_LEVELS; i++)
2180 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]);
2181
2182 dev_info(smu->adev->dev, "PcieLaneCount\n");
2183 for (i = 0; i < NUM_LINK_LEVELS; i++)
2184 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]);
2185
2186 dev_info(smu->adev->dev, "LclkFreq\n");
2187 for (i = 0; i < NUM_LINK_LEVELS; i++)
2188 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->LclkFreq[i]);
2189
2190 dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp);
2191 dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp);
2192
2193 dev_info(smu->adev->dev, "FanGain\n");
2194 for (i = 0; i < TEMP_COUNT; i++)
2195 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FanGain[i]);
2196
2197 dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin);
2198 dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm);
2199 dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm);
2200 dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm);
2201 dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm);
2202 dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature);
2203 dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk);
2204 dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16);
2205 dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect);
2206 dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding);
2207 dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable);
2208 dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev);
2209
2210 dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta);
2211 dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta);
2212 dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta);
2213 dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved);
2214
2215 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
2216 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
2217 dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect);
2218 dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs);
2219
2220 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
2221 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a,
2222 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b,
2223 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c);
2224 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
2225 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a,
2226 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b,
2227 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c);
2228 dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
2229 pptable->dBtcGbGfxPll.a,
2230 pptable->dBtcGbGfxPll.b,
2231 pptable->dBtcGbGfxPll.c);
2232 dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
2233 pptable->dBtcGbGfxDfll.a,
2234 pptable->dBtcGbGfxDfll.b,
2235 pptable->dBtcGbGfxDfll.c);
2236 dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
2237 pptable->dBtcGbSoc.a,
2238 pptable->dBtcGbSoc.b,
2239 pptable->dBtcGbSoc.c);
2240 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
2241 pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
2242 pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
2243 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
2244 pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
2245 pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
2246
2247 dev_info(smu->adev->dev, "PiecewiseLinearDroopIntGfxDfll\n");
2248 for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) {
2249 dev_info(smu->adev->dev, " Fset[%d] = 0x%x\n",
2250 i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]);
2251 dev_info(smu->adev->dev, " Vdroop[%d] = 0x%x\n",
2252 i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]);
2253 }
2254
2255 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
2256 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
2257 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
2258 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
2259 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
2260 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
2261 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
2262 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
2263
2264 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
2265 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
2266
2267 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
2268 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
2269 dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
2270 dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
2271
2272 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
2273 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
2274 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
2275 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
2276
2277 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
2278 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
2279
2280 dev_info(smu->adev->dev, "XgmiDpmPstates\n");
2281 for (i = 0; i < NUM_XGMI_LEVELS; i++)
2282 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]);
2283 dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
2284 dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
2285
2286 dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides);
2287 dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
2288 pptable->ReservedEquation0.a,
2289 pptable->ReservedEquation0.b,
2290 pptable->ReservedEquation0.c);
2291 dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
2292 pptable->ReservedEquation1.a,
2293 pptable->ReservedEquation1.b,
2294 pptable->ReservedEquation1.c);
2295 dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
2296 pptable->ReservedEquation2.a,
2297 pptable->ReservedEquation2.b,
2298 pptable->ReservedEquation2.c);
2299 dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
2300 pptable->ReservedEquation3.a,
2301 pptable->ReservedEquation3.b,
2302 pptable->ReservedEquation3.c);
2303
2304 dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]);
2305 dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]);
2306 dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]);
2307 dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]);
2308 dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]);
2309 dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]);
2310 dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]);
2311 dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]);
2312 dev_info(smu->adev->dev, "SkuReserved[8] = 0x%x\n", pptable->SkuReserved[8]);
2313
2314 dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]);
2315 dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]);
2316 dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2]);
2317 dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3]);
2318 dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4]);
2319 dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5]);
2320
2321 for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
2322 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i);
2323 dev_info(smu->adev->dev, " .Enabled = 0x%x\n",
2324 pptable->I2cControllers[i].Enabled);
2325 dev_info(smu->adev->dev, " .Speed = 0x%x\n",
2326 pptable->I2cControllers[i].Speed);
2327 dev_info(smu->adev->dev, " .SlaveAddress = 0x%x\n",
2328 pptable->I2cControllers[i].SlaveAddress);
2329 dev_info(smu->adev->dev, " .ControllerPort = 0x%x\n",
2330 pptable->I2cControllers[i].ControllerPort);
2331 dev_info(smu->adev->dev, " .ControllerName = 0x%x\n",
2332 pptable->I2cControllers[i].ControllerName);
2333 dev_info(smu->adev->dev, " .ThermalThrottler = 0x%x\n",
2334 pptable->I2cControllers[i].ThermalThrotter);
2335 dev_info(smu->adev->dev, " .I2cProtocol = 0x%x\n",
2336 pptable->I2cControllers[i].I2cProtocol);
2337 dev_info(smu->adev->dev, " .PaddingConfig = 0x%x\n",
2338 pptable->I2cControllers[i].PaddingConfig);
2339 }
2340
2341 dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl);
2342 dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda);
2343 dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr);
2344 dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]);
2345
2346 dev_info(smu->adev->dev, "Board Parameters:\n");
2347 dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
2348 dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
2349 dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping);
2350 dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping);
2351 dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
2352 dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask);
2353 dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask);
2354 dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask);
2355
2356 dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
2357 dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset);
2358 dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
2359
2360 dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
2361 dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset);
2362 dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
2363
2364 dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent);
2365 dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset);
2366 dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0);
2367
2368 dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent);
2369 dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset);
2370 dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1);
2371
2372 dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio);
2373
2374 dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio);
2375 dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity);
2376 dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio);
2377 dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity);
2378 dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio);
2379 dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity);
2380 dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio);
2381 dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity);
2382 dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0);
2383 dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1);
2384 dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2);
2385 dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask);
2386 dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie);
2387 dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError);
2388 dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]);
2389 dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]);
2390
2391 dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled);
2392 dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent);
2393 dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n", pptable->PllGfxclkSpreadFreq);
2394
2395 dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled);
2396 dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent);
2397 dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n", pptable->DfllGfxclkSpreadFreq);
2398
2399 dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding);
2400 dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq);
2401
2402 dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled);
2403 dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent);
2404 dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq);
2405
2406 dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled);
2407 dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth);
2408 dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]);
2409 dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]);
2410 dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]);
2411
2412 dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower);
2413 dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding);
2414
2415 dev_info(smu->adev->dev, "XgmiLinkSpeed\n");
2416 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2417 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]);
2418 dev_info(smu->adev->dev, "XgmiLinkWidth\n");
2419 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2420 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]);
2421 dev_info(smu->adev->dev, "XgmiFclkFreq\n");
2422 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2423 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]);
2424 dev_info(smu->adev->dev, "XgmiSocVoltage\n");
2425 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2426 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]);
2427
2428 dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled);
2429 dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled);
2430 dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]);
2431 dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]);
2432
2433 dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]);
2434 dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]);
2435 dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]);
2436 dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]);
2437 dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]);
2438 dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]);
2439 dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]);
2440 dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]);
2441 dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]);
2442 dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]);
2443 dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]);
2444
2445 dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]);
2446 dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]);
2447 dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]);
2448 dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]);
2449 dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]);
2450 dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]);
2451 dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]);
2452 dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]);
2453 }
2454
sienna_cichlid_fill_i2c_req(SwI2cRequest_t * req,bool write,uint8_t address,uint32_t numbytes,uint8_t * data)2455 static void sienna_cichlid_fill_i2c_req(SwI2cRequest_t *req, bool write,
2456 uint8_t address, uint32_t numbytes,
2457 uint8_t *data)
2458 {
2459 int i;
2460
2461 req->I2CcontrollerPort = 0;
2462 req->I2CSpeed = 2;
2463 req->SlaveAddress = address;
2464 req->NumCmds = numbytes;
2465
2466 for (i = 0; i < numbytes; i++) {
2467 SwI2cCmd_t *cmd = &req->SwI2cCmds[i];
2468
2469 /* First 2 bytes are always write for lower 2b EEPROM address */
2470 if (i < 2)
2471 cmd->CmdConfig = CMDCONFIG_READWRITE_MASK;
2472 else
2473 cmd->CmdConfig = write ? CMDCONFIG_READWRITE_MASK : 0;
2474
2475
2476 /* Add RESTART for read after address filled */
2477 cmd->CmdConfig |= (i == 2 && !write) ? CMDCONFIG_RESTART_MASK : 0;
2478
2479 /* Add STOP in the end */
2480 cmd->CmdConfig |= (i == (numbytes - 1)) ? CMDCONFIG_STOP_MASK : 0;
2481
2482 /* Fill with data regardless if read or write to simplify code */
2483 cmd->ReadWriteData = data[i];
2484 }
2485 }
2486
sienna_cichlid_i2c_read_data(struct i2c_adapter * control,uint8_t address,uint8_t * data,uint32_t numbytes)2487 static int sienna_cichlid_i2c_read_data(struct i2c_adapter *control,
2488 uint8_t address,
2489 uint8_t *data,
2490 uint32_t numbytes)
2491 {
2492 uint32_t i, ret = 0;
2493 SwI2cRequest_t req;
2494 struct amdgpu_device *adev = to_amdgpu_device(control);
2495 struct smu_table_context *smu_table = &adev->smu.smu_table;
2496 struct smu_table *table = &smu_table->driver_table;
2497
2498 if (numbytes > MAX_SW_I2C_COMMANDS) {
2499 dev_err(adev->dev, "numbytes requested %d is over max allowed %d\n",
2500 numbytes, MAX_SW_I2C_COMMANDS);
2501 return -EINVAL;
2502 }
2503
2504 memset(&req, 0, sizeof(req));
2505 sienna_cichlid_fill_i2c_req(&req, false, address, numbytes, data);
2506
2507 mutex_lock(&adev->smu.mutex);
2508 /* Now read data starting with that address */
2509 ret = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req,
2510 true);
2511 mutex_unlock(&adev->smu.mutex);
2512
2513 if (!ret) {
2514 SwI2cRequest_t *res = (SwI2cRequest_t *)table->cpu_addr;
2515
2516 /* Assume SMU fills res.SwI2cCmds[i].Data with read bytes */
2517 for (i = 0; i < numbytes; i++)
2518 data[i] = res->SwI2cCmds[i].ReadWriteData;
2519
2520 dev_dbg(adev->dev, "sienna_cichlid_i2c_read_data, address = %x, bytes = %d, data :",
2521 (uint16_t)address, numbytes);
2522
2523 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE,
2524 8, 1, data, numbytes, false);
2525 } else
2526 dev_err(adev->dev, "sienna_cichlid_i2c_read_data - error occurred :%x", ret);
2527
2528 return ret;
2529 }
2530
sienna_cichlid_i2c_write_data(struct i2c_adapter * control,uint8_t address,uint8_t * data,uint32_t numbytes)2531 static int sienna_cichlid_i2c_write_data(struct i2c_adapter *control,
2532 uint8_t address,
2533 uint8_t *data,
2534 uint32_t numbytes)
2535 {
2536 uint32_t ret;
2537 SwI2cRequest_t req;
2538 struct amdgpu_device *adev = to_amdgpu_device(control);
2539
2540 if (numbytes > MAX_SW_I2C_COMMANDS) {
2541 dev_err(adev->dev, "numbytes requested %d is over max allowed %d\n",
2542 numbytes, MAX_SW_I2C_COMMANDS);
2543 return -EINVAL;
2544 }
2545
2546 memset(&req, 0, sizeof(req));
2547 sienna_cichlid_fill_i2c_req(&req, true, address, numbytes, data);
2548
2549 mutex_lock(&adev->smu.mutex);
2550 ret = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req, true);
2551 mutex_unlock(&adev->smu.mutex);
2552
2553 if (!ret) {
2554 dev_dbg(adev->dev, "sienna_cichlid_i2c_write(), address = %x, bytes = %d , data: ",
2555 (uint16_t)address, numbytes);
2556
2557 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE,
2558 8, 1, data, numbytes, false);
2559 /*
2560 * According to EEPROM spec there is a MAX of 10 ms required for
2561 * EEPROM to flush internal RX buffer after STOP was issued at the
2562 * end of write transaction. During this time the EEPROM will not be
2563 * responsive to any more commands - so wait a bit more.
2564 */
2565 msleep(10);
2566
2567 } else
2568 dev_err(adev->dev, "sienna_cichlid_i2c_write- error occurred :%x", ret);
2569
2570 return ret;
2571 }
2572
sienna_cichlid_i2c_xfer(struct i2c_adapter * i2c_adap,struct i2c_msg * msgs,int num)2573 static int sienna_cichlid_i2c_xfer(struct i2c_adapter *i2c_adap,
2574 struct i2c_msg *msgs, int num)
2575 {
2576 uint32_t i, j, ret, data_size, data_chunk_size, next_eeprom_addr = 0;
2577 uint8_t *data_ptr, data_chunk[MAX_SW_I2C_COMMANDS] = { 0 };
2578
2579 for (i = 0; i < num; i++) {
2580 /*
2581 * SMU interface allows at most MAX_SW_I2C_COMMANDS bytes of data at
2582 * once and hence the data needs to be spliced into chunks and sent each
2583 * chunk separately
2584 */
2585 data_size = msgs[i].len - 2;
2586 data_chunk_size = MAX_SW_I2C_COMMANDS - 2;
2587 next_eeprom_addr = (msgs[i].buf[0] << 8 & 0xff00) | (msgs[i].buf[1] & 0xff);
2588 data_ptr = msgs[i].buf + 2;
2589
2590 for (j = 0; j < data_size / data_chunk_size; j++) {
2591 /* Insert the EEPROM dest addess, bits 0-15 */
2592 data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
2593 data_chunk[1] = (next_eeprom_addr & 0xff);
2594
2595 if (msgs[i].flags & I2C_M_RD) {
2596 ret = sienna_cichlid_i2c_read_data(i2c_adap,
2597 (uint8_t)msgs[i].addr,
2598 data_chunk, MAX_SW_I2C_COMMANDS);
2599
2600 memcpy(data_ptr, data_chunk + 2, data_chunk_size);
2601 } else {
2602
2603 memcpy(data_chunk + 2, data_ptr, data_chunk_size);
2604
2605 ret = sienna_cichlid_i2c_write_data(i2c_adap,
2606 (uint8_t)msgs[i].addr,
2607 data_chunk, MAX_SW_I2C_COMMANDS);
2608 }
2609
2610 if (ret) {
2611 num = -EIO;
2612 goto fail;
2613 }
2614
2615 next_eeprom_addr += data_chunk_size;
2616 data_ptr += data_chunk_size;
2617 }
2618
2619 if (data_size % data_chunk_size) {
2620 data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
2621 data_chunk[1] = (next_eeprom_addr & 0xff);
2622
2623 if (msgs[i].flags & I2C_M_RD) {
2624 ret = sienna_cichlid_i2c_read_data(i2c_adap,
2625 (uint8_t)msgs[i].addr,
2626 data_chunk, (data_size % data_chunk_size) + 2);
2627
2628 memcpy(data_ptr, data_chunk + 2, data_size % data_chunk_size);
2629 } else {
2630 memcpy(data_chunk + 2, data_ptr, data_size % data_chunk_size);
2631
2632 ret = sienna_cichlid_i2c_write_data(i2c_adap,
2633 (uint8_t)msgs[i].addr,
2634 data_chunk, (data_size % data_chunk_size) + 2);
2635 }
2636
2637 if (ret) {
2638 num = -EIO;
2639 goto fail;
2640 }
2641 }
2642 }
2643
2644 fail:
2645 return num;
2646 }
2647
sienna_cichlid_i2c_func(struct i2c_adapter * adap)2648 static u32 sienna_cichlid_i2c_func(struct i2c_adapter *adap)
2649 {
2650 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
2651 }
2652
2653
2654 static const struct i2c_algorithm sienna_cichlid_i2c_algo = {
2655 .master_xfer = sienna_cichlid_i2c_xfer,
2656 .functionality = sienna_cichlid_i2c_func,
2657 };
2658
sienna_cichlid_i2c_control_init(struct smu_context * smu,struct i2c_adapter * control)2659 static int sienna_cichlid_i2c_control_init(struct smu_context *smu, struct i2c_adapter *control)
2660 {
2661 struct amdgpu_device *adev = to_amdgpu_device(control);
2662 int res;
2663
2664 control->owner = THIS_MODULE;
2665 control->class = I2C_CLASS_SPD;
2666 control->dev.parent = &adev->pdev->dev;
2667 control->algo = &sienna_cichlid_i2c_algo;
2668 snprintf(control->name, sizeof(control->name), "AMDGPU SMU");
2669
2670 res = i2c_add_adapter(control);
2671 if (res)
2672 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
2673
2674 return res;
2675 }
2676
sienna_cichlid_i2c_control_fini(struct smu_context * smu,struct i2c_adapter * control)2677 static void sienna_cichlid_i2c_control_fini(struct smu_context *smu, struct i2c_adapter *control)
2678 {
2679 i2c_del_adapter(control);
2680 }
2681
sienna_cichlid_get_gpu_metrics(struct smu_context * smu,void ** table)2682 static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu,
2683 void **table)
2684 {
2685 struct smu_table_context *smu_table = &smu->smu_table;
2686 struct gpu_metrics_v1_0 *gpu_metrics =
2687 (struct gpu_metrics_v1_0 *)smu_table->gpu_metrics_table;
2688 SmuMetrics_t metrics;
2689 int ret = 0;
2690
2691 ret = smu_cmn_get_metrics_table(smu,
2692 &metrics,
2693 true);
2694 if (ret)
2695 return ret;
2696
2697 smu_v11_0_init_gpu_metrics_v1_0(gpu_metrics);
2698
2699 gpu_metrics->temperature_edge = metrics.TemperatureEdge;
2700 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
2701 gpu_metrics->temperature_mem = metrics.TemperatureMem;
2702 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
2703 gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc;
2704 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0;
2705
2706 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
2707 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
2708 gpu_metrics->average_mm_activity = metrics.VcnActivityPercentage;
2709
2710 gpu_metrics->average_socket_power = metrics.AverageSocketPower;
2711 gpu_metrics->energy_accumulator = metrics.EnergyAccumulator;
2712
2713 if (metrics.AverageGfxActivity <= SMU_11_0_7_GFX_BUSY_THRESHOLD)
2714 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPostDs;
2715 else
2716 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPreDs;
2717 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequencyPostDs;
2718 gpu_metrics->average_vclk0_frequency = metrics.AverageVclk0Frequency;
2719 gpu_metrics->average_dclk0_frequency = metrics.AverageDclk0Frequency;
2720 gpu_metrics->average_vclk1_frequency = metrics.AverageVclk1Frequency;
2721 gpu_metrics->average_dclk1_frequency = metrics.AverageDclk1Frequency;
2722
2723 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
2724 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
2725 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
2726 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK_0];
2727 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK_0];
2728 gpu_metrics->current_vclk1 = metrics.CurrClock[PPCLK_VCLK_1];
2729 gpu_metrics->current_dclk1 = metrics.CurrClock[PPCLK_DCLK_1];
2730
2731 gpu_metrics->throttle_status = metrics.ThrottlerStatus;
2732
2733 gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
2734
2735 gpu_metrics->pcie_link_width =
2736 smu_v11_0_get_current_pcie_link_width(smu);
2737 gpu_metrics->pcie_link_speed =
2738 smu_v11_0_get_current_pcie_link_speed(smu);
2739
2740 *table = (void *)gpu_metrics;
2741
2742 return sizeof(struct gpu_metrics_v1_0);
2743 }
2744
sienna_cichlid_enable_mgpu_fan_boost(struct smu_context * smu)2745 static int sienna_cichlid_enable_mgpu_fan_boost(struct smu_context *smu)
2746 {
2747 struct smu_table_context *table_context = &smu->smu_table;
2748 PPTable_t *smc_pptable = table_context->driver_pptable;
2749
2750 /*
2751 * Skip the MGpuFanBoost setting for those ASICs
2752 * which do not support it
2753 */
2754 if (!smc_pptable->MGpuFanBoostLimitRpm)
2755 return 0;
2756
2757 return smu_cmn_send_smc_msg_with_param(smu,
2758 SMU_MSG_SetMGpuFanBoostLimitRpm,
2759 0,
2760 NULL);
2761 }
2762
2763 static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
2764 .get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask,
2765 .set_default_dpm_table = sienna_cichlid_set_default_dpm_table,
2766 .dpm_set_vcn_enable = sienna_cichlid_dpm_set_vcn_enable,
2767 .dpm_set_jpeg_enable = sienna_cichlid_dpm_set_jpeg_enable,
2768 .i2c_init = sienna_cichlid_i2c_control_init,
2769 .i2c_fini = sienna_cichlid_i2c_control_fini,
2770 .print_clk_levels = sienna_cichlid_print_clk_levels,
2771 .force_clk_levels = sienna_cichlid_force_clk_levels,
2772 .populate_umd_state_clk = sienna_cichlid_populate_umd_state_clk,
2773 .pre_display_config_changed = sienna_cichlid_pre_display_config_changed,
2774 .display_config_changed = sienna_cichlid_display_config_changed,
2775 .notify_smc_display_config = sienna_cichlid_notify_smc_display_config,
2776 .is_dpm_running = sienna_cichlid_is_dpm_running,
2777 .get_fan_speed_rpm = sienna_cichlid_get_fan_speed_rpm,
2778 .get_power_profile_mode = sienna_cichlid_get_power_profile_mode,
2779 .set_power_profile_mode = sienna_cichlid_set_power_profile_mode,
2780 .set_watermarks_table = sienna_cichlid_set_watermarks_table,
2781 .read_sensor = sienna_cichlid_read_sensor,
2782 .get_uclk_dpm_states = sienna_cichlid_get_uclk_dpm_states,
2783 .set_performance_level = smu_v11_0_set_performance_level,
2784 .get_thermal_temperature_range = sienna_cichlid_get_thermal_temperature_range,
2785 .display_disable_memory_clock_switch = sienna_cichlid_display_disable_memory_clock_switch,
2786 .get_power_limit = sienna_cichlid_get_power_limit,
2787 .update_pcie_parameters = sienna_cichlid_update_pcie_parameters,
2788 .dump_pptable = sienna_cichlid_dump_pptable,
2789 .init_microcode = smu_v11_0_init_microcode,
2790 .load_microcode = smu_v11_0_load_microcode,
2791 .fini_microcode = smu_v11_0_fini_microcode,
2792 .init_smc_tables = sienna_cichlid_init_smc_tables,
2793 .fini_smc_tables = smu_v11_0_fini_smc_tables,
2794 .init_power = smu_v11_0_init_power,
2795 .fini_power = smu_v11_0_fini_power,
2796 .check_fw_status = smu_v11_0_check_fw_status,
2797 .setup_pptable = sienna_cichlid_setup_pptable,
2798 .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
2799 .check_fw_version = smu_v11_0_check_fw_version,
2800 .write_pptable = smu_cmn_write_pptable,
2801 .set_driver_table_location = smu_v11_0_set_driver_table_location,
2802 .set_tool_table_location = smu_v11_0_set_tool_table_location,
2803 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
2804 .system_features_control = smu_v11_0_system_features_control,
2805 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
2806 .send_smc_msg = smu_cmn_send_smc_msg,
2807 .init_display_count = NULL,
2808 .set_allowed_mask = smu_v11_0_set_allowed_mask,
2809 .get_enabled_mask = smu_cmn_get_enabled_mask,
2810 .feature_is_enabled = smu_cmn_feature_is_enabled,
2811 .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
2812 .notify_display_change = NULL,
2813 .set_power_limit = smu_v11_0_set_power_limit,
2814 .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
2815 .enable_thermal_alert = smu_v11_0_enable_thermal_alert,
2816 .disable_thermal_alert = smu_v11_0_disable_thermal_alert,
2817 .set_min_dcef_deep_sleep = NULL,
2818 .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
2819 .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
2820 .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
2821 .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
2822 .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
2823 .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
2824 .gfx_off_control = smu_v11_0_gfx_off_control,
2825 .register_irq_handler = smu_v11_0_register_irq_handler,
2826 .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
2827 .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
2828 .baco_is_support= sienna_cichlid_is_baco_supported,
2829 .baco_get_state = smu_v11_0_baco_get_state,
2830 .baco_set_state = smu_v11_0_baco_set_state,
2831 .baco_enter = smu_v11_0_baco_enter,
2832 .baco_exit = smu_v11_0_baco_exit,
2833 .mode1_reset_is_support = sienna_cichlid_is_mode1_reset_supported,
2834 .mode1_reset = smu_v11_0_mode1_reset,
2835 .get_dpm_ultimate_freq = sienna_cichlid_get_dpm_ultimate_freq,
2836 .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
2837 .run_btc = sienna_cichlid_run_btc,
2838 .set_power_source = smu_v11_0_set_power_source,
2839 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
2840 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
2841 .get_gpu_metrics = sienna_cichlid_get_gpu_metrics,
2842 .enable_mgpu_fan_boost = sienna_cichlid_enable_mgpu_fan_boost,
2843 .gfx_ulv_control = smu_v11_0_gfx_ulv_control,
2844 .deep_sleep_control = smu_v11_0_deep_sleep_control,
2845 .get_fan_parameters = sienna_cichlid_get_fan_parameters,
2846 .interrupt_work = smu_v11_0_interrupt_work,
2847 };
2848
sienna_cichlid_set_ppt_funcs(struct smu_context * smu)2849 void sienna_cichlid_set_ppt_funcs(struct smu_context *smu)
2850 {
2851 smu->ppt_funcs = &sienna_cichlid_ppt_funcs;
2852 smu->message_map = sienna_cichlid_message_map;
2853 smu->clock_map = sienna_cichlid_clk_map;
2854 smu->feature_map = sienna_cichlid_feature_mask_map;
2855 smu->table_map = sienna_cichlid_table_map;
2856 smu->pwr_src_map = sienna_cichlid_pwr_src_map;
2857 smu->workload_map = sienna_cichlid_workload_map;
2858 }
2859