1 // SPDX-License-Identifier: GPL-2.0
2
3 /* Copyright (c) 2018 Rockchip Electronics Co. Ltd. */
4
5 #define pr_fmt(fmt) "sfc_nand: " fmt
6
7 #include <linux/bug.h>
8 #include <linux/delay.h>
9 #include <linux/kernel.h>
10 #include <linux/slab.h>
11
12 #include "rkflash_debug.h"
13 #include "rk_sftl.h"
14 #include "sfc_nand.h"
15
16 static u32 sfc_nand_get_ecc_status0(void);
17 static u32 sfc_nand_get_ecc_status1(void);
18 static u32 sfc_nand_get_ecc_status2(void);
19 static u32 sfc_nand_get_ecc_status3(void);
20 static u32 sfc_nand_get_ecc_status4(void);
21 static u32 sfc_nand_get_ecc_status5(void);
22 static u32 sfc_nand_get_ecc_status6(void);
23 static u32 sfc_nand_get_ecc_status7(void);
24 static u32 sfc_nand_get_ecc_status8(void);
25 static u32 sfc_nand_get_ecc_status9(void);
26
27 static struct nand_info spi_nand_tbl[] = {
28 /* TC58CVG0S0HxAIx */
29 { 0x98, 0xC2, 0x00, 4, 0x40, 1, 1024, 0x00, 18, 0x8, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 },
30 /* TC58CVG1S0HxAIx */
31 { 0x98, 0xCB, 0x00, 4, 0x40, 2, 1024, 0x00, 19, 0x8, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 },
32 /* TC58CVG2S0HRAIJ */
33 { 0x98, 0xED, 0x00, 8, 0x40, 1, 2048, 0x0C, 20, 0x8, 0, { 0x04, 0x0C, 0x08, 0x10 }, &sfc_nand_get_ecc_status0 },
34 /* TC58CVG1S3HRAIJ */
35 { 0x98, 0xEB, 0x00, 4, 0x40, 1, 2048, 0x0C, 19, 0x8, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 },
36 /* TC58CVG0S3HRAIJ */
37 { 0x98, 0xE2, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 },
38
39 /* MX35LF1GE4AB */
40 { 0xC2, 0x12, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 },
41 /* MX35LF2GE4AB */
42 { 0xC2, 0x22, 0x00, 4, 0x40, 2, 1024, 0x0C, 19, 0x4, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 },
43 /* MX35LF2GE4AD */
44 { 0xC2, 0x26, 0x00, 4, 0x40, 1, 2048, 0x0C, 19, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 },
45 /* MX35LF4GE4AD */
46 { 0xC2, 0x37, 0x00, 8, 0x40, 1, 2048, 0x0C, 20, 0x8, 1, { 0x04, 0x08, 0x14, 0x18 }, &sfc_nand_get_ecc_status0 },
47 /* MX35UF1GE4AC */
48 { 0xC2, 0x92, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 },
49 /* MX35UF2GE4AC */
50 { 0xC2, 0xA2, 0x00, 4, 0x40, 1, 2048, 0x0C, 19, 0x4, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 },
51 /* MX35UF1GE4AD */
52 { 0xC2, 0x96, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 },
53 /* MX35UF2GE4AD */
54 { 0xC2, 0xA6, 0x00, 4, 0x40, 1, 2048, 0x0C, 19, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 },
55 /* MX35UF4GE4AD */
56 { 0xC2, 0xB7, 0x00, 8, 0x40, 1, 2048, 0x0C, 20, 0x8, 1, { 0x04, 0x08, 0x14, 0x18 }, &sfc_nand_get_ecc_status0 },
57
58 /* GD5F1GQ4UAYIG */
59 { 0xC8, 0xF1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 },
60 /* GD5F1GQ4RB9IGR */
61 { 0xC8, 0xD1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status3 },
62 /* GD5F2GQ40BY2GR */
63 { 0xC8, 0xD2, 0x00, 4, 0x40, 2, 1024, 0x0C, 19, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status3 },
64 /* GD5F1GQ5UEYIG */
65 { 0xC8, 0x51, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status2 },
66 /* GD5F2GQ5UEYIG */
67 { 0xC8, 0x52, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status2 },
68 /* GD5F1GQ4R */
69 { 0xC8, 0xC1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status3 },
70 /* GD5F4GQ6RExxG 1*4096 */
71 { 0xC8, 0x45, 0x00, 4, 0x40, 2, 2048, 0x4C, 20, 0x4, 1, { 0x04, 0x08, 0x14, 0x18 }, &sfc_nand_get_ecc_status2 },
72 /* GD5F4GQ6UExxG 1*4096 */
73 { 0xC8, 0x55, 0x00, 4, 0x40, 2, 2048, 0x4C, 20, 0x4, 1, { 0x04, 0x08, 0x14, 0x18 }, &sfc_nand_get_ecc_status2 },
74 /* GD5F1GQ4UExxH */
75 { 0xC8, 0xD9, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status3 },
76 /* GD5F1GQ5REYIG */
77 { 0xC8, 0x41, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status2 },
78 /* GD5F2GQ5REYIG */
79 { 0xC8, 0x42, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status2 },
80 /* GD5F2GM7RxG */
81 { 0xC8, 0x82, 0x00, 4, 0x40, 1, 2048, 0x0C, 19, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status2 },
82 /* GD5F2GM7UxG */
83 { 0xC8, 0x92, 0x00, 4, 0x40, 1, 2048, 0x0C, 19, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status2 },
84 /* GD5F1GM7UxG */
85 { 0xC8, 0x91, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status2 },
86 /* GD5F4GQ4UAYIG 1*4096 */
87 { 0xC8, 0xF4, 0x00, 4, 0x40, 2, 2048, 0x0C, 20, 0x8, 1, { 0x04, 0x08, 0x14, 0x18 }, &sfc_nand_get_ecc_status0 },
88
89 /* W25N01GV */
90 { 0xEF, 0xAA, 0x21, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 0, { 0x04, 0x14, 0x24, 0xFF }, &sfc_nand_get_ecc_status1 },
91 /* W25N02KVZEIR */
92 { 0xEF, 0xAA, 0x22, 4, 0x40, 1, 2048, 0x4C, 19, 0x8, 0, { 0x04, 0x14, 0x24, 0xFF }, &sfc_nand_get_ecc_status0 },
93 /* W25N04KVZEIR */
94 { 0xEF, 0xAA, 0x23, 4, 0x40, 1, 4096, 0x4C, 20, 0x8, 0, { 0x04, 0x14, 0x24, 0x34 }, &sfc_nand_get_ecc_status0 },
95 /* W25N01GW */
96 { 0xEF, 0xBA, 0x21, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 0, { 0x04, 0x14, 0x24, 0xFF }, &sfc_nand_get_ecc_status1 },
97 /* W25N02KW */
98 { 0xEF, 0xBA, 0x22, 4, 0x40, 1, 2048, 0x4C, 19, 0x8, 0, { 0x04, 0x14, 0x24, 0xFF }, &sfc_nand_get_ecc_status0 },
99 /* W25N512GVEIG */
100 { 0xEF, 0xAA, 0x20, 4, 0x40, 1, 512, 0x4C, 17, 0x1, 0, { 0x04, 0x14, 0x24, 0xFF }, &sfc_nand_get_ecc_status1 },
101 /* W25N01KV */
102 { 0xEF, 0xAE, 0x21, 4, 0x40, 1, 1024, 0x4C, 18, 0x4, 0, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 },
103
104 /* HYF2GQ4UAACAE */
105 { 0xC9, 0x52, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0xE, 1, { 0x04, 0x24, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 },
106 /* HYF1GQ4UDACAE */
107 { 0xC9, 0x21, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 },
108 /* HYF1GQ4UPACAE */
109 { 0xC9, 0xA1, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 },
110 /* HYF2GQ4UDACAE */
111 { 0xC9, 0x22, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 },
112 /* HYF2GQ4UHCCAE */
113 { 0xC9, 0x5A, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0xE, 1, { 0x04, 0x24, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 },
114 /* HYF4GQ4UAACBE */
115 { 0xC9, 0xD4, 0x00, 8, 0x40, 1, 2048, 0x4C, 20, 0x4, 1, { 0x20, 0x40, 0x24, 0x44 }, &sfc_nand_get_ecc_status0 },
116
117 /* FS35ND01G-S1 */
118 { 0xCD, 0xB1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x10, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status5 },
119 /* FS35ND02G-S2 */
120 { 0xCD, 0xA2, 0x00, 4, 0x40, 1, 2048, 0x00, 19, 0x4, 0, { 0x10, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status5 },
121 /* FS35ND01G-S1Y2 */
122 { 0xCD, 0xEA, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x4, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 },
123 /* FS35ND02G-S3Y2 */
124 { 0xCD, 0xEB, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x4, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 },
125 /* FS35ND04G-S2Y2 1*4096 */
126 { 0xCD, 0xEC, 0x00, 4, 0x40, 2, 2048, 0x4C, 20, 0x4, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 },
127 /* F35SQA001G */
128 { 0xCD, 0x71, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 },
129 /* F35SQA002G */
130 { 0xCD, 0x72, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x1, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 },
131 /* F35SQA512M */
132 { 0xCD, 0x70, 0x00, 4, 0x40, 1, 512, 0x4C, 17, 0x1, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 },
133 /* F35UQA512M */
134 { 0xCD, 0x60, 0x00, 4, 0x40, 1, 512, 0x4C, 17, 0x1, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 },
135
136 /* DS35Q1GA-IB */
137 { 0xE5, 0x71, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 },
138 /* DS35Q2GA-IB */
139 { 0xE5, 0x72, 0x00, 4, 0x40, 2, 1024, 0x0C, 19, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 },
140 /* DS35M1GA-1B */
141 { 0xE5, 0x21, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 },
142 /* DS35M2GA-IB */
143 { 0xE5, 0x22, 0x00, 4, 0x40, 2, 1024, 0x0C, 19, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 },
144 /* DS35Q1GB-IB */
145 { 0xE5, 0xF1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status6 },
146 /* DS35Q2GB-IB */
147 { 0xE5, 0xF2, 0x00, 4, 0x40, 2, 1024, 0x0C, 19, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status6 },
148 /* DS35Q4GM */
149 { 0xE5, 0xF4, 0x00, 4, 0x40, 2, 2048, 0x0C, 20, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status6 },
150 /* DS35M1GB-IB */
151 { 0xE5, 0xA1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status6 },
152
153 /* EM73C044VCC-H */
154 { 0xD5, 0x22, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 },
155 /* EM73D044VCE-H */
156 { 0xD5, 0x20, 0x00, 4, 0x40, 1, 2048, 0x0C, 19, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 },
157 /* EM73E044SNA-G */
158 { 0xD5, 0x03, 0x00, 8, 0x40, 1, 2048, 0x4C, 20, 0x8, 1, { 0x04, 0x28, 0x08, 0x2C }, &sfc_nand_get_ecc_status0 },
159 /* EM73C044VCF-H */
160 { 0xD5, 0x25, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 },
161
162 /* XT26G02A */
163 { 0x0B, 0xE2, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x8, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status4 },
164 /* XT26G01A */
165 { 0x0B, 0xE1, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x8, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status4 },
166 /* XT26G04A */
167 { 0x0B, 0xE3, 0x00, 4, 0x80, 1, 2048, 0x4C, 20, 0x8, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status4 },
168 /* XT26G01B */
169 { 0x0B, 0xF1, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x8, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status4 },
170 /* XT26G02B */
171 { 0x0B, 0xF2, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x4, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status5 },
172 /* XT26G01C */
173 { 0x0B, 0x11, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x8, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status7 },
174 /* XT26G02C */
175 { 0x0B, 0x12, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x8, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status7 },
176 /* XT26G04C */
177 { 0x0B, 0x13, 0x00, 8, 0x40, 1, 2048, 0x4C, 20, 0x8, 1, { 0x04, 0x08, 0x0C, 0x10 }, &sfc_nand_get_ecc_status7 },
178 /* XT26G11C */
179 { 0x0B, 0x15, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 },
180
181 /* MT29F2G01ABA, XT26G02E, F50L2G41XA */
182 { 0x2C, 0x24, 0x00, 4, 0x40, 2, 1024, 0x4C, 19, 0x8, 0, { 0x20, 0x24, 0xFF, 0xFF }, &sfc_nand_get_ecc_status6 },
183 /* MT29F1G01ABA, F50L1G41XA */
184 { 0x2C, 0x14, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x8, 0, { 0x20, 0x24, 0xFF, 0xFF }, &sfc_nand_get_ecc_status6 },
185
186 /* FM25S01 */
187 { 0xA1, 0xA1, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 0, { 0x00, 0x04, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 },
188 /* FM25S01A */
189 { 0xA1, 0xE4, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 },
190 /* FM25S02A */
191 { 0xA1, 0xE5, 0x00, 4, 0x40, 2, 1024, 0x4C, 19, 0x1, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 },
192 /* FM25LS01 */
193 { 0xA1, 0xA5, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 },
194
195 /* IS37SML01G1 */
196 { 0xC8, 0x21, 0x00, 4, 0x40, 1, 1024, 0x00, 18, 0x1, 0, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 },
197 /* F50L1G41LB */
198 { 0xC8, 0x01, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 0, { 0x14, 0x24, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 },
199 /* ATO25D1GA */
200 { 0x9B, 0x12, 0x00, 4, 0x40, 1, 1024, 0x40, 18, 0x1, 1, { 0x14, 0x24, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 },
201 /* BWJX08K-2Gb */
202 { 0xBC, 0xB3, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x8, 1, { 0x04, 0x10, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 },
203 /* JS28U1GQSCAHG-83 */
204 { 0xBF, 0x21, 0x00, 4, 0x40, 1, 1024, 0x40, 18, 0x4, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status8 },
205 /* SGM7000I-S24W1GH */
206 { 0xEA, 0xC1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 },
207 /* TX25G01 */
208 { 0xA1, 0xF1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status8 },
209 /* S35ML02G3 */
210 { 0x01, 0x25, 0x00, 4, 0x40, 2, 1024, 0x4C, 19, 0x4, 1, { 0x04, 0x08, 0x0C, 0x10 }, &sfc_nand_get_ecc_status9 },
211 /* S35ML04G3 */
212 { 0x01, 0x35, 0x00, 4, 0x40, 2, 2048, 0x4C, 20, 0x4, 1, { 0x04, 0x08, 0x0C, 0x10 }, &sfc_nand_get_ecc_status9 },
213 };
214
215 static struct nand_info *p_nand_info;
216 static u32 *gp_page_buf;
217 static struct SFNAND_DEV sfc_nand_dev;
218
sfc_nand_get_info(u8 * nand_id)219 static struct nand_info *sfc_nand_get_info(u8 *nand_id)
220 {
221 u32 i;
222
223 for (i = 0; i < ARRAY_SIZE(spi_nand_tbl); i++) {
224 if (spi_nand_tbl[i].id0 == nand_id[0] &&
225 spi_nand_tbl[i].id1 == nand_id[1]) {
226 if (spi_nand_tbl[i].id2 &&
227 spi_nand_tbl[i].id2 != nand_id[2])
228 continue;
229
230 return &spi_nand_tbl[i];
231 }
232 }
233
234 return NULL;
235 }
236
sfc_nand_write_en(void)237 static int sfc_nand_write_en(void)
238 {
239 int ret;
240 struct rk_sfc_op op;
241
242 op.sfcmd.d32 = 0;
243 op.sfcmd.b.cmd = CMD_WRITE_EN;
244
245 op.sfctrl.d32 = 0;
246
247 ret = sfc_request(&op, 0, NULL, 0);
248 return ret;
249 }
250
sfc_nand_rw_preset(void)251 static int sfc_nand_rw_preset(void)
252 {
253 int ret;
254 struct rk_sfc_op op;
255
256 op.sfcmd.d32 = 0;
257 op.sfcmd.b.cmd = 0xff;
258 op.sfcmd.b.cs = 2;
259
260 op.sfctrl.d32 = 0;
261 op.sfctrl.b.datalines = 2;
262 op.sfctrl.b.cmdlines = 2;
263 op.sfctrl.b.addrlines = 2;
264
265 ret = sfc_request(&op, 0, NULL, 0);
266 return ret;
267 }
268
sfc_nand_read_feature(u8 addr,u8 * data)269 static int sfc_nand_read_feature(u8 addr, u8 *data)
270 {
271 int ret;
272 struct rk_sfc_op op;
273
274 op.sfcmd.d32 = 0;
275 op.sfcmd.b.cmd = 0x0F;
276 op.sfcmd.b.addrbits = SFC_ADDR_XBITS;
277
278 op.sfctrl.d32 = 0;
279 op.sfctrl.b.addrbits = 8;
280
281 *data = 0;
282
283 ret = sfc_request(&op, addr, data, 1);
284
285 if (ret != SFC_OK)
286 return ret;
287
288 return SFC_OK;
289 }
290
sfc_nand_write_feature(u32 addr,u8 status)291 static int sfc_nand_write_feature(u32 addr, u8 status)
292 {
293 int ret;
294 struct rk_sfc_op op;
295
296 sfc_nand_write_en();
297
298 op.sfcmd.d32 = 0;
299 op.sfcmd.b.cmd = 0x1F;
300 op.sfcmd.b.addrbits = SFC_ADDR_XBITS;
301 op.sfcmd.b.rw = SFC_WRITE;
302
303 op.sfctrl.d32 = 0;
304 op.sfctrl.b.addrbits = 8;
305
306 ret = sfc_request(&op, addr, &status, 1);
307
308 if (ret != SFC_OK)
309 return ret;
310
311 return ret;
312 }
313
sfc_nand_wait_busy(u8 * data,int timeout)314 static int sfc_nand_wait_busy(u8 *data, int timeout)
315 {
316 int ret;
317 int i;
318 u8 status;
319
320 *data = 0;
321
322 for (i = 0; i < timeout; i++) {
323 ret = sfc_nand_read_feature(0xC0, &status);
324
325 if (ret != SFC_OK)
326 return ret;
327
328 *data = status;
329
330 if (!(status & (1 << 0)))
331 return SFC_OK;
332
333 sfc_delay(1);
334 }
335
336 return SFC_NAND_WAIT_TIME_OUT;
337 }
338
339 /*
340 * ecc default:
341 * ecc bits: 0xC0[4,5]
342 * 0b00, No bit errors were detected
343 * 0b01, Bit errors were detected and corrected.
344 * 0b10, Multiple bit errors were detected and not corrected.
345 * 0b11, Bits errors were detected and corrected, bit error count
346 * reach the bit flip detection threshold
347 */
sfc_nand_get_ecc_status0(void)348 static u32 sfc_nand_get_ecc_status0(void)
349 {
350 u32 ret;
351 u32 i;
352 u8 ecc;
353 u8 status;
354 u32 timeout = 1000 * 1000;
355
356 for (i = 0; i < timeout; i++) {
357 ret = sfc_nand_read_feature(0xC0, &status);
358
359 if (ret != SFC_OK)
360 return SFC_NAND_ECC_ERROR;
361
362 if (!(status & (1 << 0)))
363 break;
364
365 sfc_delay(1);
366 }
367
368 ecc = (status >> 4) & 0x03;
369
370 if (ecc <= 1)
371 ret = SFC_NAND_ECC_OK;
372 else if (ecc == 2)
373 ret = (u32)SFC_NAND_ECC_ERROR;
374 else
375 ret = SFC_NAND_ECC_REFRESH;
376
377 return ret;
378 }
379
380 /*
381 * ecc spectial type1:
382 * ecc bits: 0xC0[4,5]
383 * 0b00, No bit errors were detected;
384 * 0b01, Bits errors were detected and corrected, bit error count
385 * may reach the bit flip detection threshold;
386 * 0b10, Multiple bit errors were detected and not corrected;
387 * 0b11, Reserved.
388 */
sfc_nand_get_ecc_status1(void)389 static u32 sfc_nand_get_ecc_status1(void)
390 {
391 u32 ret;
392 u32 i;
393 u8 ecc;
394 u8 status;
395 u32 timeout = 1000 * 1000;
396
397 for (i = 0; i < timeout; i++) {
398 ret = sfc_nand_read_feature(0xC0, &status);
399
400 if (ret != SFC_OK)
401 return SFC_NAND_ECC_ERROR;
402
403 if (!(status & (1 << 0)))
404 break;
405
406 sfc_delay(1);
407 }
408
409 ecc = (status >> 4) & 0x03;
410
411 if (ecc == 0)
412 ret = SFC_NAND_ECC_OK;
413 else if (ecc == 1)
414 ret = SFC_NAND_ECC_REFRESH;
415 else
416 ret = (u32)SFC_NAND_ECC_ERROR;
417
418 return ret;
419 }
420
421 /*
422 * ecc spectial type2:
423 * ecc bits: 0xC0[4,5] 0xF0[4,5]
424 * [0b0000, 0b0011], No bit errors were detected;
425 * [0b0100, 0b0111], Bit errors were detected and corrected. Not
426 * reach Flipping Bits;
427 * [0b1000, 0b1011], Multiple bit errors were detected and
428 * not corrected.
429 * [0b1100, 0b1111], reserved.
430 */
sfc_nand_get_ecc_status2(void)431 static u32 sfc_nand_get_ecc_status2(void)
432 {
433 u32 ret;
434 u32 i;
435 u8 ecc;
436 u8 status, status1;
437 u32 timeout = 1000 * 1000;
438
439 for (i = 0; i < timeout; i++) {
440 ret = sfc_nand_read_feature(0xC0, &status);
441
442 if (ret != SFC_OK)
443 return SFC_NAND_ECC_ERROR;
444
445 ret = sfc_nand_read_feature(0xF0, &status1);
446
447 if (ret != SFC_OK)
448 return SFC_NAND_ECC_ERROR;
449
450 if (!(status & (1 << 0)))
451 break;
452
453 sfc_delay(1);
454 }
455
456 ecc = (status >> 4) & 0x03;
457 ecc = (ecc << 2) | ((status1 >> 4) & 0x03);
458
459 if (ecc < 7)
460 ret = SFC_NAND_ECC_OK;
461 else if (ecc == 7)
462 ret = SFC_NAND_ECC_REFRESH;
463 else
464 ret = (u32)SFC_NAND_ECC_ERROR;
465
466 return ret;
467 }
468
469 /*
470 * ecc spectial type3:
471 * ecc bits: 0xC0[4,5] 0xF0[4,5]
472 * [0b0000, 0b0011], No bit errors were detected;
473 * [0b0100, 0b0111], Bit errors were detected and corrected. Not
474 * reach Flipping Bits;
475 * [0b1000, 0b1011], Multiple bit errors were detected and
476 * not corrected.
477 * [0b1100, 0b1111], Bit error count equals the bit flip
478 * detectio nthreshold
479 */
sfc_nand_get_ecc_status3(void)480 static u32 sfc_nand_get_ecc_status3(void)
481 {
482 u32 ret;
483 u32 i;
484 u8 ecc;
485 u8 status, status1;
486 u32 timeout = 1000 * 1000;
487
488 for (i = 0; i < timeout; i++) {
489 ret = sfc_nand_read_feature(0xC0, &status);
490
491 if (ret != SFC_OK)
492 return SFC_NAND_ECC_ERROR;
493
494 ret = sfc_nand_read_feature(0xF0, &status1);
495
496 if (ret != SFC_OK)
497 return SFC_NAND_ECC_ERROR;
498
499 if (!(status & (1 << 0)))
500 break;
501
502 sfc_delay(1);
503 }
504
505 ecc = (status >> 4) & 0x03;
506 ecc = (ecc << 2) | ((status1 >> 4) & 0x03);
507
508 if (ecc < 7)
509 ret = SFC_NAND_ECC_OK;
510 else if (ecc == 7 || ecc >= 12)
511 ret = SFC_NAND_ECC_REFRESH;
512 else
513 ret = (u32)SFC_NAND_ECC_ERROR;
514
515 return ret;
516 }
517
518 /*
519 * ecc spectial type4:
520 * ecc bits: 0xC0[2,5]
521 * [0b0000], No bit errors were detected;
522 * [0b0001, 0b0111], Bit errors were detected and corrected. Not
523 * reach Flipping Bits;
524 * [0b1000], Multiple bit errors were detected and
525 * not corrected.
526 * [0b1100], Bit error count equals the bit flip
527 * detection threshold
528 * else, reserved
529 */
sfc_nand_get_ecc_status4(void)530 static u32 sfc_nand_get_ecc_status4(void)
531 {
532 u32 ret;
533 u32 i;
534 u8 ecc;
535 u8 status;
536 u32 timeout = 1000 * 1000;
537
538 for (i = 0; i < timeout; i++) {
539 ret = sfc_nand_read_feature(0xC0, &status);
540
541 if (ret != SFC_OK)
542 return SFC_NAND_ECC_ERROR;
543
544 if (!(status & (1 << 0)))
545 break;
546
547 sfc_delay(1);
548 }
549
550 ecc = (status >> 2) & 0x0f;
551
552 if (ecc < 7)
553 ret = SFC_NAND_ECC_OK;
554 else if (ecc == 7 || ecc == 12)
555 ret = SFC_NAND_ECC_REFRESH;
556 else
557 ret = (u32)SFC_NAND_ECC_ERROR;
558
559 return ret;
560 }
561
562 /*
563 * ecc spectial type5:
564 * ecc bits: 0xC0[4,6]
565 * [0b000], No bit errors were detected;
566 * [0b001, 0b011], Bit errors were detected and corrected. Not
567 * reach Flipping Bits;
568 * [0b100], Bit error count equals the bit flip
569 * detection threshold
570 * [0b101, 0b110], Reserved;
571 * [0b111], Multiple bit errors were detected and
572 * not corrected.
573 */
sfc_nand_get_ecc_status5(void)574 static u32 sfc_nand_get_ecc_status5(void)
575 {
576 u32 ret;
577 u32 i;
578 u8 ecc;
579 u8 status;
580 u32 timeout = 1000 * 1000;
581
582 for (i = 0; i < timeout; i++) {
583 ret = sfc_nand_read_feature(0xC0, &status);
584
585 if (ret != SFC_OK)
586 return SFC_NAND_ECC_ERROR;
587
588 if (!(status & (1 << 0)))
589 break;
590
591 sfc_delay(1);
592 }
593
594 ecc = (status >> 4) & 0x07;
595
596 if (ecc < 4)
597 ret = SFC_NAND_ECC_OK;
598 else if (ecc == 4)
599 ret = SFC_NAND_ECC_REFRESH;
600 else
601 ret = (u32)SFC_NAND_ECC_ERROR;
602
603 return ret;
604 }
605
606 /*
607 * ecc spectial type6:
608 * ecc bits: 0xC0[4,6]
609 * [0b000], No bit errors were detected;
610 * [0b001], 1-3 Bit errors were detected and corrected. Not
611 * reach Flipping Bits;
612 * [0b010], Multiple bit errors were detected and
613 * not corrected.
614 * [0b011], 4-6 Bit errors were detected and corrected. Not
615 * reach Flipping Bits;
616 * [0b101], Bit error count equals the bit flip
617 * detectionthreshold
618 * others, Reserved.
619 */
sfc_nand_get_ecc_status6(void)620 static u32 sfc_nand_get_ecc_status6(void)
621 {
622 u32 ret;
623 u32 i;
624 u8 ecc;
625 u8 status;
626 u32 timeout = 1000 * 1000;
627
628 for (i = 0; i < timeout; i++) {
629 ret = sfc_nand_read_feature(0xC0, &status);
630
631 if (ret != SFC_OK)
632 return SFC_NAND_ECC_ERROR;
633
634 if (!(status & (1 << 0)))
635 break;
636
637 sfc_delay(1);
638 }
639
640 ecc = (status >> 4) & 0x07;
641
642 if (ecc == 0 || ecc == 1 || ecc == 3)
643 ret = SFC_NAND_ECC_OK;
644 else if (ecc == 5)
645 ret = SFC_NAND_ECC_REFRESH;
646 else
647 ret = (u32)SFC_NAND_ECC_ERROR;
648
649 return ret;
650 }
651
652 /*
653 * ecc spectial type7:
654 * ecc bits: 0xC0[4,7]
655 * [0b0000], No bit errors were detected;
656 * [0b0001, 0b0111], 1-7 Bit errors were detected and corrected. Not
657 * reach Flipping Bits;
658 * [0b1000], 8 Bit errors were detected and corrected. Bit error count
659 * equals the bit flip detectionthreshold;
660 * [0b1111], Bit errors greater than ECC capability(8 bits) and not corrected;
661 * others, Reserved.
662 */
sfc_nand_get_ecc_status7(void)663 static u32 sfc_nand_get_ecc_status7(void)
664 {
665 u32 ret;
666 u32 i;
667 u8 ecc;
668 u8 status;
669 u32 timeout = 1000 * 1000;
670
671 for (i = 0; i < timeout; i++) {
672 ret = sfc_nand_read_feature(0xC0, &status);
673
674 if (ret != SFC_OK)
675 return SFC_NAND_ECC_ERROR;
676
677 if (!(status & (1 << 0)))
678 break;
679
680 sfc_delay(1);
681 }
682
683 ecc = (status >> 4) & 0xf;
684
685 if (ecc < 7)
686 ret = SFC_NAND_ECC_OK;
687 else if (ecc == 7 || ecc == 8)
688 ret = SFC_NAND_ECC_REFRESH;
689 else
690 ret = (u32)SFC_NAND_ECC_ERROR;
691
692 return ret;
693 }
694
695 /*
696 * ecc spectial type8:
697 * ecc bits: 0xC0[4,6]
698 * [0b000], No bit errors were detected;
699 * [0b001, 0b011], 1~3 Bit errors were detected and corrected. Not
700 * reach Flipping Bits;
701 * [0b100], Bit error count equals the bit flip
702 * detection threshold
703 * others, Reserved.
704 */
sfc_nand_get_ecc_status8(void)705 static u32 sfc_nand_get_ecc_status8(void)
706 {
707 u32 ret;
708 u32 i;
709 u8 ecc;
710 u8 status;
711 u32 timeout = 1000 * 1000;
712
713 for (i = 0; i < timeout; i++) {
714 ret = sfc_nand_read_feature(0xC0, &status);
715
716 if (ret != SFC_OK)
717 return SFC_NAND_ECC_ERROR;
718
719 if (!(status & (1 << 0)))
720 break;
721
722 sfc_delay(1);
723 }
724
725 ecc = (status >> 4) & 0x07;
726
727 if (ecc < 4)
728 ret = SFC_NAND_ECC_OK;
729 else if (ecc == 4)
730 ret = SFC_NAND_ECC_REFRESH;
731 else
732 ret = (u32)SFC_NAND_ECC_ERROR;
733
734 return ret;
735 }
736
737 /*
738 * ecc spectial type9:
739 * ecc bits: 0xC0[4,5]
740 * 0b00, No bit errors were detected
741 * 0b01, 1-2Bit errors were detected and corrected.
742 * 0b10, 3-4Bit errors were detected and corrected.
743 * 0b11, 11 can be used as uncorrectable
744 */
sfc_nand_get_ecc_status9(void)745 static u32 sfc_nand_get_ecc_status9(void)
746 {
747 u32 ret;
748 u32 i;
749 u8 ecc;
750 u8 status;
751 u32 timeout = 1000 * 1000;
752
753 for (i = 0; i < timeout; i++) {
754 ret = sfc_nand_read_feature(0xC0, &status);
755
756 if (ret != SFC_OK)
757 return SFC_NAND_ECC_ERROR;
758
759 if (!(status & (1 << 0)))
760 break;
761
762 sfc_delay(1);
763 }
764
765 ecc = (status >> 4) & 0x03;
766
767 if (ecc <= 1)
768 ret = SFC_NAND_ECC_OK;
769 else if (ecc == 2)
770 ret = SFC_NAND_ECC_REFRESH;
771 else
772 ret = (u32)SFC_NAND_ECC_ERROR;
773
774 return ret;
775 }
776
sfc_nand_erase_block(u8 cs,u32 addr)777 u32 sfc_nand_erase_block(u8 cs, u32 addr)
778 {
779 int ret;
780 struct rk_sfc_op op;
781 u8 status;
782
783 rkflash_print_dio("%s %x\n", __func__, addr);
784 op.sfcmd.d32 = 0;
785 op.sfcmd.b.cmd = 0xd8;
786 op.sfcmd.b.addrbits = SFC_ADDR_24BITS;
787 op.sfcmd.b.rw = SFC_WRITE;
788
789 op.sfctrl.d32 = 0;
790
791 sfc_nand_write_en();
792 ret = sfc_request(&op, addr, NULL, 0);
793
794 if (ret != SFC_OK)
795 return ret;
796
797 ret = sfc_nand_wait_busy(&status, 1000 * 1000);
798
799 if (status & (1 << 2))
800 return SFC_NAND_PROG_ERASE_ERROR;
801
802 return ret;
803 }
804
sfc_nand_read_cache(u32 row,u32 * p_page_buf,u32 column,u32 len)805 static u32 sfc_nand_read_cache(u32 row, u32 *p_page_buf, u32 column, u32 len)
806 {
807 int ret;
808 u32 plane;
809 struct rk_sfc_op op;
810
811 op.sfcmd.d32 = 0;
812 op.sfcmd.b.cmd = sfc_nand_dev.page_read_cmd;
813 op.sfcmd.b.addrbits = SFC_ADDR_XBITS;
814 op.sfcmd.b.dummybits = 8;
815
816 op.sfctrl.d32 = 0;
817 op.sfctrl.b.datalines = sfc_nand_dev.read_lines;
818 op.sfctrl.b.addrbits = 16;
819
820 plane = p_nand_info->plane_per_die == 2 ? ((row >> 6) & 0x1) << 12 : 0;
821
822 ret = sfc_request(&op, plane | column, p_page_buf, len);
823 if (ret != SFC_OK)
824 return SFC_NAND_HW_ERROR;
825
826 return ret;
827 }
828
sfc_nand_prog_page_raw(u8 cs,u32 addr,u32 * p_page_buf)829 u32 sfc_nand_prog_page_raw(u8 cs, u32 addr, u32 *p_page_buf)
830 {
831 int ret;
832 u32 plane;
833 struct rk_sfc_op op;
834 u8 status;
835 u32 page_size = SFC_NAND_SECTOR_FULL_SIZE * p_nand_info->sec_per_page;
836 u32 data_area_size = SFC_NAND_SECTOR_SIZE * p_nand_info->sec_per_page;
837
838 rkflash_print_dio("%s %x %x\n", __func__, addr, p_page_buf[0]);
839 sfc_nand_write_en();
840
841 if (sfc_nand_dev.prog_lines == DATA_LINES_X4 &&
842 p_nand_info->feature & FEA_SOFT_QOP_BIT &&
843 sfc_get_version() < SFC_VER_3)
844 sfc_nand_rw_preset();
845
846 op.sfcmd.d32 = 0;
847 op.sfcmd.b.cmd = sfc_nand_dev.page_prog_cmd;
848 op.sfcmd.b.addrbits = SFC_ADDR_XBITS;
849 op.sfcmd.b.rw = SFC_WRITE;
850
851 op.sfctrl.d32 = 0;
852 op.sfctrl.b.datalines = sfc_nand_dev.prog_lines;
853 op.sfctrl.b.addrbits = 16;
854 plane = p_nand_info->plane_per_die == 2 ? ((addr >> 6) & 0x1) << 12 : 0;
855 sfc_request(&op, plane, p_page_buf, page_size);
856
857 /*
858 * At the moment of power lost or dev running in harsh environment, flash
859 * maybe work in a unkonw state and result in bit flip, when this situation
860 * is detected by cache recheck, it's better to wait a second for a reliable
861 * hardware environment to avoid abnormal data written to flash array.
862 */
863 if (p_nand_info->id0 == MID_GIGADEV) {
864 sfc_nand_read_cache(addr, (u32 *)sfc_nand_dev.recheck_buffer, 0, data_area_size);
865 if (memcmp(sfc_nand_dev.recheck_buffer, p_page_buf, data_area_size)) {
866 rkflash_print_error("%s cache bitflip1\n", __func__);
867 msleep(1000);
868 sfc_request(&op, plane, p_page_buf, page_size);
869 }
870 }
871
872 op.sfcmd.d32 = 0;
873 op.sfcmd.b.cmd = 0x10;
874 op.sfcmd.b.addrbits = SFC_ADDR_24BITS;
875 op.sfcmd.b.rw = SFC_WRITE;
876
877 op.sfctrl.d32 = 0;
878 ret = sfc_request(&op, addr, p_page_buf, 0);
879
880 if (ret != SFC_OK)
881 return ret;
882
883 ret = sfc_nand_wait_busy(&status, 1000 * 1000);
884 if (status & (1 << 3))
885 return SFC_NAND_PROG_ERASE_ERROR;
886
887 return ret;
888 }
889
sfc_nand_prog_page(u8 cs,u32 addr,u32 * p_data,u32 * p_spare)890 u32 sfc_nand_prog_page(u8 cs, u32 addr, u32 *p_data, u32 *p_spare)
891 {
892 int ret;
893 u32 sec_per_page = p_nand_info->sec_per_page;
894 u32 data_size = sec_per_page * SFC_NAND_SECTOR_SIZE;
895 struct nand_mega_area *meta = &p_nand_info->meta;
896
897 memcpy(gp_page_buf, p_data, data_size);
898 memset(&gp_page_buf[data_size / 4], 0xff, sec_per_page * 16);
899 gp_page_buf[(data_size + meta->off0) / 4] = p_spare[0];
900 gp_page_buf[(data_size + meta->off1) / 4] = p_spare[1];
901
902 if (sec_per_page == 8) {
903 gp_page_buf[(data_size + meta->off2) / 4] = p_spare[2];
904 gp_page_buf[(data_size + meta->off3) / 4] = p_spare[3];
905 }
906
907 ret = sfc_nand_prog_page_raw(cs, addr, gp_page_buf);
908
909 return ret;
910 }
911
sfc_nand_read(u32 row,u32 * p_page_buf,u32 column,u32 len)912 u32 sfc_nand_read(u32 row, u32 *p_page_buf, u32 column, u32 len)
913 {
914 int ret;
915 u32 plane;
916 struct rk_sfc_op op;
917 u32 ecc_result;
918 u8 status;
919
920 op.sfcmd.d32 = 0;
921 op.sfcmd.b.cmd = 0x13;
922 op.sfcmd.b.rw = SFC_WRITE;
923 op.sfcmd.b.addrbits = SFC_ADDR_24BITS;
924
925 op.sfctrl.d32 = 0;
926
927 sfc_request(&op, row, p_page_buf, 0);
928
929 if (sfc_nand_dev.read_lines == DATA_LINES_X4 &&
930 p_nand_info->feature & FEA_SOFT_QOP_BIT &&
931 sfc_get_version() < SFC_VER_3)
932 sfc_nand_rw_preset();
933
934 sfc_nand_wait_busy(&status, 1000 * 1000);
935 ecc_result = p_nand_info->ecc_status();
936
937 op.sfcmd.d32 = 0;
938 op.sfcmd.b.cmd = sfc_nand_dev.page_read_cmd;
939 op.sfcmd.b.addrbits = SFC_ADDR_XBITS;
940 op.sfcmd.b.dummybits = 8;
941
942 op.sfctrl.d32 = 0;
943 op.sfctrl.b.datalines = sfc_nand_dev.read_lines;
944 op.sfctrl.b.addrbits = 16;
945
946 plane = p_nand_info->plane_per_die == 2 ? ((row >> 6) & 0x1) << 12 : 0;
947 ret = sfc_request(&op, plane | column, p_page_buf, len);
948 rkflash_print_dio("%s %x %x\n", __func__, row, p_page_buf[0]);
949
950 if (ret != SFC_OK)
951 return SFC_NAND_HW_ERROR;
952
953 return ecc_result;
954 }
955
sfc_nand_read_page_raw(u8 cs,u32 addr,u32 * p_page_buf)956 u32 sfc_nand_read_page_raw(u8 cs, u32 addr, u32 *p_page_buf)
957 {
958 u32 page_size = SFC_NAND_SECTOR_FULL_SIZE * p_nand_info->sec_per_page;
959
960 return sfc_nand_read(addr, p_page_buf, 0, page_size);
961 }
962
sfc_nand_read_page(u8 cs,u32 addr,u32 * p_data,u32 * p_spare)963 u32 sfc_nand_read_page(u8 cs, u32 addr, u32 *p_data, u32 *p_spare)
964 {
965 u32 ret;
966 u32 sec_per_page = p_nand_info->sec_per_page;
967 u32 data_size = sec_per_page * SFC_NAND_SECTOR_SIZE;
968 struct nand_mega_area *meta = &p_nand_info->meta;
969 int retries = 0;
970
971 retry:
972 ret = sfc_nand_read_page_raw(cs, addr, gp_page_buf);
973 memcpy(p_data, gp_page_buf, data_size);
974 p_spare[0] = gp_page_buf[(data_size + meta->off0) / 4];
975 p_spare[1] = gp_page_buf[(data_size + meta->off1) / 4];
976
977 if (p_nand_info->sec_per_page == 8) {
978 p_spare[2] = gp_page_buf[(data_size + meta->off2) / 4];
979 p_spare[3] = gp_page_buf[(data_size + meta->off3) / 4];
980 }
981
982 if (ret == SFC_NAND_HW_ERROR)
983 ret = SFC_NAND_ECC_ERROR;
984
985 if (ret != SFC_NAND_ECC_OK) {
986 rkflash_print_error("%s[0x%x], ret=0x%x\n", __func__, addr, ret);
987
988 if (p_data)
989 rkflash_print_hex("data:", p_data, 4, 8);
990
991 if (p_spare)
992 rkflash_print_hex("spare:", p_spare, 4, 2);
993 if (ret == SFC_NAND_ECC_ERROR && retries < 1) {
994 retries++;
995 goto retry;
996 }
997 }
998
999 return ret;
1000 }
1001
sfc_nand_check_bad_block(u8 cs,u32 addr)1002 u32 sfc_nand_check_bad_block(u8 cs, u32 addr)
1003 {
1004 u32 ret;
1005 u32 data_size = p_nand_info->sec_per_page * SFC_NAND_SECTOR_SIZE;
1006 u32 marker = 0;
1007
1008 ret = sfc_nand_read(addr, &marker, data_size, 2);
1009
1010 /* unify with mtd framework */
1011 if (ret == SFC_NAND_ECC_ERROR || (u16)marker != 0xffff)
1012 rkflash_print_error("%s page= %x ret= %x spare= %x\n",
1013 __func__, addr, ret, marker);
1014
1015 /* Original bad block */
1016 if ((u16)marker != 0xffff)
1017 return true;
1018
1019 return false;
1020 }
1021
sfc_nand_mark_bad_block(u8 cs,u32 addr)1022 u32 sfc_nand_mark_bad_block(u8 cs, u32 addr)
1023 {
1024 u32 ret;
1025 u32 data_size = p_nand_info->sec_per_page * SFC_NAND_SECTOR_SIZE;
1026
1027 ret = sfc_nand_read_page_raw(cs, addr, gp_page_buf);
1028
1029 if (ret)
1030 return SFC_NAND_HW_ERROR;
1031
1032 gp_page_buf[data_size / 4] = 0x0;
1033 ret = sfc_nand_prog_page_raw(cs, addr, gp_page_buf);
1034
1035 if (ret)
1036 return SFC_NAND_HW_ERROR;
1037
1038 return ret;
1039 }
1040
sfc_nand_read_id(u8 * data)1041 int sfc_nand_read_id(u8 *data)
1042 {
1043 int ret;
1044 struct rk_sfc_op op;
1045
1046 op.sfcmd.d32 = 0;
1047 op.sfcmd.b.cmd = CMD_READ_JEDECID;
1048 op.sfcmd.b.addrbits = SFC_ADDR_XBITS;
1049
1050 op.sfctrl.d32 = 0;
1051 op.sfctrl.b.addrbits = 8;
1052
1053 ret = sfc_request(&op, 0, data, 3);
1054
1055 return ret;
1056 }
1057
1058 #if defined(CONFIG_RK_SFTL)
1059 /*
1060 * Read the 1st page's 1st byte of a phy_blk
1061 * If not FF, it's bad blk
1062 */
sfc_nand_get_bad_block_list(u16 * table,u32 die)1063 static int sfc_nand_get_bad_block_list(u16 *table, u32 die)
1064 {
1065 u32 bad_cnt, page;
1066 u32 blk_per_die;
1067 u16 blk;
1068
1069 rkflash_print_info("%s\n", __func__);
1070
1071 bad_cnt = 0;
1072 blk_per_die = p_nand_info->plane_per_die *
1073 p_nand_info->blk_per_plane;
1074
1075 for (blk = 0; blk < blk_per_die; blk++) {
1076 page = (blk + blk_per_die * die) *
1077 p_nand_info->page_per_blk;
1078
1079 if (sfc_nand_check_bad_block(die, page)) {
1080 table[bad_cnt++] = blk;
1081 rkflash_print_error("die[%d], bad_blk[%d]\n", die, blk);
1082 }
1083 }
1084
1085 return (int)bad_cnt;
1086 }
1087
sfc_nand_ftl_ops_init(void)1088 void sfc_nand_ftl_ops_init(void)
1089 {
1090 /* para init */
1091 g_nand_phy_info.nand_type = 1;
1092 g_nand_phy_info.die_num = 1;
1093 g_nand_phy_info.plane_per_die = p_nand_info->plane_per_die;
1094 g_nand_phy_info.blk_per_plane = p_nand_info->blk_per_plane;
1095 g_nand_phy_info.page_per_blk = p_nand_info->page_per_blk;
1096 g_nand_phy_info.page_per_slc_blk = p_nand_info->page_per_blk;
1097 g_nand_phy_info.byte_per_sec = SFC_NAND_SECTOR_SIZE;
1098 g_nand_phy_info.sec_per_page = p_nand_info->sec_per_page;
1099 g_nand_phy_info.sec_per_blk = p_nand_info->sec_per_page *
1100 p_nand_info->page_per_blk;
1101 g_nand_phy_info.reserved_blk = 8;
1102 g_nand_phy_info.blk_per_die = p_nand_info->plane_per_die *
1103 p_nand_info->blk_per_plane;
1104 g_nand_phy_info.ecc_bits = p_nand_info->max_ecc_bits;
1105
1106 /* driver register */
1107 g_nand_ops.get_bad_blk_list = sfc_nand_get_bad_block_list;
1108 g_nand_ops.erase_blk = sfc_nand_erase_block;
1109 g_nand_ops.prog_page = sfc_nand_prog_page;
1110 g_nand_ops.read_page = sfc_nand_read_page;
1111 g_nand_ops.bch_sel = NULL;
1112 }
1113 #endif
1114
sfc_nand_enable_QE(void)1115 static int sfc_nand_enable_QE(void)
1116 {
1117 int ret = SFC_OK;
1118 u8 status;
1119
1120 ret = sfc_nand_read_feature(0xB0, &status);
1121
1122 if (ret != SFC_OK)
1123 return ret;
1124
1125 if (status & 1) /* is QE bit set */
1126 return SFC_OK;
1127
1128 status |= 1;
1129
1130 return sfc_nand_write_feature(0xB0, status);
1131 }
1132
sfc_nand_init(void)1133 u32 sfc_nand_init(void)
1134 {
1135 u8 status, id_byte[8];
1136
1137 sfc_nand_read_id(id_byte);
1138 rkflash_print_error("sfc_nand id: %x %x %x\n",
1139 id_byte[0], id_byte[1], id_byte[2]);
1140
1141 if (id_byte[0] == 0xFF || id_byte[0] == 0x00)
1142 return (u32)FTL_NO_FLASH;
1143
1144 p_nand_info = sfc_nand_get_info(id_byte);
1145
1146 if (!p_nand_info) {
1147 pr_err("The device not support yet!\n");
1148
1149 return (u32)FTL_UNSUPPORTED_FLASH;
1150 }
1151
1152 if (!gp_page_buf)
1153 gp_page_buf = (u32 *)__get_free_pages(GFP_KERNEL | GFP_DMA32, get_order(SFC_NAND_PAGE_MAX_SIZE));
1154 if (!gp_page_buf)
1155 return -ENOMEM;
1156
1157 sfc_nand_dev.manufacturer = id_byte[0];
1158 sfc_nand_dev.mem_type = id_byte[1];
1159 sfc_nand_dev.capacity = p_nand_info->density;
1160 sfc_nand_dev.block_size = p_nand_info->page_per_blk * p_nand_info->sec_per_page;
1161 sfc_nand_dev.page_size = p_nand_info->sec_per_page;
1162
1163 /* disable block lock */
1164 sfc_nand_write_feature(0xA0, 0);
1165 sfc_nand_dev.read_lines = DATA_LINES_X1;
1166 sfc_nand_dev.prog_lines = DATA_LINES_X1;
1167 sfc_nand_dev.page_read_cmd = 0x03;
1168 sfc_nand_dev.page_prog_cmd = 0x02;
1169 if (!sfc_nand_dev.recheck_buffer)
1170 sfc_nand_dev.recheck_buffer = (u8 *)__get_free_pages(GFP_KERNEL | GFP_DMA32, get_order(SFC_NAND_PAGE_MAX_SIZE));
1171 if (!sfc_nand_dev.recheck_buffer) {
1172 pr_err("%s recheck_buffer alloc failed\n", __func__);
1173 return -ENOMEM;
1174 }
1175
1176 if (p_nand_info->feature & FEA_4BIT_READ) {
1177 if ((p_nand_info->has_qe_bits && sfc_nand_enable_QE() == SFC_OK) ||
1178 !p_nand_info->has_qe_bits) {
1179 sfc_nand_dev.read_lines = DATA_LINES_X4;
1180 sfc_nand_dev.page_read_cmd = 0x6b;
1181 }
1182 }
1183
1184 if (p_nand_info->feature & FEA_4BIT_PROG &&
1185 sfc_nand_dev.read_lines == DATA_LINES_X4) {
1186 sfc_nand_dev.prog_lines = DATA_LINES_X4;
1187 sfc_nand_dev.page_prog_cmd = 0x32;
1188 }
1189
1190 sfc_nand_read_feature(0xA0, &status);
1191 rkflash_print_info("sfc_nand A0 = 0x%x\n", status);
1192 sfc_nand_read_feature(0xB0, &status);
1193 rkflash_print_info("sfc_nand B0 = 0x%x\n", status);
1194 rkflash_print_info("read_lines = %x\n", sfc_nand_dev.read_lines);
1195 rkflash_print_info("prog_lines = %x\n", sfc_nand_dev.prog_lines);
1196 rkflash_print_info("page_read_cmd = %x\n", sfc_nand_dev.page_read_cmd);
1197 rkflash_print_info("page_prog_cmd = %x\n", sfc_nand_dev.page_prog_cmd);
1198
1199 return SFC_OK;
1200 }
1201
sfc_nand_deinit(void)1202 void sfc_nand_deinit(void)
1203 {
1204 /* to-do */
1205 free_pages((unsigned long)sfc_nand_dev.recheck_buffer, get_order(SFC_NAND_PAGE_MAX_SIZE));
1206 free_pages((unsigned long)gp_page_buf, get_order(SFC_NAND_PAGE_MAX_SIZE));
1207 }
1208
sfc_nand_get_private_dev(void)1209 struct SFNAND_DEV *sfc_nand_get_private_dev(void)
1210 {
1211 return &sfc_nand_dev;
1212 }
1213
sfc_nand_get_nand_info(void)1214 struct nand_info *sfc_nand_get_nand_info(void)
1215 {
1216 return p_nand_info;
1217 }
1218