1 /*
2 * Copyright (c) 2024, MediaTek Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <common/debug.h>
8 #include <lib/utils_def.h>
9 #include <platform_def.h>
10
11 #include <apusys_devapc.h>
12 #include <apusys_devapc_def.h>
13 #include <mtk_mmap_pool.h>
14
15 /* AO CONTROL DEVAPC - apu_rcx_ao_infra_dapc_con */
16 static const struct apc_dom_16 APUSYS_CTRL_DAPC_AO[] = {
17 /* ctrl index = 0 */
18 SLAVE_RCX_BULK0("apu_ao_ctl_o-0"),
19 SLAVE_MD32_APB("apu_ao_ctl_o-1"),
20 SLAVE_ACP_TCU_SSC("apu_ao_ctl_o-2"),
21 SLAVE_PTP_THM("apu_ao_ctl_o-3"),
22 SLAVE_VCORE("apu_ao_ctl_o-4"),
23 SLAVE_IOMMU0_BANK0("apu_ao_ctl_o-5"),
24 SLAVE_IOMMU0_BANK1("apu_ao_ctl_o-6"),
25 SLAVE_IOMMU0_BANK2("apu_ao_ctl_o-7"),
26 SLAVE_IOMMU0_BANK3("apu_ao_ctl_o-8"),
27 SLAVE_IOMMU0_BANK4("apu_ao_ctl_o-9"),
28
29 /* ctrl index = 10 */
30 SLAVE_IOMMU1_BANK0("apu_ao_ctl_o-10"),
31 SLAVE_IOMMU1_BANK1("apu_ao_ctl_o-11"),
32 SLAVE_IOMMU1_BANK2("apu_ao_ctl_o-12"),
33 SLAVE_IOMMU1_BANK3("apu_ao_ctl_o-13"),
34 SLAVE_IOMMU1_BANK4("apu_ao_ctl_o-14"),
35 SLAVE_S0_SSC("apu_ao_ctl_o-15"),
36 SLAVE_N0_SSC("apu_ao_ctl_o-16"),
37 SLAVE_S1_SSC("apu_ao_ctl_o-17"),
38 SLAVE_N1_SSC("apu_ao_ctl_o-18"),
39 SLAVE_ACP_SSC("apu_ao_ctl_o-19"),
40
41 /* ctrl index = 20 */
42 SLAVE_WDEC("apu_ao_ctl_o-20"),
43 SLAVE_SMMU_IP_REG("apu_ao_ctl_o-21"),
44 SLAVE_SMMU_NSEC("apu_ao_ctl_o-22"),
45 SLAVE_SMMU_SEC("apu_ao_ctl_o-23"),
46 SLAVE_ARE0("apu_ao_ctl_o-24"),
47 SLAVE_ARE1("apu_ao_ctl_o-25"),
48 SLAVE_SONC("apu_ao_ctl_o-26"),
49 SLAVE_RPC("apu_ao_ctl_o-28"),
50 SLAVE_PCU("apu_ao_ctl_o-29"),
51 SLAVE_AO_CTRL("apu_ao_ctl_o-30"),
52
53 /* ctrl index = 30 */
54 SLAVE_AO_CTRL("apu_ao_ctl_o-31"),
55 SLAVE_ACC("apu_ao_ctl_o-32"),
56 SLAVE_SEC("apu_ao_ctl_o-33"),
57 SLAVE_PLL("apu_ao_ctl_o-34"),
58 SLAVE_RPC_MDLA("apu_ao_ctl_o-35"),
59 SLAVE_TOP_PMU("apu_ao_ctl_o-36"),
60 SLAVE_AO_BCRM("apu_ao_ctl_o-37"),
61 SLAVE_AO_DAPC_WRAP("apu_ao_ctl_o-38"),
62 SLAVE_AO_DAPC_CON("apu_ao_ctl_o-39"),
63 SLAVE_UNDEFINE0("apu_ao_ctl_o-40"),
64
65 /* ctrl index = 40 */
66 SLAVE_UNDEFINE1("apu_ao_ctl_o-41"),
67 SLAVE_RCX_BULK0("apu_ao_ctl_o-42"),
68 SLAVE_UNDEFINE2("apu_ao_ctl_o-43"),
69 SLAVE_UNDEFINE3("apu_ao_ctl_o-44"),
70 SLAVE_UNDEFINE4("apu_ao_ctl_o-45"),
71 SLAVE_UNDEFINE5("apu_ao_ctl_o-46"),
72 SLAVE_UNDEFINE6("apu_ao_ctl_o-47"),
73 SLAVE_UNDEFINE7("apu_ao_ctl_o-48"),
74 SLAVE_DATA_BULK("apu_ao_ctl_o-49"),
75 SLAVE_ACX0_BULK("apu_ao_ctl_o-50"),
76
77 /* ctrl index = 50 */
78 SLAVE_ACX0_AO("apu_ao_ctl_o-51"),
79 SLAVE_ACX1_BULK("apu_ao_ctl_o-52"),
80 SLAVE_ACX1_AO("apu_ao_ctl_o-53"),
81 SLAVE_NCX_BULK("apu_ao_ctl_o-54"),
82 SLAVE_NCX_AO("apu_ao_ctl_o-55"),
83 SLAVE_ACX0_BULK("apu_rcx2acx0_o-0"),
84 SLAVE_ACX0_AO("apu_rcx2acx0_o-1"),
85 SLAVE_ACX0_BULK("apu_sae2acx0_o-0"),
86 SLAVE_ACX0_AO("apu_sae2acx0_o-1"),
87 SLAVE_ACX1_BULK("apu_rcx2acx1_o-0"),
88
89 /* ctrl index = 60 */
90 SLAVE_ACX1_AO("apu_rcx2acx1_o-1"),
91 SLAVE_ACX1_BULK("apu_sae2acx1_o-0"),
92 SLAVE_ACX1_AO("apu_sae2acx1_o-1"),
93 SLAVE_NCX_BULK("apu_rcx2ncx_o-0"),
94 SLAVE_NCX_AO("apu_rcx2ncx_o-1"),
95 SLAVE_NCX_BULK("apu_sae2ncx_o-0"),
96 SLAVE_NCX_AO("apu_sae2ncx_o-1"),
97 };
98
99
100 /* RCX CONTROL DEVAPC - apu_rcx_infra_dapc_con */
101 static const struct apc_dom_16 APUSYS_CTRL_DAPC_RCX[] = {
102 /* ctrl index = 0 */
103 SLAVE_ACX0_BULK("acx0_apbs-0"),
104 SLAVE_ACX0_RPC("acx0_apbs-1"),
105 SLAVE_ACX0_AO_CTRL("acx0_apbs-2"),
106 SLAVE_UNDEFINE8("acx0_apbs-3"),
107 SLAVE_ACX1_BULK("acx1_apbs-0"),
108 SLAVE_ACX1_RPC("acx1_apbs-1"),
109 SLAVE_ACX1_AO_CTRL("acx1_apbs-2"),
110 SLAVE_UNDEFINE9("acx1_apbs-3"),
111 SLAVE_NCX_BULK("ncx_apbs-0"),
112 SLAVE_NCX_RPC("ncx_apbs-1"),
113
114 /* ctrl index = 10 */
115 SLAVE_NCX_AO_CTRL("ncx_apbs-2"),
116 SLAVE_UNDEFINE10("ncx_apbs-3"),
117 SLAVE_MD32_SYSCTRL("md32_apb_s-0"),
118 SLAVE_MD32_PMU("md32_apb_s-1"),
119 SLAVE_MD32_WDT("md32_apb_s-2"),
120 SLAVE_MD32_CACHE("md32_apb_s-3"),
121 SLAVE_ARE0("apusys_ao-0"),
122 SLAVE_ARE1("apusys_ao-1"),
123 SLAVE_SONC("apusys_ao-2"),
124 SLAVE_RPC("apusys_ao-3"),
125
126 /* ctrl index = 20 */
127 SLAVE_PCU("apusys_ao-4"),
128 SLAVE_AO_CTRL("apusys_ao-5"),
129 SLAVE_AO_CTRL("apusys_ao-6"),
130 SLAVE_SEC("apusys_ao-7"),
131 SLAVE_PLL("apusys_ao-8"),
132 SLAVE_RPC_MDLA("apusys_ao-9"),
133 SLAVE_TOP_PMU("apusys_ao-10"),
134 SLAVE_AO_BCRM("apusys_ao-11"),
135 SLAVE_AO_DAPC_WRAP("apusys_ao-12"),
136 SLAVE_AO_DAPC_CON("apusys_ao-13"),
137
138 /* ctrl index = 30 */
139 SLAVE_VCORE("apusys_ao-14"),
140 SLAVE_IOMMU0_BANK0("apusys_ao-15"),
141 SLAVE_IOMMU0_BANK1("apusys_ao-16"),
142 SLAVE_IOMMU0_BANK2("apusys_ao-17"),
143 SLAVE_IOMMU0_BANK3("apusys_ao-18"),
144 SLAVE_IOMMU0_BANK4("apusys_ao-19"),
145 SLAVE_IOMMU1_BANK0("apu_ao_ctl_o-20"),
146 SLAVE_IOMMU1_BANK1("apu_ao_ctl_o-21"),
147 SLAVE_IOMMU1_BANK2("apu_ao_ctl_o-22"),
148 SLAVE_IOMMU1_BANK3("apu_ao_ctl_o-23"),
149
150 /* ctrl index = 40 */
151 SLAVE_IOMMU1_BANK4("apu_ao_ctl_o-24"),
152 SLAVE_S0_SSC("apu_ao_ctl_o-25"),
153 SLAVE_N0_SSC("apu_ao_ctl_o-26"),
154 SLAVE_S1_SSC("apu_ao_ctl_o-27"),
155 SLAVE_N1_SSC("apu_ao_ctl_o-28"),
156 SLAVE_ACP_SSC("apu_ao_ctl_o-29"),
157 SLAVE_ACP_TCU_SSC("apu_ao_ctl_o-30"),
158 SLAVE_PTP_THM("apu_ao_ctl_o-31"),
159 SLAVE_WDEC("apu_ao_ctl_o-32"),
160 SLAVE_SMMU_IP_REG("apu_ao_ctl_o-33"),
161
162 /* ctrl index = 50 */
163 SLAVE_SMMU_NSEC("apu_ao_ctl_o-34"),
164 SLAVE_SMMU_SEC("apu_ao_ctl_o-35"),
165 SLAVE_DATA_BULK("noc_axi"),
166 SLAVE_MD32_DBG("md32_dbg"),
167 SLAVE_MDLA_DBG("mdla_dbg"),
168 SLAVE_INFRA_DBG("apb_infra_dbg"),
169 SLAVE_LOG_TOP0("apu_logtop-0"),
170 SLAVE_LOG_TOP1("apu_logtop-1"),
171 SLAVE_RCX_CFG("apu_rcx_cfg"),
172 SLAVE_ACX_IPS("apu_acx_ips"),
173
174 /* ctrl index = 60 */
175 SLAVE_SEMA_STIMER("apu_sema_stimer"),
176 SLAVE_EMI_CFG("apu_emi_cfg"),
177 SLAVE_CPE_SENSOR("apu_cpe_sensor"),
178 SLAVE_CPE_COEF("apu_cpe_coef"),
179 SLAVE_CPE_CTRL("apu_cpe_ctrl"),
180 SLAVE_TPPA("apu_dfd"),
181 SLAVE_SENSOR_ACX0_DLA0("apu_sen_acx0_dla0"),
182 SLAVE_SENSOR_ACX0_VPU("apu_sen_acx0_vpu"),
183 SLAVE_SENSOR_ACX1_DLA0("apu_sen_acx1_dla0"),
184 SLAVE_SENSOR_ACX1_VPU("apu_sen_acx1_vpu"),
185
186 /* ctrl index = 70 */
187 SLAVE_SENSOR_NCX_DLA0("apu_sen_ncx_dla0"),
188 SLAVE_SENSOR_NCX_NVE("apu_sen_ncx_nve"),
189 SLAVE_RCX_TCU0("noc_cfg-0"),
190 SLAVE_RCX_TCU1("noc_cfg-1"),
191 SLAVE_RCX_TCU2("noc_cfg-2"),
192 SLAVE_RCX_TCU3("noc_cfg-3"),
193 SLAVE_RCX_TCU4("noc_cfg-4"),
194 SLAVE_RCX_TCU5("noc_cfg-5"),
195 SLAVE_RCX_TCU6("noc_cfg-6"),
196 SLAVE_RCX_NOC_CFG("noc_cfg-7"),
197
198 /* ctrl index = 80 */
199 SLAVE_SCMDQ("apu_hse-0"),
200 SLAVE_HSE("apu_hse-1"),
201 SLAVE_MDLA_CORE_CTRL("mdla_cfg-0"),
202 SLAVE_MDLA_BIU("mdla_cfg-1"),
203 SLAVE_MDLA_PMU("mdla_cfg-2"),
204 SLAVE_MDLA_CMDE("mdla_cfg-3"),
205 SLAVE_EDPA0("apu_edpa-0"),
206 SLAVE_EDPA1("apu_edpa-1"),
207 SLAVE_RCX_BCRM("infra_bcrm"),
208 SLAVE_RCX_DAPC_WRAP("infra_dpac_wrap"),
209
210 /* ctrl index = 90 */
211 SLAVE_RCX_DAPC_CON("infra_dapc_con"),
212 SLAVE_RCX_CMU("rcx_cmu"),
213 SLAVE_RCX_ACS("apu_rcx_acs"),
214 SLAVE_RCX_CBFC("rcx_cbfc"),
215 SLAVE_ACC("acc"),
216 };
217
set_slave_ctrl_apc(uint32_t slave,enum apusys_apc_type type,enum apusys_apc_domain_id domain_id,enum apusys_apc_perm_type perm)218 static enum apusys_apc_err_status set_slave_ctrl_apc(uint32_t slave,
219 enum apusys_apc_type type,
220 enum apusys_apc_domain_id domain_id,
221 enum apusys_apc_perm_type perm)
222 {
223 uint32_t apc_register_index;
224 uint32_t apc_set_index;
225 uint32_t base = 0;
226 uint32_t clr_bit;
227 uint32_t set_bit;
228 uint32_t slave_num_in_1_dom;
229 uint32_t slave_num, dom_num;
230 uint32_t dapc_base;
231
232 if (perm >= PERM_NUM) {
233 ERROR("%s: permission type:0x%x is not supported!\n", __func__, perm);
234 return APUSYS_APC_ERR_PERMISSION_NOT_SUPPORTED;
235 }
236
237 switch (type) {
238 case DAPC_AO:
239 slave_num_in_1_dom = APUSYS_CTRL_DAPC_AO_SLAVE_NUM_IN_1_DOM;
240 slave_num = APUSYS_CTRL_DAPC_AO_SLAVE_NUM;
241 dom_num = APUSYS_CTRL_DAPC_AO_DOM_NUM;
242 dapc_base = APUSYS_CTRL_DAPC_AO_BASE;
243 break;
244 case DAPC_RCX:
245 slave_num_in_1_dom = APUSYS_CTRL_DAPC_RCX_SLAVE_NUM_IN_1_DOM;
246 slave_num = APUSYS_CTRL_DAPC_RCX_SLAVE_NUM;
247 dom_num = APUSYS_CTRL_DAPC_RCX_DOM_NUM;
248 dapc_base = APUSYS_CTRL_DAPC_RCX_BASE;
249 break;
250 default:
251 ERROR("%s: unsupported devapc type: %u\n", __func__, type);
252 return APUSYS_APC_ERR_GENERIC;
253 }
254
255 apc_register_index = slave / slave_num_in_1_dom;
256 apc_set_index = slave % slave_num_in_1_dom;
257
258 clr_bit = DEVAPC_MASK << (apc_set_index * DEVAPC_DOM_SHIFT);
259 set_bit = (uint32_t)perm << (apc_set_index * DEVAPC_DOM_SHIFT);
260
261 if (slave < slave_num && domain_id < dom_num) {
262 base = dapc_base + domain_id * DEVAPC_DOM_SIZE
263 + apc_register_index * DEVAPC_REG_SIZE;
264 } else {
265 ERROR("%s: out of boundary, devapc type: %d, slave: 0x%x, domain_id: 0x%x\n",
266 __func__, type, slave, domain_id);
267 return APUSYS_APC_ERR_OUT_OF_BOUNDARY;
268 }
269
270 if (!base)
271 return APUSYS_APC_ERR_GENERIC;
272
273 mmio_clrsetbits_32(base, clr_bit, set_bit);
274 return APUSYS_APC_OK;
275 }
276
set_slave_ao_ctrl_apc(uint32_t slave,enum apusys_apc_domain_id domain_id,enum apusys_apc_perm_type perm)277 static enum apusys_apc_err_status set_slave_ao_ctrl_apc(uint32_t slave,
278 enum apusys_apc_domain_id domain_id,
279 enum apusys_apc_perm_type perm)
280 {
281 return set_slave_ctrl_apc(slave, DAPC_AO, domain_id, perm);
282 }
283
set_slave_rcx_ctrl_apc(uint32_t slave,enum apusys_apc_domain_id domain_id,enum apusys_apc_perm_type perm)284 static enum apusys_apc_err_status set_slave_rcx_ctrl_apc(uint32_t slave,
285 enum apusys_apc_domain_id domain_id,
286 enum apusys_apc_perm_type perm)
287 {
288 return set_slave_ctrl_apc(slave, DAPC_RCX, domain_id, perm);
289 }
290
apusys_devapc_init(uint32_t base)291 static void apusys_devapc_init(uint32_t base)
292 {
293 mmio_write_32(APUSYS_DAPC_CON(base), APUSYS_DAPC_CON_VIO_MASK);
294 }
295
apusys_devapc_ao_init(void)296 int apusys_devapc_ao_init(void)
297 {
298 int32_t ret = APUSYS_APC_OK;
299
300 apusys_devapc_init(APUSYS_CTRL_DAPC_AO_BASE);
301
302 ret = SET_APUSYS_DAPC_V1(APUSYS_CTRL_DAPC_AO, set_slave_ao_ctrl_apc);
303
304 if (ret) {
305 ERROR("[APUAPC_AO] %s: set_apusys_ao_ctrl_dapc failed\n", __func__);
306 return ret;
307 }
308
309 #ifdef DUMP_CFG
310 DUMP_APUSYS_DAPC_V1(APUSYS_CTRL_DAPC_AO);
311 #endif
312
313 INFO("[APUAPC_AO] %s done\n", __func__);
314
315 return ret;
316 }
317
apusys_devapc_rcx_init(void)318 int apusys_devapc_rcx_init(void)
319 {
320 int32_t ret = APUSYS_APC_OK;
321
322 apusys_devapc_init(APUSYS_CTRL_DAPC_RCX_BASE);
323
324 ret = SET_APUSYS_DAPC_V1(APUSYS_CTRL_DAPC_RCX, set_slave_rcx_ctrl_apc);
325 if (ret) {
326 ERROR("[APUAPC_RCX] %s: set_slave_rcx_ctrl_apc failed\n", __func__);
327 return ret;
328 }
329
330 #ifdef DUMP_CFG
331 DUMP_APUSYS_DAPC_V1(APUSYS_CTRL_DAPC_RCX);
332 #endif
333
334 INFO("[APUAPC_RCX] %s done\n", __func__);
335
336 return ret;
337 }
338