1 /*
2 * Copyright 2011, Marvell Semiconductor Inc.
3 * Lei Wen <leiwen@marvell.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 *
7 * Back ported to the 8xx platform (from the 8260 platform) by
8 * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
9 */
10 #ifndef __SDHCI_HW_H
11 #define __SDHCI_HW_H
12
13 #include <asm/io.h>
14 #include <mmc.h>
15 #include <asm/gpio.h>
16
17 /*
18 * Controller registers
19 */
20
21 #define SDHCI_DMA_ADDRESS 0x00
22
23 #define SDHCI_BLOCK_SIZE 0x04
24 #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
25
26 #define SDHCI_BLOCK_COUNT 0x06
27
28 #define SDHCI_ARGUMENT 0x08
29
30 #define SDHCI_TRANSFER_MODE 0x0C
31 #define SDHCI_TRNS_DMA BIT(0)
32 #define SDHCI_TRNS_BLK_CNT_EN BIT(1)
33 #define SDHCI_TRNS_ACMD12 BIT(2)
34 #define SDHCI_TRNS_READ BIT(4)
35 #define SDHCI_TRNS_MULTI BIT(5)
36
37 #define SDHCI_COMMAND 0x0E
38 #define SDHCI_CMD_RESP_MASK 0x03
39 #define SDHCI_CMD_CRC 0x08
40 #define SDHCI_CMD_INDEX 0x10
41 #define SDHCI_CMD_DATA 0x20
42 #define SDHCI_CMD_ABORTCMD 0xC0
43
44 #define SDHCI_CMD_RESP_NONE 0x00
45 #define SDHCI_CMD_RESP_LONG 0x01
46 #define SDHCI_CMD_RESP_SHORT 0x02
47 #define SDHCI_CMD_RESP_SHORT_BUSY 0x03
48
49 #define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))
50 #define SDHCI_GET_CMD(c) ((c>>8) & 0x3f)
51
52 #define SDHCI_RESPONSE 0x10
53
54 #define SDHCI_BUFFER 0x20
55
56 #define SDHCI_PRESENT_STATE 0x24
57 #define SDHCI_CMD_INHIBIT BIT(0)
58 #define SDHCI_DATA_INHIBIT BIT(1)
59 #define SDHCI_DOING_WRITE BIT(8)
60 #define SDHCI_DOING_READ BIT(9)
61 #define SDHCI_SPACE_AVAILABLE BIT(10)
62 #define SDHCI_DATA_AVAILABLE BIT(11)
63 #define SDHCI_CARD_PRESENT BIT(16)
64 #define SDHCI_CARD_STATE_STABLE BIT(17)
65 #define SDHCI_CARD_DETECT_PIN_LEVEL BIT(18)
66 #define SDHCI_WRITE_PROTECT BIT(19)
67 #define SDHCI_DATA_0_LVL BIT(20)
68
69 #define SDHCI_HOST_CONTROL 0x28
70 #define SDHCI_CTRL_LED BIT(0)
71 #define SDHCI_CTRL_4BITBUS BIT(1)
72 #define SDHCI_CTRL_HISPD BIT(2)
73 #define SDHCI_CTRL_DMA_MASK 0x18
74 #define SDHCI_CTRL_SDMA 0x00
75 #define SDHCI_CTRL_ADMA1 0x08
76 #define SDHCI_CTRL_ADMA32 0x10
77 #define SDHCI_CTRL_ADMA64 0x18
78 #define SDHCI_CTRL_8BITBUS BIT(5)
79 #define SDHCI_CTRL_CD_TEST_INS BIT(6)
80 #define SDHCI_CTRL_CD_TEST BIT(7)
81
82 #define SDHCI_POWER_CONTROL 0x29
83 #define SDHCI_POWER_ON 0x01
84 #define SDHCI_POWER_180 0x0A
85 #define SDHCI_POWER_300 0x0C
86 #define SDHCI_POWER_330 0x0E
87
88 #define SDHCI_BLOCK_GAP_CONTROL 0x2A
89
90 #define SDHCI_WAKE_UP_CONTROL 0x2B
91 #define SDHCI_WAKE_ON_INT BIT(0)
92 #define SDHCI_WAKE_ON_INSERT BIT(1)
93 #define SDHCI_WAKE_ON_REMOVE BIT(2)
94
95 #define SDHCI_CLOCK_CONTROL 0x2C
96 #define SDHCI_DIVIDER_SHIFT 8
97 #define SDHCI_DIVIDER_HI_SHIFT 6
98 #define SDHCI_DIV_MASK 0xFF
99 #define SDHCI_DIV_MASK_LEN 8
100 #define SDHCI_DIV_HI_MASK 0x300
101 #define SDHCI_PROG_CLOCK_MODE BIT(5)
102 #define SDHCI_CLOCK_CARD_EN BIT(2)
103 #define SDHCI_CLOCK_INT_STABLE BIT(1)
104 #define SDHCI_CLOCK_INT_EN BIT(0)
105
106 #define SDHCI_TIMEOUT_CONTROL 0x2E
107
108 #define SDHCI_SOFTWARE_RESET 0x2F
109 #define SDHCI_RESET_ALL 0x01
110 #define SDHCI_RESET_CMD 0x02
111 #define SDHCI_RESET_DATA 0x04
112
113 #define SDHCI_INT_STATUS 0x30
114 #define SDHCI_INT_ENABLE 0x34
115 #define SDHCI_SIGNAL_ENABLE 0x38
116 #define SDHCI_INT_RESPONSE BIT(0)
117 #define SDHCI_INT_DATA_END BIT(1)
118 #define SDHCI_INT_DMA_END BIT(3)
119 #define SDHCI_INT_SPACE_AVAIL BIT(4)
120 #define SDHCI_INT_DATA_AVAIL BIT(5)
121 #define SDHCI_INT_CARD_INSERT BIT(6)
122 #define SDHCI_INT_CARD_REMOVE BIT(7)
123 #define SDHCI_INT_CARD_INT BIT(8)
124 #define SDHCI_INT_ERROR BIT(15)
125 #define SDHCI_INT_TIMEOUT BIT(16)
126 #define SDHCI_INT_CRC BIT(17)
127 #define SDHCI_INT_END_BIT BIT(18)
128 #define SDHCI_INT_INDEX BIT(19)
129 #define SDHCI_INT_DATA_TIMEOUT BIT(20)
130 #define SDHCI_INT_DATA_CRC BIT(21)
131 #define SDHCI_INT_DATA_END_BIT BIT(22)
132 #define SDHCI_INT_BUS_POWER BIT(23)
133 #define SDHCI_INT_ACMD12ERR BIT(24)
134 #define SDHCI_INT_ADMA_ERROR BIT(25)
135
136 #define SDHCI_INT_NORMAL_MASK 0x00007FFF
137 #define SDHCI_INT_ERROR_MASK 0xFFFF8000
138
139 #define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \
140 SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX)
141 #define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \
142 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \
143 SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \
144 SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR)
145 #define SDHCI_INT_ALL_MASK ((unsigned int)-1)
146
147 #define SDHCI_ACMD12_ERR 0x3C
148
149 /* 3E-3F reserved */
150 #define SDHCI_HOST_CONTROL2 0x3E
151 #define SDHCI_CTRL_UHS_MASK 0x0007
152 #define SDHCI_CTRL_UHS_SDR12 0x0000
153 #define SDHCI_CTRL_UHS_SDR25 0x0001
154 #define SDHCI_CTRL_UHS_SDR50 0x0002
155 #define SDHCI_CTRL_UHS_SDR104 0x0003
156 #define SDHCI_CTRL_UHS_DDR50 0x0004
157 #define SDHCI_CTRL_HS400 0x0005
158 #define SDHCI_CTRL_VDD_180 0x0008
159 #define SDHCI_CTRL_DRV_TYPE_MASK 0x0030
160 #define SDHCI_CTRL_DRV_TYPE_B 0x0000
161 #define SDHCI_CTRL_DRV_TYPE_A 0x0010
162 #define SDHCI_CTRL_DRV_TYPE_C 0x0020
163 #define SDHCI_CTRL_DRV_TYPE_D 0x0030
164 #define SDHCI_CTRL_EXEC_TUNING 0x0040
165 #define SDHCI_CTRL_TUNED_CLK 0x0080
166 #define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000
167
168 #define SDHCI_CAPABILITIES 0x40
169 #define SDHCI_TIMEOUT_CLK_MASK 0x0000003F
170 #define SDHCI_TIMEOUT_CLK_SHIFT 0
171 #define SDHCI_TIMEOUT_CLK_UNIT 0x00000080
172 #define SDHCI_CLOCK_BASE_MASK 0x00003F00
173 #define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00
174 #define SDHCI_CLOCK_BASE_SHIFT 8
175 #define SDHCI_MAX_BLOCK_MASK 0x00030000
176 #define SDHCI_MAX_BLOCK_SHIFT 16
177 #define SDHCI_CAN_DO_8BIT BIT(18)
178 #define SDHCI_CAN_DO_ADMA2 BIT(19)
179 #define SDHCI_CAN_DO_ADMA1 BIT(20)
180 #define SDHCI_CAN_DO_HISPD BIT(21)
181 #define SDHCI_CAN_DO_SDMA BIT(22)
182 #define SDHCI_CAN_VDD_330 BIT(24)
183 #define SDHCI_CAN_VDD_300 BIT(25)
184 #define SDHCI_CAN_VDD_180 BIT(26)
185 #define SDHCI_CAN_64BIT BIT(28)
186
187 #define SDHCI_CAPABILITIES_1 0x44
188 #define SDHCI_CLOCK_MUL_MASK 0x00FF0000
189 #define SDHCI_CLOCK_MUL_SHIFT 16
190
191 #define SDHCI_MAX_CURRENT 0x48
192
193 /* 4C-4F reserved for more max current */
194
195 #define SDHCI_SET_ACMD12_ERROR 0x50
196 #define SDHCI_SET_INT_ERROR 0x52
197
198 #define SDHCI_ADMA_ERROR 0x54
199
200 /* 55-57 reserved */
201
202 #define SDHCI_ADMA_ADDRESS 0x58
203
204 /* 60-FB reserved */
205
206 #define SDHCI_SLOT_INT_STATUS 0xFC
207
208 #define SDHCI_HOST_VERSION 0xFE
209 #define SDHCI_VENDOR_VER_MASK 0xFF00
210 #define SDHCI_VENDOR_VER_SHIFT 8
211 #define SDHCI_SPEC_VER_MASK 0x00FF
212 #define SDHCI_SPEC_VER_SHIFT 0
213 #define SDHCI_SPEC_100 0
214 #define SDHCI_SPEC_200 1
215 #define SDHCI_SPEC_300 2
216
217 #define SDHCI_GET_VERSION(x) (x->version & SDHCI_SPEC_VER_MASK)
218
219 /*
220 * End of controller registers.
221 */
222
223 #define SDHCI_MAX_DIV_SPEC_200 256
224 #define SDHCI_MAX_DIV_SPEC_300 2046
225
226 /*
227 * quirks
228 */
229 #define SDHCI_QUIRK_32BIT_DMA_ADDR (1 << 0)
230 #define SDHCI_QUIRK_REG32_RW (1 << 1)
231 #define SDHCI_QUIRK_BROKEN_R1B (1 << 2)
232 #define SDHCI_QUIRK_NO_HISPD_BIT (1 << 3)
233 #define SDHCI_QUIRK_BROKEN_VOLTAGE (1 << 4)
234 #define SDHCI_QUIRK_WAIT_SEND_CMD (1 << 6)
235 #define SDHCI_QUIRK_USE_WIDE8 (1 << 8)
236
237 /* to make gcc happy */
238 struct sdhci_host;
239
240 /*
241 * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2.
242 */
243 #define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024)
244 #define SDHCI_DEFAULT_BOUNDARY_ARG (7)
245 struct sdhci_ops {
246 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
247 u32 (*read_l)(struct sdhci_host *host, int reg);
248 u16 (*read_w)(struct sdhci_host *host, int reg);
249 u8 (*read_b)(struct sdhci_host *host, int reg);
250 void (*write_l)(struct sdhci_host *host, u32 val, int reg);
251 void (*write_w)(struct sdhci_host *host, u16 val, int reg);
252 void (*write_b)(struct sdhci_host *host, u8 val, int reg);
253 #endif
254 int (*get_cd)(struct sdhci_host *host);
255 void (*set_control_reg)(struct sdhci_host *host);
256 void (*set_ios_post)(struct sdhci_host *host);
257 int (*set_clock)(struct sdhci_host *host, unsigned int clock);
258 void (*set_clock_ext)(struct sdhci_host *host, u32 div);
259
260 /**
261 * set_enhanced_strobe() - Set HS400 Enhanced Strobe config
262 *
263 * This is called after setting the card speed and mode to
264 * HS400 ES, and should set any host-specific configuration
265 * necessary for it.
266 *
267 * @host: SDHCI host structure
268 * Return: 0 if successful, -ve on error
269 */
270 int (*set_enhanced_strobe)(struct sdhci_host *host);
271 };
272
273 struct sdhci_host {
274 const char *name;
275 void *ioaddr;
276 unsigned int quirks;
277 unsigned int host_caps;
278 unsigned int version;
279 unsigned int max_clk; /* Maximum Base Clock frequency */
280 unsigned int clk_mul; /* Clock Multiplier value */
281 unsigned int clock;
282 struct mmc *mmc;
283 const struct sdhci_ops *ops;
284 int index;
285
286 int bus_width;
287 struct gpio_desc pwr_gpio; /* Power GPIO */
288 struct gpio_desc cd_gpio; /* Card Detect GPIO */
289
290 uint voltages;
291
292 struct mmc_config cfg;
293 };
294
295 void sdhci_enable_clk(struct sdhci_host *host, u16 clk);
296 int sdhci_set_clock(struct sdhci_host *host, unsigned int clock);
297
298 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
299
sdhci_writel(struct sdhci_host * host,u32 val,int reg)300 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
301 {
302 if (unlikely(host->ops->write_l))
303 host->ops->write_l(host, val, reg);
304 else
305 writel(val, host->ioaddr + reg);
306 }
307
sdhci_writew(struct sdhci_host * host,u16 val,int reg)308 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
309 {
310 if (unlikely(host->ops->write_w))
311 host->ops->write_w(host, val, reg);
312 else
313 writew(val, host->ioaddr + reg);
314 }
315
sdhci_writeb(struct sdhci_host * host,u8 val,int reg)316 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
317 {
318 if (unlikely(host->ops->write_b))
319 host->ops->write_b(host, val, reg);
320 else
321 writeb(val, host->ioaddr + reg);
322 }
323
sdhci_readl(struct sdhci_host * host,int reg)324 static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
325 {
326 if (unlikely(host->ops->read_l))
327 return host->ops->read_l(host, reg);
328 else
329 return readl(host->ioaddr + reg);
330 }
331
sdhci_readw(struct sdhci_host * host,int reg)332 static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
333 {
334 if (unlikely(host->ops->read_w))
335 return host->ops->read_w(host, reg);
336 else
337 return readw(host->ioaddr + reg);
338 }
339
sdhci_readb(struct sdhci_host * host,int reg)340 static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
341 {
342 if (unlikely(host->ops->read_b))
343 return host->ops->read_b(host, reg);
344 else
345 return readb(host->ioaddr + reg);
346 }
347
348 #else
349
sdhci_writel(struct sdhci_host * host,u32 val,int reg)350 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
351 {
352 writel(val, host->ioaddr + reg);
353 }
354
sdhci_writew(struct sdhci_host * host,u16 val,int reg)355 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
356 {
357 writew(val, host->ioaddr + reg);
358 }
359
sdhci_writeb(struct sdhci_host * host,u8 val,int reg)360 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
361 {
362 writeb(val, host->ioaddr + reg);
363 }
sdhci_readl(struct sdhci_host * host,int reg)364 static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
365 {
366 return readl(host->ioaddr + reg);
367 }
368
sdhci_readw(struct sdhci_host * host,int reg)369 static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
370 {
371 return readw(host->ioaddr + reg);
372 }
373
sdhci_readb(struct sdhci_host * host,int reg)374 static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
375 {
376 return readb(host->ioaddr + reg);
377 }
378 #endif
379
380 #ifdef CONFIG_BLK
381 /**
382 * sdhci_setup_cfg() - Set up the configuration for DWMMC
383 *
384 * This is used to set up an SDHCI device when you are using CONFIG_BLK.
385 *
386 * This should be called from your MMC driver's probe() method once you have
387 * the information required.
388 *
389 * Generally your driver will have a platform data structure which holds both
390 * the configuration (struct mmc_config) and the MMC device info (struct mmc).
391 * For example:
392 *
393 * struct msm_sdhc_plat {
394 * struct mmc_config cfg;
395 * struct mmc mmc;
396 * };
397 *
398 * ...
399 *
400 * Inside U_BOOT_DRIVER():
401 * .platdata_auto_alloc_size = sizeof(struct msm_sdhc_plat),
402 *
403 * To access platform data:
404 * struct msm_sdhc_plat *plat = dev_get_platdata(dev);
405 *
406 * See msm_sdhci.c for an example.
407 *
408 * @cfg: Configuration structure to fill in (generally &plat->mmc)
409 * @host: SDHCI host structure
410 * @f_max: Maximum supported clock frequency in HZ (0 for default)
411 * @f_min: Minimum supported clock frequency in HZ (0 for default)
412 */
413 int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
414 u32 f_max, u32 f_min);
415
416 /**
417 * sdhci_bind() - Set up a new MMC block device
418 *
419 * This is used to set up an SDHCI block device when you are using CONFIG_BLK.
420 * It should be called from your driver's bind() method.
421 *
422 * See msm_sdhci.c for an example.
423 *
424 * @dev: Device to set up
425 * @mmc: Pointer to mmc structure (normally &plat->mmc)
426 * @cfg: Empty configuration structure (generally &plat->cfg). This is
427 * normally all zeroes at this point. The only purpose of passing
428 * this in is to set mmc->cfg to it.
429 * @return 0 if OK, -ve if the block device could not be created
430 */
431 int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg);
432 #else
433
434 /**
435 * add_sdhci() - Add a new SDHCI interface
436 *
437 * This is used when you are not using CONFIG_BLK. Convert your driver over!
438 *
439 * @host: SDHCI host structure
440 * @f_max: Maximum supported clock frequency in HZ (0 for default)
441 * @f_min: Minimum supported clock frequency in HZ (0 for default)
442 * @return 0 if OK, -ve on error
443 */
444 int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min);
445 #endif /* !CONFIG_BLK */
446
447 #ifdef CONFIG_DM_MMC
448 /* Export the operations to drivers */
449 int sdhci_probe(struct udevice *dev);
450 extern const struct dm_mmc_ops sdhci_ops;
451 #else
452 #endif
453
454 #endif /* __SDHCI_HW_H */
455