1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * maxim-max96745.c -- I2C register interface access for max96745 serdes chip
4 *
5 * Copyright (c) 2023-2028 Rockchip Electronics Co. Ltd.
6 *
7 * Author: luowei <lw@rock-chips.com>
8 */
9 #include "../core.h"
10 #include "maxim-max96745.h"
11 struct serdes_function_data {
12 u8 gpio_out_dis:1;
13 u8 gpio_io_rx_en:1;
14 u8 gpio_tx_en_a:1;
15 u8 gpio_tx_en_b:1;
16 u8 gpio_rx_en_a:1;
17 u8 gpio_rx_en_b:1;
18 u8 gpio_tx_id;
19 u8 gpio_rx_id;
20 u16 mdelay;
21 };
22
23 struct config_desc {
24 u16 reg;
25 u8 mask;
26 u8 val;
27 };
28
29 struct serdes_group_data {
30 const struct config_desc *configs;
31 int num_configs;
32 };
33
34 static int MAX96745_MFP0_pins[] = {0};
35 static int MAX96745_MFP1_pins[] = {1};
36 static int MAX96745_MFP2_pins[] = {2};
37 static int MAX96745_MFP3_pins[] = {3};
38 static int MAX96745_MFP4_pins[] = {4};
39 static int MAX96745_MFP5_pins[] = {5};
40 static int MAX96745_MFP6_pins[] = {6};
41 static int MAX96745_MFP7_pins[] = {7};
42
43 static int MAX96745_MFP8_pins[] = {8};
44 static int MAX96745_MFP9_pins[] = {9};
45 static int MAX96745_MFP10_pins[] = {10};
46 static int MAX96745_MFP11_pins[] = {11};
47 static int MAX96745_MFP12_pins[] = {12};
48 static int MAX96745_MFP13_pins[] = {13};
49 static int MAX96745_MFP14_pins[] = {14};
50 static int MAX96745_MFP15_pins[] = {15};
51
52 static int MAX96745_MFP16_pins[] = {16};
53 static int MAX96745_MFP17_pins[] = {17};
54 static int MAX96745_MFP18_pins[] = {18};
55 static int MAX96745_MFP19_pins[] = {19};
56 static int MAX96745_MFP20_pins[] = {20};
57 static int MAX96745_MFP21_pins[] = {21};
58 static int MAX96745_MFP22_pins[] = {22};
59 static int MAX96745_MFP23_pins[] = {23};
60
61 static int MAX96745_MFP24_pins[] = {24};
62 static int MAX96745_MFP25_pins[] = {25};
63 static int MAX96745_I2C_pins[] = {3, 7};
64 static int MAX96745_UART_pins[] = {3, 7};
65
66 #define GROUP_DESC(nm) \
67 { \
68 .name = #nm, \
69 .pins = nm ## _pins, \
70 .num_pins = ARRAY_SIZE(nm ## _pins), \
71 }
72
73 static const char *serdes_gpio_groups[] = {
74 "MAX96745_MFP0", "MAX96745_MFP1", "MAX96745_MFP2", "MAX96745_MFP3",
75 "MAX96745_MFP4", "MAX96745_MFP5", "MAX96745_MFP6", "MAX96745_MFP7",
76
77 "MAX96745_MFP8", "MAX96745_MFP9", "MAX96745_MFP10", "MAX96745_MFP11",
78 "MAX96745_MFP12", "MAX96745_MFP13", "MAX96745_MFP14", "MAX96745_MFP15",
79
80 "MAX96745_MFP16", "MAX96745_MFP17", "MAX96745_MFP18", "MAX96745_MFP19",
81 "MAX96745_MFP20", "MAX96745_MFP21", "MAX96745_MFP22", "MAX96745_MFP23",
82
83 "MAX96745_MFP24", "MAX96745_MFP25",
84 };
85
86 static const char *MAX96745_I2C_groups[] = { "MAX96745_I2C" };
87 static const char *MAX96745_UART_groups[] = { "MAX96745_UART" };
88
89 #define FUNCTION_DESC(nm) \
90 { \
91 .name = #nm, \
92 .group_names = nm##_groups, \
93 .num_group_names = ARRAY_SIZE(nm##_groups), \
94 } \
95
96 #define FUNCTION_DESC_GPIO_OUTPUT_A(id) \
97 { \
98 .name = "SER_TXID"#id"_TO_DES_LINKA", \
99 .group_names = serdes_gpio_groups, \
100 .num_group_names = ARRAY_SIZE(serdes_gpio_groups), \
101 .data = (void *)(const struct serdes_function_data []) { \
102 { .gpio_out_dis = 1, .gpio_tx_en_a = 1, \
103 .gpio_io_rx_en = 1, .gpio_tx_id = id } \
104 }, \
105 } \
106
107 #define FUNCTION_DESC_GPIO_OUTPUT_B(id) \
108 { \
109 .name = "SER_TXID"#id"_TO_DES_LINKB", \
110 .group_names = serdes_gpio_groups, \
111 .num_group_names = ARRAY_SIZE(serdes_gpio_groups), \
112 .data = (void *)(const struct serdes_function_data []) { \
113 { .gpio_out_dis = 1, .gpio_tx_en_b = 1, \
114 .gpio_io_rx_en = 1, .gpio_tx_id = id } \
115 }, \
116 } \
117
118 #define FUNCTION_DESC_GPIO_INPUT_A(id) \
119 { \
120 .name = "DES_RXID"#id"_TO_SER_LINKA", \
121 .group_names = serdes_gpio_groups, \
122 .num_group_names = ARRAY_SIZE(serdes_gpio_groups), \
123 .data = (void *)(const struct serdes_function_data []) { \
124 { .gpio_rx_en_a = 1, .gpio_rx_id = id } \
125 }, \
126 } \
127
128 #define FUNCTION_DESC_GPIO_INPUT_B(id) \
129 { \
130 .name = "DES_RXID"#id"_TO_SER_LINKB", \
131 .group_names = serdes_gpio_groups, \
132 .num_group_names = ARRAY_SIZE(serdes_gpio_groups), \
133 .data = (void *)(const struct serdes_function_data []) { \
134 { .gpio_rx_en_b = 1, .gpio_rx_id = id } \
135 }, \
136 } \
137
138 #define FUNCTION_DESC_GPIO() \
139 { \
140 .name = "MAX96745_GPIO", \
141 .group_names = serdes_gpio_groups, \
142 .num_group_names = ARRAY_SIZE(serdes_gpio_groups), \
143 .data = (void *)(const struct serdes_function_data []) { \
144 { } \
145 }, \
146 } \
147
148 static struct pinctrl_pin_desc max96745_pins_desc[] = {
149 PINCTRL_PIN(MAXIM_MAX96745_MFP0, "MAX96745_MFP0"),
150 PINCTRL_PIN(MAXIM_MAX96745_MFP1, "MAX96745_MFP1"),
151 PINCTRL_PIN(MAXIM_MAX96745_MFP2, "MAX96745_MFP2"),
152 PINCTRL_PIN(MAXIM_MAX96745_MFP3, "MAX96745_MFP3"),
153 PINCTRL_PIN(MAXIM_MAX96745_MFP4, "MAX96745_MFP4"),
154 PINCTRL_PIN(MAXIM_MAX96745_MFP5, "MAX96745_MFP5"),
155 PINCTRL_PIN(MAXIM_MAX96745_MFP6, "MAX96745_MFP6"),
156 PINCTRL_PIN(MAXIM_MAX96745_MFP7, "MAX96745_MFP7"),
157
158 PINCTRL_PIN(MAXIM_MAX96745_MFP8, "MAX96745_MFP8"),
159 PINCTRL_PIN(MAXIM_MAX96745_MFP9, "MAX96745_MFP9"),
160 PINCTRL_PIN(MAXIM_MAX96745_MFP10, "MAX96745_MFP10"),
161 PINCTRL_PIN(MAXIM_MAX96745_MFP11, "MAX96745_MFP11"),
162 PINCTRL_PIN(MAXIM_MAX96745_MFP12, "MAX96745_MFP12"),
163 PINCTRL_PIN(MAXIM_MAX96745_MFP13, "MAX96745_MFP13"),
164 PINCTRL_PIN(MAXIM_MAX96745_MFP14, "MAX96745_MFP14"),
165 PINCTRL_PIN(MAXIM_MAX96745_MFP15, "MAX96745_MFP15"),
166
167 PINCTRL_PIN(MAXIM_MAX96745_MFP16, "MAX96745_MFP16"),
168 PINCTRL_PIN(MAXIM_MAX96745_MFP17, "MAX96745_MFP17"),
169 PINCTRL_PIN(MAXIM_MAX96745_MFP18, "MAX96745_MFP18"),
170 PINCTRL_PIN(MAXIM_MAX96745_MFP19, "MAX96745_MFP19"),
171 PINCTRL_PIN(MAXIM_MAX96745_MFP20, "MAX96745_MFP20"),
172 PINCTRL_PIN(MAXIM_MAX96745_MFP21, "MAX96745_MFP21"),
173 PINCTRL_PIN(MAXIM_MAX96745_MFP22, "MAX96745_MFP22"),
174 PINCTRL_PIN(MAXIM_MAX96745_MFP23, "MAX96745_MFP23"),
175
176 PINCTRL_PIN(MAXIM_MAX96745_MFP24, "MAX96745_MFP24"),
177 PINCTRL_PIN(MAXIM_MAX96745_MFP25, "MAX96745_MFP25"),
178 };
179
180 static struct group_desc max96745_groups_desc[] = {
181 GROUP_DESC(MAX96745_MFP0),
182 GROUP_DESC(MAX96745_MFP1),
183 GROUP_DESC(MAX96745_MFP2),
184 GROUP_DESC(MAX96745_MFP3),
185 GROUP_DESC(MAX96745_MFP4),
186 GROUP_DESC(MAX96745_MFP5),
187 GROUP_DESC(MAX96745_MFP6),
188 GROUP_DESC(MAX96745_MFP7),
189
190 GROUP_DESC(MAX96745_MFP8),
191 GROUP_DESC(MAX96745_MFP9),
192 GROUP_DESC(MAX96745_MFP10),
193 GROUP_DESC(MAX96745_MFP11),
194 GROUP_DESC(MAX96745_MFP12),
195 GROUP_DESC(MAX96745_MFP13),
196 GROUP_DESC(MAX96745_MFP14),
197 GROUP_DESC(MAX96745_MFP15),
198
199 GROUP_DESC(MAX96745_MFP16),
200 GROUP_DESC(MAX96745_MFP17),
201 GROUP_DESC(MAX96745_MFP18),
202 GROUP_DESC(MAX96745_MFP19),
203 GROUP_DESC(MAX96745_MFP20),
204 GROUP_DESC(MAX96745_MFP21),
205 GROUP_DESC(MAX96745_MFP22),
206 GROUP_DESC(MAX96745_MFP23),
207
208 GROUP_DESC(MAX96745_MFP24),
209 GROUP_DESC(MAX96745_MFP25),
210
211 GROUP_DESC(MAX96745_I2C),
212 GROUP_DESC(MAX96745_UART),
213 };
214
215 static struct function_desc max96745_functions_desc[] = {
216 FUNCTION_DESC_GPIO_INPUT_A(0),
217 FUNCTION_DESC_GPIO_INPUT_A(1),
218 FUNCTION_DESC_GPIO_INPUT_A(2),
219 FUNCTION_DESC_GPIO_INPUT_A(3),
220 FUNCTION_DESC_GPIO_INPUT_A(4),
221 FUNCTION_DESC_GPIO_INPUT_A(5),
222 FUNCTION_DESC_GPIO_INPUT_A(6),
223 FUNCTION_DESC_GPIO_INPUT_A(7),
224
225 FUNCTION_DESC_GPIO_INPUT_A(8),
226 FUNCTION_DESC_GPIO_INPUT_A(9),
227 FUNCTION_DESC_GPIO_INPUT_A(10),
228 FUNCTION_DESC_GPIO_INPUT_A(11),
229 FUNCTION_DESC_GPIO_INPUT_A(12),
230 FUNCTION_DESC_GPIO_INPUT_A(13),
231 FUNCTION_DESC_GPIO_INPUT_A(14),
232 FUNCTION_DESC_GPIO_INPUT_A(15),
233
234 FUNCTION_DESC_GPIO_INPUT_A(16),
235 FUNCTION_DESC_GPIO_INPUT_A(17),
236 FUNCTION_DESC_GPIO_INPUT_A(18),
237 FUNCTION_DESC_GPIO_INPUT_A(19),
238 FUNCTION_DESC_GPIO_INPUT_A(20),
239 FUNCTION_DESC_GPIO_INPUT_A(21),
240 FUNCTION_DESC_GPIO_INPUT_A(22),
241 FUNCTION_DESC_GPIO_INPUT_A(23),
242
243 FUNCTION_DESC_GPIO_INPUT_A(24),
244 FUNCTION_DESC_GPIO_INPUT_A(25),
245
246 FUNCTION_DESC_GPIO_OUTPUT_A(0),
247 FUNCTION_DESC_GPIO_OUTPUT_A(1),
248 FUNCTION_DESC_GPIO_OUTPUT_A(2),
249 FUNCTION_DESC_GPIO_OUTPUT_A(3),
250 FUNCTION_DESC_GPIO_OUTPUT_A(4),
251 FUNCTION_DESC_GPIO_OUTPUT_A(5),
252 FUNCTION_DESC_GPIO_OUTPUT_A(6),
253 FUNCTION_DESC_GPIO_OUTPUT_A(7),
254
255 FUNCTION_DESC_GPIO_OUTPUT_A(8),
256 FUNCTION_DESC_GPIO_OUTPUT_A(9),
257 FUNCTION_DESC_GPIO_OUTPUT_A(10),
258 FUNCTION_DESC_GPIO_OUTPUT_A(11),
259 FUNCTION_DESC_GPIO_OUTPUT_A(12),
260 FUNCTION_DESC_GPIO_OUTPUT_A(13),
261 FUNCTION_DESC_GPIO_OUTPUT_A(14),
262 FUNCTION_DESC_GPIO_OUTPUT_A(15),
263
264 FUNCTION_DESC_GPIO_OUTPUT_A(16),
265 FUNCTION_DESC_GPIO_OUTPUT_A(17),
266 FUNCTION_DESC_GPIO_OUTPUT_A(18),
267 FUNCTION_DESC_GPIO_OUTPUT_A(19),
268 FUNCTION_DESC_GPIO_OUTPUT_A(20),
269 FUNCTION_DESC_GPIO_OUTPUT_A(21),
270 FUNCTION_DESC_GPIO_OUTPUT_A(22),
271 FUNCTION_DESC_GPIO_OUTPUT_A(23),
272
273 FUNCTION_DESC_GPIO_OUTPUT_A(24),
274 FUNCTION_DESC_GPIO_OUTPUT_A(25),
275
276 FUNCTION_DESC_GPIO_INPUT_B(0),
277 FUNCTION_DESC_GPIO_INPUT_B(1),
278 FUNCTION_DESC_GPIO_INPUT_B(2),
279 FUNCTION_DESC_GPIO_INPUT_B(3),
280 FUNCTION_DESC_GPIO_INPUT_B(4),
281 FUNCTION_DESC_GPIO_INPUT_B(5),
282 FUNCTION_DESC_GPIO_INPUT_B(6),
283 FUNCTION_DESC_GPIO_INPUT_B(7),
284
285 FUNCTION_DESC_GPIO_INPUT_B(8),
286 FUNCTION_DESC_GPIO_INPUT_B(9),
287 FUNCTION_DESC_GPIO_INPUT_B(10),
288 FUNCTION_DESC_GPIO_INPUT_B(11),
289 FUNCTION_DESC_GPIO_INPUT_B(12),
290 FUNCTION_DESC_GPIO_INPUT_B(13),
291 FUNCTION_DESC_GPIO_INPUT_B(14),
292 FUNCTION_DESC_GPIO_INPUT_B(15),
293
294 FUNCTION_DESC_GPIO_INPUT_B(16),
295 FUNCTION_DESC_GPIO_INPUT_B(17),
296 FUNCTION_DESC_GPIO_INPUT_B(18),
297 FUNCTION_DESC_GPIO_INPUT_B(19),
298 FUNCTION_DESC_GPIO_INPUT_B(20),
299 FUNCTION_DESC_GPIO_INPUT_B(21),
300 FUNCTION_DESC_GPIO_INPUT_B(22),
301 FUNCTION_DESC_GPIO_INPUT_B(23),
302
303 FUNCTION_DESC_GPIO_INPUT_B(24),
304 FUNCTION_DESC_GPIO_INPUT_B(25),
305
306 FUNCTION_DESC_GPIO_OUTPUT_B(0),
307 FUNCTION_DESC_GPIO_OUTPUT_B(1),
308 FUNCTION_DESC_GPIO_OUTPUT_B(2),
309 FUNCTION_DESC_GPIO_OUTPUT_B(3),
310 FUNCTION_DESC_GPIO_OUTPUT_B(4),
311 FUNCTION_DESC_GPIO_OUTPUT_B(5),
312 FUNCTION_DESC_GPIO_OUTPUT_B(6),
313 FUNCTION_DESC_GPIO_OUTPUT_B(7),
314
315 FUNCTION_DESC_GPIO_OUTPUT_B(8),
316 FUNCTION_DESC_GPIO_OUTPUT_B(9),
317 FUNCTION_DESC_GPIO_OUTPUT_B(10),
318 FUNCTION_DESC_GPIO_OUTPUT_B(11),
319 FUNCTION_DESC_GPIO_OUTPUT_B(12),
320 FUNCTION_DESC_GPIO_OUTPUT_B(13),
321 FUNCTION_DESC_GPIO_OUTPUT_B(14),
322 FUNCTION_DESC_GPIO_OUTPUT_B(15),
323
324 FUNCTION_DESC_GPIO_OUTPUT_B(16),
325 FUNCTION_DESC_GPIO_OUTPUT_B(17),
326 FUNCTION_DESC_GPIO_OUTPUT_B(18),
327 FUNCTION_DESC_GPIO_OUTPUT_B(19),
328 FUNCTION_DESC_GPIO_OUTPUT_B(20),
329 FUNCTION_DESC_GPIO_OUTPUT_B(21),
330 FUNCTION_DESC_GPIO_OUTPUT_B(22),
331 FUNCTION_DESC_GPIO_OUTPUT_B(23),
332
333 FUNCTION_DESC_GPIO_OUTPUT_B(24),
334 FUNCTION_DESC_GPIO_OUTPUT_B(25),
335
336 FUNCTION_DESC_GPIO(),
337
338 FUNCTION_DESC(MAX96745_I2C),
339 FUNCTION_DESC(MAX96745_UART),
340 };
341
342 static struct serdes_chip_pinctrl_info max96745_pinctrl_info = {
343 .pins = max96745_pins_desc,
344 .num_pins = ARRAY_SIZE(max96745_pins_desc),
345 .groups = max96745_groups_desc,
346 .num_groups = ARRAY_SIZE(max96745_groups_desc),
347 .functions = max96745_functions_desc,
348 .num_functions = ARRAY_SIZE(max96745_functions_desc),
349 };
350
max96745_bridge_linka_locked(struct serdes * serdes)351 static bool max96745_bridge_linka_locked(struct serdes *serdes)
352 {
353 u32 val;
354
355 if (dm_gpio_is_valid(&serdes->lock_gpio)) {
356 val = dm_gpio_get_value(&serdes->lock_gpio);
357 SERDES_DBG_CHIP("serdes %s:val=%d\n", __func__, val);
358 return val;
359 }
360
361 if (serdes_reg_read(serdes, 0x002a, &val)) {
362 SERDES_DBG_CHIP("serdes %s: false val=%d\n", __func__, val);
363 return false;
364 }
365
366 if (!FIELD_GET(LOCKED, val)) {
367 SERDES_DBG_CHIP("serdes %s: false val=%d\n", __func__, val);
368 return false;
369 }
370
371 return true;
372 }
373
max96745_bridge_linkb_locked(struct serdes * serdes)374 static bool max96745_bridge_linkb_locked(struct serdes *serdes)
375 {
376 u32 val;
377
378 if (dm_gpio_is_valid(&serdes->lock_gpio)) {
379 val = dm_gpio_get_value(&serdes->lock_gpio);
380 SERDES_DBG_CHIP("serdes %s:val=%d\n", __func__, val);
381 return val;
382 }
383
384 if (serdes_reg_read(serdes, 0x002a, &val)) {
385 SERDES_DBG_CHIP("serdes %s: false val=%d\n", __func__, val);
386 return false;
387 }
388
389 if (!FIELD_GET(LOCKED, val)) {
390 SERDES_DBG_CHIP("serdes %s: false val=%d\n", __func__, val);
391 return false;
392 }
393
394 return true;
395 }
396
max96745_bridge_detect(struct serdes * serdes,int link)397 static bool max96745_bridge_detect(struct serdes *serdes, int link)
398 {
399 if (link == LINKA)
400 return max96745_bridge_linka_locked(serdes);
401 else
402 return max96745_bridge_linkb_locked(serdes);
403 }
404
max96745_bridge_enable(struct serdes * serdes)405 static int max96745_bridge_enable(struct serdes *serdes)
406 {
407 struct drm_display_mode *mode =
408 &serdes->serdes_bridge->bridge->state->conn_state.mode;
409 u8 cxtp, tx_rate;
410 int ret;
411 unsigned int value;
412
413 ret = serdes_reg_read(serdes, 0x0011, &value);
414 if (ret < 0)
415 return ret;
416
417 cxtp = FIELD_GET(CXTP_A, value);
418
419 ret = serdes_reg_read(serdes, 0x0028, &value);
420 if (ret < 0)
421 return ret;
422
423 tx_rate = FIELD_GET(TX_RATE, value);
424
425 if (!cxtp && mode->clock > 95000 && tx_rate == 1) {
426 ret = serdes_set_bits(serdes, 0x0028, TX_RATE,
427 FIELD_PREP(TX_RATE, 2));
428 if (ret < 0)
429 return ret;
430
431 ret = serdes_set_bits(serdes, 0x0029, RESET_ONESHOT,
432 FIELD_PREP(RESET_ONESHOT, 1));
433 if (ret < 0)
434 return ret;
435
436 if (readx_poll_timeout(max96745_bridge_linka_locked, serdes,
437 ret, ret, 200000))
438 printf("%s: GMSL link not locked\n", __func__);
439 }
440
441 return ret;
442 }
443
max96745_bridge_disable(struct serdes * serdes)444 static int max96745_bridge_disable(struct serdes *serdes)
445 {
446 u8 cxtp, tx_rate;
447 int ret;
448 unsigned int value;
449
450 ret = serdes_reg_read(serdes, 0x0011, &value);
451 if (ret < 0)
452 return ret;
453
454 cxtp = FIELD_GET(CXTP_A, value);
455
456 ret = serdes_reg_read(serdes, 0x0028, &value);
457 if (ret < 0)
458 return ret;
459
460 tx_rate = FIELD_GET(TX_RATE, value);
461
462 if (!cxtp && tx_rate == 2) {
463 ret = serdes_set_bits(serdes, 0x0028, TX_RATE,
464 FIELD_PREP(TX_RATE, 1));
465 if (ret < 0)
466 return ret;
467
468 ret = serdes_set_bits(serdes, 0x0029, RESET_ONESHOT,
469 FIELD_PREP(RESET_ONESHOT, 1));
470 if (ret < 0)
471 return ret;
472
473 if (readx_poll_timeout(max96745_bridge_linka_locked, serdes,
474 ret, ret, 200000))
475 printf("%s: GMSL link not locked\n", __func__);
476 }
477
478 return ret;
479 }
480
481 static struct serdes_chip_bridge_ops max96745_bridge_ops = {
482 .detect = max96745_bridge_detect,
483 .enable = max96745_bridge_enable,
484 .disable = max96745_bridge_disable,
485 };
486
max96745_pinctrl_set_pin_mux(struct serdes * serdes,unsigned int pin_selector,unsigned int func_selector)487 static int max96745_pinctrl_set_pin_mux(struct serdes *serdes,
488 unsigned int pin_selector,
489 unsigned int func_selector)
490 {
491 struct function_desc *func;
492 struct pinctrl_pin_desc *pin;
493 int offset;
494 u16 ms;
495
496 func = &serdes->chip_data->pinctrl_info->functions[func_selector];
497 if (!func) {
498 printf("%s: func is null\n", __func__);
499 return -EINVAL;
500 }
501
502 pin = &serdes->chip_data->pinctrl_info->pins[pin_selector];
503 if (!pin) {
504 printf("%s: pin is null\n", __func__);
505 return -EINVAL;
506 }
507
508 SERDES_DBG_CHIP("%s: serdes %s func=%s data=%p pin=%s num=%d\n",
509 __func__, serdes->dev->name,
510 func->name, func->data,
511 pin->name, pin->number);
512
513 if (func->data) {
514 struct serdes_function_data *data = func->data;
515
516 ms = data->mdelay;
517 offset = pin->number;
518 if (offset > 32)
519 dev_err(serdes->dev, "%s offset=%d > 32\n",
520 serdes->dev->name, offset);
521 else
522 SERDES_DBG_CHIP("%s: serdes %s txid=%d rxid=%d off=%d\n",
523 __func__, serdes->dev->name,
524 data->gpio_tx_id, data->gpio_rx_id, offset);
525 if (!ms) {
526 serdes_set_bits(serdes,
527 GPIO_A_REG(offset),
528 GPIO_OUT_DIS,
529 FIELD_PREP(GPIO_OUT_DIS, data->gpio_out_dis));
530 if (data->gpio_tx_en_a || data->gpio_tx_en_b)
531 serdes_set_bits(serdes,
532 GPIO_B_REG(offset),
533 GPIO_TX_ID,
534 FIELD_PREP(GPIO_TX_ID, data->gpio_tx_id));
535 if (data->gpio_rx_en_a || data->gpio_rx_en_b)
536 serdes_set_bits(serdes,
537 GPIO_C_REG(offset),
538 GPIO_RX_ID,
539 FIELD_PREP(GPIO_RX_ID, data->gpio_rx_id));
540 serdes_set_bits(serdes,
541 GPIO_D_REG(offset),
542 GPIO_TX_EN_A | GPIO_TX_EN_B | GPIO_IO_RX_EN |
543 GPIO_RX_EN_A | GPIO_RX_EN_B,
544 FIELD_PREP(GPIO_TX_EN_A, data->gpio_tx_en_a) |
545 FIELD_PREP(GPIO_TX_EN_B, data->gpio_tx_en_b) |
546 FIELD_PREP(GPIO_RX_EN_A, data->gpio_rx_en_a) |
547 FIELD_PREP(GPIO_RX_EN_B, data->gpio_rx_en_b) |
548 FIELD_PREP(GPIO_IO_RX_EN, data->gpio_io_rx_en));
549 } else {
550 mdelay(ms);
551 SERDES_DBG_CHIP("%s: delay %dms\n", __func__, ms);
552 }
553 }
554
555 return 0;
556 }
557
max96745_pinctrl_set_grp_mux(struct serdes * serdes,unsigned int group_selector,unsigned int func_selector)558 static int max96745_pinctrl_set_grp_mux(struct serdes *serdes,
559 unsigned int group_selector,
560 unsigned int func_selector)
561 {
562 struct serdes_pinctrl *pinctrl = serdes->serdes_pinctrl;
563 struct function_desc *func;
564 struct group_desc *grp;
565 int i, offset;
566
567 func = &serdes->chip_data->pinctrl_info->functions[func_selector];
568 if (!func) {
569 printf("%s: func is null\n", __func__);
570 return -EINVAL;
571 }
572
573 grp = &serdes->chip_data->pinctrl_info->groups[group_selector];
574 if (!grp) {
575 printf("%s: grp is null\n", __func__);
576 return -EINVAL;
577 }
578
579 SERDES_DBG_CHIP("%s: serdes %s func=%s data=%p grp=%s data=%p, num=%d\n",
580 __func__, serdes->chip_data->name, func->name,
581 func->data, grp->name, grp->data, grp->num_pins);
582
583 if (func->data) {
584 struct serdes_function_data *fdata = func->data;
585
586 for (i = 0; i < grp->num_pins; i++) {
587 offset = grp->pins[i] - pinctrl->pin_base;
588 if (offset > 32)
589 dev_err(serdes->dev, "%s offset=%d > 32\n",
590 serdes->dev->name, offset);
591 else
592 SERDES_DBG_CHIP("%s: serdes %s txid=%d rxid=%d off=%d\n",
593 __func__, serdes->dev->name,
594 fdata->gpio_tx_id,
595 fdata->gpio_rx_id, offset);
596
597 serdes_set_bits(serdes,
598 GPIO_A_REG(offset),
599 GPIO_OUT_DIS,
600 FIELD_PREP(GPIO_OUT_DIS, fdata->gpio_out_dis));
601 if (fdata->gpio_tx_en_a || fdata->gpio_tx_en_b)
602 serdes_set_bits(serdes,
603 GPIO_B_REG(offset),
604 GPIO_TX_ID,
605 FIELD_PREP(GPIO_TX_ID, fdata->gpio_tx_id));
606 if (fdata->gpio_rx_en_a || fdata->gpio_rx_en_b)
607 serdes_set_bits(serdes,
608 GPIO_C_REG(offset),
609 GPIO_RX_ID,
610 FIELD_PREP(GPIO_RX_ID, fdata->gpio_rx_id));
611 serdes_set_bits(serdes,
612 GPIO_D_REG(offset),
613 GPIO_TX_EN_A | GPIO_TX_EN_B | GPIO_IO_RX_EN |
614 GPIO_RX_EN_A | GPIO_RX_EN_B,
615 FIELD_PREP(GPIO_TX_EN_A, fdata->gpio_tx_en_a) |
616 FIELD_PREP(GPIO_TX_EN_B, fdata->gpio_tx_en_b) |
617 FIELD_PREP(GPIO_RX_EN_A, fdata->gpio_rx_en_a) |
618 FIELD_PREP(GPIO_RX_EN_B, fdata->gpio_rx_en_b) |
619 FIELD_PREP(GPIO_IO_RX_EN, fdata->gpio_io_rx_en));
620 }
621 }
622
623 return 0;
624 }
625
max96745_pinctrl_config_set(struct serdes * serdes,unsigned int pin_selector,unsigned int param,unsigned int argument)626 static int max96745_pinctrl_config_set(struct serdes *serdes,
627 unsigned int pin_selector,
628 unsigned int param,
629 unsigned int argument)
630 {
631 u8 res_cfg;
632
633 switch (param) {
634 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
635 serdes_set_bits(serdes, GPIO_B_REG(pin_selector),
636 OUT_TYPE, FIELD_PREP(OUT_TYPE, 0));
637 break;
638 case PIN_CONFIG_DRIVE_PUSH_PULL:
639 serdes_set_bits(serdes, GPIO_B_REG(pin_selector),
640 OUT_TYPE, FIELD_PREP(OUT_TYPE, 1));
641 break;
642 case PIN_CONFIG_BIAS_DISABLE:
643 serdes_set_bits(serdes, GPIO_C_REG(pin_selector),
644 PULL_UPDN_SEL,
645 FIELD_PREP(PULL_UPDN_SEL, 0));
646 break;
647 case PIN_CONFIG_BIAS_PULL_UP:
648 switch (argument) {
649 case 40000:
650 res_cfg = 0;
651 break;
652 case 1000000:
653 res_cfg = 1;
654 break;
655 default:
656 return -EINVAL;
657 }
658
659 serdes_set_bits(serdes, GPIO_A_REG(pin_selector),
660 RES_CFG, FIELD_PREP(RES_CFG, res_cfg));
661 serdes_set_bits(serdes, GPIO_C_REG(pin_selector),
662 PULL_UPDN_SEL,
663 FIELD_PREP(PULL_UPDN_SEL, 1));
664 break;
665 case PIN_CONFIG_BIAS_PULL_DOWN:
666 switch (argument) {
667 case 40000:
668 res_cfg = 0;
669 break;
670 case 1000000:
671 res_cfg = 1;
672 break;
673 default:
674 return -EINVAL;
675 }
676
677 serdes_set_bits(serdes, GPIO_A_REG(pin_selector),
678 RES_CFG, FIELD_PREP(RES_CFG, res_cfg));
679 serdes_set_bits(serdes, GPIO_C_REG(pin_selector),
680 PULL_UPDN_SEL,
681 FIELD_PREP(PULL_UPDN_SEL, 2));
682 break;
683 case PIN_CONFIG_OUTPUT:
684 serdes_set_bits(serdes, GPIO_A_REG(pin_selector),
685 GPIO_OUT_DIS | GPIO_OUT,
686 FIELD_PREP(GPIO_OUT_DIS, 0) |
687 FIELD_PREP(GPIO_OUT, argument));
688 break;
689 default:
690 return -EOPNOTSUPP;
691 }
692
693 return 0;
694 }
695
696 static struct serdes_chip_pinctrl_ops max96745_pinctrl_ops = {
697 .pinconf_set = max96745_pinctrl_config_set,
698 .pinmux_set = max96745_pinctrl_set_pin_mux,
699 .pinmux_group_set = max96745_pinctrl_set_grp_mux,
700 };
701
max96745_gpio_direction_input(struct serdes * serdes,int gpio)702 static int max96745_gpio_direction_input(struct serdes *serdes, int gpio)
703 {
704 return 0;
705 }
706
max96745_gpio_direction_output(struct serdes * serdes,int gpio,int value)707 static int max96745_gpio_direction_output(struct serdes *serdes, int gpio, int value)
708 {
709 return 0;
710 }
711
max96745_gpio_get_level(struct serdes * serdes,int gpio)712 static int max96745_gpio_get_level(struct serdes *serdes, int gpio)
713 {
714 return 0;
715 }
716
max96745_gpio_set_level(struct serdes * serdes,int gpio,int value)717 static int max96745_gpio_set_level(struct serdes *serdes, int gpio, int value)
718 {
719 return 0;
720 }
721
max96745_gpio_set_config(struct serdes * serdes,int gpio,unsigned long config)722 static int max96745_gpio_set_config(struct serdes *serdes,
723 int gpio, unsigned long config)
724 {
725 return 0;
726 }
727
max96745_gpio_to_irq(struct serdes * serdes,int gpio)728 static int max96745_gpio_to_irq(struct serdes *serdes, int gpio)
729 {
730 return 0;
731 }
732
733 static struct serdes_chip_gpio_ops max96745_gpio_ops = {
734 .direction_input = max96745_gpio_direction_input,
735 .direction_output = max96745_gpio_direction_output,
736 .get_level = max96745_gpio_get_level,
737 .set_level = max96745_gpio_set_level,
738 .set_config = max96745_gpio_set_config,
739 .to_irq = max96745_gpio_to_irq,
740 };
741
max96745_select(struct serdes * serdes,int chan)742 static int max96745_select(struct serdes *serdes, int chan)
743 {
744 /*0076 for linkA and 0086 for linkB*/
745 if (chan == DUAL_LINK) {
746 serdes_set_bits(serdes, 0x0076, DIS_REM_CC,
747 FIELD_PREP(DIS_REM_CC, 0));
748 serdes_set_bits(serdes, 0x0086, DIS_REM_CC,
749 FIELD_PREP(DIS_REM_CC, 0));
750 SERDES_DBG_CHIP("%s: enable %s remote i2c of linkA/linkB\n",
751 __func__,
752 serdes->chip_data->name);
753 } else if (chan == LINKA) {
754 serdes_set_bits(serdes, 0x0076, DIS_REM_CC,
755 FIELD_PREP(DIS_REM_CC, 0));
756 serdes_set_bits(serdes, 0x0086, DIS_REM_CC,
757 FIELD_PREP(DIS_REM_CC, 1));
758 SERDES_DBG_CHIP("%s: only enable %s remote i2c of linkA\n",
759 __func__,
760 serdes->chip_data->name);
761 } else if (chan == LINKB) {
762 serdes_set_bits(serdes, 0x0076, DIS_REM_CC,
763 FIELD_PREP(DIS_REM_CC, 1));
764 serdes_set_bits(serdes, 0x0086, DIS_REM_CC,
765 FIELD_PREP(DIS_REM_CC, 0));
766 SERDES_DBG_CHIP("%s: only enable %s remote i2c of linkB\n",
767 __func__,
768 serdes->chip_data->name);
769 } else if (chan == SPLITTER_MODE) {
770 serdes_set_bits(serdes, 0x0076, DIS_REM_CC,
771 FIELD_PREP(DIS_REM_CC, 0));
772 serdes_set_bits(serdes, 0x0086, DIS_REM_CC,
773 FIELD_PREP(DIS_REM_CC, 0));
774 SERDES_DBG_CHIP("%s: enable %s remote i2c of linkA/B\n",
775 __func__,
776 serdes->chip_data->name);
777 }
778
779 return 0;
780 }
781
max96745_deselect(struct serdes * serdes,int chan)782 static int max96745_deselect(struct serdes *serdes, int chan)
783 {
784 if (chan == DUAL_LINK) {
785 serdes_set_bits(serdes, 0x0076, DIS_REM_CC,
786 FIELD_PREP(DIS_REM_CC, 1));
787 serdes_set_bits(serdes, 0x0086, DIS_REM_CC,
788 FIELD_PREP(DIS_REM_CC, 1));
789 SERDES_DBG_CHIP("%s: disable %s remote i2c of linkA/B\n",
790 __func__,
791 serdes->chip_data->name);
792 } else if (chan == LINKA) {
793 serdes_set_bits(serdes, 0x0076, DIS_REM_CC,
794 FIELD_PREP(DIS_REM_CC, 1));
795 serdes_set_bits(serdes, 0x0086, DIS_REM_CC,
796 FIELD_PREP(DIS_REM_CC, 0));
797 SERDES_DBG_CHIP("%s: only disable %s remote i2c of linkA\n",
798 __func__,
799 serdes->chip_data->name);
800 } else if (chan == LINKB) {
801 serdes_set_bits(serdes, 0x0076, DIS_REM_CC,
802 FIELD_PREP(DIS_REM_CC, 0));
803 serdes_set_bits(serdes, 0x0086, DIS_REM_CC,
804 FIELD_PREP(DIS_REM_CC, 1));
805 SERDES_DBG_CHIP("%s: only disable %s remote i2c of linkB\n",
806 __func__,
807 serdes->chip_data->name);
808 } else if (chan == SPLITTER_MODE) {
809 serdes_set_bits(serdes, 0x0076, DIS_REM_CC,
810 FIELD_PREP(DIS_REM_CC, 1));
811 serdes_set_bits(serdes, 0x0086, DIS_REM_CC,
812 FIELD_PREP(DIS_REM_CC, 1));
813 SERDES_DBG_CHIP("%s: disable %s remote i2c of linkA/B\n",
814 __func__,
815 serdes->chip_data->name);
816 }
817
818 return 0;
819 }
820
821 static struct serdes_chip_split_ops max96745_split_ops = {
822 .select = max96745_select,
823 .deselect = max96745_deselect,
824 };
825
826 struct serdes_chip_data serdes_max96745_data = {
827 .name = "max96745",
828 .serdes_type = TYPE_SER,
829 .serdes_id = MAXIM_ID_MAX96745,
830 .connector_type = DRM_MODE_CONNECTOR_eDP,
831 .pinctrl_info = &max96745_pinctrl_info,
832 .bridge_ops = &max96745_bridge_ops,
833 .pinctrl_ops = &max96745_pinctrl_ops,
834 .gpio_ops = &max96745_gpio_ops,
835 .split_ops = &max96745_split_ops,
836 };
837 EXPORT_SYMBOL_GPL(serdes_max96745_data);
838
839 MODULE_LICENSE("GPL");
840