1 /*
2 * Driver for Rockchip Smart Card Reader Controller
3 *
4 * Copyright (C) 2012-2016 ROCKCHIP, Inc.
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16 #include <linux/list.h>
17 #include <linux/kernel.h>
18 #include <linux/clk.h>
19 #include <linux/io.h>
20 #include <linux/module.h>
21 #include <linux/of.h>
22 #include <linux/of_device.h>
23 #include <linux/platform_device.h>
24 #include <linux/time.h>
25 #include <linux/delay.h>
26 #include <linux/interrupt.h>
27 #include <linux/slab.h>
28 #include <linux/kobject.h>
29 #include <linux/sysfs.h>
30 #include <linux/kthread.h>
31
32 #include "rk_scr.h"
33
34 #undef DEBUG_RK_SCR
35 #define DEBUG_RK_SCR 1
36
37 #if DEBUG_RK_SCR
38 #define DAL_LOGV(x...) pr_info("RK_SCR: "x)
39 #else
40 #define DAL_LOGV(x...) do { } while (0)
41 #endif
42
43 #define SMC_DEFAULT_TIMEOUT 2000 /*ms*/
44 #define SMC_RECEIVE_BUF_LEN (64 * 1024)
45
46 struct rk_scr_device {
47 int irq;
48 struct clk *clk_scr;
49 void __iomem *regs;
50 struct scr_chip_info chip_info[RK_SCR_NUM];
51 struct rk_scr scr[RK_SCR_NUM];
52 struct completion is_done;
53 struct mutex scr_mutex; /* mutex for scr operation */
54 unsigned char *recv_buffer;
55 unsigned recv_data_count;
56 unsigned recv_data_offset;
57 unsigned char atr_buffer[SMC_ATR_MAX_LENGTH];
58 unsigned char atr_length;
59 };
60
61 static struct rk_scr_device *rk_scr;
62
to_rk_scr(int id)63 static struct rk_scr *to_rk_scr(int id)
64 {
65 if (id < RK_SCR_NUM)
66 return &rk_scr->scr[id];
67
68 return NULL;
69 }
70
to_opened_rk_scr(int id)71 static struct rk_scr *to_opened_rk_scr(int id)
72 {
73 struct rk_scr *scr;
74
75 scr = to_rk_scr(id);
76
77 if (scr && scr->is_open)
78 return scr;
79
80 return NULL;
81 }
82
rk_scr_deactive(struct rk_scr * scr)83 static void rk_scr_deactive(struct rk_scr *scr)
84 {
85 struct scr_reg_t *scr_reg = scr->hw->reg_base;
86
87 DAL_LOGV("Deactive card\n");
88 scr_reg->CTRL2 |= DEACT;
89 scr_reg->CTRL1 = 0;
90 scr->is_active = false;
91 }
92
rk_scr_set_clk(struct rk_scr * scr)93 static void rk_scr_set_clk(struct rk_scr *scr)
94 {
95 struct scr_reg_t *scr_reg = scr->hw->reg_base;
96 unsigned int freq_mhz;
97
98 freq_mhz = clk_get_rate(scr->clk) / 1000 / 1000;
99 DAL_LOGV("freq_mhz = %d\n", freq_mhz);
100 scr_reg->CGSCDIV = ((2 * freq_mhz / 13 - 1)
101 + (freq_mhz / 8 - 1) + 1) / 2;
102 DAL_LOGV("scr_reg->CGSCDIV = %d\n", scr_reg->CGSCDIV);
103 }
104
rk_scr_set_work_waitingtime(struct rk_scr * scr,unsigned char wi)105 static void rk_scr_set_work_waitingtime(struct rk_scr *scr,
106 unsigned char wi)
107 {
108 struct scr_reg_t *scr_reg = scr->hw->reg_base;
109 unsigned int wt;
110
111 DAL_LOGV("WI: %d\n", wi);
112 wt = 960 * wi * scr->D;
113 scr_reg->C2CLIM = (wt > 0x0FFFF) ? 0x0FFFF : wt;
114 }
115
rk_scr_set_etu_duration(struct rk_scr * scr,unsigned int F,unsigned int D)116 static void rk_scr_set_etu_duration(struct rk_scr *scr, unsigned int F,
117 unsigned int D)
118 {
119 struct scr_reg_t *scr_reg = scr->hw->reg_base;
120
121 DAL_LOGV("Set Etu F: %d D: %d\n", F, D);
122
123 scr->F = F;
124 scr->D = D;
125 scr_reg->CGBITDIV = (scr_reg->CGSCDIV + 1) * (F / D) - 1;
126 DAL_LOGV("scr_reg->CGBITDIV = %d\n", scr_reg->CGBITDIV);
127 scr_reg->CGBITTUNE = 0;
128
129 rk_scr_set_work_waitingtime(scr, 10);
130 }
131
rk_scr_set_scr_voltage(struct rk_scr * scr,enum hal_scr_voltage_e level)132 static void rk_scr_set_scr_voltage(struct rk_scr *scr,
133 enum hal_scr_voltage_e level)
134 {
135 struct scr_reg_t *scr_reg = scr->hw->reg_base;
136
137 scr_reg->CTRL2 = 0;
138
139 switch (level) {
140 case HAL_SCR_VOLTAGE_CLASS_A:
141 scr_reg->CTRL2 |= VCC50;
142 break;
143
144 case HAL_SCR_VOLTAGE_CLASS_B:
145 scr_reg->CTRL2 |= VCC33;
146 break;
147
148 case HAL_SCR_VOLTAGE_CLASS_C:
149 scr_reg->CTRL2 |= VCC18;
150 break;
151
152 case HAL_SCR_VOLTAGE_NULL:
153 break;
154 }
155 }
156
rk_scr_powerdown(struct rk_scr * scr)157 static void rk_scr_powerdown(struct rk_scr *scr)
158 {
159 rk_scr_set_scr_voltage(scr, HAL_SCR_VOLTAGE_NULL);
160 }
161
rk_scr_set_clockstop_mode(struct rk_scr * scr,enum hal_scr_clock_stop_mode_e mode)162 static void rk_scr_set_clockstop_mode(struct rk_scr *scr,
163 enum hal_scr_clock_stop_mode_e mode)
164 {
165 struct scr_reg_t *scr_reg = scr->hw->reg_base;
166
167 if (mode == HAL_SCR_CLOCK_STOP_L)
168 scr_reg->CTRL1 &= ~CLKSTOPVAL;
169 else if (mode == HAL_SCR_CLOCK_STOP_H)
170 scr_reg->CTRL1 |= CLKSTOPVAL;
171 }
172
rk_scr_clock_start(struct rk_scr * scr)173 static void rk_scr_clock_start(struct rk_scr *scr)
174 {
175 struct scr_reg_t *scr_reg = scr->hw->reg_base;
176 int time_out = 10000;
177
178 #ifdef SCR_DEBUG
179 scr_reg->INTEN1 = CLKSTOPRUN;
180 #endif
181 scr_reg->CTRL1 &= ~CLKSTOP;
182 #ifdef SCR_DEBUG
183 if (scr_reg->CTRL1 & CLKSTOP)
184 DAL_LOGV("Before clock is Stopped\n");
185 else
186 DAL_LOGV("Before clock is running\n");
187 #endif
188 while ((scr_reg->CTRL1 & CLKSTOP) && (time_out-- > 0))
189 usleep_range(100, 110);
190 }
191
rk_scr_clock_stop(struct rk_scr * scr)192 static void rk_scr_clock_stop(struct rk_scr *scr)
193 {
194 struct scr_reg_t *scr_reg = scr->hw->reg_base;
195 int time_out = 10000;
196
197 #ifdef SCR_DEBUG
198 scr_reg->INTEN1 = CLKSTOPRUN;
199 #endif
200 scr_reg->CTRL1 |= CLKSTOP;
201 DAL_LOGV("Stop Clock\n");
202 if (scr->is_active) {
203 while ((!(scr_reg->CTRL1 & CLKSTOP)) && (time_out-- > 0))
204 usleep_range(100, 110);
205 }
206 }
207
rk_scr_reset(struct rk_scr * scr,unsigned char * rx_buffer)208 static void rk_scr_reset(struct rk_scr *scr, unsigned char *rx_buffer)
209 {
210 struct scr_reg_t *scr_reg = scr->hw->reg_base;
211
212 if (!rx_buffer)
213 DAL_LOGV("_scr_reset: invalid argument\n");
214
215 /*
216 * must disable all SCR interrupts.
217 * It will protect the global data.
218 */
219 scr_reg->INTEN1 = 0;
220
221 scr->rx_buf = rx_buffer;
222 scr->rx_expected = 0xff;
223 scr->rx_cnt = 0;
224
225 /*
226 * must in the critical section. If we don't, when we have written CTRL2
227 * before enable expected interrupts, other interrupts occurred,
228 * we may miss expected interrupts.
229 */
230 if (scr->is_active) {
231 DAL_LOGV("Warm Reset\n");
232 scr_reg->CTRL2 |= WARMRST;
233 } else {
234 DAL_LOGV("Active & Cold Reset\n");
235 scr->is_active = true;
236 scr_reg->CTRL1 = TXEN | RXEN | TS2FIFO | ATRSTFLUSH | GINTEN;
237 scr_reg->CTRL2 |= ACT;
238 }
239
240 /*
241 * If we enable the interrupts before write CTRL2, we may get
242 * expected interrupts which belong to the last transfer not
243 * for the reset.This may damage the global data.
244 */
245 scr_reg->RXFIFOTH = MAX_RXTHR;
246 scr_reg->TXFIFOTH = MAX_TXTHR;
247 scr_reg->INTEN1 = RXTHRESHOLD | RXFIFULL | RXPERR |
248 C2CFULL | ATRFAIL | ATRDONE;
249 DAL_LOGV("Start Rx\n");
250 }
251
rk_scr_write_bytes(struct rk_scr * scr)252 static void rk_scr_write_bytes(struct rk_scr *scr)
253 {
254 struct scr_reg_t *scr_reg = scr->hw->reg_base;
255 int count = FIFO_DEPTH - scr_reg->TXFIFOCNT;
256 int remainder = scr->tx_expected - scr->tx_cnt;
257 int i = 0;
258
259 if (remainder < count)
260 count = remainder;
261
262 while (i++ < count)
263 scr_reg->FIFODATA = scr->tx_buf[scr->tx_cnt++];
264 }
265
rk_scr_read_bytes(struct rk_scr * scr)266 static void rk_scr_read_bytes(struct rk_scr *scr)
267 {
268 struct scr_reg_t *scr_reg = scr->hw->reg_base;
269 int count = scr_reg->RXFIFOCNT;
270 int remainder = scr->rx_expected - scr->rx_cnt;
271 int i = 0;
272
273 if (remainder < count)
274 count = remainder;
275
276 while (i++ < count)
277 scr->rx_buf[scr->rx_cnt++] = (unsigned char)scr_reg->FIFODATA;
278 }
279
rk_scr_irqhandler(int irq,void * priv)280 static irqreturn_t rk_scr_irqhandler(int irq, void *priv)
281 {
282 struct rk_scr *scr = (struct rk_scr *)priv;
283 struct scr_reg_t *scr_reg = scr->hw->reg_base;
284 enum hal_scr_irq_cause_e user_cause = HAL_SCR_IRQ_INVALID;
285 unsigned int stat;
286
287 stat = (unsigned int)scr_reg->INTSTAT1;
288 if (!stat)
289 return 0;
290
291 if (stat & TXFIEMPTY) {
292 scr_reg->INTSTAT1 |= TXFIEMPTY;
293
294 /* during this period, TXFIEMPTY may occurred. */
295 rk_scr_write_bytes(scr);
296
297 if (scr->tx_cnt == scr->tx_expected) {
298 scr_reg->INTEN1 &= ~TXFIEMPTY;
299 scr_reg->INTSTAT1 |= TXFIEMPTY;
300 }
301 }
302 #ifdef SCR_DEBUG
303 else if (stat & CLKSTOPRUN) {
304 scr_reg->INTSTAT1 |= CLKSTOPRUN;
305
306 if (scr_reg->CTRL1 & CLKSTOP)
307 DAL_LOGV("Clock is stopped\n");
308 else
309 DAL_LOGV("Clock is started\n");
310 }
311 #endif
312 else if ((stat & RXTHRESHOLD) || (stat & RXFIFULL)) {
313 unsigned int threshold;
314
315 scr_reg->INTEN1 &= ~RXTHRESHOLD;
316 scr_reg->INTSTAT1 |= RXTHRESHOLD | RXFIFULL;
317
318 if (scr->rx_cnt < scr->rx_expected) {
319 rk_scr_read_bytes(scr);
320 if (scr->rx_cnt < scr->rx_expected) {
321 unsigned int remainder =
322 scr->rx_expected - scr->rx_cnt;
323
324 threshold = (remainder < MAX_RXTHR)
325 ? remainder : MAX_RXTHR;
326 } else {
327 scr_reg->INTEN1 &= ~C2CFULL;
328 threshold = 1;
329 if (scr->user_mask.rx_success)
330 user_cause = HAL_SCR_RX_SUCCESS;
331 }
332 } else {
333 threshold = 1;
334 scr->rx_buf[scr->rx_cnt++] =
335 (unsigned char)scr_reg->FIFODATA;
336 if (scr->user_mask.extra_rx)
337 user_cause = HAL_SCR_EXTRA_RX;
338 }
339 scr_reg->INTEN1 |= RXTHRESHOLD;
340 /*
341 * when RX FIFO now is FULL,
342 * that will not generate RXTHRESHOLD interrupt.
343 * But it will generate RXFIFULL interrupt.
344 */
345 scr_reg->RXFIFOTH = FIFO_DEPTH;
346 scr_reg->RXFIFOTH = threshold;
347 } else if (stat & ATRDONE) {
348 DAL_LOGV("ATR Done\n");
349 scr_reg->INTSTAT1 |= ATRDONE;
350 scr_reg->INTEN1 = 0;
351 rk_scr_read_bytes(scr);
352 if (scr->user_mask.atr_success)
353 user_cause = HAL_SCR_ATR_SUCCESS;
354 } else if (stat & ATRFAIL) {
355 DAL_LOGV("ATR Fail\n");
356
357 scr_reg->INTSTAT1 |= ATRFAIL;
358 scr_reg->INTEN1 = 0;
359
360 if (scr->user_mask.reset_timeout)
361 user_cause = HAL_SCR_RESET_TIMEOUT;
362 } else if (stat & TXPERR) {
363 DAL_LOGV("TXPERR\n");
364
365 scr_reg->INTSTAT1 |= TXPERR;
366 scr_reg->INTEN1 = 0;
367
368 if (scr->user_mask.parity_error)
369 user_cause = HAL_SCR_PARITY_ERROR;
370 } else if (stat & RXPERR) {
371 DAL_LOGV("RXPERR\n");
372 scr_reg->INTSTAT1 |= RXPERR;
373 scr_reg->INTEN1 = 0;
374 rk_scr_read_bytes(scr);
375 if (scr->user_mask.parity_error)
376 user_cause = HAL_SCR_PARITY_ERROR;
377 } else if (stat & C2CFULL) {
378 DAL_LOGV("Timeout\n");
379 scr_reg->INTSTAT1 |= C2CFULL;
380 scr_reg->INTEN1 = 0;
381 rk_scr_read_bytes(scr);
382
383 if (scr->user_mask.wwt_timeout)
384 user_cause = HAL_SCR_WWT_TIMEOUT;
385 }
386
387 if (user_cause != HAL_SCR_IRQ_INVALID) {
388 scr->in_process = false;
389 if (scr->user_handler)
390 scr->user_handler(user_cause);
391 }
392 return 0;
393 }
394
_rk_scr_init(struct rk_scr * scr)395 static void _rk_scr_init(struct rk_scr *scr)
396 {
397 struct scr_reg_t *scr_reg = scr->hw->reg_base;
398
399 rk_scr_deactive(scr);
400 rk_scr_set_clk(scr);
401 rk_scr_set_etu_duration(scr, 372, 1);
402
403 /* TXREPEAT = 3 & RXREPEAT = 3 */
404 scr_reg->REPEAT = 0x33;
405
406 /*
407 * Character LeadEdge to Character LeadEdge minimum waiting time
408 * in terms of ETUs. (GT)
409 */
410 scr_reg->SCGT = 12;
411
412 /*
413 * Character LeadEdge to Character LeadEdge maximum waiting time
414 * in terms of ETUs. (WT)
415 */
416 scr_reg->C2CLIM = 9600;
417
418 /*
419 * If no Vpp is necessary, the activation and deactivation part of Vpp
420 * can be omitted by clearing the AUTOADEAVPP bit in SCPADS register.
421 */
422 scr_reg->SCPADS = 0;
423
424 /*
425 * Activation / deactivation step time
426 * in terms of SmartCard Clock Cycles
427 */
428 scr_reg->ADEATIME = 0;
429
430 /*
431 * Duration of low state during Smart Card reset sequence
432 * in terms of smart card clock cycles
433 * require >
434 */
435 scr_reg->LOWRSTTIME = 1000;
436
437 /*
438 * ATR start limit - in terms of SmartCard Clock Cycles
439 * require 400 ~ 40000
440 */
441 scr_reg->ATRSTARTLIMIT = 40000;
442
443 /* enable the detect interrupt */
444 scr_reg->INTEN1 = SCINS;
445 scr_reg->INTEN2 = 0;
446
447 scr_reg->INTSTAT1 = 0xffff;
448 scr_reg->INTSTAT2 = 0xffff;
449
450 scr_reg->FIFOCTRL = FC_TXFIFLUSH | FC_RXFIFLUSH;
451 scr_reg->TXFIFOTH = 0;
452 scr_reg->RXFIFOTH = 0;
453
454 scr_reg->CTRL1 = 0;
455 scr_reg->CTRL2 = 0;
456 }
457
_rk_scr_deinit(struct rk_scr * scr)458 static void _rk_scr_deinit(struct rk_scr *scr)
459 {
460 struct scr_reg_t *scr_reg = scr->hw->reg_base;
461
462 /* disable all interrupt */
463 scr_reg->INTEN1 = 0;
464 scr_reg->INTEN2 = 0;
465
466 rk_scr_deactive(scr);
467 rk_scr_powerdown(scr);
468 }
469
rk_scr_freqchanged_notifiy(struct notifier_block * nb,unsigned long action,void * data,int len)470 int rk_scr_freqchanged_notifiy(struct notifier_block *nb,
471 unsigned long action, void *data, int len)
472 {
473 int idx;
474 struct rk_scr *scr = NULL;
475 /*alter by xieshufa not sure*/
476 struct clk_notifier_data *msg;
477
478 switch (action) {
479 /*case ABORT_RATE_CHANGE:*/
480 case POST_RATE_CHANGE:
481 break;
482 default:
483 return 0;
484 }
485
486 msg = data;
487 for (idx = 0; idx < RK_SCR_NUM; idx++) {
488 struct rk_scr *p = to_rk_scr(idx);
489
490 if (msg->clk == p->clk) {
491 scr = p;
492 break;
493 }
494 }
495
496 if (scr) {
497 rk_scr_set_clk(scr);
498 rk_scr_set_etu_duration(scr, scr->F, scr->D);
499 }
500
501 return 0;
502 }
503
rk_scr_open(int id)504 static int rk_scr_open(int id)
505 {
506 struct rk_scr_device *rk_scr_dev = rk_scr;
507 struct rk_scr *scr = to_rk_scr(id);
508 struct hal_scr_irq_status_t
509 default_scr_user_mask = {1, 1, 1, 1, 1, 1, 1, 1};
510 int result = 0;
511
512 if (!scr)
513 return -1;
514
515 rk_scr_dev->chip_info[id].reg_base = rk_scr_dev->regs;
516 rk_scr_dev->chip_info[id].irq = rk_scr_dev->irq;
517
518 scr->hw = &rk_scr_dev->chip_info[id];
519 scr->clk = rk_scr_dev->clk_scr;
520
521 result = clk_prepare_enable(scr->clk);
522 DAL_LOGV("scr clk_enable result = %d\n", result);
523
524 (&scr->freq_changed_notifier)->priority = 0;
525 clk_notifier_register(scr->clk, &scr->freq_changed_notifier);
526 scr->user_mask = default_scr_user_mask;
527
528 _rk_scr_init(scr);
529
530 scr->is_open = true;
531
532 return 0;
533 }
534
rk_scr_close(int id)535 static void rk_scr_close(int id)
536 {
537 struct rk_scr *scr;
538
539 scr = to_opened_rk_scr(id);
540 if (!scr)
541 return;
542
543 scr->is_open = false;
544
545 _rk_scr_deinit(scr);
546
547 if (scr->clk) {
548 clk_disable(scr->clk);
549 clk_notifier_unregister(scr->clk, &scr->freq_changed_notifier);
550 }
551 }
552
rk_scr_read(int id,unsigned int n_rx_byte,unsigned char * p_rx_byte)553 static int rk_scr_read(int id, unsigned int n_rx_byte,
554 unsigned char *p_rx_byte)
555 {
556 struct rk_scr *scr;
557 struct scr_reg_t *scr_reg;
558 unsigned int inten1 = 0;
559
560 scr = to_opened_rk_scr(id);
561 if (!scr)
562 return -1;
563
564 if (!((n_rx_byte != 0) && (p_rx_byte))) {
565 DAL_LOGV("rk_scr_read: invalid argument\n");
566 return -1;
567 }
568
569 scr_reg = scr->hw->reg_base;
570
571 /*
572 * must disable all SCR interrupts.
573 * It will protect the global data.
574 */
575 scr_reg->INTEN1 = 0;
576
577 scr->rx_buf = p_rx_byte;
578 scr->rx_expected = n_rx_byte;
579 scr->rx_cnt = 0;
580
581 scr_reg->RXFIFOTH = (scr->rx_expected < MAX_RXTHR)
582 ? scr->rx_expected : MAX_RXTHR;
583 inten1 = RXTHRESHOLD | RXFIFULL | RXPERR | C2CFULL;
584
585 scr_reg->INTEN1 = inten1;
586
587 return 0;
588 }
589
rk_scr_write(int id,unsigned int n_tx_byte,const unsigned char * p_tx_byte)590 static int rk_scr_write(int id, unsigned int n_tx_byte,
591 const unsigned char *p_tx_byte)
592 {
593 struct rk_scr *scr;
594 struct scr_reg_t *scr_reg;
595 unsigned int inten1 = 0;
596 unsigned timeout_count = 1500;
597 unsigned long udelay = 0;
598
599 timeout_count = 1500;
600 udelay = msecs_to_jiffies(timeout_count) + jiffies;
601
602 scr = to_opened_rk_scr(id);
603 if (!scr)
604 return -1;
605
606 if (!((n_tx_byte != 0) && (p_tx_byte))) {
607 DAL_LOGV("rk_scr_write: invalid argument\n");
608 return -1;
609 }
610
611 scr_reg = scr->hw->reg_base;
612
613 /*
614 * must disable all SCR interrupts.
615 * It will protect the global data.
616 */
617 scr_reg->INTEN1 = 0;
618
619 scr->tx_buf = p_tx_byte;
620 scr->tx_expected = n_tx_byte;
621 scr->tx_cnt = 0;
622
623 scr_reg->FIFOCTRL = FC_TXFIFLUSH | FC_RXFIFLUSH;
624
625 /* send data until FIFO full or send over. */
626 while ((scr->tx_cnt < scr->tx_expected) &&
627 (time_before(jiffies, udelay))) {
628 if (!(scr_reg->FIFOCTRL & FC_TXFIFULL))
629 scr_reg->FIFODATA = scr->tx_buf[scr->tx_cnt++];
630 }
631 /* need enable tx interrupt to continue */
632 if (scr->tx_cnt < scr->tx_expected) {
633 pr_err("\n@rk_scr_write: FC_TXFIFULL@\n");
634 inten1 |= TXFIEMPTY | TXPERR;
635 }
636
637 scr_reg->INTEN1 = inten1;
638
639 return 0;
640 }
641
rk_scr_transfer(int id,unsigned int n_tx_byte,unsigned char * p_tx_byte,unsigned int n_rx_byte,unsigned char * p_rx_byte)642 int rk_scr_transfer(int id,
643 unsigned int n_tx_byte, unsigned char *p_tx_byte,
644 unsigned int n_rx_byte, unsigned char *p_rx_byte)
645 {
646 struct rk_scr *scr;
647 struct scr_reg_t *scr_reg;
648 unsigned int inten1;
649
650 scr = to_opened_rk_scr(id);
651 if (!scr)
652 return -1;
653
654 if (!((n_tx_byte != 0) &&
655 (p_tx_byte) &&
656 (n_rx_byte != 0) &&
657 (p_rx_byte))) {
658 DAL_LOGV("rk_scr_transfer: invalid argument\n");
659 return -1;
660 }
661
662 if (scr->in_process)
663 return -1;
664
665 scr->in_process = true;
666 scr_reg = scr->hw->reg_base;
667
668 /*
669 * must disable all SCR interrupts.
670 * It will protect the global data.
671 */
672 scr_reg->INTEN1 = 0;
673 rk_scr_clock_start(scr);
674
675 scr->tx_buf = p_tx_byte;
676 scr->tx_expected = n_tx_byte;
677 scr->tx_cnt = 0;
678
679 scr->rx_buf = p_rx_byte;
680 scr->rx_expected = n_rx_byte;
681 scr->rx_cnt = 0;
682
683 scr_reg->FIFOCTRL = FC_TXFIFLUSH | FC_RXFIFLUSH;
684
685 scr_reg->RXFIFOTH = (scr->rx_expected < MAX_RXTHR)
686 ? scr->rx_expected : MAX_RXTHR;
687 scr_reg->TXFIFOTH = MAX_TXTHR;
688
689 inten1 = RXTHRESHOLD | RXFIFULL | RXPERR | C2CFULL;
690
691 /* send data until FIFO full or send over. */
692 while ((scr->tx_cnt < scr->tx_expected) &&
693 !(scr_reg->FIFOCTRL & FC_TXFIFULL)) {
694 scr_reg->FIFODATA = scr->tx_buf[scr->tx_cnt++];
695 }
696
697 /* need enable tx interrupt to continue */
698 if (scr->tx_cnt < scr->tx_expected)
699 inten1 |= TXFIEMPTY | TXPERR;
700
701 scr_reg->INTEN1 = inten1;
702
703 return 0;
704 }
705
706 static enum hal_scr_id_e g_curr_sur_id = HAL_SCR_ID0;
_scr_init(void)707 void _scr_init(void)
708 {
709 enum hal_scr_id_e id = g_curr_sur_id;
710
711 rk_scr_open(id);
712 }
713
_scr_close(void)714 void _scr_close(void)
715 {
716 enum hal_scr_id_e id = g_curr_sur_id;
717
718 rk_scr_close(id);
719 }
720
_scr_set_voltage(enum hal_scr_voltage_e level)721 bool _scr_set_voltage(enum hal_scr_voltage_e level)
722 {
723 enum hal_scr_id_e id = g_curr_sur_id;
724 struct rk_scr *scr = to_opened_rk_scr(id);
725
726 if (scr) {
727 rk_scr_set_scr_voltage(scr, level);
728 return true;
729 }
730
731 return false;
732 }
733
_scr_reset(unsigned char * rx_bytes)734 void _scr_reset(unsigned char *rx_bytes)
735 {
736 enum hal_scr_id_e id = g_curr_sur_id;
737 struct rk_scr *scr = to_opened_rk_scr(id);
738
739 if (scr)
740 rk_scr_reset(scr, rx_bytes);
741 }
742
_scr_set_etu_duration(unsigned int F,unsigned int D)743 void _scr_set_etu_duration(unsigned int F, unsigned int D)
744 {
745 enum hal_scr_id_e id = g_curr_sur_id;
746 struct rk_scr *scr = to_opened_rk_scr(id);
747
748 if (scr)
749 rk_scr_set_etu_duration(scr, F, D);
750 }
751
_scr_set_clock_stopmode(enum hal_scr_clock_stop_mode_e mode)752 void _scr_set_clock_stopmode(enum hal_scr_clock_stop_mode_e mode)
753 {
754 enum hal_scr_id_e id = g_curr_sur_id;
755 struct rk_scr *scr = to_opened_rk_scr(id);
756
757 if (scr)
758 rk_scr_set_clockstop_mode(scr, mode);
759 }
760
_scr_set_work_waitingtime(unsigned char wi)761 void _scr_set_work_waitingtime(unsigned char wi)
762 {
763 enum hal_scr_id_e id = g_curr_sur_id;
764 struct rk_scr *scr = to_opened_rk_scr(id);
765
766 if (scr)
767 rk_scr_set_work_waitingtime(scr, wi);
768 }
769
_scr_clock_start(void)770 void _scr_clock_start(void)
771 {
772 enum hal_scr_id_e id = g_curr_sur_id;
773 struct rk_scr *scr = to_opened_rk_scr(id);
774
775 if (scr)
776 rk_scr_clock_start(scr);
777 }
778
_scr_clock_stop(void)779 void _scr_clock_stop(void)
780 {
781 enum hal_scr_id_e id = g_curr_sur_id;
782 struct rk_scr *scr = to_opened_rk_scr(id);
783
784 if (scr)
785 rk_scr_clock_stop(scr);
786 }
787
_scr_tx_byte(unsigned int n_tx_byte,const unsigned char * p_tx_byte)788 bool _scr_tx_byte(unsigned int n_tx_byte,
789 const unsigned char *p_tx_byte)
790 {
791 enum hal_scr_id_e id = g_curr_sur_id;
792 int ret = 0;
793
794 ret = rk_scr_write(id, n_tx_byte, p_tx_byte);
795 if (ret)
796 return false;
797 return true;
798 }
799
_scr_rx_byte(unsigned int n_rx_byte,unsigned char * p_rx_byte)800 bool _scr_rx_byte(unsigned int n_rx_byte, unsigned char *p_rx_byte)
801 {
802 enum hal_scr_id_e id = g_curr_sur_id;
803 int ret = 0;
804
805 ret = rk_scr_read(id, n_rx_byte, p_rx_byte);
806 if (ret)
807 return false;
808 return true;
809 }
810
_scr_tx_byte_rx_byte(unsigned int n_tx_byte,unsigned char * p_tx_byte,unsigned int n_rx_byte,unsigned char * p_rx_byte)811 bool _scr_tx_byte_rx_byte(unsigned int n_tx_byte,
812 unsigned char *p_tx_byte,
813 unsigned int n_rx_byte,
814 unsigned char *p_rx_byte)
815 {
816 enum hal_scr_id_e id = g_curr_sur_id;
817 int ret;
818
819 ret = rk_scr_transfer(id, n_tx_byte, p_tx_byte, n_rx_byte, p_rx_byte);
820 if (ret)
821 return false;
822
823 return true;
824 }
825
_scr_get_num_rx_bytes(void)826 unsigned int _scr_get_num_rx_bytes(void)
827 {
828 enum hal_scr_id_e id = g_curr_sur_id;
829 struct rk_scr *scr = to_opened_rk_scr(id);
830
831 if (scr)
832 return scr->rx_cnt;
833
834 return 0;
835 }
836
_scr_get_num_tx_bytes(void)837 unsigned int _scr_get_num_tx_bytes(void)
838 {
839 enum hal_scr_id_e id = g_curr_sur_id;
840 struct rk_scr *scr = to_opened_rk_scr(id);
841
842 if (scr)
843 return scr->tx_cnt;
844
845 return 0;
846 }
847
_scr_powerdown(void)848 void _scr_powerdown(void)
849 {
850 enum hal_scr_id_e id = g_curr_sur_id;
851 struct rk_scr *scr = to_opened_rk_scr(id);
852
853 if (scr)
854 rk_scr_powerdown(scr);
855 }
856
_scr_irq_set_handler(hal_scr_irq_handler_t handler)857 void _scr_irq_set_handler(hal_scr_irq_handler_t handler)
858 {
859 enum hal_scr_id_e id = g_curr_sur_id;
860 struct rk_scr *scr = to_rk_scr(id);
861
862 if (scr)
863 scr->user_handler = handler;
864 }
865
_scr_irq_set_mask(struct hal_scr_irq_status_t mask)866 void _scr_irq_set_mask(struct hal_scr_irq_status_t mask)
867 {
868 enum hal_scr_id_e id = g_curr_sur_id;
869 struct rk_scr *scr = to_rk_scr(id);
870
871 if (scr)
872 scr->user_mask = mask;
873 }
874
_scr_irq_get_mask(void)875 struct hal_scr_irq_status_t _scr_irq_get_mask(void)
876 {
877 enum hal_scr_id_e id = g_curr_sur_id;
878 struct rk_scr *scr = to_rk_scr(id);
879 struct hal_scr_irq_status_t user_mask = {0};
880
881 if (scr)
882 return scr->user_mask;
883
884 return user_mask;
885 }
886
_scr_irq_get_detect_status(void)887 enum hal_scr_detect_status_e _scr_irq_get_detect_status(void)
888 {
889 enum hal_scr_id_e id = g_curr_sur_id;
890 struct rk_scr *scr = to_rk_scr(id);
891
892 if (scr && (scr->hw->reg_base->SCPADS & SCPRESENT)) {
893 DAL_LOGV("\n scr_check_card_insert: yes.\n");
894 return SMC_DRV_INT_CARDIN;
895 }
896
897 DAL_LOGV("\n scr_check_card_insert: no.\n");
898 return SMC_DRV_INT_CARDOUT;
899 }
900
_scr_rx_done(void)901 unsigned char _scr_rx_done(void)
902 {
903 enum hal_scr_id_e id = g_curr_sur_id;
904 struct rk_scr *scr = to_rk_scr(id);
905
906 if (scr->hw->reg_base->INTSTAT1 & RXDONE)
907 return 1;
908 else
909 return 0;
910 }
911
scr_set_etu_duration_struct(int f_and_d)912 void scr_set_etu_duration_struct(int f_and_d)
913 {
914 switch (f_and_d) {
915 case HAL_SCR_ETU_F_372_AND_D_1:
916 _scr_set_etu_duration(372, 1);
917 break;
918 case HAL_SCR_ETU_F_512_AND_D_8:
919 _scr_set_etu_duration(512, 8);
920 break;
921 case HAL_SCR_ETU_F_512_AND_D_4:
922 _scr_set_etu_duration(512, 4);
923 break;
924 }
925 }
926
scr_check_card_insert(void)927 int scr_check_card_insert(void)
928 {
929 int card_detect = -1;
930
931 card_detect = _scr_irq_get_detect_status();
932 if (card_detect)
933 return SMC_DRV_INT_CARDIN;
934 else
935 return SMC_DRV_INT_CARDOUT;
936 }
937
scr_activate_card(void)938 static void scr_activate_card(void)
939 {
940 _scr_init();
941 _scr_set_voltage(HAL_SCR_VOLTAGE_CLASS_B);
942 }
943
scr_deactivate_card(void)944 static void scr_deactivate_card(void)
945 {
946 _scr_close();
947 }
948
scr_isr_callback(enum hal_scr_irq_cause_e cause)949 static void scr_isr_callback(enum hal_scr_irq_cause_e cause)
950 {
951 complete(&rk_scr->is_done);
952 }
953
scr_write(unsigned char * buf,unsigned int write_cnt,unsigned int * to_read_cnt)954 ssize_t scr_write(unsigned char *buf,
955 unsigned int write_cnt, unsigned int *to_read_cnt)
956 {
957 unsigned time_out = SMC_DEFAULT_TIMEOUT;
958 unsigned long udelay = 0;
959 int ret;
960
961 mutex_lock(&rk_scr->scr_mutex);
962 if (scr_check_card_insert() == SMC_DRV_INT_CARDOUT) {
963 mutex_unlock(&rk_scr->scr_mutex);
964 return SMC_ERROR_CARD_NOT_INSERT;
965 }
966
967 udelay = msecs_to_jiffies(time_out) + jiffies;
968
969 init_completion(&rk_scr->is_done);
970 rk_scr->recv_data_count = 0;
971 rk_scr->recv_data_offset = 0;
972 _scr_clock_start();
973
974 _scr_tx_byte(write_cnt, buf);
975 if (*to_read_cnt != 0) {
976 /* Set registers, ready to receive.*/
977 _scr_rx_byte(*to_read_cnt, rk_scr->recv_buffer);
978
979 ret = wait_for_completion_timeout(&rk_scr->is_done,
980 msecs_to_jiffies(time_out));
981 rk_scr->recv_data_count = _scr_get_num_rx_bytes();
982 if (ret == 0) {
983 _scr_clock_stop();
984 mutex_unlock(&rk_scr->scr_mutex);
985 return TIMEOUT;
986 }
987 }
988 _scr_clock_stop();
989 mutex_unlock(&rk_scr->scr_mutex);
990 return SUCCESSFUL;
991 }
992
scr_read(unsigned char * buf,unsigned int to_read_cnt,unsigned int * have_read_cnt)993 ssize_t scr_read(unsigned char *buf, unsigned int to_read_cnt,
994 unsigned int *have_read_cnt)
995 {
996 unsigned data_len = 0;
997 unsigned data_remain = 0;
998 unsigned data_available = 0;
999 unsigned data_offset = 0;
1000 unsigned time_out_ms = SMC_DEFAULT_TIMEOUT;
1001 unsigned data_count = 0;
1002 unsigned char data_remain_flag = 0;
1003 unsigned long udelay = 0;
1004
1005 if (!rk_scr->recv_buffer)
1006 return SMC_ERROR_RX_ERR;
1007
1008 mutex_lock(&rk_scr->scr_mutex);
1009 if (scr_check_card_insert() == SMC_DRV_INT_CARDOUT) {
1010 mutex_unlock(&rk_scr->scr_mutex);
1011 return SMC_ERROR_CARD_NOT_INSERT;
1012 }
1013
1014 udelay = msecs_to_jiffies(time_out_ms) + jiffies;
1015 data_remain = to_read_cnt;
1016 data_count = 0;
1017 _scr_clock_start();
1018
1019 if (data_remain != 0xffffff)
1020 data_remain_flag = 1;
1021
1022 while (time_before(jiffies, udelay)) {
1023 data_available = rk_scr->recv_data_count
1024 - rk_scr->recv_data_offset;
1025 if (data_available) {
1026 if (data_remain_flag)
1027 data_len = (data_available > data_remain)
1028 ? (data_remain) : (data_available);
1029 else
1030 data_len = data_available;
1031 data_offset = rk_scr->recv_data_offset;
1032 memcpy(&buf[data_count],
1033 &rk_scr->recv_buffer[data_offset],
1034 data_len);
1035 data_count += data_len;
1036 rk_scr->recv_data_offset += data_len;
1037 if (data_remain_flag)
1038 data_remain -= data_len;
1039 }
1040
1041 if (data_remain_flag && (data_remain == 0))
1042 break;
1043 msleep(50);
1044 }
1045 _scr_clock_stop();
1046 *have_read_cnt = data_count;
1047 mutex_unlock(&rk_scr->scr_mutex);
1048
1049 return SUCCESSFUL;
1050 }
1051
scr_open(void)1052 int scr_open(void)
1053 {
1054 mutex_lock(&rk_scr->scr_mutex);
1055 _scr_irq_set_handler(scr_isr_callback);
1056 if (!rk_scr->recv_buffer) {
1057 rk_scr->recv_buffer = kmalloc(SMC_RECEIVE_BUF_LEN, GFP_DMA);
1058 if (!rk_scr->recv_buffer)
1059 return NO_MEMORY;
1060 }
1061 memset(rk_scr->recv_buffer, 0, SMC_RECEIVE_BUF_LEN);
1062 init_completion(&rk_scr->is_done);
1063 rk_scr->recv_data_count = 0;
1064 rk_scr->recv_data_offset = 0;
1065 scr_activate_card();
1066 mutex_unlock(&rk_scr->scr_mutex);
1067
1068 return SUCCESSFUL;
1069 }
1070
scr_close(void)1071 int scr_close(void)
1072 {
1073 mutex_lock(&rk_scr->scr_mutex);
1074 scr_deactivate_card();
1075 kfree(rk_scr->recv_buffer);
1076 rk_scr->recv_buffer = NULL;
1077 mutex_unlock(&rk_scr->scr_mutex);
1078
1079 return SUCCESSFUL;
1080 }
1081
scr_reset(void)1082 int scr_reset(void)
1083 {
1084 unsigned long timeout_ms = SMC_DEFAULT_TIMEOUT;
1085 int i = 0;
1086 int ret;
1087
1088 DAL_LOGV("-----------------scr_reset------------------\n");
1089 mutex_lock(&rk_scr->scr_mutex);
1090 if (scr_check_card_insert() == SMC_DRV_INT_CARDOUT) {
1091 mutex_unlock(&rk_scr->scr_mutex);
1092 return SMC_ERROR_CARD_NOT_INSERT;
1093 }
1094
1095 init_completion(&rk_scr->is_done);
1096
1097 rk_scr->recv_data_count = 0;
1098 rk_scr->recv_data_offset = 0;
1099 memset(rk_scr->atr_buffer, 0, SMC_ATR_MAX_LENGTH);
1100 rk_scr->atr_length = 0;
1101
1102 _scr_clock_start();
1103 _scr_reset(rk_scr->recv_buffer);
1104
1105 ret = wait_for_completion_timeout(&rk_scr->is_done,
1106 msecs_to_jiffies(timeout_ms));
1107 rk_scr->recv_data_count = _scr_get_num_rx_bytes();
1108
1109 _scr_clock_stop();
1110
1111 if ((rk_scr->recv_data_count <= SMC_ATR_MAX_LENGTH) &&
1112 (rk_scr->recv_data_count > 0)) {
1113 memcpy(rk_scr->atr_buffer, rk_scr->recv_buffer,
1114 rk_scr->recv_data_count);
1115 rk_scr->atr_length = rk_scr->recv_data_count;
1116 } else {
1117 DAL_LOGV("ATR error: rk_scr->recv_data_count = %d.\n",
1118 rk_scr->recv_data_count);
1119 mutex_unlock(&rk_scr->scr_mutex);
1120 return SMC_ERROR_ATR_ERR;
1121 }
1122
1123 DAL_LOGV("\n--------ATR start-----------\n");
1124 DAL_LOGV("rk_scr->atr_length = %d\n", rk_scr->atr_length);
1125 for (i = 0; i < rk_scr->recv_data_count; i++)
1126 DAL_LOGV("0x%2x\n", rk_scr->atr_buffer[i]);
1127 DAL_LOGV("\n--------ATR end-----------\n");
1128 mutex_unlock(&rk_scr->scr_mutex);
1129
1130 return SUCCESSFUL;
1131 }
1132
scr_get_atr_data(unsigned char * atr_buf,unsigned char * atr_len)1133 int scr_get_atr_data(unsigned char *atr_buf, unsigned char *atr_len)
1134 {
1135 if ((!atr_buf) || (!atr_len))
1136 return SMC_ERROR_BAD_PARAMETER;
1137
1138 mutex_lock(&rk_scr->scr_mutex);
1139 if ((rk_scr->atr_length < SMC_ATR_MIN_LENGTH) ||
1140 (rk_scr->atr_length > SMC_ATR_MAX_LENGTH)) {
1141 mutex_unlock(&rk_scr->scr_mutex);
1142 return SMC_ERROR_ATR_ERR;
1143 }
1144
1145 memcpy(atr_buf, &rk_scr->atr_buffer[0], rk_scr->atr_length);
1146 *atr_len = rk_scr->atr_length;
1147 mutex_unlock(&rk_scr->scr_mutex);
1148
1149 return SUCCESSFUL;
1150 }
1151
scr_set_etu_duration(unsigned int F,unsigned int D)1152 void scr_set_etu_duration(unsigned int F, unsigned int D)
1153 {
1154 mutex_lock(&rk_scr->scr_mutex);
1155 _scr_set_etu_duration(F, D);
1156 mutex_unlock(&rk_scr->scr_mutex);
1157 }
1158
scr_set_work_waitingtime(unsigned char wi)1159 void scr_set_work_waitingtime(unsigned char wi)
1160 {
1161 mutex_lock(&rk_scr->scr_mutex);
1162 _scr_set_work_waitingtime(wi);
1163 mutex_unlock(&rk_scr->scr_mutex);
1164 }
1165
1166 static int scr_sysfs_value;
1167
scr_sysfs_show(struct kobject * kobj,struct kobj_attribute * attr,char * buf)1168 static ssize_t scr_sysfs_show(struct kobject *kobj,
1169 struct kobj_attribute *attr,
1170 char *buf)
1171 {
1172 scr_open();
1173 scr_reset();
1174 scr_close();
1175
1176 return sprintf(buf, "%d\n", scr_sysfs_value);
1177 }
1178
scr_sysfs_store(struct kobject * kobj,struct kobj_attribute * attr,const char * buf,size_t count)1179 static ssize_t scr_sysfs_store(struct kobject *kobj,
1180 struct kobj_attribute *attr,
1181 const char *buf, size_t count)
1182 {
1183 int ret;
1184
1185 ret = sscanf(buf, "%du", &scr_sysfs_value);
1186 if (ret != 1)
1187 return -EINVAL;
1188
1189 return 0;
1190 }
1191
1192 static struct kobj_attribute scr_sysfs_attribute =
1193 __ATTR(scr_sysfs, 0664, scr_sysfs_show, scr_sysfs_store);
1194
1195 struct attribute *rockchip_smartcard_attributes[] = {
1196 &scr_sysfs_attribute.attr,
1197 NULL
1198 };
1199
1200 static const struct attribute_group rockchip_smartcard_group = {
1201 .attrs = rockchip_smartcard_attributes,
1202 };
1203
1204 /* #define CONFIG_SMARTCARD_MUX_SEL_T0 */
1205 /* #define CONFIG_SMARTCARD_MUX_SEL_T1 */
1206 #define RK_SCR_CLK_NAME "g_pclk_sim_card"
rk_scr_probe(struct platform_device * pdev)1207 static int rk_scr_probe(struct platform_device *pdev)
1208 {
1209 struct rk_scr_device *rk_scr_dev = NULL;
1210 struct resource *res = NULL;
1211 struct device *dev = NULL;
1212 int ret = 0;
1213
1214 dev = &pdev->dev;
1215 rk_scr_dev = devm_kzalloc(dev, sizeof(*rk_scr_dev), GFP_KERNEL);
1216 if (!rk_scr_dev) {
1217 dev_err(dev, "failed to allocate scr_device\n");
1218 return -ENOMEM;
1219 }
1220 rk_scr = rk_scr_dev;
1221 mutex_init(&rk_scr->scr_mutex);
1222
1223 rk_scr_dev->irq = platform_get_irq(pdev, 0);
1224 if (rk_scr_dev->irq < 0) {
1225 dev_err(dev, "failed to get scr irq\n");
1226 return -ENOENT;
1227 }
1228
1229 ret = devm_request_irq(dev, rk_scr_dev->irq, rk_scr_irqhandler,
1230 0, "rockchip-scr",
1231 (void *)&rk_scr->scr[g_curr_sur_id]);
1232 if (ret < 0) {
1233 dev_err(dev, "failed to attach scr irq\n");
1234 return ret;
1235 }
1236
1237 rk_scr_dev->clk_scr = devm_clk_get(dev, RK_SCR_CLK_NAME);
1238 if (IS_ERR(rk_scr_dev->clk_scr)) {
1239 dev_err(dev, "failed to get scr clock\n");
1240 return PTR_ERR(rk_scr_dev->clk_scr);
1241 }
1242
1243 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1244 rk_scr_dev->regs = devm_ioremap_resource(dev, res);
1245 if (IS_ERR(rk_scr_dev->regs))
1246 return PTR_ERR(rk_scr_dev->regs);
1247
1248 #ifdef CONFIG_SMARTCARD_MUX_SEL_T0
1249 writel_relaxed(((0x1 << 22) | (0x1 << 6)),
1250 RK_GRF_VIRT + RK3288_GRF_SOC_CON2);
1251 #endif
1252
1253 #ifdef CONFIG_SMARTCARD_MUX_SEL_T1
1254 pinctrl_select_state(dev->pins->p,
1255 pinctrl_lookup_state(dev->pins->p, "sc_t1"));
1256 writel_relaxed(((0x1 << 22) | (0x0 << 6)),
1257 (RK_GRF_VIRT + RK3288_GRF_SOC_CON2));
1258 #endif
1259
1260 dev_set_drvdata(dev, rk_scr_dev);
1261
1262 ret = sysfs_create_group(&pdev->dev.kobj, &rockchip_smartcard_group);
1263 if (ret < 0)
1264 dev_err(&pdev->dev, "Create sysfs group failed (%d)\n", ret);
1265 DAL_LOGV("rk_scr_pdev->name = %s\n", pdev->name);
1266 DAL_LOGV("rk_scr_dev->irq = 0x%x\n", rk_scr_dev->irq);
1267
1268 return ret;
1269 }
1270
1271 #ifdef CONFIG_PM
rk_scr_suspend(struct device * dev)1272 static int rk_scr_suspend(struct device *dev)
1273 {
1274 struct rk_scr_device *rk_scr_dev = dev_get_drvdata(dev);
1275
1276 disable_irq(rk_scr_dev->irq);
1277 clk_disable(rk_scr_dev->clk_scr);
1278
1279 return 0;
1280 }
1281
rk_scr_resume(struct device * dev)1282 static int rk_scr_resume(struct device *dev)
1283 {
1284 struct rk_scr_device *rk_scr_dev = dev_get_drvdata(dev);
1285
1286 clk_enable(rk_scr_dev->clk_scr);
1287 enable_irq(rk_scr_dev->irq);
1288
1289 return 0;
1290 }
1291 #else
1292 #define rk_scr_suspend NULL
1293 #define rk_scr_resume NULL
1294 #endif
1295
1296 #ifdef CONFIG_OF
1297 static const struct of_device_id rockchip_scr_dt_match[] = {
1298 { .compatible = "rockchip-scr",},
1299 {},
1300 };
1301 MODULE_DEVICE_TABLE(of, rockchip_scr_dt_match);
1302 #endif /* CONFIG_OF */
1303
1304 static const struct dev_pm_ops scr_pm_ops = {
1305 .suspend = rk_scr_suspend,
1306 .resume = rk_scr_resume,
1307 };
1308
1309 static struct platform_driver rk_scr_driver = {
1310 .driver = {
1311 .name = "rockchip-scr",
1312 .owner = THIS_MODULE,
1313 .pm = &scr_pm_ops,
1314 .of_match_table = of_match_ptr(rockchip_scr_dt_match),
1315 },
1316 .probe = rk_scr_probe,
1317 };
1318
1319 module_platform_driver(rk_scr_driver);
1320
1321 MODULE_DESCRIPTION("rockchip Smart Card controller driver");
1322 MODULE_AUTHOR("<rockchip>");
1323 MODULE_LICENSE("GPL");
1324