1 /* 2 * Copyright 2020 Rockchip Electronics Co. LTD 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef __HAL_H265D_CTX_H__ 18 #define __HAL_H265D_CTX_H__ 19 20 #include "mpp_device.h" 21 #include "mpp_hal.h" 22 #include "hal_bufs.h" 23 24 #define MAX_GEN_REG 3 25 #define H265D_RCB_BUF_COUNT 10 26 27 typedef struct H265dRegBuf_t { 28 RK_S32 use_flag; 29 MppBuffer scaling_list_data; 30 MppBuffer pps_data; 31 MppBuffer rps_data; 32 void* hw_regs; 33 } H265dRegBuf; 34 35 typedef struct h265d_rcb_info_t { 36 RK_S32 reg; 37 RK_S32 size; 38 RK_S32 offset; 39 } H265dRcbInfo; 40 41 typedef struct HalH265dCtx_t { 42 /* for hal api call back */ 43 const MppHalApi *api; 44 45 /* for hardware info */ 46 MppClientType client_type; 47 RK_U32 hw_id; 48 MppDev dev; 49 MppDecCfgSet *cfg; 50 51 /* for resource */ 52 MppBufSlots slots; 53 MppBufSlots packet_slots; 54 MppBufferGroup group; 55 MppBuffer cabac_table_data; 56 MppBuffer scaling_list_data; 57 MppBuffer pps_data; 58 MppBuffer rps_data; 59 60 RK_S32 width; 61 RK_S32 height; 62 RK_S32 rcb_buf_size; 63 H265dRcbInfo rcb_info[H265D_RCB_BUF_COUNT]; 64 MppBuffer rcb_buf[MAX_GEN_REG]; 65 66 void* hw_regs; 67 H265dRegBuf g_buf[MAX_GEN_REG]; 68 RK_U32 fast_mode; 69 MppCbCtx *dec_cb; 70 RK_U32 fast_mode_err_found; 71 void *scaling_rk; 72 void *scaling_qm; 73 HalBufs cmv_bufs; 74 RK_U32 mv_size; 75 RK_S32 mv_count; 76 77 RK_U32 is_v345; 78 RK_U32 is_v34x; 79 /* rcb info */ 80 RK_U32 chroma_fmt_idc; 81 RK_U8 ctu_size; 82 RK_U8 num_row_tiles; 83 RK_U8 bit_depth; 84 RK_U8 error_index; 85 /* for vdpu34x */ 86 MppBuffer bufs; 87 RK_S32 bufs_fd; 88 RK_U32 offset_cabac; 89 RK_U32 offset_spspps[MAX_GEN_REG]; 90 RK_U32 offset_rps[MAX_GEN_REG]; 91 RK_U32 offset_sclst[MAX_GEN_REG]; 92 RK_U32 spspps_offset; 93 RK_U32 rps_offset; 94 RK_U32 sclst_offset; 95 void *pps_buf; 96 void *sw_rps_buf; 97 98 const MppDecHwCap *hw_info; 99 } HalH265dCtx; 100 101 typedef struct ScalingList { 102 /* This is a little wasteful, since sizeID 0 only needs 8 coeffs, 103 * and size ID 3 only has 2 arrays, not 6. */ 104 RK_U8 sl[4][6][64]; 105 RK_U8 sl_dc[2][6]; 106 } scalingList_t; 107 108 typedef struct ScalingFactor_Model { 109 RK_U8 scalingfactor0[1248]; 110 RK_U8 scalingfactor1[96]; /*4X4 TU Rotate, total 16X4*/ 111 RK_U8 scalingdc[12]; /*N1005 Vienna Meeting*/ 112 RK_U8 reserverd[4]; /*16Bytes align*/ 113 } scalingFactor_t; 114 115 #endif 116