1 /* SPDX-License-Identifier: Apache-2.0 OR MIT */ 2 /* 3 * Copyright (c) 2024 Rockchip Electronics Co., Ltd. 4 */ 5 6 #ifndef __HAL_H265D_CTX_H__ 7 #define __HAL_H265D_CTX_H__ 8 9 #include "mpp_device.h" 10 #include "mpp_hal.h" 11 #include "hal_bufs.h" 12 13 #define MAX_GEN_REG 3 14 /* before vdpu383 10 buf */ 15 #define H265D_RCB_BUF_COUNT 11 16 17 typedef struct H265dRegBuf_t { 18 RK_S32 use_flag; 19 MppBuffer scaling_list_data; 20 MppBuffer pps_data; 21 MppBuffer rps_data; 22 void* hw_regs; 23 } H265dRegBuf; 24 25 typedef struct H265dRcbInfo_t { 26 RK_S32 reg; 27 RK_S32 size; 28 RK_S32 offset; 29 } H265dRcbInfo; 30 31 typedef struct HalH265dCtx_t { 32 /* for hal api call back */ 33 const MppHalApi *api; 34 35 /* for hardware info */ 36 MppClientType client_type; 37 RK_U32 hw_id; 38 MppDev dev; 39 MppDecCfgSet *cfg; 40 41 /* for resource */ 42 MppBufSlots slots; 43 MppBufSlots packet_slots; 44 MppBufferGroup group; 45 MppBuffer cabac_table_data; 46 MppBuffer scaling_list_data; 47 MppBuffer pps_data; 48 MppBuffer rps_data; 49 50 RK_S32 width; 51 RK_S32 height; 52 RK_S32 rcb_buf_size; 53 H265dRcbInfo rcb_info[H265D_RCB_BUF_COUNT]; 54 MppBuffer rcb_buf[MAX_GEN_REG]; 55 56 void* hw_regs; 57 H265dRegBuf g_buf[MAX_GEN_REG]; 58 RK_U32 fast_mode; 59 MppCbCtx *dec_cb; 60 RK_U32 fast_mode_err_found; 61 void *scaling_rk; 62 void *scaling_qm; 63 HalBufs cmv_bufs; 64 RK_U32 mv_size; 65 RK_S32 mv_count; 66 67 struct { 68 RK_U32 is_v341 : 1; 69 RK_U32 is_v345 : 1; 70 RK_U32 is_v34x : 1; 71 RK_U32 is_v383 : 1; 72 RK_U32 is_v384a : 1; 73 }; 74 /* rcb info */ 75 RK_U32 chroma_fmt_idc; 76 RK_U8 ctu_size; 77 RK_U8 num_row_tiles; 78 RK_U8 bit_depth; 79 RK_U8 error_index[MAX_GEN_REG]; 80 /* for vdpu34x */ 81 MppBuffer bufs; 82 RK_S32 bufs_fd; 83 RK_U32 offset_cabac; 84 RK_U32 offset_spspps[MAX_GEN_REG]; 85 RK_U32 offset_rps[MAX_GEN_REG]; 86 RK_U32 offset_sclst[MAX_GEN_REG]; 87 RK_U32 spspps_offset; 88 RK_U32 rps_offset; 89 RK_U32 sclst_offset; 90 void *pps_buf; 91 void *sw_rps_buf; 92 HalBufs origin_bufs; 93 MppBuffer missing_ref_buf; 94 RK_U32 missing_ref_buf_size; 95 96 const MppDecHwCap *hw_info; 97 } HalH265dCtx; 98 99 typedef struct ScalingList { 100 /* This is a little wasteful, since sizeID 0 only needs 8 coeffs, 101 * and size ID 3 only has 2 arrays, not 6. */ 102 RK_U8 sl[4][6][64]; 103 RK_U8 sl_dc[2][6]; 104 } scalingList_t; 105 106 typedef struct ScalingFactor_Model { 107 RK_U8 scalingfactor0[1248]; 108 RK_U8 scalingfactor1[96]; /*4X4 TU Rotate, total 16X4*/ 109 RK_U8 scalingdc[12]; /*N1005 Vienna Meeting*/ 110 RK_U8 reserverd[4]; /*16Bytes align*/ 111 } scalingFactor_t; 112 113 #endif 114