1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 *
19 ******************************************************************************/
20 #define _HCI_INTF_C_
21
22 #include <drv_types.h>
23 #include <hal_data.h>
24
25 #include <linux/pci_regs.h>
26
27 #ifndef CONFIG_PCI_HCI
28
29 #error "CONFIG_PCI_HCI shall be on!\n"
30
31 #endif
32
33
34 #if defined(PLATFORM_LINUX) && defined (PLATFORM_WINDOWS)
35
36 #error "Shall be Linux or Windows, but not both!\n"
37
38 #endif
39
40 #ifdef CONFIG_80211N_HT
41 extern int rtw_ht_enable;
42 extern int rtw_bw_mode;
43 extern int rtw_ampdu_enable;/* for enable tx_ampdu */
44 #endif
45
46 #ifdef CONFIG_GLOBAL_UI_PID
47 int ui_pid[3] = {0, 0, 0};
48 #endif
49
50 extern int pm_netdev_open(struct net_device *pnetdev, u8 bnormal);
51 int rtw_resume_process(_adapter *padapter);
52
53 #ifdef CONFIG_PM
54 static int rtw_pci_suspend(struct pci_dev *pdev, pm_message_t state);
55 static int rtw_pci_resume(struct pci_dev *pdev);
56 #endif
57
58 static int rtw_drv_init(struct pci_dev *pdev, const struct pci_device_id *pdid);
59 static void rtw_dev_remove(struct pci_dev *pdev);
60
61 static struct specific_device_id specific_device_id_tbl[] = {
62 {.idVendor = 0x0b05, .idProduct = 0x1791, .flags = SPEC_DEV_ID_DISABLE_HT},
63 {.idVendor = 0x13D3, .idProduct = 0x3311, .flags = SPEC_DEV_ID_DISABLE_HT},
64 {}
65 };
66
67 struct pci_device_id rtw_pci_id_tbl[] = {
68 #ifdef CONFIG_RTL8188E
69 {PCI_DEVICE(PCI_VENDER_ID_REALTEK, 0x8179), .driver_data = RTL8188E},
70 #endif
71 #ifdef CONFIG_RTL8812A
72 {PCI_DEVICE(PCI_VENDER_ID_REALTEK, 0x8812), .driver_data = RTL8812},
73 #endif
74 #ifdef CONFIG_RTL8821A
75 {PCI_DEVICE(PCI_VENDER_ID_REALTEK, 0x8821), .driver_data = RTL8821},
76 #endif
77 #ifdef CONFIG_RTL8192E
78 {PCI_DEVICE(PCI_VENDER_ID_REALTEK, 0x818B), .driver_data = RTL8192E},
79 #endif
80 #ifdef CONFIG_RTL8723B
81 {PCI_DEVICE(PCI_VENDER_ID_REALTEK, 0xb723), .driver_data = RTL8723B},
82 #endif
83 #ifdef CONFIG_RTL8723D
84 {PCI_DEVICE(PCI_VENDER_ID_REALTEK, 0xd723), .driver_data = RTL8723D},
85 #endif
86 #ifdef CONFIG_RTL8814A
87 {PCI_DEVICE(PCI_VENDER_ID_REALTEK, 0x8813), .driver_data = RTL8814A},
88 #endif
89 #ifdef CONFIG_RTL8822B
90 {PCI_DEVICE(PCI_VENDER_ID_REALTEK, 0xB822), .driver_data = RTL8822B},
91 #endif
92 {},
93 };
94
95 struct pci_drv_priv {
96 struct pci_driver rtw_pci_drv;
97 int drv_registered;
98 };
99
100
101 static struct pci_drv_priv pci_drvpriv = {
102 .rtw_pci_drv.name = (char *)DRV_NAME,
103 .rtw_pci_drv.probe = rtw_drv_init,
104 .rtw_pci_drv.remove = rtw_dev_remove,
105 .rtw_pci_drv.shutdown = rtw_dev_remove,
106 .rtw_pci_drv.id_table = rtw_pci_id_tbl,
107 #ifdef CONFIG_PM
108 .rtw_pci_drv.suspend = rtw_pci_suspend,
109 .rtw_pci_drv.resume = rtw_pci_resume,
110 #endif
111 };
112
113
114 MODULE_DEVICE_TABLE(pci, rtw_pci_id_tbl);
115
116
117 static u16 pcibridge_vendors[PCI_BRIDGE_VENDOR_MAX] = {
118 INTEL_VENDOR_ID,
119 ATI_VENDOR_ID,
120 AMD_VENDOR_ID,
121 SIS_VENDOR_ID,
122 NVI_VENDOR_ID
123 };
124
125 #define PCI_PM_CAP_ID 0x01 /* The Capability ID for PME function */
PlatformClearPciPMEStatus(PADAPTER Adapter)126 void PlatformClearPciPMEStatus(PADAPTER Adapter)
127 {
128 struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(Adapter);
129 struct pci_dev *pdev = pdvobjpriv->ppcidev;
130 BOOLEAN PCIClkReq = _FALSE;
131 u8 CapId = 0xff;
132 u8 CapPointer = 0;
133 /* u16 CapHdr; */
134 RT_PCI_CAPABILITIES_HEADER CapHdr;
135 u8 PMCSReg;
136 int result;
137
138 /* Get the Capability pointer first, */
139 /* the Capability Pointer is located at offset 0x34 from the Function Header */
140
141 result = pci_read_config_byte(pdev, 0x34, &CapPointer);
142 if (result != 0)
143 RTW_INFO("%s() pci_read_config_byte 0x34 Failed!\n", __FUNCTION__);
144 else {
145 RTW_INFO("PlatformClearPciPMEStatus(): PCI configration 0x34 = 0x%2x\n", CapPointer);
146 do {
147 /* end of pci capability */
148 if (CapPointer == 0x00) {
149 CapId = 0xff;
150 break;
151 }
152
153 /* result = pci_read_config_word(pdev, CapPointer, &CapHdr); */
154 result = pci_read_config_byte(pdev, CapPointer, &CapHdr.CapabilityID);
155 if (result != 0) {
156 RTW_INFO("%s() pci_read_config_byte %x Failed!\n", __FUNCTION__, CapPointer);
157 CapId = 0xff;
158 break;
159 }
160
161 result = pci_read_config_byte(pdev, CapPointer + 1, &CapHdr.Next);
162 if (result != 0) {
163 RTW_INFO("%s() pci_read_config_byte %x Failed!\n", __FUNCTION__, CapPointer);
164 CapId = 0xff;
165 break;
166 }
167
168 /* CapId = CapHdr & 0xFF; */
169 CapId = CapHdr.CapabilityID;
170
171 RTW_INFO("PlatformClearPciPMEStatus(): in pci configration1, CapPointer%x = %x\n", CapPointer, CapId);
172
173 if (CapId == PCI_PM_CAP_ID)
174 break;
175 else {
176 /* point to next Capability */
177 /* CapPointer = (CapHdr >> 8) & 0xFF; */
178 CapPointer = CapHdr.Next;
179 }
180 } while (_TRUE);
181
182 if (CapId == PCI_PM_CAP_ID) {
183 /* Get the PM CSR (Control/Status Register), */
184 /* The PME_Status is located at PM Capatibility offset 5, bit 7 */
185 result = pci_read_config_byte(pdev, CapPointer + 5, &PMCSReg);
186 if (PMCSReg & BIT7) {
187 /* PME event occured, clear the PM_Status by write 1 */
188 PMCSReg = PMCSReg | BIT7;
189
190 pci_write_config_byte(pdev, CapPointer + 5, PMCSReg);
191 PCIClkReq = _TRUE;
192 /* Read it back to check */
193 pci_read_config_byte(pdev, CapPointer + 5, &PMCSReg);
194 RTW_INFO("PlatformClearPciPMEStatus(): Clear PME status 0x%2x to 0x%2x\n", CapPointer + 5, PMCSReg);
195 } else
196 RTW_INFO("PlatformClearPciPMEStatus(): PME status(0x%2x) = 0x%2x\n", CapPointer + 5, PMCSReg);
197 } else
198 RTW_INFO("PlatformClearPciPMEStatus(): Cannot find PME Capability\n");
199 }
200
201 RTW_INFO("PME, value_offset = %x, PME EN = %x\n", CapPointer + 5, PCIClkReq);
202 }
203
rtw_pci_platform_switch_device_pci_aspm(_adapter * padapter,u8 value)204 static u8 rtw_pci_platform_switch_device_pci_aspm(_adapter *padapter, u8 value)
205 {
206 struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
207 struct pci_priv *pcipriv = &(pdvobjpriv->pcipriv);
208 BOOLEAN bResult = _FALSE;
209 int Result = 0;
210 int error;
211
212 Result = pci_write_config_byte(pdvobjpriv->ppcidev, pcipriv->pciehdr_offset + 0x10, value); /* enable I/O space */
213 RTW_INFO("PlatformSwitchDevicePciASPM(0x%x) = 0x%x\n", pcipriv->pciehdr_offset + 0x10, value);
214 if (Result != 0) {
215 RTW_INFO("PlatformSwitchDevicePciASPM() Failed!\n");
216 bResult = _FALSE;
217 } else
218 bResult = _TRUE;
219
220 return bResult;
221 }
222
223 /*
224 * When we set 0x01 to enable clk request. Set 0x0 to disable clk req.
225 * */
rtw_pci_switch_clk_req(_adapter * padapter,u8 value)226 static u8 rtw_pci_switch_clk_req(_adapter *padapter, u8 value)
227 {
228 struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
229 u8 buffer, bResult = _FALSE;
230 int error;
231
232 buffer = value;
233
234 if (!rtw_is_hw_init_completed(padapter))
235 return bResult;
236
237 /* the clock request is located at offset 0x81, suppose the PCIE Capability register is located at offset 0x70 */
238 /* the correct code should be: search the PCIE capability register first and then the clock request is located offset 0x11 */
239 error = pci_write_config_byte(pdvobjpriv->ppcidev, 0x81, buffer);
240 if (error != 0)
241 RTW_INFO("rtw_pci_switch_clk_req error (%d)\n", error);
242 else
243 bResult = _TRUE;
244
245 return bResult;
246 }
247
248 /*Disable RTL8192SE ASPM & Disable Pci Bridge ASPM*/
rtw_pci_disable_aspm(_adapter * padapter)249 void rtw_pci_disable_aspm(_adapter *padapter)
250 {
251 struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
252 struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(pdvobjpriv);
253 struct pci_dev *pdev = pdvobjpriv->ppcidev;
254 struct pci_dev *bridge_pdev = pdev->bus->self;
255 struct pci_priv *pcipriv = &(pdvobjpriv->pcipriv);
256 u8 linkctrl_reg;
257 u8 pcibridge_linkctrlreg, aspmlevel = 0;
258
259
260 /* We shall check RF Off Level for ASPM function instead of registry settings, revised by Roger, 2013.03.29. */
261 if (!(pwrpriv->reg_rfps_level & (RT_RF_LPS_LEVEL_ASPM | RT_RF_PS_LEVEL_ALWAYS_ASPM)))
262 return;
263
264 if (!rtw_is_hw_init_completed(padapter))
265 return;
266
267 if (pcipriv->pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
268 RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("%s(): PCI(Bridge) UNKNOWN.\n", __FUNCTION__));
269 return;
270 }
271
272 linkctrl_reg = pcipriv->linkctrl_reg;
273 pcibridge_linkctrlreg = pcipriv->pcibridge_linkctrlreg;
274
275 /* Set corresponding value. */
276 aspmlevel |= BIT(0) | BIT(1);
277 linkctrl_reg &= ~aspmlevel;
278 pcibridge_linkctrlreg &= ~aspmlevel;
279
280 /* */
281 /* 09/08/21 MH From Sd1 suggestion. we need to adjust ASPM enable sequence */
282 /* CLK_REQ ==> delay 50us ==> Device ==> Host ==> delay 50us */
283 /* */
284
285 if (pwrpriv->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
286 RT_CLEAR_PS_LEVEL(pwrpriv, RT_RF_OFF_LEVL_CLK_REQ);
287 rtw_pci_switch_clk_req(padapter, 0x0);
288 }
289
290 {
291 /*for promising device will in L0 state after an I/O.*/
292 u8 tmp_u1b;
293 pci_read_config_byte(pdev, (pcipriv->pciehdr_offset + 0x10), &tmp_u1b);
294 }
295
296 rtw_pci_platform_switch_device_pci_aspm(padapter, linkctrl_reg);
297
298 rtw_udelay_os(50);
299
300 /* When there exists anyone's BusNum, DevNum, and FuncNum that are set to 0xff, */
301 /* we do not execute any action and return. Added by tynli. */
302 if ((pcipriv->busnumber == 0xff && pcipriv->devnumber == 0xff && pcipriv->funcnumber == 0xff) ||
303 (pcipriv->pcibridge_busnum == 0xff && pcipriv->pcibridge_devnum == 0xff && pcipriv->pcibridge_funcnum == 0xff)) {
304 /* Do Nothing!! */
305 } else {
306 /* 4 */ /* Disable Pci Bridge ASPM */
307 pci_write_config_byte(bridge_pdev, (pcipriv->pcibridge_pciehdr_offset + 0x10), pcibridge_linkctrlreg);
308 RTW_INFO("PlatformDisableASPM():PciBridge Write reg[%x] = %x\n",
309 (pcipriv->pcibridge_pciehdr_offset + 0x10), pcibridge_linkctrlreg);
310 rtw_udelay_os(50);
311 }
312
313 }
314
315 /*Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for
316 power saving We should follow the sequence to enable
317 RTL8192SE first then enable Pci Bridge ASPM
318 or the system will show bluescreen.*/
rtw_pci_enable_aspm(_adapter * padapter)319 void rtw_pci_enable_aspm(_adapter *padapter)
320 {
321 struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
322 struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(pdvobjpriv);
323 struct pci_dev *pdev = pdvobjpriv->ppcidev;
324 struct pci_dev *bridge_pdev = pdev->bus->self;
325 struct pci_priv *pcipriv = &(pdvobjpriv->pcipriv);
326 u16 aspmlevel = 0;
327 u8 u_pcibridge_aspmsetting = 0;
328 u8 u_device_aspmsetting = 0;
329 u32 u_device_aspmsupportsetting = 0;
330
331
332 /* We shall check RF Off Level for ASPM function instead of registry settings, revised by Roger, 2013.03.29. */
333 if (!(pwrpriv->reg_rfps_level & (RT_RF_LPS_LEVEL_ASPM | RT_RF_PS_LEVEL_ALWAYS_ASPM)))
334 return;
335
336 /* When there exists anyone's BusNum, DevNum, and FuncNum that are set to 0xff, */
337 /* we do not execute any action and return. Added by tynli. */
338 if ((pcipriv->busnumber == 0xff && pcipriv->devnumber == 0xff && pcipriv->funcnumber == 0xff) ||
339 (pcipriv->pcibridge_busnum == 0xff && pcipriv->pcibridge_devnum == 0xff && pcipriv->pcibridge_funcnum == 0xff)) {
340 RTW_INFO("rtw_pci_enable_aspm(): Fail to enable ASPM. Cannot find the Bus of PCI(Bridge).\n");
341 return;
342 }
343
344 /* Get Bridge ASPM Support
345 * not to enable bridge aspm if bridge does not support
346 * Added by sherry 20100803 */
347 {
348 /* Get the Link Capability, it ls located at offset 0x0c from the PCIE Capability */
349 pci_read_config_dword(bridge_pdev, (pcipriv->pcibridge_pciehdr_offset + 0x0C), &u_device_aspmsupportsetting);
350
351 RTW_INFO("rtw_pci_enable_aspm(): Bridge ASPM support %x\n", u_device_aspmsupportsetting);
352 if (((u_device_aspmsupportsetting & BIT(11)) != BIT(11)) || ((u_device_aspmsupportsetting & BIT(10)) != BIT(10))) {
353 if (pdvobjpriv->const_devicepci_aspm_setting == 3) {
354 RTW_INFO("rtw_pci_enable_aspm(): Bridge not support L0S or L1\n");
355 return;
356 } else if (pdvobjpriv->const_devicepci_aspm_setting == 2) {
357 if ((u_device_aspmsupportsetting & BIT(11)) != BIT(11)) {
358 RTW_INFO("rtw_pci_enable_aspm(): Bridge not support L1\n");
359 return;
360 }
361 } else if (pdvobjpriv->const_devicepci_aspm_setting == 1) {
362 if ((u_device_aspmsupportsetting & BIT(10)) != BIT(10)) {
363 RTW_INFO("rtw_pci_enable_aspm(): Bridge not support L0s\n");
364 return;
365 }
366
367 }
368 } else
369 RTW_INFO("rtw_pci_enable_aspm(): Bridge support L0s and L1\n");
370 }
371
372 /*
373 * Skip following settings if ASPM has already enabled, added by Roger, 2013.03.15.
374 * */
375 if ((pcipriv->pcibridge_linkctrlreg & (BIT0 | BIT1)) &&
376 (pcipriv->linkctrl_reg & (BIT0 | BIT1))) {
377 /* BIT0: L0S, BIT1:L1 */
378
379 RTW_INFO("PlatformEnableASPM(): ASPM is already enabled, skip incoming settings!!\n");
380 return;
381 }
382
383 /* 4 Enable Pci Bridge ASPM */
384 /* Write PCI bridge PCIE-capability Link Control Register */
385 /* Justin: Can we change the ASPM Control register ? */
386 /* The system BIOS should set this register with a correct value */
387 /* If we change the force enable the ASPM L1/L0s, this may cause the system hang */
388 u_pcibridge_aspmsetting = pcipriv->pcibridge_linkctrlreg;
389 u_pcibridge_aspmsetting |= pdvobjpriv->const_hostpci_aspm_setting;
390
391 if (pcipriv->pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL ||
392 pcipriv->pcibridge_vendor == PCI_BRIDGE_VENDOR_SIS)
393 u_pcibridge_aspmsetting &= ~BIT(0); /* for intel host 42 device 43 */
394
395 pci_write_config_byte(bridge_pdev, (pcipriv->pcibridge_pciehdr_offset + 0x10), u_pcibridge_aspmsetting);
396 RTW_INFO("PlatformEnableASPM():PciBridge Write reg[%x] = %x\n",
397 (pcipriv->pcibridge_pciehdr_offset + 0x10),
398 u_pcibridge_aspmsetting);
399
400 rtw_udelay_os(50);
401
402 /*Get ASPM level (with/without Clock Req)*/
403 aspmlevel |= pdvobjpriv->const_devicepci_aspm_setting;
404 u_device_aspmsetting = pcipriv->linkctrl_reg;
405 u_device_aspmsetting |= aspmlevel; /* device 43 */
406
407 rtw_pci_platform_switch_device_pci_aspm(padapter, u_device_aspmsetting);
408
409 if (pwrpriv->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
410 rtw_pci_switch_clk_req(padapter, (pwrpriv->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) ? 1 : 0);
411 RT_SET_PS_LEVEL(pwrpriv, RT_RF_OFF_LEVL_CLK_REQ);
412 }
413
414 rtw_udelay_os(50);
415 }
416
rtw_pci_get_amd_l1_patch(struct dvobj_priv * pdvobjpriv,struct pci_dev * pdev)417 static u8 rtw_pci_get_amd_l1_patch(struct dvobj_priv *pdvobjpriv, struct pci_dev *pdev)
418 {
419 u8 status = _FALSE;
420 u8 offset_e0;
421 u32 offset_e4;
422
423 pci_write_config_byte(pdev, 0xE0, 0xA0);
424 pci_read_config_byte(pdev, 0xE0, &offset_e0);
425
426 if (offset_e0 == 0xA0) {
427 pci_read_config_dword(pdev, 0xE4, &offset_e4);
428 if (offset_e4 & BIT(23))
429 status = _TRUE;
430 }
431
432 return status;
433 }
434
rtw_pci_get_linkcontrol_reg(struct pci_dev * pdev,u8 * LinkCtrlReg,u8 * HdrOffset)435 static s32 rtw_pci_get_linkcontrol_reg(struct pci_dev *pdev, u8 *LinkCtrlReg, u8 *HdrOffset)
436 {
437 u8 CapabilityPointer;
438 RT_PCI_CAPABILITIES_HEADER CapabilityHdr;
439 s32 status = _FAIL;
440
441 /* get CapabilityOffset */
442 pci_read_config_byte(pdev, 0x34, &CapabilityPointer); /* the capability pointer is located offset 0x34 */
443
444 /* Loop through the capabilities in search of the power management capability. */
445 /* The list is NULL-terminated, so the last offset will always be zero. */
446
447 while (CapabilityPointer != 0) {
448 /* Read the header of the capability at this offset. If the retrieved capability is not */
449 /* the power management capability that we are looking for, follow the link to the */
450 /* next capability and continue looping. */
451
452 /* 4 get CapabilityHdr */
453 /* pci_read_config_word(pdev, CapabilityPointer, (u16 *)&CapabilityHdr); */
454 pci_read_config_byte(pdev, CapabilityPointer, (u8 *)&CapabilityHdr.CapabilityID);
455 pci_read_config_byte(pdev, CapabilityPointer + 1, (u8 *)&CapabilityHdr.Next);
456
457 /* Found the PCI express capability */
458 if (CapabilityHdr.CapabilityID == PCI_CAPABILITY_ID_PCI_EXPRESS)
459 break;
460 else {
461 /* This is some other capability. Keep looking for the PCI express capability. */
462 CapabilityPointer = CapabilityHdr.Next;
463 }
464 }
465
466 /* Get the Link Control Register, it located at offset 0x10 from the Capability Header */
467 if (CapabilityHdr.CapabilityID == PCI_CAPABILITY_ID_PCI_EXPRESS) {
468 *HdrOffset = CapabilityPointer;
469 pci_read_config_byte(pdev, CapabilityPointer + 0x10, LinkCtrlReg);
470
471 status = _SUCCESS;
472 } else {
473 /* We didn't find a PCIe capability. */
474 RTW_INFO("GetPciLinkCtrlReg(): Cannot Find PCIe Capability\n");
475 }
476
477 return status;
478 }
479
rtw_set_pci_cache_line_size(struct pci_dev * pdev,u8 CacheLineSizeToSet)480 static s32 rtw_set_pci_cache_line_size(struct pci_dev *pdev, u8 CacheLineSizeToSet)
481 {
482 u8 ucPciCacheLineSize;
483 s32 Result;
484
485 /* ucPciCacheLineSize = pPciConfig->CacheLineSize; */
486 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &ucPciCacheLineSize);
487
488 if (ucPciCacheLineSize < 8 || ucPciCacheLineSize > 16) {
489 RTW_INFO("Driver Sets default Cache Line Size...\n");
490
491 ucPciCacheLineSize = CacheLineSizeToSet;
492
493 Result = pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, ucPciCacheLineSize);
494
495 if (Result != 0) {
496 RTW_INFO("pci_write_config_byte (CacheLineSize) Result=%d\n", Result);
497 goto _SET_CACHELINE_SIZE_FAIL;
498 }
499
500 Result = pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &ucPciCacheLineSize);
501 if (Result != 0) {
502 RTW_INFO("pci_read_config_byte (PciCacheLineSize) Result=%d\n", Result);
503 goto _SET_CACHELINE_SIZE_FAIL;
504 }
505
506 if ((ucPciCacheLineSize != CacheLineSizeToSet)) {
507 RTW_INFO("Failed to set Cache Line Size to 0x%x! ucPciCacheLineSize=%x\n", CacheLineSizeToSet, ucPciCacheLineSize);
508 goto _SET_CACHELINE_SIZE_FAIL;
509 }
510 }
511
512 return _SUCCESS;
513
514 _SET_CACHELINE_SIZE_FAIL:
515
516 return _FAIL;
517 }
518
519
520 #define PCI_CMD_ENABLE_BUS_MASTER BIT(2)
521 #define PCI_CMD_DISABLE_INTERRUPT BIT(10)
522 #define CMD_BUS_MASTER BIT(2)
523
rtw_pci_parse_configuration(struct pci_dev * pdev,struct dvobj_priv * pdvobjpriv)524 static s32 rtw_pci_parse_configuration(struct pci_dev *pdev, struct dvobj_priv *pdvobjpriv)
525 {
526 struct pci_priv *pcipriv = &(pdvobjpriv->pcipriv);
527 /* PPCI_COMMON_CONFIG pPciConfig = (PPCI_COMMON_CONFIG) pucBuffer; */
528 /* u16 usPciCommand = pPciConfig->Command; */
529 u16 usPciCommand = 0;
530 int Result, ret;
531 u8 CapabilityOffset;
532 RT_PCI_CAPABILITIES_HEADER CapabilityHdr;
533 u8 PCIeCap;
534 u8 LinkCtrlReg;
535 u8 ClkReqReg;
536
537 /* RTW_INFO("%s==>\n", __FUNCTION__); */
538
539 pci_read_config_word(pdev, PCI_COMMAND, &usPciCommand);
540
541 do {
542 /* 3 Enable bus matering if it isn't enabled by the BIOS */
543 if (!(usPciCommand & PCI_CMD_ENABLE_BUS_MASTER)) {
544 RTW_INFO("Bus master is not enabled by BIOS! usPciCommand=%x\n", usPciCommand);
545
546 usPciCommand |= CMD_BUS_MASTER;
547
548 Result = pci_write_config_word(pdev, PCI_COMMAND, usPciCommand);
549 if (Result != 0) {
550 RTW_INFO("pci_write_config_word (Command) Result=%d\n", Result);
551 ret = _FAIL;
552 break;
553 }
554
555 Result = pci_read_config_word(pdev, PCI_COMMAND, &usPciCommand);
556 if (Result != 0) {
557 RTW_INFO("pci_read_config_word (Command) Result=%d\n", Result);
558 ret = _FAIL;
559 break;
560 }
561
562 if (!(usPciCommand & PCI_CMD_ENABLE_BUS_MASTER)) {
563 RTW_INFO("Failed to enable bus master! usPciCommand=%x\n", usPciCommand);
564 ret = _FAIL;
565 break;
566 }
567 }
568 RTW_INFO("Bus master is enabled. usPciCommand=%x\n", usPciCommand);
569
570 /* 3 Enable interrupt */
571 if ((usPciCommand & PCI_CMD_DISABLE_INTERRUPT)) {
572 RTW_INFO("INTDIS==1 usPciCommand=%x\n", usPciCommand);
573
574 usPciCommand &= (~PCI_CMD_DISABLE_INTERRUPT);
575
576 Result = pci_write_config_word(pdev, PCI_COMMAND, usPciCommand);
577 if (Result != 0) {
578 RTW_INFO("pci_write_config_word (Command) Result=%d\n", Result);
579 ret = _FAIL;
580 break;
581 }
582
583 Result = pci_read_config_word(pdev, PCI_COMMAND, &usPciCommand);
584 if (Result != 0) {
585 RTW_INFO("pci_read_config_word (Command) Result=%d\n", Result);
586 ret = _FAIL;
587 break;
588 }
589
590 if ((usPciCommand & PCI_CMD_DISABLE_INTERRUPT)) {
591 RTW_INFO("Failed to set INTDIS to 0! usPciCommand=%x\n", usPciCommand);
592 ret = _FAIL;
593 break;
594 }
595 }
596
597 /* */
598 /* Description: Find PCI express capability offset. Porting from 818xB by tynli 2008.12.19 */
599 /* */
600 /* ------------------------------------------------------------- */
601
602 /* 3 PCIeCap */
603 /* The device supports capability lists. Find the capabilities. */
604
605 /* CapabilityOffset = pPciConfig->u.type0.CapabilitiesPtr; */
606 pci_read_config_byte(pdev, PCI_CAPABILITY_LIST, &CapabilityOffset);
607
608 /* Loop through the capabilities in search of the power management capability. */
609 /* The list is NULL-terminated, so the last offset will always be zero. */
610
611 while (CapabilityOffset != 0) {
612 /* Read the header of the capability at this offset. If the retrieved capability is not */
613 /* the power management capability that we are looking for, follow the link to the */
614 /* next capability and continue looping. */
615
616 /* Result = pci_read_config_word(pdev, CapabilityOffset, (u16 *)&CapabilityHdr); */
617 Result = pci_read_config_byte(pdev, CapabilityOffset, (u8 *)&CapabilityHdr.CapabilityID);
618 if (Result != 0)
619 break;
620
621 Result = pci_read_config_byte(pdev, CapabilityOffset + 1, (u8 *)&CapabilityHdr.Next);
622 if (Result != 0)
623 break;
624
625 /* Found the PCI express capability */
626 if (CapabilityHdr.CapabilityID == PCI_CAPABILITY_ID_PCI_EXPRESS)
627 break;
628 else {
629 /* This is some other capability. Keep looking for the PCI express capability. */
630 CapabilityOffset = CapabilityHdr.Next;
631 }
632 }
633
634 if (Result != 0) {
635 RTW_INFO("pci_read_config_word (RT_PCI_CAPABILITIES_HEADER) Result=%d\n", Result);
636 break;
637 }
638
639 if (CapabilityHdr.CapabilityID == PCI_CAPABILITY_ID_PCI_EXPRESS) {
640 pcipriv->pciehdr_offset = CapabilityOffset;
641 RTW_INFO("PCIe Header Offset =%x\n", CapabilityOffset);
642
643 /* Skip past the capabilities header and read the PCI express capability */
644 /* Justin: The PCI-e capability size should be 2 bytes, why we just get 1 byte */
645 /* Beside, this PCIeCap seems no one reference it in the driver code */
646 Result = pci_read_config_byte(pdev, CapabilityOffset + 2, &PCIeCap);
647
648 if (Result != 0) {
649 RTW_INFO("pci_read_config_byte (PCIE Capability) Result=%d\n", Result);
650 break;
651 }
652
653 pcipriv->pcie_cap = PCIeCap;
654 RTW_INFO("PCIe Capability =%x\n", PCIeCap);
655
656 /* 3 Link Control Register */
657 /* Read "Link Control Register" Field (80h ~81h) */
658 Result = pci_read_config_byte(pdev, CapabilityOffset + 0x10, &LinkCtrlReg);
659 if (Result != 0) {
660 RTW_INFO("pci_read_config_byte (Link Control Register) Result=%d\n", Result);
661 break;
662 }
663
664 pcipriv->linkctrl_reg = LinkCtrlReg;
665 RTW_INFO("Link Control Register =%x\n", LinkCtrlReg);
666
667 /* 3 Get Capability of PCI Clock Request */
668 /* The clock request setting is located at 0x81[0] */
669 Result = pci_read_config_byte(pdev, CapabilityOffset + 0x11, &ClkReqReg);
670 if (Result != 0) {
671 pcipriv->pci_clk_req = _FALSE;
672 RTW_INFO("pci_read_config_byte (Clock Request Register) Result=%d\n", Result);
673 break;
674 }
675 if (ClkReqReg & BIT(0))
676 pcipriv->pci_clk_req = _TRUE;
677 else
678 pcipriv->pci_clk_req = _FALSE;
679 RTW_INFO("Clock Request =%x\n", pcipriv->pci_clk_req);
680 } else {
681 /* We didn't find a PCIe capability. */
682 RTW_INFO("Didn't Find PCIe Capability\n");
683 break;
684 }
685
686 /* 3 Fill Cacheline */
687 ret = rtw_set_pci_cache_line_size(pdev, 8);
688 if (ret != _SUCCESS) {
689 RTW_INFO("rtw_set_pci_cache_line_size fail\n");
690 break;
691 }
692
693 /* Include 92C suggested by SD1. Added by tynli. 2009.11.25.
694 * Enable the Backdoor */
695 {
696 u8 tmp;
697
698 Result = pci_read_config_byte(pdev, 0x98, &tmp);
699
700 tmp |= BIT4;
701
702 Result = pci_write_config_byte(pdev, 0x98, tmp);
703
704 }
705 ret = _SUCCESS;
706 } while (_FALSE);
707
708 return ret;
709 }
710
711 /*
712 * Update PCI dependent default settings.
713 * */
rtw_pci_update_default_setting(_adapter * padapter)714 static void rtw_pci_update_default_setting(_adapter *padapter)
715 {
716 struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
717 struct pci_priv *pcipriv = &(pdvobjpriv->pcipriv);
718 struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(pdvobjpriv);
719 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
720
721 /* reset pPSC->reg_rfps_level & priv->b_support_aspm */
722 pwrpriv->reg_rfps_level = 0;
723
724 /* Update PCI ASPM setting */
725 /* pwrpriv->const_amdpci_aspm = pdvobjpriv->const_amdpci_aspm; */
726 switch (pdvobjpriv->const_pci_aspm) {
727 case 0: /* No ASPM */
728 break;
729
730 case 1: /* ASPM dynamically enabled/disable. */
731 pwrpriv->reg_rfps_level |= RT_RF_LPS_LEVEL_ASPM;
732 break;
733
734 case 2: /* ASPM with Clock Req dynamically enabled/disable. */
735 pwrpriv->reg_rfps_level |= (RT_RF_LPS_LEVEL_ASPM | RT_RF_OFF_LEVL_CLK_REQ);
736 break;
737
738 case 3: /* Always enable ASPM and Clock Req from initialization to halt. */
739 pwrpriv->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM);
740 pwrpriv->reg_rfps_level |= (RT_RF_PS_LEVEL_ALWAYS_ASPM | RT_RF_OFF_LEVL_CLK_REQ);
741 break;
742
743 case 4: /* Always enable ASPM without Clock Req from initialization to halt. */
744 pwrpriv->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM | RT_RF_OFF_LEVL_CLK_REQ);
745 pwrpriv->reg_rfps_level |= RT_RF_PS_LEVEL_ALWAYS_ASPM;
746 break;
747
748 case 5: /* Linux do not support ASPM OSC, added by Roger, 2013.03.27. */
749 break;
750 }
751
752 pwrpriv->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
753
754 /* Update Radio OFF setting */
755 switch (pdvobjpriv->const_hwsw_rfoff_d3) {
756 case 1:
757 if (pwrpriv->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
758 pwrpriv->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
759 break;
760
761 case 2:
762 if (pwrpriv->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
763 pwrpriv->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
764 pwrpriv->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
765 break;
766
767 case 3:
768 pwrpriv->reg_rfps_level |= RT_RF_OFF_LEVL_PCI_D3;
769 break;
770 }
771
772 /* Update Rx 2R setting */
773 /* pPSC->reg_rfps_level |= ((pDevice->RegLPS2RDisable) ? RT_RF_LPS_DISALBE_2R : 0); */
774
775 /* */
776 /* Set HW definition to determine if it supports ASPM. */
777 /* */
778 switch (pdvobjpriv->const_support_pciaspm) {
779 case 1: { /* Support ASPM. */
780 u8 b_support_backdoor = _TRUE;
781 u8 b_support_l1_on_amd = _FALSE;
782
783 rtw_hal_get_def_var(padapter, HAL_DEF_PCI_AMD_L1_SUPPORT, &b_support_l1_on_amd);
784
785 if (pHalData->CustomerID == RT_CID_TOSHIBA &&
786 pcipriv->pcibridge_vendor == PCI_BRIDGE_VENDOR_AMD &&
787 !pcipriv->amd_l1_patch && !b_support_l1_on_amd) {
788 RTW_INFO("%s(): Disable L1 Backdoor!!\n", __FUNCTION__);
789 b_support_backdoor = _FALSE;
790 }
791 rtw_hal_set_def_var(padapter, HAL_DEF_PCI_SUUPORT_L1_BACKDOOR, &b_support_backdoor);
792 }
793 break;
794
795 default:
796 /* Do nothing. Set when finding the chipset. */
797 break;
798 }
799 }
800
rtw_pci_initialize_adapter_common(_adapter * padapter)801 static void rtw_pci_initialize_adapter_common(_adapter *padapter)
802 {
803 struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
804
805 rtw_pci_update_default_setting(padapter);
806
807 if (pwrpriv->reg_rfps_level & RT_RF_PS_LEVEL_ALWAYS_ASPM) {
808 /* Always enable ASPM & Clock Req. */
809 rtw_pci_enable_aspm(padapter);
810 RT_SET_PS_LEVEL(pwrpriv, RT_RF_PS_LEVEL_ALWAYS_ASPM);
811 }
812
813 }
814
815 /*
816 * 2009/10/28 MH Enable rtl8192ce DMA64 function. We need to enable 0x719 BIT5
817 * */
818 #ifdef CONFIG_64BIT_DMA
PlatformEnableDMA64(PADAPTER Adapter)819 u8 PlatformEnableDMA64(PADAPTER Adapter)
820 {
821 struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(Adapter);
822 struct pci_dev *pdev = pdvobjpriv->ppcidev;
823 u8 bResult = _TRUE;
824 u8 value;
825
826 pci_read_config_byte(pdev, 0x719, &value);
827
828 /* 0x719 Bit5 is DMA64 bit fetch. */
829 value |= (BIT5);
830
831 pci_write_config_byte(pdev, 0x719, value);
832
833 return bResult;
834 }
835 #endif
836
837 #if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 5, 0)) || (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 18))
838 #define rtw_pci_interrupt(x, y, z) rtw_pci_interrupt(x, y)
839 #endif
840
rtw_pci_interrupt(int irq,void * priv,struct pt_regs * regs)841 static irqreturn_t rtw_pci_interrupt(int irq, void *priv, struct pt_regs *regs)
842 {
843 struct dvobj_priv *dvobj = (struct dvobj_priv *)priv;
844 _adapter *adapter = dvobj->padapters[IFACE_ID0];
845
846 if (dvobj->irq_enabled == 0)
847 return IRQ_HANDLED;
848
849 if (rtw_hal_interrupt_handler(adapter) == _FAIL)
850 return IRQ_HANDLED;
851 /* return IRQ_NONE; */
852
853 return IRQ_HANDLED;
854 }
855
856 #ifdef RTK_DMP_PLATFORM
857 #define pci_iounmap(x, y) iounmap(y)
858 #endif
859
pci_alloc_irq(struct dvobj_priv * dvobj)860 int pci_alloc_irq(struct dvobj_priv *dvobj)
861 {
862 int err;
863 struct pci_dev *pdev = dvobj->ppcidev;
864 int ret;
865
866 ret = pci_enable_msi(pdev);
867
868 RTW_INFO("pci_enable_msi ret=%d\n", ret);
869
870 #if defined(IRQF_SHARED)
871 err = request_irq(pdev->irq, &rtw_pci_interrupt, IRQF_SHARED, DRV_NAME, dvobj);
872 #else
873 err = request_irq(pdev->irq, &rtw_pci_interrupt, SA_SHIRQ, DRV_NAME, dvobj);
874 #endif
875 if (err)
876 RTW_INFO("Error allocating IRQ %d", pdev->irq);
877 else {
878 dvobj->irq_alloc = 1;
879 dvobj->irq = pdev->irq;
880 RTW_INFO("Request_irq OK, IRQ %d\n", pdev->irq);
881 }
882
883 return err ? _FAIL : _SUCCESS;
884 }
885
rtw_decide_chip_type_by_pci_driver_data(struct dvobj_priv * pdvobj,const struct pci_device_id * pdid)886 static void rtw_decide_chip_type_by_pci_driver_data(struct dvobj_priv *pdvobj, const struct pci_device_id *pdid)
887 {
888 pdvobj->chip_type = pdid->driver_data;
889
890 #ifdef CONFIG_RTL8188E
891 if (pdvobj->chip_type == RTL8188E) {
892 pdvobj->HardwareType = HARDWARE_TYPE_RTL8188EE;
893 RTW_INFO("CHIP TYPE: RTL8188E\n");
894 }
895 #endif
896
897 #ifdef CONFIG_RTL8812A
898 if (pdvobj->chip_type == RTL8812) {
899 pdvobj->HardwareType = HARDWARE_TYPE_RTL8812E;
900 RTW_INFO("CHIP TYPE: RTL8812AE\n");
901 }
902 #endif
903
904 #ifdef CONFIG_RTL8821A
905 if (pdvobj->chip_type == RTL8821) {
906 pdvobj->HardwareType = HARDWARE_TYPE_RTL8821E;
907 RTW_INFO("CHIP TYPE: RTL8821AE\n");
908 }
909 #endif
910
911 #ifdef CONFIG_RTL8723B
912 if (pdvobj->chip_type == RTL8723B) {
913 pdvobj->HardwareType = HARDWARE_TYPE_RTL8723BE;
914 RTW_INFO("CHIP TYPE: RTL8723BE\n");
915 }
916 #endif
917 #ifdef CONFIG_RTL8723D
918 if (pdvobj->chip_type == RTL8723D) {
919 pdvobj->HardwareType = HARDWARE_TYPE_RTL8723DE;
920 RTW_INFO("CHIP TYPE: RTL8723DE\n");
921 }
922 #endif
923 #ifdef CONFIG_RTL8192E
924 if (pdvobj->chip_type == RTL8192E) {
925 pdvobj->HardwareType = HARDWARE_TYPE_RTL8192EE;
926 RTW_INFO("CHIP TYPE: RTL8192EE\n");
927 }
928 #endif
929
930 #ifdef CONFIG_RTL8814A
931 if (pdvobj->chip_type == RTL8814A) {
932 pdvobj->HardwareType = HARDWARE_TYPE_RTL8814AE;
933 RTW_INFO("CHIP TYPE: RTL8814AE\n");
934 }
935 #endif
936
937 #if defined(CONFIG_RTL8822B)
938 if (pdvobj->chip_type == RTL8822B) {
939 pdvobj->HardwareType = HARDWARE_TYPE_RTL8822BE;
940 RTW_INFO("CHIP TYPE: RTL8822BE\n");
941 }
942 #endif
943 }
944
pci_dvobj_init(struct pci_dev * pdev,const struct pci_device_id * pdid)945 static struct dvobj_priv *pci_dvobj_init(struct pci_dev *pdev, const struct pci_device_id *pdid)
946 {
947 int err;
948 u32 status = _FAIL;
949 struct dvobj_priv *dvobj = NULL;
950 struct pci_priv *pcipriv = NULL;
951 struct pci_dev *bridge_pdev = pdev->bus->self;
952 /* u32 pci_cfg_space[16]; */
953 unsigned long pmem_start, pmem_len, pmem_flags;
954 u8 tmp;
955 u8 PciBgVIdIdx;
956 int i;
957
958 _func_enter_;
959
960 dvobj = devobj_init();
961 if (dvobj == NULL)
962 goto exit;
963
964
965 dvobj->ppcidev = pdev;
966 pcipriv = &(dvobj->pcipriv);
967 pci_set_drvdata(pdev, dvobj);
968
969
970 err = pci_enable_device(pdev);
971 if (err != 0) {
972 RTW_ERR("%s : Cannot enable new PCI device\n", pci_name(pdev));
973 goto free_dvobj;
974 }
975
976 #ifdef CONFIG_64BIT_DMA
977 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
978 RTW_INFO("RTL819xCE: Using 64bit DMA\n");
979 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
980 if (err != 0) {
981 RTW_ERR("Unable to obtain 64bit DMA for consistent allocations\n");
982 goto disable_picdev;
983 }
984 dvobj->bdma64 = _TRUE;
985 } else
986 #endif
987 {
988 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
989 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
990 if (err != 0) {
991 RTW_ERR("Unable to obtain 32bit DMA for consistent allocations\n");
992 goto disable_picdev;
993 }
994 }
995 }
996
997 pci_set_master(pdev);
998
999 err = pci_request_regions(pdev, DRV_NAME);
1000 if (err != 0) {
1001 RTW_ERR("Can't obtain PCI resources\n");
1002 goto disable_picdev;
1003 }
1004
1005 #ifdef RTK_129X_PLATFORM
1006 if (pdev->bus->number == 0x00) {
1007 pmem_start = PCIE_SLOT1_MEM_START;
1008 pmem_len = PCIE_SLOT1_MEM_LEN;
1009 pmem_flags = 0;
1010 RTW_PRINT("RTD129X: PCIE SLOT1\n");
1011 } else if (pdev->bus->number == 0x01) {
1012 pmem_start = PCIE_SLOT2_MEM_START;
1013 pmem_len = PCIE_SLOT2_MEM_LEN;
1014 pmem_flags = 0;
1015 RTW_PRINT("RTD129X: PCIE SLOT2\n");
1016 } else {
1017 RTW_ERR(KERN_ERR "RTD129X: Wrong Slot Num\n");
1018 goto release_regions;
1019 }
1020 #else
1021 /* Search for memory map resource (index 0~5) */
1022 for (i = 0 ; i < 6 ; i++) {
1023 pmem_start = pci_resource_start(pdev, i);
1024 pmem_len = pci_resource_len(pdev, i);
1025 pmem_flags = pci_resource_flags(pdev, i);
1026
1027 if (pmem_flags & IORESOURCE_MEM)
1028 break;
1029 }
1030
1031 if (i == 6) {
1032 RTW_ERR("%s: No MMIO resource found, abort!\n", __func__);
1033 goto release_regions;
1034 }
1035 #endif /* RTK_DMP_PLATFORM */
1036
1037 #ifdef RTK_DMP_PLATFORM
1038 dvobj->pci_mem_start = (unsigned long)ioremap(pmem_start, pmem_len);
1039 #elif defined(RTK_129X_PLATFORM)
1040 if (pdev->bus->number == 0x00)
1041 dvobj->ctrl_start =
1042 (unsigned long)ioremap(PCIE_SLOT1_CTRL_START, 0x200);
1043 else if (pdev->bus->number == 0x01)
1044 dvobj->ctrl_start =
1045 (unsigned long)ioremap(PCIE_SLOT2_CTRL_START, 0x200);
1046
1047 if (dvobj->ctrl_start == 0) {
1048 RTW_ERR("RTD129X: Can't map CTRL mem\n");
1049 goto release_regions;
1050 }
1051
1052 dvobj->mask_addr = dvobj->ctrl_start + PCIE_MASK_OFFSET;
1053 dvobj->tran_addr = dvobj->ctrl_start + PCIE_TRANSLATE_OFFSET;
1054
1055 dvobj->pci_mem_start =
1056 (unsigned long)ioremap(pmem_start, pmem_len);
1057 #else
1058 /* shared mem start */
1059 dvobj->pci_mem_start = (unsigned long)pci_iomap(pdev, i, pmem_len);
1060 #endif
1061 if (dvobj->pci_mem_start == 0) {
1062 RTW_ERR("Can't map PCI mem\n");
1063 goto release_regions;
1064 }
1065
1066 RTW_INFO("Memory mapped space start: 0x%08lx len:%08lx flags:%08lx, after map:0x%08lx\n",
1067 pmem_start, pmem_len, pmem_flags, dvobj->pci_mem_start);
1068
1069 /*find bus info*/
1070 pcipriv->busnumber = pdev->bus->number;
1071 pcipriv->devnumber = PCI_SLOT(pdev->devfn);
1072 pcipriv->funcnumber = PCI_FUNC(pdev->devfn);
1073
1074 /*find bridge info*/
1075 if (bridge_pdev) {
1076 pcipriv->pcibridge_busnum = bridge_pdev->bus->number;
1077 pcipriv->pcibridge_devnum = PCI_SLOT(bridge_pdev->devfn);
1078 pcipriv->pcibridge_funcnum = PCI_FUNC(bridge_pdev->devfn);
1079 pcipriv->pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN;
1080 pcipriv->pcibridge_vendorid = bridge_pdev->vendor;
1081 pcipriv->pcibridge_deviceid = bridge_pdev->device;
1082 }
1083
1084 #if 0
1085 /* Read PCI configuration Space Header */
1086 for (i = 0; i < 16; i++)
1087 pci_read_config_dword(pdev, (i << 2), &pci_cfg_space[i]);
1088 #endif
1089
1090 /*step 1-1., decide the chip_type via device info*/
1091 dvobj->interface_type = RTW_PCIE;
1092 rtw_decide_chip_type_by_pci_driver_data(dvobj, pdid);
1093
1094
1095 /* rtw_pci_parse_configuration(pdev, dvobj, (u8 *)&pci_cfg_space); */
1096 rtw_pci_parse_configuration(pdev, dvobj);
1097
1098 for (PciBgVIdIdx = 0; PciBgVIdIdx < PCI_BRIDGE_VENDOR_MAX; PciBgVIdIdx++) {
1099 if (pcipriv->pcibridge_vendorid == pcibridge_vendors[PciBgVIdIdx]) {
1100 pcipriv->pcibridge_vendor = PciBgVIdIdx;
1101 RTW_INFO("Pci Bridge Vendor is found: VID=0x%x, VendorIdx=%d\n", pcipriv->pcibridge_vendorid, PciBgVIdIdx);
1102 break;
1103 }
1104 }
1105
1106 if (pcipriv->pcibridge_vendor != PCI_BRIDGE_VENDOR_UNKNOWN) {
1107 rtw_pci_get_linkcontrol_reg(bridge_pdev, &pcipriv->pcibridge_linkctrlreg, &pcipriv->pcibridge_pciehdr_offset);
1108
1109 if (pcipriv->pcibridge_vendor == PCI_BRIDGE_VENDOR_AMD)
1110 pcipriv->amd_l1_patch = rtw_pci_get_amd_l1_patch(dvobj, bridge_pdev);
1111 }
1112
1113 status = _SUCCESS;
1114
1115 iounmap:
1116 if (status != _SUCCESS && dvobj->pci_mem_start != 0) {
1117 #if 1/* def RTK_DMP_PLATFORM */
1118 pci_iounmap(pdev, (void *)dvobj->pci_mem_start);
1119 #endif
1120 dvobj->pci_mem_start = 0;
1121 }
1122
1123 #ifdef RTK_129X_PLATFORM
1124 if (status != _SUCCESS && dvobj->ctrl_start != 0) {
1125 pci_iounmap(pdev, (void *)dvobj->ctrl_start);
1126 dvobj->ctrl_start = 0;
1127 }
1128 #endif
1129
1130 release_regions:
1131 if (status != _SUCCESS)
1132 pci_release_regions(pdev);
1133 disable_picdev:
1134 if (status != _SUCCESS)
1135 pci_disable_device(pdev);
1136 free_dvobj:
1137 if (status != _SUCCESS && dvobj) {
1138 pci_set_drvdata(pdev, NULL);
1139 devobj_deinit(dvobj);
1140 dvobj = NULL;
1141 }
1142 exit:
1143 _func_exit_;
1144 return dvobj;
1145 }
1146
1147
pci_dvobj_deinit(struct pci_dev * pdev)1148 static void pci_dvobj_deinit(struct pci_dev *pdev)
1149 {
1150 struct dvobj_priv *dvobj = pci_get_drvdata(pdev);
1151 _func_enter_;
1152
1153 pci_set_drvdata(pdev, NULL);
1154 if (dvobj) {
1155 if (dvobj->irq_alloc) {
1156 free_irq(pdev->irq, dvobj);
1157 pci_disable_msi(pdev);
1158 dvobj->irq_alloc = 0;
1159 }
1160
1161 if (dvobj->pci_mem_start != 0) {
1162 #if 1/* def RTK_DMP_PLATFORM */
1163 pci_iounmap(pdev, (void *)dvobj->pci_mem_start);
1164 #endif
1165 dvobj->pci_mem_start = 0;
1166 }
1167
1168 #ifdef RTK_129X_PLATFORM
1169 if (dvobj->ctrl_start != 0) {
1170 pci_iounmap(pdev, (void *)dvobj->ctrl_start);
1171 dvobj->ctrl_start = 0;
1172 }
1173 #endif
1174 devobj_deinit(dvobj);
1175 }
1176
1177 pci_release_regions(pdev);
1178 pci_disable_device(pdev);
1179
1180 _func_exit_;
1181 }
1182
1183
rtw_set_hal_ops(_adapter * padapter)1184 u8 rtw_set_hal_ops(_adapter *padapter)
1185 {
1186 /* alloc memory for HAL DATA */
1187 if (rtw_hal_data_init(padapter) == _FAIL)
1188 return _FAIL;
1189
1190 #ifdef CONFIG_RTL8188E
1191 if (rtw_get_chip_type(padapter) == RTL8188E)
1192 rtl8188ee_set_hal_ops(padapter);
1193 #endif
1194
1195 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
1196 if ((rtw_get_chip_type(padapter) == RTL8812) || (rtw_get_chip_type(padapter) == RTL8821))
1197 rtl8812ae_set_hal_ops(padapter);
1198 #endif
1199
1200 #ifdef CONFIG_RTL8723B
1201 if (rtw_get_chip_type(padapter) == RTL8723B)
1202 rtl8723be_set_hal_ops(padapter);
1203 #endif
1204
1205 #ifdef CONFIG_RTL8723D
1206 if (rtw_get_chip_type(padapter) == RTL8723D)
1207 rtl8723de_set_hal_ops(padapter);
1208 #endif
1209
1210 #ifdef CONFIG_RTL8192E
1211 if (rtw_get_chip_type(padapter) == RTL8192E)
1212 rtl8192ee_set_hal_ops(padapter);
1213 #endif
1214
1215 #ifdef CONFIG_RTL8814A
1216 if (rtw_get_chip_type(padapter) == RTL8814A)
1217 rtl8814ae_set_hal_ops(padapter);
1218 #endif
1219
1220 #if defined(CONFIG_RTL8822B)
1221 if (rtw_get_chip_type(padapter) == RTL8822B)
1222 rtl8822be_set_hal_ops(padapter);
1223 #endif
1224
1225 if (rtw_hal_ops_check(padapter) == _FAIL)
1226 return _FAIL;
1227
1228 if (hal_spec_init(padapter) == _FAIL)
1229 return _FAIL;
1230
1231 return _SUCCESS;
1232 }
1233
pci_set_intf_ops(_adapter * padapter,struct _io_ops * pops)1234 void pci_set_intf_ops(_adapter *padapter, struct _io_ops *pops)
1235 {
1236 #ifdef CONFIG_RTL8188E
1237 if (rtw_get_chip_type(padapter) == RTL8188E)
1238 rtl8188ee_set_intf_ops(pops);
1239 #endif
1240
1241 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
1242 if ((rtw_get_chip_type(padapter) == RTL8812) || (rtw_get_chip_type(padapter) == RTL8821))
1243 rtl8812ae_set_intf_ops(pops);
1244 #endif
1245
1246 #ifdef CONFIG_RTL8723B
1247 if (rtw_get_chip_type(padapter) == RTL8723B)
1248 rtl8723be_set_intf_ops(pops);
1249 #endif
1250
1251 #ifdef CONFIG_RTL8723D
1252 if (rtw_get_chip_type(padapter) == RTL8723D)
1253 rtl8723de_set_intf_ops(pops);
1254 #endif
1255
1256 #ifdef CONFIG_RTL8192E
1257 if (rtw_get_chip_type(padapter) == RTL8192E)
1258 rtl8192ee_set_intf_ops(pops);
1259 #endif
1260
1261 #ifdef CONFIG_RTL8814A
1262 if (rtw_get_chip_type(padapter) == RTL8814A)
1263 rtl8814ae_set_intf_ops(pops);
1264 #endif
1265
1266 #if defined(CONFIG_RTL8822B)
1267 if (rtw_get_chip_type(padapter) == RTL8822B)
1268 rtl8822be_set_intf_ops(pops);
1269 #endif
1270
1271 }
1272
pci_intf_start(_adapter * padapter)1273 static void pci_intf_start(_adapter *padapter)
1274 {
1275
1276 RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("+pci_intf_start\n"));
1277 RTW_INFO("+pci_intf_start\n");
1278
1279 /* Enable hw interrupt */
1280 rtw_hal_enable_interrupt(padapter);
1281
1282 RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("-pci_intf_start\n"));
1283 RTW_INFO("-pci_intf_start\n");
1284 }
rtw_mi_pci_tasklets_kill(_adapter * padapter)1285 static void rtw_mi_pci_tasklets_kill(_adapter *padapter)
1286 {
1287 int i;
1288 _adapter *iface;
1289 struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
1290
1291 for (i = 0; i < dvobj->iface_nums; i++) {
1292 iface = dvobj->padapters[i];
1293 if ((iface) && rtw_is_adapter_up(iface)) {
1294 #ifndef CONFIG_NAPI
1295 tasklet_kill(&(padapter->recvpriv.recv_tasklet));
1296 #endif
1297 tasklet_kill(&(padapter->recvpriv.irq_prepare_beacon_tasklet));
1298 tasklet_kill(&(padapter->xmitpriv.xmit_tasklet));
1299 }
1300 }
1301 }
1302
pci_intf_stop(_adapter * padapter)1303 static void pci_intf_stop(_adapter *padapter)
1304 {
1305
1306 RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("+pci_intf_stop\n"));
1307
1308 /* Disable hw interrupt */
1309 if (!rtw_is_surprise_removed(padapter)) {
1310 /* device still exists, so driver can do i/o operation */
1311 rtw_hal_disable_interrupt(padapter);
1312 rtw_mi_pci_tasklets_kill(padapter);
1313
1314 rtw_hal_set_hwreg(padapter, HW_VAR_PCIE_STOP_TX_DMA, 0);
1315
1316 rtw_hal_irp_reset(padapter);
1317
1318 RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("pci_intf_stop: SurpriseRemoved==_FALSE\n"));
1319 } else {
1320 /* Clear irq_enabled to prevent handle interrupt function. */
1321 adapter_to_dvobj(padapter)->irq_enabled = 0;
1322 }
1323
1324 RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("-pci_intf_stop\n"));
1325
1326 }
1327
disable_ht_for_spec_devid(const struct pci_device_id * pdid)1328 static void disable_ht_for_spec_devid(const struct pci_device_id *pdid)
1329 {
1330 #ifdef CONFIG_80211N_HT
1331 u16 vid, pid;
1332 u32 flags;
1333 int i;
1334 int num = sizeof(specific_device_id_tbl) / sizeof(struct specific_device_id);
1335
1336 for (i = 0; i < num; i++) {
1337 vid = specific_device_id_tbl[i].idVendor;
1338 pid = specific_device_id_tbl[i].idProduct;
1339 flags = specific_device_id_tbl[i].flags;
1340
1341 if ((pdid->vendor == vid) && (pdid->device == pid) && (flags & SPEC_DEV_ID_DISABLE_HT)) {
1342 rtw_ht_enable = 0;
1343 rtw_bw_mode = 0;
1344 rtw_ampdu_enable = 0;
1345 }
1346
1347 }
1348 #endif
1349 }
1350
1351 #ifdef CONFIG_PM
rtw_pci_suspend(struct pci_dev * pdev,pm_message_t state)1352 static int rtw_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1353 {
1354 int ret = 0;
1355 struct dvobj_priv *dvobj = pci_get_drvdata(pdev);
1356 _adapter *padapter = dvobj->padapters[IFACE_ID0];
1357
1358 ret = rtw_suspend_common(padapter);
1359 ret = pci_save_state(pdev);
1360 if (ret != 0) {
1361 RTW_INFO("%s Failed on pci_save_state (%d)\n", __FUNCTION__, ret);
1362 goto exit;
1363 }
1364
1365 #ifdef CONFIG_WOWLAN
1366 device_set_wakeup_enable(&pdev->dev, true);
1367 #endif
1368 pci_disable_device(pdev);
1369
1370 #ifdef CONFIG_WOWLAN
1371 ret = pci_enable_wake(pdev, pci_choose_state(pdev, state), true);
1372 if (ret != 0)
1373 RTW_INFO("%s Failed on pci_enable_wake (%d)\n", __FUNCTION__, ret);
1374 #endif
1375 ret = pci_set_power_state(pdev, pci_choose_state(pdev, state));
1376 if (ret != 0)
1377 RTW_INFO("%s Failed on pci_set_power_state (%d)\n", __FUNCTION__, ret);
1378
1379 exit:
1380 return ret;
1381
1382 }
1383
rtw_resume_process(_adapter * padapter)1384 int rtw_resume_process(_adapter *padapter)
1385 {
1386 return rtw_resume_common(padapter);
1387 }
1388
rtw_pci_resume(struct pci_dev * pdev)1389 static int rtw_pci_resume(struct pci_dev *pdev)
1390 {
1391 struct dvobj_priv *dvobj = pci_get_drvdata(pdev);
1392 _adapter *padapter = dvobj->padapters[IFACE_ID0];
1393 struct net_device *pnetdev = padapter->pnetdev;
1394 struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj);
1395 int err = 0;
1396
1397 err = pci_set_power_state(pdev, PCI_D0);
1398 if (err != 0) {
1399 RTW_INFO("%s Failed on pci_set_power_state (%d)\n", __FUNCTION__, err);
1400 goto exit;
1401 }
1402
1403 err = pci_enable_device(pdev);
1404 if (err != 0) {
1405 RTW_INFO("%s Failed on pci_enable_device (%d)\n", __FUNCTION__, err);
1406 goto exit;
1407 }
1408
1409
1410 #ifdef CONFIG_WOWLAN
1411 err = pci_enable_wake(pdev, PCI_D0, 0);
1412 if (err != 0) {
1413 RTW_INFO("%s Failed on pci_enable_wake (%d)\n", __FUNCTION__, err);
1414 goto exit;
1415 }
1416 #endif
1417 #if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 37))
1418 pci_restore_state(pdev);
1419 #else
1420 err = pci_restore_state(pdev);
1421 if (err != 0) {
1422 RTW_INFO("%s Failed on pci_restore_state (%d)\n", __FUNCTION__, err);
1423 goto exit;
1424 }
1425 #endif
1426
1427 #ifdef CONFIG_WOWLAN
1428 device_set_wakeup_enable(&pdev->dev, false);
1429 #endif
1430
1431 if (pwrpriv->bInternalAutoSuspend)
1432 err = rtw_resume_process(padapter);
1433 else {
1434 if (pwrpriv->wowlan_mode || pwrpriv->wowlan_ap_mode) {
1435 rtw_resume_lock_suspend();
1436 err = rtw_resume_process(padapter);
1437 rtw_resume_unlock_suspend();
1438 } else {
1439 #ifdef CONFIG_RESUME_IN_WORKQUEUE
1440 rtw_resume_in_workqueue(pwrpriv);
1441 #else
1442 if (rtw_is_earlysuspend_registered(pwrpriv)) {
1443 /* jeff: bypass resume here, do in late_resume */
1444 rtw_set_do_late_resume(pwrpriv, _TRUE);
1445 } else {
1446 rtw_resume_lock_suspend();
1447 err = rtw_resume_process(padapter);
1448 rtw_resume_unlock_suspend();
1449 }
1450 #endif
1451 }
1452 }
1453
1454 exit:
1455
1456 return err;
1457 }
1458 #endif/* CONFIG_PM */
1459
rtw_pci_primary_adapter_init(struct dvobj_priv * dvobj,struct pci_dev * pdev)1460 _adapter *rtw_pci_primary_adapter_init(struct dvobj_priv *dvobj, struct pci_dev *pdev)
1461 {
1462 _adapter *padapter = NULL;
1463 int status = _FAIL;
1464
1465 padapter = (_adapter *)rtw_zvmalloc(sizeof(*padapter));
1466 if (padapter == NULL)
1467 goto exit;
1468
1469 if (loadparam(padapter) != _SUCCESS)
1470 goto free_adapter;
1471
1472 padapter->dvobj = dvobj;
1473
1474 rtw_set_drv_stopped(padapter);/*init*/
1475
1476 dvobj->padapters[dvobj->iface_nums++] = padapter;
1477 padapter->iface_id = IFACE_ID0;
1478
1479 /* set adapter_type/iface type for primary padapter */
1480 padapter->isprimary = _TRUE;
1481 padapter->adapter_type = PRIMARY_ADAPTER;
1482 #ifdef CONFIG_MI_WITH_MBSSID_CAM
1483 padapter->hw_port = HW_PORT0;
1484 #else
1485 #ifndef CONFIG_HWPORT_SWAP
1486 padapter->hw_port = HW_PORT0;
1487 #else /* CONFIG_HWPORT_SWAP */
1488 padapter->hw_port = HW_PORT1;
1489 #endif /* !CONFIG_HWPORT_SWAP */
1490 #endif
1491
1492 if (rtw_init_io_priv(padapter, pci_set_intf_ops) == _FAIL)
1493 goto free_adapter;
1494
1495 /* step 2. hook HalFunc, allocate HalData */
1496 /* hal_set_hal_ops(padapter); */
1497 if (rtw_set_hal_ops(padapter) == _FAIL) {
1498 RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("Initialize hal resource Failed!\n"));
1499 goto free_hal_data;
1500 }
1501
1502 /* step 3. */
1503 padapter->intf_start = &pci_intf_start;
1504 padapter->intf_stop = &pci_intf_stop;
1505
1506 /* .3 */
1507 rtw_hal_read_chip_version(padapter);
1508
1509 /* .4 */
1510 rtw_hal_chip_configure(padapter);
1511
1512 /* step 4. read efuse/eeprom data and get mac_addr */
1513 if (rtw_hal_read_chip_info(padapter) == _FAIL) {
1514 RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("Initialize driver read chip info Failed!\n"));
1515 goto free_hal_data;
1516 }
1517
1518 /* step 5. */
1519 if (rtw_init_drv_sw(padapter) == _FAIL) {
1520 RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("Initialize driver software resource Failed!\n"));
1521 goto free_hal_data;
1522 }
1523
1524 #ifdef CONFIG_BT_COEXIST
1525 rtw_btcoex_Initialize(padapter);
1526 #endif /* CONFIG_BT_COEXIST */
1527
1528 if (rtw_hal_inirp_init(padapter) == _FAIL) {
1529 RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("Initialize PCI desc ring Failed!\n"));
1530 goto free_timer;
1531 }
1532 rtw_macaddr_cfg(adapter_mac_addr(padapter), get_hal_mac_addr(padapter));
1533
1534 #ifdef CONFIG_MI_WITH_MBSSID_CAM
1535 rtw_mbid_camid_alloc(padapter, adapter_mac_addr(padapter));
1536 #endif
1537 #ifdef CONFIG_P2P
1538 rtw_init_wifidirect_addrs(padapter, adapter_mac_addr(padapter), adapter_mac_addr(padapter));
1539 #endif /* CONFIG_P2P */
1540
1541 rtw_hal_disable_interrupt(padapter);
1542
1543 /* step 6. Init pci related configuration */
1544 rtw_pci_initialize_adapter_common(padapter);
1545
1546 RTW_INFO("bDriverStopped:%s, bSurpriseRemoved:%s, bup:%d, hw_init_completed:%s\n"
1547 , rtw_is_drv_stopped(padapter) ? "True" : "False"
1548 , rtw_is_surprise_removed(padapter) ? "True" : "False"
1549 , padapter->bup
1550 , rtw_is_hw_init_completed(padapter) ? "True" : "False"
1551 );
1552
1553 status = _SUCCESS;
1554
1555 free_timer:
1556 #ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS
1557 if (status != _SUCCESS)
1558 _cancel_timer_ex(&padapter->recvpriv.signal_stat_timer);
1559 #endif
1560
1561 free_hal_data:
1562 if (status != _SUCCESS && padapter->HalData)
1563 rtw_hal_free_data(padapter);
1564
1565 free_adapter:
1566 if (status != _SUCCESS && padapter) {
1567 rtw_vmfree((u8 *)padapter, sizeof(*padapter));
1568 padapter = NULL;
1569 }
1570 exit:
1571 return padapter;
1572 }
1573
rtw_pci_primary_adapter_deinit(_adapter * padapter)1574 static void rtw_pci_primary_adapter_deinit(_adapter *padapter)
1575 {
1576 struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
1577
1578 /* padapter->intf_stop(padapter); */
1579
1580 if (check_fwstate(pmlmepriv, _FW_LINKED))
1581 rtw_disassoc_cmd(padapter, 0, _FALSE);
1582
1583 #ifdef CONFIG_AP_MODE
1584 if (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE) {
1585 free_mlme_ap_info(padapter);
1586 #ifdef CONFIG_HOSTAPD_MLME
1587 hostapd_mode_unload(padapter);
1588 #endif
1589 }
1590 #endif
1591
1592 /*rtw_cancel_all_timer(padapte);*/
1593 #ifdef CONFIG_WOWLAN
1594 adapter_to_pwrctl(padapter)->wowlan_mode = _FALSE;
1595 #endif /* CONFIG_WOWLAN */
1596 rtw_dev_unload(padapter);
1597
1598 RTW_INFO("%s, hw_init_completed=%s\n", __func__, rtw_is_hw_init_completed(padapter) ? "_TRUE" : "_FALSE");
1599
1600 rtw_hal_inirp_deinit(padapter);
1601 rtw_free_drv_sw(padapter);
1602
1603 /* TODO: use rtw_os_ndevs_deinit instead at the first stage of driver's dev deinit function */
1604 rtw_os_ndev_free(padapter);
1605
1606 #ifdef RTW_HALMAC
1607 rtw_halmac_deinit_adapter(adapter_to_dvobj(padapter));
1608 #endif /* RTW_HALMAC */
1609
1610 rtw_vmfree((u8 *)padapter, sizeof(_adapter));
1611
1612 #ifdef CONFIG_PLATFORM_RTD2880B
1613 RTW_INFO("wlan link down\n");
1614 rtd2885_wlan_netlink_sendMsg("linkdown", "8712");
1615 #endif
1616 }
1617
1618 /*
1619 * drv_init() - a device potentially for us
1620 *
1621 * notes: drv_init() is called when the bus driver has located a card for us to support.
1622 * We accept the new device by returning 0.
1623 */
rtw_drv_init(struct pci_dev * pdev,const struct pci_device_id * pdid)1624 static int rtw_drv_init(struct pci_dev *pdev, const struct pci_device_id *pdid)
1625 {
1626 int i, err = -ENODEV;
1627
1628 int status = _FAIL;
1629 _adapter *padapter = NULL;
1630 struct dvobj_priv *dvobj;
1631 struct net_device *pnetdev;
1632
1633 RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("+rtw_drv_init\n"));
1634 /* RTW_INFO("+rtw_drv_init\n"); */
1635
1636 /* step 0. */
1637 disable_ht_for_spec_devid(pdid);
1638
1639 /* Initialize dvobj_priv */
1640 dvobj = pci_dvobj_init(pdev, pdid);
1641 if (dvobj == NULL) {
1642 RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("initialize device object priv Failed!\n"));
1643 goto exit;
1644 }
1645
1646 /* Initialize primary adapter */
1647 padapter = rtw_pci_primary_adapter_init(dvobj, pdev);
1648 if (padapter == NULL) {
1649 RTW_INFO("rtw_pci_primary_adapter_init Failed!\n");
1650 goto free_dvobj;
1651 }
1652
1653 /* Initialize virtual interface */
1654 #ifdef CONFIG_CONCURRENT_MODE
1655 if (padapter->registrypriv.virtual_iface_num > (CONFIG_IFACE_NUMBER - 1))
1656 padapter->registrypriv.virtual_iface_num = (CONFIG_IFACE_NUMBER - 1);
1657
1658 for (i = 0; i < padapter->registrypriv.virtual_iface_num; i++) {
1659 if (rtw_drv_add_vir_if(padapter, pci_set_intf_ops) == NULL) {
1660 RTW_INFO("rtw_drv_add_iface failed! (%d)\n", i);
1661 goto free_if_vir;
1662 }
1663 }
1664 #endif
1665
1666 #ifdef CONFIG_GLOBAL_UI_PID
1667 if (ui_pid[1] != 0) {
1668 RTW_INFO("ui_pid[1]:%d\n", ui_pid[1]);
1669 rtw_signal_process(ui_pid[1], SIGUSR2);
1670 }
1671 #endif
1672
1673 /* dev_alloc_name && register_netdev */
1674 if (rtw_os_ndevs_init(dvobj) != _SUCCESS)
1675 goto free_if_vir;
1676
1677 #ifdef CONFIG_HOSTAPD_MLME
1678 hostapd_mode_init(padapter);
1679 #endif
1680
1681 #ifdef CONFIG_PLATFORM_RTD2880B
1682 RTW_INFO("wlan link up\n");
1683 rtd2885_wlan_netlink_sendMsg("linkup", "8712");
1684 #endif
1685
1686 /* alloc irq */
1687 if (pci_alloc_irq(dvobj) != _SUCCESS)
1688 goto os_ndevs_deinit;
1689
1690 RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("-871x_drv - drv_init, success!\n"));
1691 /* RTW_INFO("-871x_drv - drv_init, success!\n"); */
1692
1693 status = _SUCCESS;
1694
1695 os_ndevs_deinit:
1696 if (status != _SUCCESS)
1697 rtw_os_ndevs_deinit(dvobj);
1698 free_if_vir:
1699 if (status != _SUCCESS) {
1700 #ifdef CONFIG_CONCURRENT_MODE
1701 rtw_drv_stop_vir_ifaces(dvobj);
1702 rtw_drv_free_vir_ifaces(dvobj);
1703 #endif
1704 }
1705
1706 if (status != _SUCCESS && padapter)
1707 rtw_pci_primary_adapter_deinit(padapter);
1708
1709 free_dvobj:
1710 if (status != _SUCCESS)
1711 pci_dvobj_deinit(pdev);
1712 exit:
1713 return status == _SUCCESS ? 0 : -ENODEV;
1714 }
1715
1716 /*
1717 * dev_remove() - our device is being removed
1718 */
1719 /* rmmod module & unplug(SurpriseRemoved) will call r871xu_dev_remove() => how to recognize both */
rtw_dev_remove(struct pci_dev * pdev)1720 static void rtw_dev_remove(struct pci_dev *pdev)
1721 {
1722 struct dvobj_priv *pdvobjpriv = pci_get_drvdata(pdev);
1723 _adapter *padapter = pdvobjpriv->padapters[IFACE_ID0];
1724 struct net_device *pnetdev = padapter->pnetdev;
1725
1726 _func_exit_;
1727
1728 if (pdvobjpriv->processing_dev_remove == _TRUE) {
1729 RTW_WARN("%s-line%d: Warning! device has been removed!\n", __FUNCTION__, __LINE__);
1730 return;
1731 }
1732
1733 RTW_INFO("+rtw_dev_remove\n");
1734
1735 pdvobjpriv->processing_dev_remove = _TRUE;
1736
1737 if (unlikely(!padapter))
1738 return;
1739
1740 /* TODO: use rtw_os_ndevs_deinit instead at the first stage of driver's dev deinit function */
1741 rtw_os_ndevs_unregister(pdvobjpriv);
1742 #ifdef CONFIG_NAPI
1743 netif_napi_del(&padapter->napi);
1744 #endif
1745
1746 #if 0
1747 #ifdef RTK_DMP_PLATFORM
1748 rtw_clr_surprise_removed(padapter); /* always trate as device exists*/
1749 /* this will let the driver to disable it's interrupt */
1750 #else
1751 if (pci_drvpriv.drv_registered == _TRUE) {
1752 /* RTW_INFO("r871xu_dev_remove():padapter->bSurpriseRemoved == _TRUE\n"); */
1753 rtw_set_surprise_removed(padapter);
1754 }
1755 /*else
1756 {
1757
1758 GET_HAL_DATA(padapter)->hw_init_completed = _FALSE;
1759
1760 }*/
1761 #endif
1762 #endif
1763
1764 #if defined(CONFIG_HAS_EARLYSUSPEND) || defined(CONFIG_ANDROID_POWER)
1765 rtw_unregister_early_suspend(dvobj_to_pwrctl(pdvobjpriv));
1766 #endif
1767
1768 if (padapter->bFWReady == _TRUE) {
1769 rtw_pm_set_ips(padapter, IPS_NONE);
1770 rtw_pm_set_lps(padapter, PS_MODE_ACTIVE);
1771
1772 LeaveAllPowerSaveMode(padapter);
1773 }
1774
1775 rtw_set_drv_stopped(padapter); /*for stop thread*/
1776 rtw_stop_cmd_thread(padapter);
1777 #ifdef CONFIG_CONCURRENT_MODE
1778 rtw_drv_stop_vir_ifaces(pdvobjpriv);
1779 #endif
1780
1781 #ifdef CONFIG_BT_COEXIST
1782 #ifdef CONFIG_BT_COEXIST_SOCKET_TRX
1783 if (GET_HAL_DATA(padapter)->EEPROMBluetoothCoexist)
1784 rtw_btcoex_close_socket(padapter);
1785 #endif
1786 rtw_btcoex_HaltNotify(padapter);
1787 #endif
1788
1789 rtw_pci_primary_adapter_deinit(padapter);
1790
1791 #ifdef CONFIG_CONCURRENT_MODE
1792 rtw_drv_free_vir_ifaces(pdvobjpriv);
1793 #endif
1794
1795 pci_dvobj_deinit(pdev);
1796
1797 RTW_INFO("-r871xu_dev_remove, done\n");
1798
1799 _func_exit_;
1800 return;
1801 }
1802
1803
rtw_drv_entry(void)1804 static int __init rtw_drv_entry(void)
1805 {
1806 int ret = 0;
1807
1808 RTW_PRINT("module init start\n");
1809 dump_drv_version(RTW_DBGDUMP);
1810 #ifdef BTCOEXVERSION
1811 RTW_PRINT(DRV_NAME" BT-Coex version = %s\n", BTCOEXVERSION);
1812 #endif /* BTCOEXVERSION */
1813
1814 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24))
1815 /* console_suspend_enabled=0; */
1816 #endif
1817
1818 pci_drvpriv.drv_registered = _TRUE;
1819 rtw_suspend_lock_init();
1820 rtw_drv_proc_init();
1821 rtw_ndev_notifier_register();
1822
1823 ret = pci_register_driver(&pci_drvpriv.rtw_pci_drv);
1824
1825 if (ret != 0) {
1826 pci_drvpriv.drv_registered = _FALSE;
1827 rtw_suspend_lock_uninit();
1828 rtw_drv_proc_deinit();
1829 rtw_ndev_notifier_unregister();
1830 goto exit;
1831 }
1832
1833 exit:
1834 RTW_PRINT("module init ret=%d\n", ret);
1835 return ret;
1836 }
1837
rtw_drv_halt(void)1838 static void __exit rtw_drv_halt(void)
1839 {
1840 RTW_PRINT("module exit start\n");
1841
1842 pci_drvpriv.drv_registered = _FALSE;
1843
1844 pci_unregister_driver(&pci_drvpriv.rtw_pci_drv);
1845
1846 rtw_suspend_lock_uninit();
1847 rtw_drv_proc_deinit();
1848 rtw_ndev_notifier_unregister();
1849
1850 RTW_PRINT("module exit success\n");
1851
1852 rtw_mstat_dump(RTW_DBGDUMP);
1853 }
1854
1855
1856 module_init(rtw_drv_entry);
1857 module_exit(rtw_drv_halt);
1858