1 /******************************************************************************
2 *
3 * Copyright(c) 2019 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 *****************************************************************************/
15 #ifndef _HAL_API_TMP_H_
16 #define _HAL_API_TMP_H_
17
18
19 /**** may be get from hal_com **********************************/
20
21 #define H2C_MSR_ROLE_RSVD 0
22 #define H2C_MSR_ROLE_STA 1
23 #define H2C_MSR_ROLE_AP 2
24 #define H2C_MSR_ROLE_GC 3
25 #define H2C_MSR_ROLE_GO 4
26 #define H2C_MSR_ROLE_TDLS 5
27 #define H2C_MSR_ROLE_ADHOC 6
28 #define H2C_MSR_ROLE_MESH 7
29 #define H2C_MSR_ROLE_MAX 8
30
31 /*************************************************************************************/
32 typedef enum _HW_VARIABLES {
33 HW_VAR_NET_TYPE,
34 HW_VAR_SET_OPMODE,
35 HW_VAR_MAC_ADDR,
36 HW_VAR_BSSID,
37 HW_VAR_BASIC_RATE,
38 HW_VAR_TXPAUSE,
39 HW_VAR_BCN_FUNC,
40 HW_VAR_CORRECT_TSF,
41 HW_VAR_RCR,
42 HW_VAR_MLME_DISCONNECT,
43 HW_VAR_MLME_SITESURVEY,
44 HW_VAR_MLME_JOIN,
45 HW_VAR_ON_RCR_AM,
46 HW_VAR_OFF_RCR_AM,
47 HW_VAR_BEACON_INTERVAL,
48 HW_VAR_SLOT_TIME,
49 HW_VAR_RESP_SIFS,
50 HW_VAR_ACK_PREAMBLE,
51 HW_VAR_SEC_CFG,
52 HW_VAR_SEC_DK_CFG,
53 HW_VAR_BCN_VALID,
54 HW_VAR_FREECNT,
55 HW_VAR_STOP_BCN,
56 HW_VAR_RESUME_BCN,
57
58 /* PHYDM odm->SupportAbility */
59 HW_VAR_CAM_EMPTY_ENTRY,
60 HW_VAR_CAM_INVALID_ALL,
61 HW_VAR_AC_PARAM_VO,
62 HW_VAR_AC_PARAM_VI,
63 HW_VAR_AC_PARAM_BE,
64 HW_VAR_AC_PARAM_BK,
65 HW_VAR_ACM_CTRL,
66 #ifdef CONFIG_WMMPS_STA
67 HW_VAR_UAPSD_TID,
68 #endif /* CONFIG_WMMPS_STA */
69 HW_VAR_AMPDU_MIN_SPACE,
70 #ifdef CONFIG_80211N_HT
71 HW_VAR_AMPDU_FACTOR,
72 #endif /* CONFIG_80211N_HT */
73 HW_VAR_RXDMA_AGG_PG_TH,
74 HW_VAR_SET_RPWM,
75 HW_VAR_CPWM,
76 HW_VAR_H2C_FW_PWRMODE,
77 HW_VAR_H2C_INACTIVE_IPS,
78 HW_VAR_H2C_FW_JOINBSSRPT,
79 HW_VAR_FWLPS_RF_ON,
80 HW_VAR_H2C_FW_P2P_PS_OFFLOAD,
81 #ifdef CONFIG_LPS_PG
82 HW_VAR_LPS_PG_HANDLE,
83 #endif
84 HW_VAR_TRIGGER_GPIO_0,
85 HW_VAR_BT_SET_COEXIST,
86 HW_VAR_BT_ISSUE_DELBA,
87 HW_VAR_FIFO_CLEARN_UP,
88 HW_VAR_RESTORE_HW_SEQ,
89 HW_VAR_CHECK_TXBUF,
90 HW_VAR_PCIE_STOP_TX_DMA,
91 HW_VAR_APFM_ON_MAC, /* Auto FSM to Turn On, include clock, isolation, power control for MAC only */
92 /* The valid upper nav range for the HW updating, if the true value is larger than the upper range, the HW won't update it. */
93 /* Unit in microsecond. 0 means disable this function. */
94 #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
95 HW_VAR_WOWLAN,
96 HW_VAR_WAKEUP_REASON,
97 #endif
98 HW_VAR_RPWM_TOG,
99 #ifdef CONFIG_GPIO_WAKEUP
100 HW_VAR_WOW_OUTPUT_GPIO,
101 HW_VAR_WOW_INPUT_GPIO,
102 HW_SET_GPIO_WL_CTRL,
103 #endif
104 HW_VAR_SYS_CLKR,
105 HW_VAR_NAV_UPPER,
106 HW_VAR_CHK_HI_QUEUE_EMPTY,
107 HW_VAR_CHK_MGQ_CPU_EMPTY,
108 HW_VAR_DL_BCN_SEL,
109 HW_VAR_AMPDU_MAX_TIME,
110 HW_VAR_WIRELESS_MODE,
111 HW_VAR_USB_MODE,
112 HW_VAR_PORT_SWITCH,
113 HW_VAR_PORT_CFG,
114 HW_VAR_DM_IN_LPS_LCLK,/*flag CONFIG_LPS_LCLK_WD_TIMER*/
115 #ifdef DBG_CHECK_FW_PS_STATE
116 HW_VAR_FW_PS_STATE,
117 #endif
118 HW_VAR_SOUNDING_ENTER,
119 HW_VAR_SOUNDING_LEAVE,
120 HW_VAR_SOUNDING_RATE,
121 HW_VAR_SOUNDING_STATUS,
122 HW_VAR_SOUNDING_FW_NDPA,
123 HW_VAR_SOUNDING_CLK,
124 HW_VAR_SOUNDING_SET_GID_TABLE,
125 HW_VAR_SOUNDING_CSI_REPORT,
126 HW_VAR_DL_RSVD_PAGE,
127 HW_VAR_DUMP_MAC_QUEUE_INFO,
128 HW_VAR_ASIX_IOT,
129 HW_VAR_CH_SW_NEED_TO_TAKE_CARE_IQK_INFO,
130 HW_VAR_CH_SW_IQK_INFO_BACKUP,
131 HW_VAR_CH_SW_IQK_INFO_RESTORE,
132
133 HW_VAR_DBI,
134 HW_VAR_MDIO,
135 HW_VAR_L1OFF_CAPABILITY,
136 HW_VAR_L1OFF_NIC_SUPPORT,
137 #ifdef CONFIG_TDLS
138 #ifdef CONFIG_TDLS_CH_SW
139 HW_VAR_TDLS_BCN_EARLY_C2H_RPT,
140 #endif
141 #endif
142 HW_VAR_DUMP_MAC_TXFIFO,
143 HW_VAR_PWR_CMD,
144
145 HW_VAR_SET_SOML_PARAM,
146 HW_VAR_ENABLE_RX_BAR,
147 HW_VAR_TSF_AUTO_SYNC,
148 HW_VAR_LPS_STATE_CHK,
149 #ifdef CONFIG_RTS_FULL_BW
150 HW_VAR_SET_RTS_BW,
151 #endif
152 #if defined(CONFIG_PCI_HCI)
153 HW_VAR_ENSWBCN,
154 #endif
155 HW_VAR_ACKTO,
156 HW_VAR_ACKTO_CCK,
157 } HW_VARIABLES;
158
rtw_hal_set_hwreg(_adapter * padapter,u8 var,u8 * val)159 static inline u8 rtw_hal_set_hwreg(_adapter *padapter, u8 var, u8 *val)
160 {
161 return 0;
162 }
rtw_hal_get_hwreg(_adapter * padapter,u8 var,u8 * val)163 static inline void rtw_hal_get_hwreg(_adapter *padapter, u8 var, u8 *val)
164 {}
165 typedef enum _HAL_DEF_VARIABLE {
166 HAL_DEF_IS_SUPPORT_ANT_DIV,
167 HAL_DEF_DBG_DUMP_RXPKT,/* for dbg */
168 HAL_DEF_BEAMFORMER_CAP,
169 HAL_DEF_BEAMFORMEE_CAP,
170 HW_VAR_MAX_RX_AMPDU_FACTOR,
171 HW_DEF_RA_INFO_DUMP,
172 HAL_DEF_DBG_DUMP_TXPKT,
173 HAL_DEF_TX_PAGE_SIZE,
174 HW_VAR_BEST_AMPDU_DENSITY,
175 } HAL_DEF_VARIABLE;
176
rtw_hal_set_def_var(_adapter * padapter,HAL_DEF_VARIABLE def_var,void * val)177 static inline u8 rtw_hal_set_def_var(_adapter *padapter, HAL_DEF_VARIABLE def_var, void *val)
178 {
179 return 0;
180 }
181
182 u8 rtw_hal_get_def_var(struct _ADAPTER *a,
183 enum _HAL_DEF_VARIABLE def_var, void *val);
184
rtw_hal_check_ips_status(_adapter * padapter)185 static inline u8 rtw_hal_check_ips_status(_adapter *padapter)
186 {
187 return 0;
188 }
189
190
rtw_hal_sec_read_cam_ent(_adapter * adapter,u8 id,u8 * ctrl,u8 * mac,u8 * key)191 static inline void rtw_hal_sec_read_cam_ent(_adapter *adapter, u8 id, u8 *ctrl, u8 *mac, u8 *key)
192 {}
rtw_hal_sec_write_cam_ent(_adapter * adapter,u8 id,u16 ctrl,u8 * mac,u8 * key)193 static inline void rtw_hal_sec_write_cam_ent(_adapter *adapter, u8 id, u16 ctrl, u8 *mac, u8 *key)
194 {}
rtw_hal_sec_clr_cam_ent(_adapter * adapter,u8 id)195 static inline void rtw_hal_sec_clr_cam_ent(_adapter *adapter, u8 id)
196 {}
rtw_hal_sec_read_cam_is_gk(_adapter * adapter,u8 id)197 static inline bool rtw_hal_sec_read_cam_is_gk(_adapter *adapter, u8 id)
198 {
199 return _TRUE;
200 }
201
rtw_hal_linked_info_dump(_adapter * padapter,u8 benable)202 static inline void rtw_hal_linked_info_dump(_adapter *padapter, u8 benable)
203 {}
204
rtw_hal_get_phy_edcca_flag(_adapter * adapter)205 static inline bool rtw_hal_get_phy_edcca_flag(_adapter *adapter)
206 {
207 return _TRUE;
208 }
209
rtw_hal_get_tsftr_by_port(_adapter * adapter,u8 port)210 static inline u64 rtw_hal_get_tsftr_by_port(_adapter *adapter, u8 port)
211 {
212 return 1;
213 }
214
rtw_hal_dump_rsvd_page(void * sel,_adapter * adapter,u8 page_offset,u8 page_num)215 static inline void rtw_hal_dump_rsvd_page(void *sel, _adapter *adapter, u8 page_offset, u8 page_num)
216 {}
217
218
219 /*u8 beamforming_get_htndp_tx_rate(void *dm_void, u8 bfer_str_num);*/
rtw_hal_get_htndp_tx_rate(_adapter * adapter,u8 bfer_str_num)220 static inline u8 rtw_hal_get_htndp_tx_rate(_adapter *adapter, u8 bfer_str_num)
221 {
222 return 0;
223 }
224 /*u8 beamforming_get_vht_ndp_tx_rate(void *dm_void, u8 bfer_str_num);*/
rtw_hal_get_vht_ndp_tx_rate(_adapter * adapter,u8 bfer_str_num)225 static inline u8 rtw_hal_get_vht_ndp_tx_rate(_adapter *adapter, u8 bfer_str_num)
226 {
227 return 0;
228 }
229
rtw_hal_get_sounding_info(_adapter * adapter,u16 * throughput,u8 total_bfee_num,u16 * tx_rate)230 static inline u8 rtw_hal_get_sounding_info(_adapter *adapter,u16 *throughput,
231 u8 total_bfee_num, u16 *tx_rate)
232 {
233 return 0;
234 }
235
rtw_hal_dump_target_tx_power(void * sel,_adapter * adapter)236 static inline void rtw_hal_dump_target_tx_power(void *sel, _adapter *adapter)
237 {}
238
rtw_hal_dump_tx_power_by_rate(void * sel,_adapter * adapter)239 static inline void rtw_hal_dump_tx_power_by_rate(void *sel, _adapter *adapter)
240 {}
241
rtw_hal_dump_macaddr(void * sel,_adapter * adapter)242 static inline void rtw_hal_dump_macaddr(void *sel, _adapter *adapter)
243 {}
244
rtw_hal_dump_trx_mode(void * sel,_adapter * adapter)245 static inline void rtw_hal_dump_trx_mode(void *sel, _adapter *adapter)
246 {}
247
rtw_hal_phy_adaptivity_parm_msg(void * sel,_adapter * adapter)248 static inline void rtw_hal_phy_adaptivity_parm_msg(void *sel, _adapter *adapter)
249 {}
250
rtw_hal_phy_adaptivity_parm_set(_adapter * adapter,s8 th_l2h_ini,s8 th_edcca_hl_diff)251 static inline void rtw_hal_phy_adaptivity_parm_set(_adapter *adapter,
252 s8 th_l2h_ini, s8 th_edcca_hl_diff)
253 {}
254
255
256
257 #if defined(CONFIG_RTW_LED) && defined(CONFIG_RTW_SW_LED)
258 #ifndef CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY
259 #define CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY 0
260 #endif
261
262 #if CONFIG_RTW_SW_LED_TRX_DA_CLASSIFY
263 void rtw_sw_led_blink_uc_trx_only(LED_DATA *led);
264 void rtw_sw_led_ctl_mode_uc_trx_only(_adapter *adapter, LED_CTL_MODE ctl);
265 #endif
266 void rtw_led_control(_adapter *adapter, LED_CTL_MODE ctl);
267 void rtw_led_tx_control(_adapter *adapter, const u8 *da);
268 void rtw_led_rx_control(_adapter *adapter, const u8 *da);
269 void rtw_led_set_iface_en(_adapter *adapter, u8 en);
270 void rtw_led_set_iface_en_mask(_adapter *adapter, u8 mask);
271 void rtw_led_set_ctl_en_mask(_adapter *adapter, u32 ctl_mask);
272 void rtw_led_set_ctl_en_mask_primary(_adapter *adapter);
273 void rtw_led_set_ctl_en_mask_virtual(_adapter *adapter);
274 #else
275 #define rtw_led_control(adapter, ctl) do {} while (0)
276 #define rtw_led_tx_control(adapter, da) do {} while (0)
277 #define rtw_led_rx_control(adapter, da) do {} while (0)
278 #define rtw_led_set_iface_en(adapter, en) do {} while (0)
279 #define rtw_led_set_iface_en_mask(adapter, mask) do {} while (0)
280 #define rtw_led_set_ctl_en_mask(adapter, ctl_mask) do {} while (0)
281 #define rtw_led_set_ctl_en_mask_primary(adapter) do {} while (0)
282 #define rtw_led_set_ctl_en_mask_virtual(adapter) do {} while (0)
283 #endif /* defined(CONFIG_RTW_LED) && defined(CONFIG_RTW_SW_LED) */
284
285 #ifdef CONFIG_PCI_HCI
rtw_hal_irp_reset(_adapter * padapter)286 static inline void rtw_hal_irp_reset(_adapter *padapter)
287 {}
rtw_hal_pci_dbi_write(_adapter * padapter,u16 addr,u8 data)288 static inline void rtw_hal_pci_dbi_write(_adapter *padapter, u16 addr, u8 data)
289 {}
rtw_hal_pci_dbi_read(_adapter * padapter,u16 addr)290 static inline u8 rtw_hal_pci_dbi_read(_adapter *padapter, u16 addr)
291 { return 0;}
rtw_hal_pci_mdio_write(_adapter * padapter,u8 addr,u16 data)292 static inline void rtw_hal_pci_mdio_write(_adapter *padapter, u8 addr, u16 data)
293 {}
rtw_hal_pci_mdio_read(_adapter * padapter,u8 addr)294 static inline u16 rtw_hal_pci_mdio_read(_adapter *padapter, u8 addr)
295 { return 0;}
rtw_hal_pci_l1off_nic_support(_adapter * padapter)296 static inline u8 rtw_hal_pci_l1off_nic_support(_adapter *padapter)
297 { return 0;}
298
rtw_hal_pci_l1off_capability(_adapter * padapter)299 static inline u8 rtw_hal_pci_l1off_capability(_adapter *padapter)
300 { return 0;}
301
rtw_hal_unmap_beacon_icf(_adapter * padapter)302 static inline void rtw_hal_unmap_beacon_icf(_adapter *padapter)
303 {
304 //hal->hal_ops.unmap_beacon_icf(padapter);
305 }
306 #endif
307
308 #if defined(CONFIG_PCI_HCI)
rtw_hal_check_nic_enough_desc_all(_adapter * padapter)309 static inline u8 rtw_hal_check_nic_enough_desc_all(_adapter *padapter)
310 { return _SUCCESS;}
rtw_hal_dump_xframe(_adapter * adapter,struct xmit_frame * pxmitframe)311 static s32 rtw_hal_dump_xframe(_adapter *adapter, struct xmit_frame *pxmitframe)
312 { return _SUCCESS;}
313
314
315 #endif
316
rtw_hal_macid_sleep(_adapter * adapter,u8 macid)317 static inline s32 rtw_hal_macid_sleep(_adapter *adapter, u8 macid)
318 { return 0;}
rtw_hal_macid_wakeup(_adapter * adapter,u8 macid)319 static inline s32 rtw_hal_macid_wakeup(_adapter *adapter, u8 macid)
320 { return 0;}
rtw_hal_macid_sleep_all_used(_adapter * adapter)321 static inline s32 rtw_hal_macid_sleep_all_used(_adapter *adapter)
322 { return 0;}
rtw_hal_macid_wakeup_all_used(_adapter * adapter)323 static inline s32 rtw_hal_macid_wakeup_all_used(_adapter *adapter)
324 { return 0;}
325
rtw_hal_c2h_pkt_hdl(_adapter * adapter,u8 * buf,u16 len)326 static void rtw_hal_c2h_pkt_hdl(_adapter *adapter, u8 *buf, u16 len)
327 {
328 //adapter->dvobj->hal_func.hal_mac_c2h_handler(adapter, buf, len);
329 }
rtw_hal_fill_h2c_cmd(_adapter * padapter,u8 ElementID,u32 CmdLen,u8 * pCmdBuffer)330 static inline s32 rtw_hal_fill_h2c_cmd(_adapter *padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer)
331 {
332 /*
333 _adapter *pri_adapter = GET_PRIMARY_ADAPTER(padapter);
334
335 if (GET_PHL_COM(pri_adapter)->fw_ready == _TRUE)
336 return hal->hal_ops.fill_h2c_cmd(padapter, ElementID, CmdLen, pCmdBuffer);
337 else if (padapter->registrypriv.mp_mode == 0)
338 RTW_PRINT(FUNC_ADPT_FMT" FW doesn't exit when no MP mode, by pass H2C id:0x%02x\n"
339 , FUNC_ADPT_ARG(padapter), ElementID);
340 */
341 return 0;
342 }
343
344 #ifdef CONFIG_DFS_MASTER
rtw_odm_radar_detect_reset(_adapter * adapter)345 static inline void rtw_odm_radar_detect_reset(_adapter *adapter)
346 {
347 //phydm_radar_detect_reset(adapter_to_phydm(adapter));
348 }
349
rtw_odm_radar_detect_disable(_adapter * adapter)350 static inline void rtw_odm_radar_detect_disable(_adapter *adapter)
351 {
352 //phydm_radar_detect_disable(adapter_to_phydm(adapter));
353 }
354
355 /* called after ch, bw is set */
rtw_odm_radar_detect_enable(_adapter * adapter)356 static inline void rtw_odm_radar_detect_enable(_adapter *adapter)
357 {
358 //phydm_radar_detect_enable(adapter_to_phydm(adapter));
359 }
360
rtw_odm_radar_detect(_adapter * adapter)361 static inline BOOLEAN rtw_odm_radar_detect(_adapter *adapter)
362 {
363 return 0;//phydm_radar_detect(adapter_to_phydm(adapter));
364 }
365
rtw_odm_radar_detect_polling_int_ms(struct dvobj_priv * dvobj)366 static inline u8 rtw_odm_radar_detect_polling_int_ms(struct dvobj_priv *dvobj)
367 {
368 return 0;//phydm_dfs_polling_time(dvobj_to_phydm(dvobj));
369 }
370 #endif /* CONFIG_DFS_MASTER */
371
rtw_hal_reqtxrpt(_adapter * padapter,u8 macid)372 static inline void rtw_hal_reqtxrpt(_adapter *padapter, u8 macid)
373 {
374 //if (hal->hal_ops.reqtxrpt)
375 //hal->hal_ops.reqtxrpt(padapter, macid);
376 }
rtw_hal_get_port(_adapter * adapter)377 static inline u8 rtw_hal_get_port(_adapter *adapter)
378 { return 0;}
379
rtw_hal_read_edca(_adapter * adapter,u16 * vo_params,u16 * vi_params,u16 * be_params,u16 * bk_params)380 static inline void rtw_hal_read_edca(_adapter *adapter, u16 *vo_params, u16 *vi_params,
381 u16 *be_params, u16 *bk_params)
382 {
383 //hal->hal_func.read_wmmedca_reg(padapter, vo_params, vi_params, be_params, bk_params);
384 }
385
rtw_hal_update_iqk_fw_offload_cap(_adapter * adapter)386 static inline void rtw_hal_update_iqk_fw_offload_cap(_adapter *adapter)
387 {}
388
rtw_hal_dump_sta_traffic(void * sel,_adapter * adapter,struct sta_info * psta)389 static inline void rtw_hal_dump_sta_traffic(void *sel, _adapter *adapter, struct sta_info *psta)
390 {}
rtw_hal_set_FwMediaStatusRpt_single_cmd(_adapter * adapter,bool opmode,bool miracast,bool miracast_sink,u8 role,u8 macid)391 static inline s32 rtw_hal_set_FwMediaStatusRpt_single_cmd
392 (_adapter *adapter, bool opmode, bool miracast, bool miracast_sink, u8 role, u8 macid)
393 { return 0;}
394
rtw_hal_rcr_set_chk_bssid(_adapter * adapter,u8 self_action)395 static inline void rtw_hal_rcr_set_chk_bssid(_adapter *adapter, u8 self_action)
396 {}
397
398 enum QSEL_ID {
399 QSLT_BK_ID,
400 QSLT_BE_ID,
401 QSLT_VI_ID,
402 QSLT_VO_ID,
403 QSLT_BEACON_ID,
404 QSLT_HIGH_ID,
405 QSLT_MGNT_ID,
406 QSLT_CMD_ID
407 };
408
rtw_hal_get_qsel(_adapter * adapter,enum QSEL_ID qsel)409 static inline u8 rtw_hal_get_qsel(_adapter *adapter, enum QSEL_ID qsel)
410 {
411 /*QSLT_HIGH*/
412 return 0;
413 }
414 /************************ xmit *******************/
rtw_hal_bcn_param_setting(_adapter * padapter)415 static inline void rtw_hal_bcn_param_setting(_adapter *padapter)
416 {
417 //hal->hal_ops.set_beacon_param_handler(padapter);
418 }
419
rtw_hal_set_tx_power_level(_adapter * adapter,u8 channel)420 static inline void rtw_hal_set_tx_power_level(_adapter *adapter, u8 channel)
421 {}
422
423
424 /****************** GEORGIA_TODO_REDEFINE_IO ************************/
rtw_hal_get_htsf(_adapter * adapter)425 static inline u32 rtw_hal_get_htsf(_adapter *adapter)/*get tst high 4 bytes */
426 {
427 return 0;
428 }
rtw_hal_get_ltsf(_adapter * adapter)429 static inline u32 rtw_hal_get_ltsf(_adapter *adapter)/*get tst low 4 bytes */
430 {
431 return 0;
432 }
433
rtw_hal_get_dma_statu(_adapter * adapter)434 static inline u32 rtw_hal_get_dma_statu(_adapter *adapter)
435 {
436 return 0;
437 }
438 #ifdef DBG_TXBD_DESC_DUMP
rtw_hal_get_txbd_rwreg(_adapter * adapter)439 static inline u32 rtw_hal_get_txbd_rwreg(_adapter *adapter)
440 {
441 return 0;
442 }
443 #endif
444
445 #ifdef RTW_SUPPORT_PLATFORM_SHUTDOWN
rtw_hal_sdio_leave_suspend(_adapter * adapter)446 static inline u8 rtw_hal_sdio_leave_suspend(_adapter *adapter)
447 {
448 return 0;
449 }
450 #endif
451
452 #if defined(CONFIG_FWLPS_IN_IPS)
rtw_hal_set_fw_in_ips_mode(_adapter * padapter,u8 enable)453 static inline void rtw_hal_set_fw_in_ips_mode(_adapter *padapter, u8 enable)
454 {}
455 #endif
456 #ifdef CONFIG_LPS_RPWM_TIMER
rtw_hal_is_leave_ps(_adapter * padapter)457 static inline bool rtw_hal_is_leave_ps(_adapter *padapter)
458 {
459 return _FALSE;
460 }
461 #endif
462
463
rtw_hal_get_version(char * str,u32 len)464 static inline void rtw_hal_get_version(char *str, u32 len)
465 {
466 //get hal version
467 //rtw_halmac_get_version(str, 30);
468 // get fw version
469 // get phy (bb/rf) version
470 // get btc version
471 }
472
473
474 #endif /*_HAL_API_TMP_H_*/
475