1 /******************************************************************************
2 *
3 * Copyright(c) 2015 - 2016 Realtek Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 *
19 ******************************************************************************/
20
21 #define _RTL8822BE_HALINIT_C_
22 #include <drv_types.h> /* PADAPTER, basic_types.h and etc. */
23 #include <hal_data.h> /* HAL_DATA_TYPE */
24 #include "../rtl8822b.h"
25 #include "rtl8822be.h"
26
InitMAC_TRXBD_8822BE(PADAPTER Adapter)27 u32 InitMAC_TRXBD_8822BE(PADAPTER Adapter)
28 {
29 u8 tmpU1b;
30 u16 tmpU2b;
31 u32 tmpU4b;
32 int q_idx;
33 struct recv_priv *precvpriv = &Adapter->recvpriv;
34 struct xmit_priv *pxmitpriv = &Adapter->xmitpriv;
35 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
36
37 RTW_INFO("=======>InitMAC_TXBD_8822BE()\n");
38
39 /*
40 * Set CMD TX BD (buffer descriptor) physical address(from OS API).
41 */
42 rtw_write32(Adapter, REG_H2CQ_TXBD_DESA_8822B,
43 (u64)pxmitpriv->tx_ring[TXCMD_QUEUE_INX].dma &
44 DMA_BIT_MASK(32));
45 rtw_write32(Adapter, REG_H2CQ_TXBD_NUM_8822B,
46 TX_BD_NUM_8822BE_CMD | ((RTL8822BE_SEG_NUM << 12) &
47 0x3000));
48
49 #ifdef CONFIG_64BIT_DMA
50 rtw_write32(Adapter, REG_H2CQ_TXBD_DESA_8822B + 4,
51 ((u64)pxmitpriv->tx_ring[TXCMD_QUEUE_INX].dma) >> 32);
52 #endif
53 /*
54 * Set TX/RX BD (buffer descriptor) physical address(from OS API).
55 */
56 rtw_write32(Adapter, REG_BCNQ_TXBD_DESA_8822B,
57 (u64)pxmitpriv->tx_ring[BCN_QUEUE_INX].dma &
58 DMA_BIT_MASK(32));
59 rtw_write32(Adapter, REG_MGQ_TXBD_DESA_8822B,
60 (u64)pxmitpriv->tx_ring[MGT_QUEUE_INX].dma &
61 DMA_BIT_MASK(32));
62 rtw_write32(Adapter, REG_VOQ_TXBD_DESA_8822B,
63 (u64)pxmitpriv->tx_ring[VO_QUEUE_INX].dma &
64 DMA_BIT_MASK(32));
65 rtw_write32(Adapter, REG_VIQ_TXBD_DESA_8822B,
66 (u64)pxmitpriv->tx_ring[VI_QUEUE_INX].dma &
67 DMA_BIT_MASK(32));
68 rtw_write32(Adapter, REG_BEQ_TXBD_DESA_8822B,
69 (u64)pxmitpriv->tx_ring[BE_QUEUE_INX].dma &
70 DMA_BIT_MASK(32));
71
72 /* vincent sync windows */
73 tmpU4b = rtw_read32(Adapter, REG_BEQ_TXBD_DESA_8822B);
74
75 rtw_write32(Adapter, REG_BKQ_TXBD_DESA_8822B,
76 (u64)pxmitpriv->tx_ring[BK_QUEUE_INX].dma &
77 DMA_BIT_MASK(32));
78 rtw_write32(Adapter, REG_HI0Q_TXBD_DESA_8822B,
79 (u64)pxmitpriv->tx_ring[HIGH_QUEUE_INX].dma &
80 DMA_BIT_MASK(32));
81 rtw_write32(Adapter, REG_RXQ_RXBD_DESA_8822B,
82 (u64)precvpriv->rx_ring[RX_MPDU_QUEUE].dma &
83 DMA_BIT_MASK(32));
84
85 #ifdef CONFIG_64BIT_DMA
86 /*
87 * 2009/10/28 MH For DMA 64 bits. We need to assign the high
88 * 32 bit address for NIC HW to transmit data to correct path.
89 */
90 rtw_write32(Adapter, REG_BCNQ_TXBD_DESA_8822B + 4,
91 ((u64)pxmitpriv->tx_ring[BCN_QUEUE_INX].dma) >> 32);
92 rtw_write32(Adapter, REG_MGQ_TXBD_DESA_8822B + 4,
93 ((u64)pxmitpriv->tx_ring[MGT_QUEUE_INX].dma) >> 32);
94 rtw_write32(Adapter, REG_VOQ_TXBD_DESA_8822B + 4,
95 ((u64)pxmitpriv->tx_ring[VO_QUEUE_INX].dma) >> 32);
96 rtw_write32(Adapter, REG_VIQ_TXBD_DESA_8822B + 4,
97 ((u64)pxmitpriv->tx_ring[VI_QUEUE_INX].dma) >> 32);
98 rtw_write32(Adapter, REG_BEQ_TXBD_DESA_8822B + 4,
99 ((u64)pxmitpriv->tx_ring[BE_QUEUE_INX].dma) >> 32);
100 rtw_write32(Adapter, REG_BKQ_TXBD_DESA_8822B + 4,
101 ((u64)pxmitpriv->tx_ring[BK_QUEUE_INX].dma) >> 32);
102 rtw_write32(Adapter, REG_HI0Q_TXBD_DESA_8822B + 4,
103 ((u64)pxmitpriv->tx_ring[HIGH_QUEUE_INX].dma) >> 32);
104 rtw_write32(Adapter, REG_RXQ_RXBD_DESA_8822B + 4,
105 ((u64)precvpriv->rx_ring[RX_MPDU_QUEUE].dma) >> 32);
106
107
108 /* 2009/10/28 MH If RX descriptor address is not equal to zero.
109 * We will enable DMA 64 bit functuion.
110 * Note: We never saw thd consition which the descripto address are
111 * divided into 4G down and 4G upper separate area.
112 */
113 if (((u64)precvpriv->rx_ring[RX_MPDU_QUEUE].dma) >> 32 != 0) {
114 RTW_INFO("Enable DMA64 bit\n");
115
116 /* Check if other descriptor address is zero and
117 * abnormally be in 4G lower area. */
118 if (((u64)pxmitpriv->tx_ring[MGT_QUEUE_INX].dma) >> 32)
119 RTW_INFO("MGNT_QUEUE HA=0\n");
120
121 PlatformEnableDMA64(Adapter);
122 } else
123 RTW_INFO("Enable DMA32 bit\n");
124 #endif
125
126 /* pci buffer descriptor mode: Reset the Read/Write point to 0 */
127 PlatformEFIOWrite4Byte(Adapter, REG_TSFTIMER_HCI_8822B, 0x3fffffff);
128
129 /* Reset the H2CQ R/W point index to 0 */
130 tmpU4b = rtw_read32(Adapter, REG_H2CQ_CSR_8822B);
131 rtw_write32(Adapter, REG_H2CQ_CSR_8822B, (tmpU4b | BIT8 | BIT16));
132
133 tmpU1b = rtw_read8(Adapter, REG_PCIE_CTRL + 3);
134 rtw_write8(Adapter, REG_PCIE_CTRL + 3, (tmpU1b | 0xF7));
135
136 /* 20100318 Joseph: Reset interrupt migration setting
137 * when initialization. Suggested by SD1. */
138 rtw_write32(Adapter, REG_INT_MIG, 0);
139 pHalData->bInterruptMigration = _FALSE;
140
141 /* 2009.10.19. Reset H2C protection register. by tynli. */
142 rtw_write32(Adapter, REG_MCUTST_I_8822B, 0x0);
143
144 #if MP_DRIVER == 1
145 if (Adapter->registrypriv.mp_mode == 1) {
146 rtw_write32(Adapter, REG_MACID, 0x87654321);
147 rtw_write32(Adapter, 0x0700, 0x87654321);
148 }
149 #endif
150
151 /* pic buffer descriptor mode: */
152 /* ---- tx */
153 rtw_write16(Adapter, REG_MGQ_TXBD_NUM_8822B,
154 TX_BD_NUM_8822BE | ((RTL8822BE_SEG_NUM << 12) & 0x3000));
155 rtw_write16(Adapter, REG_VOQ_TXBD_NUM_8822B,
156 TX_BD_NUM_8822BE | ((RTL8822BE_SEG_NUM << 12) & 0x3000));
157 rtw_write16(Adapter, REG_VIQ_TXBD_NUM_8822B,
158 TX_BD_NUM_8822BE | ((RTL8822BE_SEG_NUM << 12) & 0x3000));
159 rtw_write16(Adapter, REG_BEQ_TXBD_NUM_8822B,
160 TX_BD_NUM_8822BE | ((RTL8822BE_SEG_NUM << 12) & 0x3000));
161 rtw_write16(Adapter, REG_BKQ_TXBD_NUM_8822B,
162 TX_BD_NUM_8822BE | ((RTL8822BE_SEG_NUM << 12) & 0x3000));
163 rtw_write16(Adapter, REG_HI0Q_TXBD_NUM_8822B,
164 TX_BD_NUM_8822BE | ((RTL8822BE_SEG_NUM << 12) & 0x3000));
165 rtw_write16(Adapter, REG_HI1Q_TXBD_NUM_8822B,
166 TX_BD_NUM_8822BE | ((RTL8822BE_SEG_NUM << 12) & 0x3000));
167 rtw_write16(Adapter, REG_HI2Q_TXBD_NUM_8822B,
168 TX_BD_NUM_8822BE | ((RTL8822BE_SEG_NUM << 12) & 0x3000));
169 rtw_write16(Adapter, REG_HI3Q_TXBD_NUM_8822B,
170 TX_BD_NUM_8822BE | ((RTL8822BE_SEG_NUM << 12) & 0x3000));
171 rtw_write16(Adapter, REG_HI4Q_TXBD_NUM_8822B,
172 TX_BD_NUM_8822BE | ((RTL8822BE_SEG_NUM << 12) & 0x3000));
173 rtw_write16(Adapter, REG_HI5Q_TXBD_NUM_8822B,
174 TX_BD_NUM_8822BE | ((RTL8822BE_SEG_NUM << 12) & 0x3000));
175 rtw_write16(Adapter, REG_HI6Q_TXBD_NUM_8822B,
176 TX_BD_NUM_8822BE | ((RTL8822BE_SEG_NUM << 12) & 0x3000));
177 rtw_write16(Adapter, REG_HI7Q_TXBD_NUM_8822B,
178 TX_BD_NUM_8822BE | ((RTL8822BE_SEG_NUM << 12) & 0x3000));
179
180 /* rx. support 32 bits in linux */
181
182
183 /* using 64bit
184 rtw_write16(Adapter, REG_RX_RXBD_NUM_8822B,
185 RX_BD_NUM_8822BE |((RTL8822BE_SEG_NUM<<13 ) & 0x6000) |0x8000);
186 */
187
188
189 /* using 32bit */
190 rtw_write16(Adapter, REG_RX_RXBD_NUM_8822B,
191 RX_BD_NUM_8822BE | ((RTL8822BE_SEG_NUM << 13) & 0x6000));
192
193 /* reset read/write point */
194 rtw_write32(Adapter, REG_TSFTIMER_HCI_8822B, 0XFFFFFFFF);
195
196 #if 1 /* vincent windows */
197 /* Start debug mode */
198 {
199 u8 reg0x3f3 = 0;
200
201 reg0x3f3 = rtw_read8(Adapter, 0x3f3);
202 rtw_write8(Adapter, 0x3f3, reg0x3f3 | BIT2);
203 }
204
205 {
206 /* Need to disable BT coex to let MP tool Tx, this would be done in FW
207 * in the future, suggest by ChunChu, 2015.05.19
208 */
209
210 u8 tmp1Byte;
211 u16 tmp2Byte;
212 u32 tmp4Byte;
213
214 tmp2Byte = rtw_read16(Adapter, REG_SYS_FUNC_EN_8822B);
215 rtw_write16(Adapter, REG_SYS_FUNC_EN_8822B, tmp2Byte | BIT10);
216 tmp1Byte = rtw_read8(Adapter, REG_DIS_TXREQ_CLR_8822B);
217 rtw_write8(Adapter, REG_DIS_TXREQ_CLR_8822B, tmp1Byte | BIT7);
218 tmp4Byte = rtw_read32(Adapter, 0x1080);
219 rtw_write32(Adapter, 0x1080, tmp4Byte | BIT16);
220 }
221 #endif
222
223 RTW_INFO("InitMAC_TXBD_8822BE() <====\n");
224
225 return _SUCCESS;
226 }
227
228
229 static VOID
Hal_DBIWrite1Byte_8822BE(IN PADAPTER Adapter,IN u2Byte Addr,IN u1Byte Data)230 Hal_DBIWrite1Byte_8822BE(
231 IN PADAPTER Adapter,
232 IN u2Byte Addr,
233 IN u1Byte Data
234 )
235 {
236 u1Byte tmpU1b = 0, count = 0;
237 u2Byte WriteAddr = 0, Remainder = Addr % 4;
238
239
240 /* Write DBI 1Byte Data */
241 WriteAddr = REG_DBI_WDATA_V1_8822B + Remainder;
242 rtw_write8(Adapter, WriteAddr, Data);
243
244 /* Write DBI 2Byte Address & Write Enable */
245 WriteAddr = (Addr & 0xfffc) | (BIT0 << (Remainder + 12));
246 rtw_write16(Adapter, REG_DBI_FLAG_V1_8822B, WriteAddr);
247
248 /* Write DBI Write Flag */
249 rtw_write8(Adapter, REG_DBI_FLAG_V1_8822B + 2, 0x1);
250
251 tmpU1b = rtw_read8(Adapter, REG_DBI_FLAG_V1_8822B + 2);
252 count = 0;
253 while (tmpU1b && count < 20) {
254 rtw_udelay_os(10);
255 tmpU1b = rtw_read8(Adapter, REG_DBI_FLAG_V1_8822B + 2);
256 count++;
257 }
258 }
259
260 /* Description:
261 * PCI configuration space read operation on RTL814AE
262 *
263 * modify by gw from 8192EE
264 *
265 * [copy] from win driver */
266 static u1Byte
Hal_DBIRead1Byte_8822BE(IN PADAPTER Adapter,IN u2Byte Addr)267 Hal_DBIRead1Byte_8822BE(
268 IN PADAPTER Adapter,
269 IN u2Byte Addr
270 )
271 {
272 u2Byte ReadAddr = Addr & 0xfffc;
273 u1Byte ret = 0, tmpU1b = 0, count = 0;
274
275 rtw_write16(Adapter, REG_DBI_FLAG_V1_8822B, ReadAddr);
276 rtw_write8(Adapter, REG_DBI_FLAG_V1_8822B + 2, 0x2);
277 tmpU1b = rtw_read8(Adapter, REG_DBI_FLAG_V1_8822B + 2);
278 count = 0;
279 while (tmpU1b && count < 20) {
280 rtw_udelay_os(10);
281 tmpU1b = rtw_read8(Adapter, REG_DBI_FLAG_V1_8822B + 2);
282 count++;
283 }
284 if (0 == tmpU1b) {
285 ReadAddr = REG_DBI_RDATA_V1_8822B + Addr % 4;
286 ret = rtw_read8(Adapter, ReadAddr);
287 }
288
289 return ret;
290 }
291
EnableAspmBackDoor_8822BE(PADAPTER Adapter)292 VOID EnableAspmBackDoor_8822BE(PADAPTER Adapter)
293 {
294 u1Byte tmp1byte = 0;
295
296 printk("%s\n",__FUNCTION__);
297
298 //Bit7 for L0s
299 tmp1byte = Hal_DBIRead1Byte_8822BE(Adapter, 0x70f);
300 Hal_DBIWrite1Byte_8822BE(Adapter, 0x70f, (tmp1byte | BIT7 ));
301
302 //Bit 3 for L1 , Bit4 for clock req
303 tmp1byte = Hal_DBIRead1Byte_8822BE(Adapter, 0x719);
304 Hal_DBIWrite1Byte_8822BE(Adapter, 0x719, (tmp1byte | BIT3 | BIT4));
305
306
307
308 }
309
EnableL1Off_8822BE(PADAPTER Adapter)310 VOID EnableL1Off_8822BE(PADAPTER Adapter)
311 {
312 u1Byte tmp1byte = 0;
313
314 //Bit5 for L1SS
315 tmp1byte = Hal_DBIRead1Byte_8822BE(Adapter, 0x718);
316 Hal_DBIWrite1Byte_8822BE(Adapter, 0x718, (tmp1byte | BIT5 ));
317
318 }
319
EnableAspmBackDoor_8822BE_old(PADAPTER Adapter)320 VOID EnableAspmBackDoor_8822BE_old(PADAPTER Adapter)
321 {
322 u32 tmp4Byte = 0, count = 0;
323 u8 tmp1byte = 0;
324
325 /* 0x70f BIT7 is used to control L0S
326 * 20100212 Tynli: Set register offset 0x70f in PCI configuration space to the value 0x23
327 * for all bridge suggested by SD1. Origianally this is only for INTEL.
328 * 20100422 Joseph: Set PCI configuration space offset 0x70F to 0x93 to Enable L0s for all platform.
329 * This is suggested by SD1 Glayrainx and for Lenovo's request.
330 * 20120316 YJ: Use BIT31|value(read from 0x70C) intead of 0x93.
331 */
332 rtw_write16(Adapter, REG_DBI_FLAG_V1_8822B, 0x70c);
333 rtw_write8(Adapter, REG_DBI_FLAG_V1_8822B+2, 0x2);
334 tmp1byte = rtw_read8(Adapter, REG_DBI_FLAG_V1_8822B+2);
335 count = 0;
336 while(tmp1byte && count < 20) {
337 rtw_udelay_os(10);
338 tmp1byte = rtw_read8(Adapter, REG_DBI_FLAG_V1_8822B+2);
339 count++;
340 }
341 if(0 == tmp1byte) {
342 tmp4Byte=rtw_read32(Adapter, REG_DBI_RDATA_V1_8822B);
343 rtw_write32(Adapter, REG_DBI_WDATA_V1_8822B, tmp4Byte|BIT31);
344 rtw_write16(Adapter, REG_DBI_FLAG_V1_8822B, 0xf70c);
345 rtw_write8(Adapter, REG_DBI_FLAG_V1_8822B+2, 0x1);
346 }
347
348 tmp1byte = rtw_read8(Adapter, REG_DBI_FLAG_V1_8822B+2);
349 count = 0;
350 while(tmp1byte && count < 20) {
351 rtw_udelay_os(10);
352 tmp1byte = rtw_read8(Adapter, REG_DBI_FLAG_V1_8822B+2);
353 count++;
354 }
355
356 /* 0x719 Bit3 is for L1 BIT4 is for clock request
357 * 20100427 Joseph: Disable L1 for Toshiba AMD platform. If AMD platform do not contain
358 * L1 patch, driver shall disable L1 backdoor.
359 * 20120316 YJ: Use BIT11|BIT12|value(read from 0x718) intead of 0x1b.
360 */
361 rtw_write16(Adapter, REG_DBI_FLAG_V1_8822B, 0x718);
362 rtw_write8(Adapter, REG_DBI_FLAG_V1_8822B+2, 0x2);
363 tmp1byte = rtw_read8(Adapter, REG_DBI_FLAG_V1_8822B+2);
364 count = 0;
365 while(tmp1byte && count < 20) {
366 rtw_udelay_os(10);
367 tmp1byte = rtw_read8(Adapter, REG_DBI_FLAG_V1_8822B+2);
368 count++;
369 }
370
371 if(GET_HAL_DATA(Adapter)->bSupportBackDoor || (0 == tmp1byte)) {
372 tmp4Byte = rtw_read32(Adapter, REG_DBI_RDATA_V1_8822B);
373 rtw_write32(Adapter, REG_DBI_WDATA_V1_8822B, tmp4Byte|BIT11|BIT12);
374 rtw_write16(Adapter, REG_DBI_FLAG_V1_8822B, 0xf718);
375 rtw_write8(Adapter, REG_DBI_FLAG_V1_8822B+2, 0x1);
376 }
377 tmp1byte = rtw_read8(Adapter, REG_DBI_FLAG_V1_8822B+2);
378 count = 0;
379 while(tmp1byte && count < 20) {
380 rtw_udelay_os(10);
381 tmp1byte = rtw_read8(Adapter, REG_DBI_FLAG_V1_8822B+2);
382 count++;
383 }
384 }
385
rtl8822be_init(PADAPTER padapter)386 u32 rtl8822be_init(PADAPTER padapter)
387 {
388 u8 ok = _TRUE;
389 u8 val8;
390 struct registry_priv *registry_par = &padapter->registrypriv;
391 PHAL_DATA_TYPE hal;
392
393 hal = GET_HAL_DATA(padapter);
394
395 InitMAC_TRXBD_8822BE(padapter);
396
397 ok = rtl8822b_hal_init(padapter);
398 if (_FALSE == ok)
399 return _FAIL;
400
401 #if defined(USING_RX_TAG)
402 /* have to init after halmac init */
403 val8 = rtw_read8(padapter, REG_PCIE_CTRL_8822B + 2);
404 rtw_write8(padapter, REG_PCIE_CTRL_8822B + 2, (val8 | BIT4));
405 rtw_write16(padapter, REG_PCIE_CTRL_8822B, 0x8000);
406 #else
407 rtw_write16(padapter, REG_PCIE_CTRL_8822B, 0x0000);
408 #endif
409
410 rtw_write8(padapter, REG_RX_DRVINFO_SZ_8822B, 0x4);
411
412 rtl8822b_phy_init_haldm(padapter);
413 #ifdef CONFIG_BEAMFORMING
414 rtl8822b_phy_init_beamforming(padapter);
415 #endif
416
417 #ifdef CONFIG_BT_COEXIST
418 /* Init BT hw config. */
419 if (_TRUE == hal->EEPROMBluetoothCoexist)
420 rtw_btcoex_HAL_Initialize(padapter, _FALSE);
421 #endif /* CONFIG_BT_COEXIST */
422
423 //EnableAspmBackDoor_8822BE(padapter);
424 //EnableL1Off_8822BE(padapter);
425
426 rtl8822b_init_misc(padapter);
427
428 #if 0
429 /* disable pre_tx */
430 val8 = rtw_read8(padapter, REG_SW_AMPDU_BURST_MODE_CTRL_8822B);
431 val8 &= ~BIT(6);
432 rtw_write8(padapter, REG_SW_AMPDU_BURST_MODE_CTRL_8822B, val8);
433
434 /* set ampdu count to 0x3F */
435 rtw_write8(padapter, 0x4CA, 0x3F);
436 rtw_write8(padapter, 0x4CB, 0x3F);
437 #endif
438
439 return _SUCCESS;
440 }
441
rtl8822be_init_default_value(PADAPTER padapter)442 void rtl8822be_init_default_value(PADAPTER padapter)
443 {
444 PHAL_DATA_TYPE pHalData;
445
446
447 pHalData = GET_HAL_DATA(padapter);
448
449 rtl8822b_init_default_value(padapter);
450
451 /* interface related variable */
452 pHalData->CurrentWirelessMode = WIRELESS_MODE_AUTO;
453 pHalData->bDefaultAntenna = 1;
454 pHalData->TransmitConfig = BIT_CFEND_FORMAT | BIT_WMAC_TCR_ERRSTEN_3;
455
456 /* Set RCR-Receive Control Register .
457 * The value is set in InitializeAdapter8190Pci().
458 */
459 pHalData->ReceiveConfig = (
460 #ifdef CONFIG_RX_PACKET_APPEND_FCS
461 BIT_APP_FCS |
462 #endif
463 BIT_APP_MIC |
464 BIT_APP_ICV |
465 BIT_APP_PHYSTS |
466 BIT_VHT_DACK |
467 BIT_HTC_LOC_CTRL |
468 /* BIT_AMF | */
469 BIT_CBSSID_DATA |
470 BIT_CBSSID_BCN |
471 /* BIT_ACF | */
472 /* BIT_ADF | */ /* PS-Poll filter */
473 BIT_AB |
474 BIT_AB |
475 BIT_APM |
476 0);
477
478 /*
479 * Set default value of Interrupt Mask Register0
480 */
481 pHalData->IntrMaskDefault[0] = (u32)(
482 BIT(29) | /* BIT_PSTIMEOUT */
483 BIT(27) | /* BIT_GTINT3 */
484 BIT_TXBCN0ERR_MSK |
485 BIT_TXBCN0OK_MSK |
486 BIT_BCNDMAINT0_MSK |
487 BIT_HSISR_IND_ON_INT_MSK |
488 BIT_C2HCMD_MSK |
489 BIT_HIGHDOK_MSK |
490 BIT_MGTDOK_MSK |
491 BIT_BKDOK_MSK |
492 BIT_BEDOK_MSK |
493 BIT_VIDOK_MSK |
494 BIT_VODOK_MSK |
495 BIT_RDU_MSK |
496 BIT_RXOK_MSK |
497 0);
498
499 /*
500 * Set default value of Interrupt Mask Register1
501 */
502 pHalData->IntrMaskDefault[1] = (u32)(
503 BIT(9) | /* TXFOVW */
504 BIT_FOVW_MSK |
505 0);
506
507 /*
508 * Set default value of Interrupt Mask Register3
509 */
510 pHalData->IntrMaskDefault[3] = (u32)(
511 BIT_SETH2CDOK_MASK | /* H2C_TX_OK */
512 0);
513
514 /* 2012/03/27 hpfan Add for win8 DTM DPC ISR test */
515 pHalData->IntrMaskReg[0] = (u32)(
516 BIT_RDU_MSK |
517 BIT(29) | /* BIT_PSTIMEOUT */
518 0);
519
520 pHalData->IntrMaskReg[1] = (u32)(
521 BIT_C2HCMD_MSK |
522 0);
523
524 pHalData->IntrMask[0] = pHalData->IntrMaskDefault[0];
525 pHalData->IntrMask[1] = pHalData->IntrMaskDefault[1];
526 pHalData->IntrMask[3] = pHalData->IntrMaskDefault[3];
527
528 }
529