1 /******************************************************************************
2 *
3 * Copyright(c) 2015 - 2016 Realtek Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 *
19 ******************************************************************************/
20 #define _RTL8822B_OPS_C_
21
22 #include <drv_types.h> /* basic_types.h, rtw_io.h and etc. */
23 #include <rtw_xmit.h> /* struct xmit_priv */
24 #ifdef DBG_CONFIG_ERROR_DETECT
25 #include <rtw_sreset.h>
26 #endif /* DBG_CONFIG_ERROR_DETECT */
27 #include <hal_data.h> /* PHAL_DATA_TYPE, GET_HAL_DATA() */
28 #include <hal_com.h> /* rtw_hal_config_rftype(), dump_chip_info() and etc. */
29 #include "../hal_halmac.h" /* GET_RX_DESC_XXX_8822B() */
30 #include "rtl8822b.h"
31 #include "rtl8822b_hal.h"
32
33 static const struct hw_port_reg port_cfg[] = {
34 /*port 0*/
35 {
36 .net_type = (REG_CR_8822B + 2),
37 .net_type_shift = 0,
38 .macaddr = REG_MACID_8822B,
39 .bssid = REG_BSSID_8822B,
40 .bcn_ctl = REG_BCN_CTRL_8822B,
41 .tsf_rst = REG_DUAL_TSF_RST,
42 .tsf_rst_bit = BIT_TSFTR_RST_8822B,
43 .bcn_space = REG_MBSSID_BCN_SPACE_8822B,
44 .bcn_space_shift = 0,
45 .bcn_space_mask = 0xffff,
46 },
47 /*port 1*/
48 {
49 .net_type = (REG_CR_8822B + 2),
50 .net_type_shift = 2,
51 .macaddr = REG_MACID1_8822B,
52 .bssid = REG_BSSID1_8822B,
53 .bcn_ctl = REG_BCN_CTRL_CLINT0_8822B,
54 .tsf_rst = REG_DUAL_TSF_RST,
55 .tsf_rst_bit = BIT_TSFTR_CLI0_RST_8822B,
56 .bcn_space = REG_MBSSID_BCN_SPACE_8822B,
57 .bcn_space_shift = 16,
58 .bcn_space_mask = 0xfff,
59 },
60 /*port 2*/
61 {
62 .net_type = REG_CR_EXT_8822B,
63 .net_type_shift = 0,
64 .macaddr = REG_MACID2_8822B,
65 .bssid = REG_BSSID2_8822B,
66 .bcn_ctl = REG_BCN_CTRL_CLINT1_8822B,
67 .tsf_rst = REG_DUAL_TSF_RST,
68 .tsf_rst_bit = BIT_TSFTR_CLI1_RST_8822B,
69 .bcn_space = REG_MBSSID_BCN_SPACE2_8822B,
70 .bcn_space_shift = 0,
71 .bcn_space_mask = 0xfff,
72 },
73 /*port 3*/
74 {
75 .net_type = REG_CR_EXT_8822B,
76 .net_type_shift = 2,
77 .macaddr = REG_MACID3_8822B,
78 .bssid = REG_BSSID3_8822B,
79 .bcn_ctl = REG_BCN_CTRL_CLINT2_8822B,
80 .tsf_rst = REG_DUAL_TSF_RST,
81 .tsf_rst_bit = BIT_TSFTR_CLI2_RST_8822B,
82 .bcn_space = REG_MBSSID_BCN_SPACE2_8822B,
83 .bcn_space_shift = 16,
84 .bcn_space_mask = 0xfff,
85 },
86 /*port 4*/
87 {
88 .net_type = REG_CR_EXT_8822B,
89 .net_type_shift = 4,
90 .macaddr = REG_MACID4_8822B,
91 .bssid = REG_BSSID4_8822B,
92 .bcn_ctl = REG_BCN_CTRL_CLINT3_8822B,
93 .tsf_rst = REG_DUAL_TSF_RST,
94 .tsf_rst_bit = BIT_TSFTR_CLI3_RST_8822B,
95 .bcn_space = REG_MBSSID_BCN_SPACE3_8822B,
96 .bcn_space_shift = 0,
97 .bcn_space_mask = 0xfff,
98 },
99 };
100
101
read_chip_version(PADAPTER adapter)102 static void read_chip_version(PADAPTER adapter)
103 {
104 PHAL_DATA_TYPE hal;
105 u32 value32;
106
107
108 hal = GET_HAL_DATA(adapter);
109
110 value32 = rtw_read32(adapter, REG_SYS_CFG1_8822B);
111 hal->VersionID.ICType = CHIP_8822B;
112 hal->VersionID.ChipType = ((value32 & BIT_RTL_ID_8822B) ? TEST_CHIP : NORMAL_CHIP);
113 hal->VersionID.CUTVersion = BIT_GET_CHIP_VER_8822B(value32);
114 hal->VersionID.VendorType = BIT_GET_VENDOR_ID_8822B(value32);
115 hal->VersionID.VendorType >>= 2;
116 switch (hal->VersionID.VendorType) {
117 case 0:
118 hal->VersionID.VendorType = CHIP_VENDOR_TSMC;
119 break;
120 case 1:
121 hal->VersionID.VendorType = CHIP_VENDOR_SMIC;
122 break;
123 case 2:
124 hal->VersionID.VendorType = CHIP_VENDOR_UMC;
125 break;
126 }
127
128 hal->VersionID.RFType = ((value32 & BIT_RF_TYPE_ID_8822B) ? RF_TYPE_2T2R : RF_TYPE_1T1R);
129 if (adapter->registrypriv.special_rf_path == 1)
130 hal->VersionID.RFType = RF_TYPE_1T1R; /* RF_1T1R; */
131
132 hal->RegulatorMode = ((value32 & BIT_SPSLDO_SEL_8822B) ? RT_LDO_REGULATOR : RT_SWITCHING_REGULATOR);
133
134 value32 = rtw_read32(adapter, REG_SYS_STATUS1_8822B);
135 hal->VersionID.ROMVer = BIT_GET_RF_RL_ID_8822B(value32);
136
137 /* For multi-function consideration. */
138 hal->MultiFunc = RT_MULTI_FUNC_NONE;
139 value32 = rtw_read32(adapter, REG_WL_BT_PWR_CTRL_8822B);
140 hal->MultiFunc |= ((value32 & BIT_WL_FUNC_EN_8822B) ? RT_MULTI_FUNC_WIFI : 0);
141 hal->MultiFunc |= ((value32 & BIT_BT_FUNC_EN_8822B) ? RT_MULTI_FUNC_BT : 0);
142 hal->PolarityCtl = ((value32 & BIT_WL_HWPDN_SL_8822B) ? RT_POLARITY_HIGH_ACT : RT_POLARITY_LOW_ACT);
143
144 rtw_hal_config_rftype(adapter);
145
146 dump_chip_info(hal->VersionID);
147 }
148
149 /*
150 * Return:
151 * _TRUE valid ID
152 * _FALSE invalid ID
153 */
Hal_EfuseParseIDCode(PADAPTER adapter,u8 * map)154 static u8 Hal_EfuseParseIDCode(PADAPTER adapter, u8 *map)
155 {
156 u16 EEPROMId;
157
158
159 /* Check 0x8129 again for making sure autoload status!! */
160 EEPROMId = le16_to_cpu(*(u16 *)map);
161 RTW_INFO("EEPROM ID = 0x%04x\n", EEPROMId);
162 if (EEPROMId == RTL_EEPROM_ID)
163 return _TRUE;
164
165 RTW_INFO("<WARN> EEPROM ID is invalid!!\n");
166 return _FALSE;
167 }
168
Hal_EfuseParseEEPROMVer(PADAPTER adapter,u8 * map,u8 mapvalid)169 static void Hal_EfuseParseEEPROMVer(PADAPTER adapter, u8 *map, u8 mapvalid)
170 {
171 PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
172
173
174 if (_TRUE == mapvalid)
175 hal->EEPROMVersion = map[EEPROM_VERSION_8822B];
176 else
177 hal->EEPROMVersion = 1;
178
179 RTW_INFO("EEPROM Version = %d\n", hal->EEPROMVersion);
180 }
181
Hal_GetChnlGroup(u8 chnl,u8 * pGroup)182 static u8 Hal_GetChnlGroup(u8 chnl, u8 *pGroup)
183 {
184 u8 bIn24G = _TRUE;
185
186
187 if (chnl <= 14) {
188 bIn24G = _TRUE;
189
190 if (1 <= chnl && chnl <= 2)
191 *pGroup = 0;
192 else if (3 <= chnl && chnl <= 5)
193 *pGroup = 1;
194 else if (6 <= chnl && chnl <= 8)
195 *pGroup = 2;
196 else if (9 <= chnl && chnl <= 11)
197 *pGroup = 3;
198 else if (12 <= chnl && chnl <= 14)
199 *pGroup = 4;
200 else
201 RTW_INFO("%s: in 2.4 G, but Channel %d in Group not found\n", __FUNCTION__, chnl);
202 } else {
203 bIn24G = _FALSE;
204
205 if (36 <= chnl && chnl <= 42)
206 *pGroup = 0;
207 else if (44 <= chnl && chnl <= 48)
208 *pGroup = 1;
209 else if (50 <= chnl && chnl <= 58)
210 *pGroup = 2;
211 else if (60 <= chnl && chnl <= 64)
212 *pGroup = 3;
213 else if (100 <= chnl && chnl <= 106)
214 *pGroup = 4;
215 else if (108 <= chnl && chnl <= 114)
216 *pGroup = 5;
217 else if (116 <= chnl && chnl <= 122)
218 *pGroup = 6;
219 else if (124 <= chnl && chnl <= 130)
220 *pGroup = 7;
221 else if (132 <= chnl && chnl <= 138)
222 *pGroup = 8;
223 else if (140 <= chnl && chnl <= 144)
224 *pGroup = 9;
225 else if (149 <= chnl && chnl <= 155)
226 *pGroup = 10;
227 else if (157 <= chnl && chnl <= 161)
228 *pGroup = 11;
229 else if (165 <= chnl && chnl <= 171)
230 *pGroup = 12;
231 else if (173 <= chnl && chnl <= 177)
232 *pGroup = 13;
233 else
234 RTW_INFO("%s: in 5G, but Channel %d in Group not found\n", __FUNCTION__, chnl);
235 }
236
237 return bIn24G;
238 }
239
load_default_txpower(PADAPTER adapter,PTxPowerInfo24G tbl2g4,PTxPowerInfo5G tbl5g)240 static void load_default_txpower(PADAPTER adapter, PTxPowerInfo24G tbl2g4, PTxPowerInfo5G tbl5g)
241 {
242 u32 rfpath, group, txcount;
243
244
245 for (rfpath = 0; rfpath < MAX_RF_PATH; rfpath++) {
246 /* 2.4G default value */
247 for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
248 tbl2g4->IndexCCK_Base[rfpath][group] = EEPROM_DEFAULT_24G_INDEX;
249 tbl2g4->IndexBW40_Base[rfpath][group] = EEPROM_DEFAULT_24G_INDEX;
250 }
251 for (txcount = 0; txcount < MAX_TX_COUNT; txcount++) {
252 if (txcount == 0) {
253 tbl2g4->BW20_Diff[rfpath][0] = EEPROM_DEFAULT_24G_HT20_DIFF;
254 tbl2g4->OFDM_Diff[rfpath][0] = EEPROM_DEFAULT_24G_OFDM_DIFF;
255 } else {
256 tbl2g4->BW20_Diff[rfpath][txcount] = EEPROM_DEFAULT_DIFF;
257 tbl2g4->BW40_Diff[rfpath][txcount] = EEPROM_DEFAULT_DIFF;
258 tbl2g4->CCK_Diff[rfpath][txcount] = EEPROM_DEFAULT_DIFF;
259 tbl2g4->OFDM_Diff[rfpath][txcount] = EEPROM_DEFAULT_DIFF;
260 }
261 }
262
263 /* 5G default value */
264 for (group = 0; group < MAX_CHNL_GROUP_5G; group++)
265 tbl5g->IndexBW40_Base[rfpath][group] = EEPROM_DEFAULT_5G_INDEX;
266 for (txcount = 0; txcount < MAX_TX_COUNT; txcount++) {
267 if (txcount == 0) {
268 tbl5g->OFDM_Diff[rfpath][0] = EEPROM_DEFAULT_5G_OFDM_DIFF;
269 tbl5g->BW20_Diff[rfpath][0] = EEPROM_DEFAULT_5G_HT20_DIFF;
270 tbl5g->BW80_Diff[rfpath][0] = EEPROM_DEFAULT_DIFF;
271 tbl5g->BW160_Diff[rfpath][0] = EEPROM_DEFAULT_DIFF;
272 } else {
273 tbl5g->OFDM_Diff[rfpath][txcount] = EEPROM_DEFAULT_DIFF;
274 tbl5g->BW20_Diff[rfpath][txcount] = EEPROM_DEFAULT_DIFF;
275 tbl5g->BW40_Diff[rfpath][txcount] = EEPROM_DEFAULT_DIFF;
276 tbl5g->BW80_Diff[rfpath][txcount] = EEPROM_DEFAULT_DIFF;
277 tbl5g->BW160_Diff[rfpath][txcount] = EEPROM_DEFAULT_DIFF;
278 }
279 }
280 }
281 }
282
power_valid(u8 power)283 static inline u8 power_valid(u8 power)
284 {
285 if (power <= 63)
286 return _TRUE;
287
288 return _FALSE;
289 }
290
power_diff(s8 diff)291 static inline s8 power_diff(s8 diff)
292 {
293 /* bit sign number to 8 bit sign number */
294 if (diff & BIT(3))
295 diff |= 0xF0;
296
297 return diff;
298 }
299
load_txpower_from_map(PADAPTER adapter,PTxPowerInfo24G tbl2g4,PTxPowerInfo5G tbl5g,u8 * map,u8 mapvalid)300 static void load_txpower_from_map(
301 PADAPTER adapter, PTxPowerInfo24G tbl2g4, PTxPowerInfo5G tbl5g,
302 u8 *map, u8 mapvalid)
303 {
304 PHAL_DATA_TYPE hal;
305 u32 rfpath, eeAddr, group, txcount = 0;
306 u8 power;
307 s8 diff;
308
309
310 hal = GET_HAL_DATA(adapter);
311
312 hal->bTXPowerDataReadFromEEPORM = _FALSE;
313 _rtw_memset(tbl2g4, 0, sizeof(TxPowerInfo24G));
314 _rtw_memset(tbl5g, 0, sizeof(TxPowerInfo5G));
315 load_default_txpower(adapter, tbl2g4, tbl5g);
316
317 if (_FALSE == mapvalid)
318 return;
319
320 eeAddr = EEPROM_TX_PWR_INX_8822B;
321 if (0xFF == map[eeAddr])
322 return;
323
324 hal->bTXPowerDataReadFromEEPORM = _TRUE;
325
326 for (rfpath = 0; rfpath < hal->NumTotalRFPath; rfpath++) {
327 /* 2.4G */
328 for (group = 0; group < MAX_CHNL_GROUP_24G; group++) {
329 power = map[eeAddr++];
330 if (power_valid(power) == _TRUE)
331 tbl2g4->IndexCCK_Base[rfpath][group] = power;
332 }
333
334 for (group = 0; group < MAX_CHNL_GROUP_24G - 1; group++) {
335 power = map[eeAddr++];
336 if (power_valid(power) == _TRUE)
337 tbl2g4->IndexBW40_Base[rfpath][group] = power;
338 }
339
340 for (txcount = 0; txcount < MAX_TX_COUNT; txcount++) {
341 if (txcount == 0) {
342 tbl2g4->BW40_Diff[rfpath][0] = 0;
343
344 diff = (map[eeAddr] & 0xF0) >> 4;
345 tbl2g4->BW20_Diff[rfpath][0] = power_diff(diff);
346
347 diff = map[eeAddr] & 0x0F;
348 tbl2g4->OFDM_Diff[rfpath][0] = power_diff(diff);
349
350 tbl2g4->CCK_Diff[rfpath][0] = 0;
351
352 eeAddr++;
353 } else {
354 diff = (map[eeAddr] & 0xF0) >> 4;
355 tbl2g4->BW40_Diff[rfpath][txcount] = power_diff(diff);
356
357 diff = map[eeAddr] & 0x0F;
358 tbl2g4->BW20_Diff[rfpath][txcount] = power_diff(diff);
359
360 eeAddr++;
361
362 diff = (map[eeAddr] & 0xF0) >> 4;
363 tbl2g4->OFDM_Diff[rfpath][txcount] = power_diff(diff);
364
365 diff = map[eeAddr] & 0x0F;
366 tbl2g4->CCK_Diff[rfpath][txcount] = power_diff(diff);
367
368 eeAddr++;
369 }
370 }
371
372 /* 5G */
373 for (group = 0; group < MAX_CHNL_GROUP_5G; group++) {
374 power = map[eeAddr++];
375 if (power_valid(power) == _TRUE)
376 tbl5g->IndexBW40_Base[rfpath][group] = power;
377 }
378
379 for (txcount = 0; txcount < MAX_TX_COUNT; txcount++) {
380 if (txcount == 0) {
381 tbl5g->BW40_Diff[rfpath][0] = 0;
382
383 diff = (map[eeAddr] & 0xF0) >> 4;
384 tbl5g->BW20_Diff[rfpath][0] = power_diff(diff);
385
386 diff = map[eeAddr] & 0x0F;
387 tbl5g->OFDM_Diff[rfpath][0] = power_diff(diff);
388
389 eeAddr++;
390 } else {
391 diff = (map[eeAddr] & 0xF0) >> 4;
392 tbl5g->BW40_Diff[rfpath][txcount] = power_diff(diff);
393
394 diff = map[eeAddr] & 0x0F;
395 tbl5g->BW20_Diff[rfpath][txcount] = power_diff(diff);
396
397 eeAddr++;
398 }
399 }
400
401 diff = (map[eeAddr] & 0xF0) >> 4;
402 tbl5g->OFDM_Diff[rfpath][1] = power_diff(diff);
403
404 diff = map[eeAddr] & 0x0F;
405 tbl5g->OFDM_Diff[rfpath][2] = power_diff(diff);
406
407 eeAddr++;
408
409 diff = map[eeAddr] & 0x0F;
410 tbl5g->OFDM_Diff[rfpath][3] = power_diff(diff);
411
412 eeAddr++;
413
414 for (txcount = 0; txcount < MAX_TX_COUNT; txcount++) {
415 diff = (map[eeAddr] & 0xF0) >> 4;
416 tbl5g->BW80_Diff[rfpath][txcount] = power_diff(diff);
417
418 diff = map[eeAddr] & 0x0F;
419 tbl5g->BW160_Diff[rfpath][txcount] = power_diff(diff);
420
421 eeAddr++;
422 }
423 }
424 }
425
Hal_EfuseParseTxPowerInfo(PADAPTER adapter,u8 * map,u8 mapvalid)426 static void Hal_EfuseParseTxPowerInfo(PADAPTER adapter, u8 *map, u8 mapvalid)
427 {
428 PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
429 TxPowerInfo24G tbl2G4;
430 TxPowerInfo5G tbl5g;
431 u8 rfpath, ch, group = 0, txcount = 1;
432
433
434 load_txpower_from_map(adapter, &tbl2G4, &tbl5g, map, mapvalid);
435
436 for (rfpath = 0; rfpath < hal->NumTotalRFPath; rfpath++) {
437 for (ch = 0; ch < CENTER_CH_2G_NUM; ch++) {
438 Hal_GetChnlGroup(ch + 1, &group);
439
440 if (ch == 14 - 1) {
441 hal->Index24G_CCK_Base[rfpath][ch] = tbl2G4.IndexCCK_Base[rfpath][5];
442 hal->Index24G_BW40_Base[rfpath][ch] = tbl2G4.IndexBW40_Base[rfpath][group];
443 } else {
444 hal->Index24G_CCK_Base[rfpath][ch] = tbl2G4.IndexCCK_Base[rfpath][group];
445 hal->Index24G_BW40_Base[rfpath][ch] = tbl2G4.IndexBW40_Base[rfpath][group];
446 }
447
448 RTW_INFO("======= Path %d, Channel %d, Group %d =======\n", rfpath, ch + 1, group);
449 RTW_INFO("Index24G_CCK_Base[%d][%d]=0x%x\n", rfpath, ch, hal->Index24G_CCK_Base[rfpath][ch]);
450 RTW_INFO("Index24G_BW40_Base[%d][%d]=0x%x\n", rfpath, ch, hal->Index24G_BW40_Base[rfpath][ch]);
451 }
452
453 for (ch = 0; ch < CENTER_CH_5G_ALL_NUM; ch++) {
454 Hal_GetChnlGroup(center_ch_5g_all[ch], &group);
455 hal->Index5G_BW40_Base[rfpath][ch] = tbl5g.IndexBW40_Base[rfpath][group];
456
457 RTW_INFO("======= Path %d, Channel %d, Group %d =======\n", rfpath, center_ch_5g_all[ch], group);
458 RTW_INFO("Index5G_BW40_Base[%d][%d]=0x%x\n", rfpath, ch, hal->Index5G_BW40_Base[rfpath][ch]);
459 }
460
461 for (ch = 0; ch < CENTER_CH_5G_80M_NUM; ch++) {
462 u8 upper = 0, lower = 0;
463
464 Hal_GetChnlGroup(center_ch_5g_80m[ch], &group);
465 upper = tbl5g.IndexBW40_Base[rfpath][group];
466 lower = tbl5g.IndexBW40_Base[rfpath][group + 1];
467 hal->Index5G_BW80_Base[rfpath][ch] = (upper + lower) / 2;
468
469 RTW_INFO("======= Path %d, Channel %d, Group %d =======\n", rfpath, center_ch_5g_80m[ch], group);
470 RTW_INFO("Index5G_BW80_Base[%d][%d]=0x%x\n", rfpath, ch, hal->Index5G_BW80_Base[rfpath][ch]);
471 }
472
473 for (txcount = 0; txcount < hal->NumTotalRFPath; txcount++) {
474 hal->CCK_24G_Diff[rfpath][txcount] = tbl2G4.CCK_Diff[rfpath][txcount];
475 hal->OFDM_24G_Diff[rfpath][txcount] = tbl2G4.OFDM_Diff[rfpath][txcount];
476 hal->BW20_24G_Diff[rfpath][txcount] = tbl2G4.BW20_Diff[rfpath][txcount];
477 hal->BW40_24G_Diff[rfpath][txcount] = tbl2G4.BW40_Diff[rfpath][txcount];
478
479 hal->OFDM_5G_Diff[rfpath][txcount] = tbl5g.OFDM_Diff[rfpath][txcount];
480 hal->BW20_5G_Diff[rfpath][txcount] = tbl5g.BW20_Diff[rfpath][txcount];
481 hal->BW40_5G_Diff[rfpath][txcount] = tbl5g.BW40_Diff[rfpath][txcount];
482 hal->BW80_5G_Diff[rfpath][txcount] = tbl5g.BW80_Diff[rfpath][txcount];
483
484 RTW_INFO("----------------------------------- 2.4G %dSS ----------------------------------\n", txcount + 1);
485 RTW_INFO("CCK_24G_Diff[%d][%d]=%d\n", rfpath, txcount, hal->CCK_24G_Diff[rfpath][txcount]);
486 RTW_INFO("OFDM_24G_Diff[%d][%d]=%d\n", rfpath, txcount, hal->OFDM_24G_Diff[rfpath][txcount]);
487 RTW_INFO("BW20_24G_Diff[%d][%d]=%d\n", rfpath, txcount, hal->BW20_24G_Diff[rfpath][txcount]);
488 RTW_INFO("BW40_24G_Diff[%d][%d]=%d\n", rfpath, txcount, hal->BW40_24G_Diff[rfpath][txcount]);
489 RTW_INFO("------------------------------------ 5G %dSS -----------------------------------\n", txcount + 1);
490 RTW_INFO("OFDM_5G_Diff[%d][%d]=%d\n", rfpath, txcount, hal->OFDM_5G_Diff[rfpath][txcount]);
491 RTW_INFO("BW20_5G_Diff[%d][%d]=%d\n", rfpath, txcount, hal->BW20_5G_Diff[rfpath][txcount]);
492 RTW_INFO("BW40_5G_Diff[%d][%d]=%d\n", rfpath, txcount, hal->BW40_5G_Diff[rfpath][txcount]);
493 RTW_INFO("BW80_5G_Diff[%d][%d]=%d\n", rfpath, txcount, hal->BW80_5G_Diff[rfpath][txcount]);
494 }
495 }
496
497 if ((_TRUE == mapvalid) && (map[EEPROM_RF_BOARD_OPTION_8822B] != 0xFF))
498 hal->EEPROMRegulatory = map[EEPROM_RF_BOARD_OPTION_8822B] & 0x7; /* bit0~2 */
499 else
500 hal->EEPROMRegulatory = EEPROM_DEFAULT_BOARD_OPTION & 0x7; /* bit0~2 */
501 RTW_INFO("EEPROM Regulatory=0x%02x\n", hal->EEPROMRegulatory);
502 }
503
Hal_EfuseParseBoardType(PADAPTER adapter,u8 * map,u8 mapvalid)504 static void Hal_EfuseParseBoardType(PADAPTER adapter, u8 *map, u8 mapvalid)
505 {
506 PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
507
508
509 if ((_TRUE == mapvalid) && (map[EEPROM_RF_BOARD_OPTION_8822B] != 0xFF))
510 hal->InterfaceSel = (map[EEPROM_RF_BOARD_OPTION_8822B] & 0xE0) >> 5;
511 else
512 hal->InterfaceSel = (EEPROM_DEFAULT_BOARD_OPTION & 0xE0) >> 5;
513
514 RTW_INFO("EEPROM Board Type=0x%02x\n", hal->InterfaceSel);
515 }
516
Hal_EfuseParseBTCoexistInfo(PADAPTER adapter,u8 * map,u8 mapvalid)517 static void Hal_EfuseParseBTCoexistInfo(PADAPTER adapter, u8 *map, u8 mapvalid)
518 {
519 PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
520 u8 setting;
521 u32 tmpu4;
522
523
524 if ((_TRUE == mapvalid) && (map[EEPROM_RF_BOARD_OPTION_8822B] != 0xFF)) {
525 /* 0xc1[7:5] = 0x01 */
526 if (((map[EEPROM_RF_BOARD_OPTION_8822B] & 0xe0) >> 5) == 0x01)
527 hal->EEPROMBluetoothCoexist = _TRUE;
528 else
529 hal->EEPROMBluetoothCoexist = _FALSE;
530 } else
531 hal->EEPROMBluetoothCoexist = _FALSE;
532
533 hal->EEPROMBluetoothType = BT_RTL8822B;
534
535 setting = map[EEPROM_RF_BT_SETTING_8822B];
536 if ((_TRUE == mapvalid) && (setting != 0xFF)) {
537 hal->EEPROMBluetoothAntNum = setting & BIT(0);
538 /*
539 * EFUSE_0xC3[6] == 0, S1(Main)-ODM_RF_PATH_A;
540 * EFUSE_0xC3[6] == 1, S0(Aux)-ODM_RF_PATH_B
541 */
542 hal->ant_path = (setting & BIT(6)) ? ODM_RF_PATH_B : ODM_RF_PATH_A;
543 } else {
544 hal->EEPROMBluetoothAntNum = Ant_x2;
545 hal->ant_path = ODM_RF_PATH_A;
546 }
547
548 RTW_INFO("EEPROM %s BT-coex, ant_num=%d\n",
549 hal->EEPROMBluetoothCoexist == _TRUE ? "Enable" : "Disable",
550 hal->EEPROMBluetoothAntNum == Ant_x2 ? 2 : 1);
551 }
552
Hal_EfuseParseChnlPlan(PADAPTER adapter,u8 * map,u8 autoloadfail)553 static void Hal_EfuseParseChnlPlan(PADAPTER adapter, u8 *map, u8 autoloadfail)
554 {
555 adapter->mlmepriv.ChannelPlan = hal_com_config_channel_plan(
556 adapter,
557 map ? &map[EEPROM_COUNTRY_CODE_8822B] : NULL,
558 map ? map[EEPROM_ChannelPlan_8822B] : 0xFF,
559 adapter->registrypriv.alpha2,
560 adapter->registrypriv.channel_plan,
561 RTW_CHPLAN_REALTEK_DEFINE,
562 autoloadfail
563 );
564
565 RTW_INFO("EEPROM ChannelPlan=0x%02x\n", adapter->mlmepriv.ChannelPlan);
566 }
567
Hal_EfuseParseXtal(PADAPTER adapter,u8 * map,u8 mapvalid)568 static void Hal_EfuseParseXtal(PADAPTER adapter, u8 *map, u8 mapvalid)
569 {
570 PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
571
572
573 if ((_TRUE == mapvalid) && map[EEPROM_XTAL_8822B] != 0xFF)
574 hal->CrystalCap = map[EEPROM_XTAL_8822B];
575 else
576 hal->CrystalCap = EEPROM_Default_CrystalCap;
577
578 RTW_INFO("EEPROM CrystalCap=0x%02x\n", hal->CrystalCap);
579 }
580
Hal_EfuseParseThermalMeter(PADAPTER adapter,u8 * map,u8 mapvalid)581 static void Hal_EfuseParseThermalMeter(PADAPTER adapter, u8 *map, u8 mapvalid)
582 {
583 PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
584
585
586 /* ThermalMeter from EEPROM */
587 if ((_TRUE == mapvalid) && (map[EEPROM_THERMAL_METER_8822B] != 0xFF))
588 hal->EEPROMThermalMeter = map[EEPROM_THERMAL_METER_8822B];
589 else {
590 hal->EEPROMThermalMeter = EEPROM_Default_ThermalMeter;
591 hal->odmpriv.RFCalibrateInfo.bAPKThermalMeterIgnore = _TRUE;
592 }
593
594 RTW_INFO("EEPROM ThermalMeter=0x%02x\n", hal->EEPROMThermalMeter);
595 }
596
Hal_EfuseParseAntennaDiversity(PADAPTER adapter,u8 * map,u8 mapvalid)597 static void Hal_EfuseParseAntennaDiversity(PADAPTER adapter, u8 *map, u8 mapvalid)
598 {
599 #ifdef CONFIG_ANTENNA_DIVERSITY
600 PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
601 struct registry_priv *registry_par = &adapter->registrypriv;
602
603
604 if (hal->EEPROMBluetoothAntNum == Ant_x1)
605 hal->AntDivCfg = 0;
606 else {
607 if (registry_par->antdiv_cfg == 2)/* 0:OFF , 1:ON, 2:By EFUSE */
608 hal->AntDivCfg = 1;
609 else
610 hal->AntDivCfg = registry_par->antdiv_cfg;
611 }
612
613 /* If TRxAntDivType is AUTO in advanced setting, use EFUSE value instead. */
614 if (registry_par->antdiv_type == 0) {
615 hal->TRxAntDivType = map[EEPROM_RFE_OPTION_8822B];
616 if (hal->TRxAntDivType == 0xFF)
617 hal->TRxAntDivType = S0S1_SW_ANTDIV; /* internal switch S0S1 */
618 else if (hal->TRxAntDivType == 0x10)
619 hal->TRxAntDivType = S0S1_SW_ANTDIV; /* internal switch S0S1 */
620 else if (hal->TRxAntDivType == 0x11)
621 hal->TRxAntDivType = S0S1_SW_ANTDIV; /* internal switch S0S1 */
622 else
623 RTW_INFO("EEPROM efuse[0x%x]=0x%02x is unknown type\n",
624 __FUNCTION__, EEPROM_RFE_OPTION_8723B, hal->TRxAntDivType);
625 } else
626 hal->TRxAntDivType = registry_par->antdiv_type;
627
628 RTW_INFO("EEPROM AntDivCfg=%d, AntDivType=%d\n",
629 __FUNCTION__, hal->AntDivCfg, hal->TRxAntDivType);
630 #endif /* CONFIG_ANTENNA_DIVERSITY */
631 }
632
Hal_EfuseParseCustomerID(PADAPTER adapter,u8 * map,u8 mapvalid)633 static void Hal_EfuseParseCustomerID(PADAPTER adapter, u8 *map, u8 mapvalid)
634 {
635 PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
636
637
638 if (_TRUE == mapvalid)
639 hal->EEPROMCustomerID = map[EEPROM_CustomID_8723B];
640 else
641 hal->EEPROMCustomerID = 0;
642 RTW_INFO("EEPROM Customer ID=0x%02x\n", hal->EEPROMCustomerID);
643 }
644
Hal_DetectWoWMode(PADAPTER adapter)645 static void Hal_DetectWoWMode(PADAPTER adapter)
646 {
647 #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
648 adapter_to_pwrctl(adapter)->bSupportRemoteWakeup = _TRUE;
649 #else /* !(CONFIG_WOWLAN || CONFIG_AP_WOWLAN) */
650 adapter_to_pwrctl(adapter)->bSupportRemoteWakeup = _FALSE;
651 #endif /* !(CONFIG_WOWLAN || CONFIG_AP_WOWLAN) */
652
653 RTW_INFO("EEPROM SupportRemoteWakeup=%d\n", adapter_to_pwrctl(adapter)->bSupportRemoteWakeup);
654 }
655
hal_ReadPAType(PADAPTER adapter,u8 * map,u8 mapvalid)656 static void hal_ReadPAType(PADAPTER adapter, u8 *map, u8 mapvalid)
657 {
658 PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
659
660 if (mapvalid) {
661 /* AUTO */
662 if (GetRegAmplifierType2G(adapter) == 0) {
663 hal->PAType_2G = ReadLE1Byte(&map[EEPROM_2G_5G_PA_TYPE_8822B]);
664 hal->LNAType_2G = ReadLE1Byte(&map[EEPROM_2G_LNA_TYPE_GAIN_SEL_AB_8822B]);
665
666 if (hal->PAType_2G == 0xFF)
667 hal->PAType_2G = 0;
668
669 if (hal->LNAType_2G == 0xFF)
670 hal->LNAType_2G = 0;
671
672 hal->ExternalPA_2G = (hal->PAType_2G & BIT4) ? 1 : 0;
673 hal->ExternalLNA_2G = (hal->LNAType_2G & BIT3) ? 1 : 0;
674 } else {
675 hal->ExternalPA_2G = (GetRegAmplifierType2G(adapter) & ODM_BOARD_EXT_PA) ? 1 : 0;
676 hal->ExternalLNA_2G = (GetRegAmplifierType2G(adapter) & ODM_BOARD_EXT_LNA) ? 1 : 0;
677 }
678
679 /* AUTO */
680 if (GetRegAmplifierType5G(adapter) == 0) {
681 hal->PAType_5G = ReadLE1Byte(&map[EEPROM_2G_5G_PA_TYPE_8822B]);
682 hal->LNAType_5G = ReadLE1Byte(&map[EEPROM_5G_LNA_TYPE_GAIN_SEL_AB_8822B]);
683 if (hal->PAType_5G == 0xFF)
684 hal->PAType_5G = 0;
685 if (hal->LNAType_5G == 0xFF)
686 hal->LNAType_5G = 0;
687
688 hal->ExternalPA_5G = (hal->PAType_5G & BIT0) ? 1 : 0;
689 hal->ExternalLNA_5G = (hal->LNAType_5G & BIT3) ? 1 : 0;
690 } else {
691 hal->ExternalPA_5G = (GetRegAmplifierType5G(adapter) & ODM_BOARD_EXT_PA_5G) ? 1 : 0;
692 hal->ExternalLNA_5G = (GetRegAmplifierType5G(adapter) & ODM_BOARD_EXT_LNA_5G) ? 1 : 0;
693 }
694 } else {
695 hal->ExternalPA_2G = EEPROM_Default_PAType;
696 hal->ExternalPA_5G = 0xFF;
697 hal->ExternalLNA_2G = EEPROM_Default_LNAType;
698 hal->ExternalLNA_5G = 0xFF;
699
700 /* AUTO */
701 if (GetRegAmplifierType2G(adapter) == 0) {
702 hal->ExternalPA_2G = 0;
703 hal->ExternalLNA_2G = 0;
704 } else {
705 hal->ExternalPA_2G = (GetRegAmplifierType2G(adapter) & ODM_BOARD_EXT_PA) ? 1 : 0;
706 hal->ExternalLNA_2G = (GetRegAmplifierType2G(adapter) & ODM_BOARD_EXT_LNA) ? 1 : 0;
707 }
708
709 /* AUTO */
710 if (GetRegAmplifierType5G(adapter) == 0) {
711 hal->ExternalPA_5G = 0;
712 hal->ExternalLNA_5G = 0;
713 } else {
714 hal->ExternalPA_5G = (GetRegAmplifierType5G(adapter) & ODM_BOARD_EXT_PA_5G) ? 1 : 0;
715 hal->ExternalLNA_5G = (GetRegAmplifierType5G(adapter) & ODM_BOARD_EXT_LNA_5G) ? 1 : 0;
716 }
717 }
718
719 #if 0
720 RTW_INFO("EEPROM PAType_2G is 0x%x, ExternalPA_2G = %d\n", hal->PAType_2G, hal->ExternalPA_2G);
721 RTW_INFO("EEPROM PAType_5G is 0x%x, ExternalPA_5G = %d\n", hal->PAType_5G, hal->ExternalPA_5G);
722 RTW_INFO("EEPROM LNAType_2G is 0x%x, ExternalLNA_2G = %d\n", hal->LNAType_2G, hal->ExternalLNA_2G);
723 RTW_INFO("EEPROM LNAType_5G is 0x%x, ExternalLNA_5G = %d\n", hal->LNAType_5G, hal->ExternalLNA_5G);
724 #endif
725 }
726
Hal_ReadAmplifierType(PADAPTER adapter,u8 * map,u8 mapvalid)727 static void Hal_ReadAmplifierType(PADAPTER adapter, u8 *map, u8 mapvalid)
728 {
729 PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
730 u8 extTypePA_2G_A = (map[EEPROM_2G_LNA_TYPE_GAIN_SEL_AB_8822B] & BIT2) >> 2;
731 u8 extTypePA_2G_B = (map[EEPROM_2G_LNA_TYPE_GAIN_SEL_AB_8822B] & BIT6) >> 6;
732 u8 extTypePA_5G_A = (map[EEPROM_5G_LNA_TYPE_GAIN_SEL_AB_8822B] & BIT2) >> 2;
733 u8 extTypePA_5G_B = (map[EEPROM_5G_LNA_TYPE_GAIN_SEL_AB_8822B] & BIT6) >> 6;
734 u8 extTypeLNA_2G_A = (map[EEPROM_2G_LNA_TYPE_GAIN_SEL_AB_8822B] & (BIT1 | BIT0)) >> 0;
735 u8 extTypeLNA_2G_B = (map[EEPROM_2G_LNA_TYPE_GAIN_SEL_AB_8822B] & (BIT5 | BIT4)) >> 4;
736 u8 extTypeLNA_5G_A = (map[EEPROM_5G_LNA_TYPE_GAIN_SEL_AB_8822B] & (BIT1 | BIT0)) >> 0;
737 u8 extTypeLNA_5G_B = (map[EEPROM_5G_LNA_TYPE_GAIN_SEL_AB_8822B] & (BIT5 | BIT4)) >> 4;
738
739 hal_ReadPAType(adapter, map, mapvalid);
740
741 /* [2.4G] Path A and B are both extPA */
742 if ((hal->PAType_2G & (BIT5 | BIT4)) == (BIT5 | BIT4))
743 hal->TypeGPA = extTypePA_2G_B << 2 | extTypePA_2G_A;
744
745 /* [5G] Path A and B are both extPA */
746 if ((hal->PAType_5G & (BIT1 | BIT0)) == (BIT1 | BIT0))
747 hal->TypeAPA = extTypePA_5G_B << 2 | extTypePA_5G_A;
748
749 /* [2.4G] Path A and B are both extLNA */
750 if ((hal->LNAType_2G & (BIT7 | BIT3)) == (BIT7 | BIT3))
751 hal->TypeGLNA = extTypeLNA_2G_B << 2 | extTypeLNA_2G_A;
752
753 /* [5G] Path A and B are both extLNA */
754 if ((hal->LNAType_5G & (BIT7 | BIT3)) == (BIT7 | BIT3))
755 hal->TypeALNA = extTypeLNA_5G_B << 2 | extTypeLNA_5G_A;
756
757 #if 0
758 RTW_INFO("EEPROM TypeGPA = 0x%X\n", hal->TypeGPA);
759 RTW_INFO("EEPROM TypeAPA = 0x%X\n", hal->TypeAPA);
760 RTW_INFO("EEPROM TypeGLNA = 0x%X\n", hal->TypeGLNA);
761 RTW_INFO("EEPROM TypeALNA = 0x%X\n", hal->TypeALNA);
762 #endif
763 }
764
Hal_ReadRFEType(PADAPTER adapter,u8 * map,u8 mapvalid)765 static u8 Hal_ReadRFEType(PADAPTER adapter, u8 *map, u8 mapvalid)
766 {
767 PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
768
769 /* check registry valye */
770 if (GetRegRFEType(adapter) != CONFIG_RTW_RFE_TYPE) {
771 hal->RFEType = GetRegRFEType(adapter);
772 goto exit;
773 }
774
775 if (mapvalid) {
776 /* check efuse map */
777 hal->RFEType = ReadLE1Byte(&map[EEPROM_RFE_OPTION_8822B]);
778 if (0xFF != hal->RFEType)
779 goto exit;
780 }
781
782 /* error handle */
783 hal->RFEType = 0;
784 RTW_ERR("\n\nEmpty EFUSE with unknown REF type!!\n\n");
785 printk("please program efuse or specify correct RFE type.\n");
786 printk("cmd: insmod rtl8822bx.ko rtw_RFE_type=<rfe_type>\n\n");
787 return _FAIL;
788
789 exit:
790 RTW_INFO("EEPROM RFEType=0x%x\n", hal->RFEType);
791 return _SUCCESS;
792 }
793
Hal_EfuseParsePackageType(PADAPTER adapter,u8 * map,u8 mapvalid)794 static void Hal_EfuseParsePackageType(PADAPTER adapter, u8 *map, u8 mapvalid)
795 {
796 }
797
Hal_EfuseParsePABias(PADAPTER adapter)798 static void Hal_EfuseParsePABias(PADAPTER adapter)
799 {
800 struct hal_com_data *hal;
801 u8 data[2] = {0xFF, 0xFF};
802 u8 ret;
803
804
805 ret = rtw_efuse_access(adapter, 0, 0x3D7, 2, data);
806 if (_FAIL == ret) {
807 RTW_ERR("%s: Fail to read PA Bias from eFuse!\n", __FUNCTION__);
808 return;
809 }
810
811 hal = GET_HAL_DATA(adapter);
812 hal->tx_pa_bias_a = data[0]; /* efuse[0x3D7] */
813 hal->tx_pa_bias_b = data[1]; /* efuse[0x3D8] */
814
815 RTW_INFO("EEPROM PA_BIAS_A=0x%x\n", hal->tx_pa_bias_a);
816 RTW_INFO("EEPROM PA_BIAS_B=0x%x\n", hal->tx_pa_bias_b);
817 }
818
819 #ifdef CONFIG_RF_POWER_TRIM
Hal_ReadRFGainOffset(PADAPTER adapter,u8 * map,u8 mapvalid)820 static void Hal_ReadRFGainOffset(PADAPTER adapter, u8 *map, u8 mapvalid)
821 {
822 PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
823
824 /*
825 * BB_RF Gain Offset from EEPROM
826 */
827 if ((_TRUE == mapvalid) || (adapter->registrypriv.RegPwrTrimEnable == 1)) {
828 #if 0
829 hal->EEPROMRFGainOffset = map[EEPROM_RF_GAIN_OFFSET];
830 hal->EEPROMRFGainVal = EFUSE_Read1Byte(adapter, EEPROM_RF_GAIN_VAL);
831 #else
832 hal->EEPROMRFGainOffset = 0;
833 hal->EEPROMRFGainVal = 0xFF;
834 #endif
835 } else {
836 hal->EEPROMRFGainOffset = 0;
837 hal->EEPROMRFGainVal = 0xFF;
838 }
839 RTW_INFO("EEPROM RFGainOffset=0x%02x\n", hal->EEPROMRFGainOffset);
840 RTW_INFO("EEPROM RFGainVal=0x%02x\n", hal->EEPROMRFGainVal);
841 }
842 #endif /* CONFIG_RF_POWER_TRIM */
843
844 #ifdef CONFIG_USB_HCI
Hal_ReadUsbModeSwitch(PADAPTER adapter,u8 * map,u8 mapvalid)845 static void Hal_ReadUsbModeSwitch(PADAPTER adapter, u8 *map, u8 mapvalid)
846 {
847 PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
848
849 if (_TRUE == mapvalid)
850 /* check efuse 0x06 bit7 */
851 hal->EEPROMUsbSwitch = (map[EEPROM_USB_MODE_8822BU] & BIT7) >> 7;
852 else
853 hal->EEPROMUsbSwitch = _FALSE;
854
855 RTW_INFO("EEPROM USB Switch=%d\n", hal->EEPROMUsbSwitch);
856 }
857 #endif /* CONFIG_USB_HCI */
858
859 /*
860 * Description:
861 * Collect all information from efuse or files.
862 * This function will do
863 * 1. Read registers to check hardware efuse available or not
864 * 2. Read Efuse/EEPROM
865 * 3. Read file if necessary
866 * 4. Parsing Efuse data
867 */
rtl8822b_read_efuse(PADAPTER adapter)868 u8 rtl8822b_read_efuse(PADAPTER adapter)
869 {
870 struct dvobj_priv *d;
871 PHAL_DATA_TYPE hal;
872 u8 val8;
873 u32 efuse_size;
874 u8 *efuse_map = NULL;
875 u8 valid;
876 int err;
877 HALMAC_EFUSE_READ_CFG cfg;
878
879 d = adapter_to_dvobj(adapter);
880 hal = GET_HAL_DATA(adapter);
881 efuse_size = EEPROM_MAX_SIZE;
882 efuse_map = hal->efuse_eeprom_data;
883
884 err = rtw_halmac_get_logical_efuse_size(d, &efuse_size);
885 if (err || !efuse_size) {
886 RTW_INFO("%s: <ERROR> fail to get efuse size!\n", __FUNCTION__);
887 efuse_size = EEPROM_MAX_SIZE;
888 }
889 if (efuse_size > EEPROM_MAX_SIZE) {
890 RTW_INFO("%s: <ERROR> size of efuse data(%d) is large than expected(%d)!\n",
891 __FUNCTION__, efuse_size, EEPROM_MAX_SIZE);
892 efuse_size = EEPROM_MAX_SIZE;
893 }
894
895 /* 1. Read registers to check hardware eFuse available or not */
896 val8 = rtw_read8(adapter, REG_SYS_EEPROM_CTRL_8822B);
897 hal->EepromOrEfuse = (val8 & BIT_EERPOMSEL_8822B) ? _TRUE : _FALSE;
898 hal->bautoload_fail_flag = (val8 & BIT_AUTOLOAD_SUS_8822B) ? _FALSE : _TRUE;
899 if (hal->bautoload_fail_flag == _TRUE)
900 goto load_efuse_file;
901
902 /*
903 * In 8822B, bautoload_fail_flag is used to present eFuse map is valid
904 * or not, no matter the map comes from hardware or files.
905 */
906
907 /* 2. Read eFuse */
908 err = rtw_halmac_read_logical_efuse_map(d, efuse_map, efuse_size);
909 if (err) {
910 RTW_INFO("%s: <ERROR> fail to get efuse map!\n", __FUNCTION__);
911 goto load_efuse_file;
912 }
913 goto parse_efuse;
914
915 load_efuse_file:
916 /* 3. Read Efuse file if necessary */
917 #ifdef CONFIG_EFUSE_CONFIG_FILE
918 if (check_phy_efuse_tx_power_info_valid(adapter) == _FALSE) {
919 if (Hal_readPGDataFromConfigFile(adapter) != _SUCCESS)
920 RTW_INFO("%s: <WARN> invalid phy efuse and read from file fail, will use driver default!!\n", __FUNCTION__);
921 }
922 #else
923 /* check RFE_Type */
924
925 #endif /* CONFIG_EFUSE_CONFIG_FILE */
926
927 parse_efuse:
928 rtw_dump_cur_efuse(adapter);
929
930 /* 4. Parse Efuse data */
931 valid = Hal_EfuseParseIDCode(adapter, efuse_map);
932 if (_TRUE == valid)
933 hal->bautoload_fail_flag = _FALSE;
934 else
935 hal->bautoload_fail_flag = _TRUE;
936
937 Hal_EfuseParseEEPROMVer(adapter, efuse_map, valid);
938 hal_config_macaddr(adapter, hal->bautoload_fail_flag);
939 Hal_EfuseParseTxPowerInfo(adapter, efuse_map, valid);
940 Hal_EfuseParseBoardType(adapter, efuse_map, valid);
941 Hal_EfuseParseBTCoexistInfo(adapter, efuse_map, valid);
942 Hal_EfuseParseChnlPlan(adapter, efuse_map, hal->bautoload_fail_flag);
943 Hal_EfuseParseXtal(adapter, efuse_map, valid);
944 Hal_EfuseParseThermalMeter(adapter, efuse_map, valid);
945 Hal_EfuseParseAntennaDiversity(adapter, efuse_map, valid);
946 Hal_EfuseParseCustomerID(adapter, efuse_map, valid);
947 Hal_DetectWoWMode(adapter);
948 Hal_ReadAmplifierType(adapter, efuse_map, valid);
949 if (Hal_ReadRFEType(adapter, efuse_map, valid) == _FAIL)
950 return _FAIL;
951
952 /* Data out of Efuse Map */
953 Hal_EfuseParsePackageType(adapter, efuse_map, valid);
954 /* Hal_EfuseParsePABias(adapter); */
955 #ifdef CONFIG_RF_POWER_TRIM
956 Hal_ReadRFGainOffset(adapter, efuse_map, valid);
957 #endif /* CONFIG_RF_POWER_TRIM */
958
959 #ifdef CONFIG_USB_HCI
960 Hal_ReadUsbModeSwitch(adapter, efuse_map, valid);
961 #endif /* CONFIG_USB_HCI */
962 return _SUCCESS;
963 }
964
rtl8822b_run_thread(PADAPTER adapter)965 void rtl8822b_run_thread(PADAPTER adapter)
966 {
967 }
968
rtl8822b_cancel_thread(PADAPTER adapter)969 void rtl8822b_cancel_thread(PADAPTER adapter)
970 {
971 }
972
973 /*
974 * Description:
975 * Using 0x100 to check the power status of FW.
976 */
check_ips_status(PADAPTER adapter)977 static u8 check_ips_status(PADAPTER adapter)
978 {
979 u8 val8;
980
981
982 RTW_INFO(FUNC_ADPT_FMT ": Read 0x100=0x%02x 0x86=0x%02x\n",
983 FUNC_ADPT_ARG(adapter),
984 rtw_read8(adapter, 0x100), rtw_read8(adapter, 0x86));
985
986 val8 = rtw_read8(adapter, 0x100);
987 if (val8 == 0xEA)
988 return _TRUE;
989
990 return _FALSE;
991 }
992
update_ra_mask(PADAPTER adapter,u32 mac_id,u8 rssi_level)993 static void update_ra_mask(PADAPTER adapter, u32 mac_id, u8 rssi_level)
994 {
995 u64 mask, rate_bitmap, *dm_RA_Mask = NULL;
996 u8 shortGIrate = _FALSE, *dm_RteID = NULL;
997 u8 arg[4] = {0};
998 struct sta_info *psta;
999 PHAL_DATA_TYPE hal;
1000 struct macid_ctl_t *macid_ctl;
1001
1002
1003 RTW_INFO(FUNC_ADPT_FMT ": mac_id=%d rssi_level=%d\n",
1004 FUNC_ADPT_ARG(adapter), mac_id, rssi_level);
1005
1006 macid_ctl = &adapter->dvobj->macid_ctl;
1007 psta = NULL;
1008 if (mac_id < macid_ctl->num)
1009 psta = macid_ctl->sta[mac_id];
1010 if (psta == NULL) {
1011 RTW_PRINT(FUNC_ADPT_FMT " macid:%u, sta is NULL\n",
1012 FUNC_ADPT_ARG(adapter), mac_id);
1013 return;
1014 }
1015
1016 hal = GET_HAL_DATA(adapter);
1017 shortGIrate = query_ra_short_GI(psta);
1018 mask = psta->ra_mask;
1019
1020 rate_bitmap = 0xffffffff;
1021 rate_bitmap = PhyDM_Get_Rate_Bitmap_Ex(&hal->odmpriv, mac_id, mask, rssi_level, dm_RA_Mask, dm_RteID);
1022 RTW_INFO("%s => mac_id:%d, networkType:0x%02x, mask:0x%016llx\n\t ==> rssi_level:%d, rate_bitmap:0x%016llx, shortGIrate=%d\n",
1023 __FUNCTION__, mac_id, psta->wireless_mode, mask, rssi_level, rate_bitmap, shortGIrate);
1024
1025 mask &= rate_bitmap;
1026
1027 #ifdef CONFIG_BT_COEXIST
1028 if (hal->EEPROMBluetoothCoexist) {
1029 rate_bitmap = rtw_btcoex_GetRaMask(adapter);
1030 mask &= ~rate_bitmap;
1031 }
1032 #endif /* CONFIG_BT_COEXIST */
1033
1034 arg[0] = mac_id;
1035 arg[1] = psta->raid;
1036 arg[2] = shortGIrate;
1037 arg[3] = psta->init_rate;
1038
1039 rtl8822b_set_FwMacIdConfig_cmd(adapter, mask, arg);
1040 }
1041
InitBeaconParameters(PADAPTER adapter)1042 static void InitBeaconParameters(PADAPTER adapter)
1043 {
1044 PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
1045 u16 val16;
1046 u8 val8;
1047
1048
1049 val8 = BIT_DIS_TSF_UDT_8822B;
1050 val16 = val8 | (val8 << 8); /* port0 and port1 */
1051 #ifdef CONFIG_BT_COEXIST
1052 if (hal->EEPROMBluetoothCoexist)
1053 /* Enable port0 beacon function for PSTDMA under BTCOEX */
1054 val16 |= EN_BCN_FUNCTION;
1055 #endif
1056 rtw_write16(adapter, REG_BCN_CTRL_8822B, val16);
1057
1058 rtw_write16(adapter, REG_TBTT_PROHIBIT_8822B, 0x6404); /* ms */
1059
1060 rtw_write8(adapter, REG_DRVERLYINT_8822B, DRIVER_EARLY_INT_TIME_8822B); /* 5ms */
1061 rtw_write8(adapter, REG_BCNDMATIM_8822B, BCN_DMA_ATIME_INT_TIME_8822B); /* 2ms */
1062
1063 /*
1064 * Suggested by designer timchen. Change beacon AIFS to the largest number
1065 * beacause test chip does not contension before sending beacon.
1066 */
1067 rtw_write16(adapter, REG_BCNTCFG_8822B, 0x660F);
1068
1069 hal->RegBcnCtrlVal = rtw_read8(adapter, REG_BCN_CTRL_8822B);
1070 hal->RegTxPause = rtw_read8(adapter, REG_TXPAUSE_8822B);
1071 hal->RegFwHwTxQCtrl = rtw_read8(adapter, REG_FWHW_TXQ_CTRL_8822B + 2);
1072 hal->RegReg542 = rtw_read8(adapter, REG_TBTT_PROHIBIT_8822B + 2);
1073 hal->RegCR_1 = rtw_read8(adapter, REG_CR_8822B + 1);
1074 }
1075
rtl8822b_resume_tx_beacon(PADAPTER adapter)1076 void rtl8822b_resume_tx_beacon(PADAPTER adapter)
1077 {
1078 PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
1079
1080
1081 hal->RegFwHwTxQCtrl |= (BIT_EN_BCNQ_DL_8822B >> 16);
1082 rtw_write8(adapter, REG_FWHW_TXQ_CTRL_8822B + 2, hal->RegFwHwTxQCtrl);
1083
1084 rtw_write8(adapter, REG_TBTT_PROHIBIT_8822B + 1, 0xff);
1085 hal->RegReg542 |= BIT(0);
1086 rtw_write8(adapter, REG_TBTT_PROHIBIT_8822B + 2, hal->RegReg542);
1087 }
1088
rtl8822b_stop_tx_beacon(PADAPTER adapter)1089 void rtl8822b_stop_tx_beacon(PADAPTER adapter)
1090 {
1091 PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
1092
1093
1094 hal->RegFwHwTxQCtrl &= ~(BIT_EN_BCNQ_DL_8822B >> 16);
1095 rtw_write8(adapter, REG_FWHW_TXQ_CTRL_8822B + 2, hal->RegFwHwTxQCtrl);
1096
1097 rtw_write8(adapter, REG_TBTT_PROHIBIT_8822B + 1, 0x64);
1098 hal->RegReg542 &= ~BIT(0);
1099 rtw_write8(adapter, REG_TBTT_PROHIBIT_8822B + 2, hal->RegReg542);
1100 }
1101
beacon_function_enable(PADAPTER adapter,u8 Enable,u8 Linked)1102 static void beacon_function_enable(PADAPTER adapter, u8 Enable, u8 Linked)
1103 {
1104 u8 val8;
1105 u32 bcn_ctrl_reg;
1106
1107 /* port0 */
1108 bcn_ctrl_reg = REG_BCN_CTRL_8822B;
1109 val8 = BIT_DIS_TSF_UDT_8822B | BIT_EN_BCN_FUNCTION_8822B;
1110 #ifdef CONFIG_CONCURRENT_MODE
1111 /* port1 */
1112 if (adapter->hw_port == HW_PORT1) {
1113 bcn_ctrl_reg = REG_BCN_CTRL_CLINT0_8822B;
1114 val8 = BIT_CLI0_DIS_TSF_UDT_8822B | BIT_CLI0_EN_BCN_FUNCTION_8822B;
1115 }
1116 #endif
1117
1118 rtw_write8(adapter, bcn_ctrl_reg, val8);
1119 rtw_write8(adapter, REG_RD_CTRL_8822B + 1, 0x6F);
1120 }
1121
set_beacon_related_registers(PADAPTER adapter)1122 static void set_beacon_related_registers(PADAPTER adapter)
1123 {
1124 u8 val8;
1125 u32 value32;
1126 PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
1127 struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
1128 struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
1129 u32 bcn_ctrl_reg, bcn_interval_reg;
1130
1131
1132 /* reset TSF, enable update TSF, correcting TSF On Beacon */
1133 /*
1134 * REG_BCN_INTERVAL
1135 * REG_BCNDMATIM
1136 * REG_ATIMWND
1137 * REG_TBTT_PROHIBIT
1138 * REG_DRVERLYINT
1139 * REG_BCN_MAX_ERR
1140 * REG_BCNTCFG (0x510)
1141 * REG_DUAL_TSF_RST
1142 * REG_BCN_CTRL (0x550)
1143 */
1144
1145 bcn_ctrl_reg = REG_BCN_CTRL_8822B;
1146 #ifdef CONFIG_CONCURRENT_MODE
1147 if (adapter->hw_port == HW_PORT1)
1148 bcn_ctrl_reg = REG_BCN_CTRL_CLINT0_8822B;
1149 #endif
1150
1151 /*
1152 * ATIM window
1153 */
1154 rtw_write16(adapter, REG_ATIMWND_8822B, 2);
1155
1156 /*
1157 * Beacon interval (in unit of TU).
1158 */
1159 #ifdef CONFIG_CONCURRENT_MODE
1160 /* Port 1 bcn interval */
1161 if (adapter->hw_port == HW_PORT1) {
1162 u16 val16;
1163
1164 val16 = rtw_read16(adapter, (REG_MBSSID_BCN_SPACE_8822B + 2));
1165 val16 |= (pmlmeinfo->bcn_interval & BIT_MASK_BCN_SPACE_CLINT0_8822B);
1166 rtw_write16(adapter, REG_MBSSID_BCN_SPACE_8822B + 2, val16);
1167 } else
1168 #endif
1169 /* Port 0 bcn interval */
1170 rtw_write16(adapter, REG_MBSSID_BCN_SPACE_8822B, pmlmeinfo->bcn_interval);
1171
1172 InitBeaconParameters(adapter);
1173
1174 rtw_write8(adapter, REG_SLOT_8822B, 0x09);
1175
1176 /* Reset TSF Timer to zero */
1177 val8 = BIT_TSFTR_RST_8822B;
1178 #ifdef CONFIG_CONCURRENT_MODE
1179 if (adapter->hw_port == HW_PORT1)
1180 val8 = BIT_TSFTR_CLI0_RST_8822B;
1181 #endif
1182 rtw_write8(adapter, REG_DUAL_TSF_RST_8822B, val8);
1183 val8 = BIT_TSFTR_RST_8822B;
1184 rtw_write8(adapter, REG_DUAL_TSF_RST_8822B, val8);
1185
1186 rtw_write8(adapter, REG_RXTSF_OFFSET_CCK_8822B, 0x50);
1187 rtw_write8(adapter, REG_RXTSF_OFFSET_OFDM_8822B, 0x50);
1188
1189 beacon_function_enable(adapter, _TRUE, _TRUE);
1190
1191 rtl8822b_resume_tx_beacon(adapter);
1192 }
1193
1194 /*
1195 * arg[0] = macid
1196 * arg[1] = raid
1197 * arg[2] = shortGIrate
1198 * arg[3] = init_rate
1199 */
add_rateatid(PADAPTER adapter,u64 rate_bitmap,u8 * arg,u8 rssi_level)1200 void add_rateatid(PADAPTER adapter, u64 rate_bitmap, u8 *arg, u8 rssi_level)
1201 {
1202 PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
1203 u64 *dm_RA_Mask = NULL;
1204 u8 *dm_RteID = NULL;
1205 u8 macid;
1206
1207 macid = arg[0];
1208
1209 if (rssi_level != DM_RATR_STA_INIT)
1210 rate_bitmap = PhyDM_Get_Rate_Bitmap_Ex(&hal->odmpriv, macid, rate_bitmap, rssi_level, dm_RA_Mask, dm_RteID);
1211
1212 rtl8822b_set_FwMacIdConfig_cmd(adapter, rate_bitmap, arg);
1213 }
1214
xmit_status_check(PADAPTER p)1215 static void xmit_status_check(PADAPTER p)
1216 {
1217 PHAL_DATA_TYPE hal = GET_HAL_DATA(p);
1218 struct sreset_priv *psrtpriv = &hal->srestpriv;
1219 struct xmit_priv *pxmitpriv = &p->xmitpriv;
1220 unsigned long current_time = 0;
1221 unsigned int diff_time = 0;
1222 u32 txdma_status = 0;
1223
1224 txdma_status = rtw_read32(p, REG_TXDMA_STATUS_8822B);
1225 if (txdma_status != 0x00) {
1226 RTW_INFO("%s REG_TXDMA_STATUS:0x%08x\n", __FUNCTION__, txdma_status);
1227 rtw_hal_sreset_reset(p);
1228 }
1229 #ifdef CONFIG_USB_HCI
1230 current_time = rtw_get_current_time();
1231
1232 if (0 == pxmitpriv->free_xmitbuf_cnt || 0 == pxmitpriv->free_xmit_extbuf_cnt) {
1233 diff_time = rtw_get_passing_time_ms(psrtpriv->last_tx_time);
1234
1235 if (diff_time > 2000) {
1236 if (psrtpriv->last_tx_complete_time == 0)
1237 psrtpriv->last_tx_complete_time = current_time;
1238 else {
1239 diff_time = rtw_get_passing_time_ms(psrtpriv->last_tx_complete_time);
1240 if (diff_time > 4000) {
1241 u32 ability = 0;
1242
1243 ability = rtw_phydm_ability_get(p);
1244
1245 RTW_INFO("%s tx hang %s\n", __FUNCTION__,
1246 (ability & ODM_BB_ADAPTIVITY) ? "ODM_BB_ADAPTIVITY" : "");
1247
1248 if (!(ability & ODM_BB_ADAPTIVITY))
1249 rtw_hal_sreset_reset(p);
1250 }
1251 }
1252 }
1253 }
1254 #endif /* CONFIG_USB_HCI */
1255
1256 if (psrtpriv->dbg_trigger_point == SRESET_TGP_XMIT_STATUS) {
1257 psrtpriv->dbg_trigger_point = SRESET_TGP_NULL;
1258 rtw_hal_sreset_reset(p);
1259 return;
1260 }
1261 }
1262
linked_status_check(PADAPTER p)1263 static void linked_status_check(PADAPTER p)
1264 {
1265 PHAL_DATA_TYPE hal = GET_HAL_DATA(p);
1266 struct sreset_priv *psrtpriv = &hal->srestpriv;
1267 u32 rx_dma_status = 0;
1268
1269 rx_dma_status = rtw_read32(p, REG_RXDMA_STATUS_8822B);
1270 if (rx_dma_status != 0x00)
1271 RTW_INFO("%s REG_RXDMA_STATUS:0x%08x\n", __FUNCTION__, rx_dma_status);
1272
1273 if (psrtpriv->dbg_trigger_point == SRESET_TGP_LINK_STATUS) {
1274 psrtpriv->dbg_trigger_point = SRESET_TGP_NULL;
1275 rtw_hal_sreset_reset(p);
1276 return;
1277 }
1278 }
1279
1280 #ifdef CONFIG_TSF_RESET_OFFLOAD
reset_tsf(PADAPTER adapter,u8 reset_port)1281 static int reset_tsf(PADAPTER adapter, u8 reset_port)
1282 {
1283 u8 reset_cnt_before = 0, reset_cnt_after = 0, loop_cnt = 0;
1284 u32 reg_reset_tsf_cnt = (HW_PORT0 == reset_port) ?
1285 REG_FW_RESET_TSF_CNT_0 : REG_FW_RESET_TSF_CNT_1;
1286
1287
1288 /* site survey will cause reset_tsf fail */
1289 rtw_mi_buddy_scan_abort(adapter, _FALSE);
1290 reset_cnt_after = reset_cnt_before = rtw_read8(adapter, reg_reset_tsf_cnt);
1291 rtl8822b_reset_tsf(adapter, reset_port);
1292
1293 while ((reset_cnt_after == reset_cnt_before) && (loop_cnt < 10)) {
1294 rtw_msleep_os(100);
1295 loop_cnt++;
1296 reset_cnt_after = rtw_read8(adapter, reg_reset_tsf_cnt);
1297 }
1298
1299 return (loop_cnt >= 10) ? _FAIL : _TRUE;
1300 }
1301 #endif /* CONFIG_TSF_RESET_OFFLOAD */
1302
set_opmode_monitor(PADAPTER adapter)1303 static void set_opmode_monitor(PADAPTER adapter)
1304 {
1305 u32 rcr_bits;
1306 u16 value_rxfltmap2;
1307 struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
1308
1309
1310 /* Leave IPS */
1311 rtw_pm_set_ips(adapter, IPS_NONE);
1312 LeaveAllPowerSaveMode(adapter);
1313
1314 /* Receive all type */
1315 rcr_bits = BIT_AAP_8822B | BIT_APM_8822B | BIT_AM_8822B
1316 | BIT_AB_8822B | BIT_APWRMGT_8822B
1317 | BIT_APP_PHYSTS_8822B;
1318
1319 /* Append FCS */
1320 rcr_bits |= BIT_APP_FCS_8822B;
1321
1322 /* Receive all data frames */
1323 value_rxfltmap2 = 0xFFFF;
1324
1325 rtl8822b_rcr_config(adapter, rcr_bits);
1326
1327 rtw_write16(adapter, REG_RXFLTMAP_8822B, value_rxfltmap2);
1328 }
1329
set_opmode_port0(PADAPTER adapter,u8 mode)1330 static void set_opmode_port0(PADAPTER adapter, u8 mode)
1331 {
1332 u8 is_ap_exist;
1333 u8 val8;
1334 u32 val32;
1335
1336 #ifdef CONFIG_CONCURRENT_MODE
1337 is_ap_exist = rtw_mi_check_status(adapter, MI_AP_MODE);
1338 #else /* !CONFIG_CONCURRENT_MODE */
1339 is_ap_exist = _FALSE;
1340 #endif /* !CONFIG_CONCURRENT_MODE */
1341
1342 /* disable Port0 TSF update */
1343 val8 = rtw_read8(adapter, REG_BCN_CTRL_8822B);
1344 val8 |= BIT_DIS_TSF_UDT_8822B;
1345 rtw_write8(adapter, REG_BCN_CTRL_8822B, val8);
1346
1347 Set_MSR(adapter, mode);
1348
1349 RTW_INFO(FUNC_ADPT_FMT ": hw_port(%d) mode=%d\n",
1350 FUNC_ADPT_ARG(adapter), adapter->hw_port, mode);
1351
1352 switch (mode) {
1353 case _HW_STATE_NOLINK_:
1354 case _HW_STATE_STATION_:
1355 if (_FALSE == is_ap_exist) {
1356 rtl8822b_stop_tx_beacon(adapter);
1357 #ifdef CONFIG_PCI_HCI
1358 UpdateInterruptMask8822BE(adapter, 0, 0, RT_BCN_INT_MASKS, 0);
1359 #endif /* CONFIG_PCI_HCI */
1360 }
1361
1362 /* disable beacon function */
1363 val8 = BIT_DIS_TSF_UDT_8822B | BIT_EN_BCN_FUNCTION_8822B;
1364 rtw_write8(adapter, REG_BCN_CTRL_8822B, val8);
1365
1366 /* disable atim wnd(only for Port0) */
1367 val8 = rtw_read8(adapter, REG_DIS_ATIM_8822B);
1368 val8 |= BIT_DIS_ATIM_ROOT_8822B;
1369 rtw_write8(adapter, REG_DIS_ATIM_8822B, val8);
1370
1371 /* clear rx ctrl frame */
1372 rtw_write16(adapter, REG_RXFLTMAP1_8822B, 0);
1373 break;
1374
1375 case _HW_STATE_ADHOC_:
1376 rtl8822b_resume_tx_beacon(adapter);
1377 val8 = BIT_DIS_TSF_UDT_8822B | BIT_EN_BCN_FUNCTION_8822B;
1378 rtw_write8(adapter, REG_BCN_CTRL_8822B, val8);
1379
1380 /* clear rx ctrl frame */
1381 rtw_write16(adapter, REG_RXFLTMAP1_8822B, 0);
1382 break;
1383
1384 case _HW_STATE_AP_:
1385 #ifdef CONFIG_PCI_HCI
1386 UpdateInterruptMask8822BE(adapter, RT_BCN_INT_MASKS, 0, 0, 0);
1387 #endif /* CONFIG_PCI_HCI */
1388
1389 rtl8822b_resume_tx_beacon(adapter);
1390
1391 /*
1392 * enable BCN0 Function for if1
1393 * disable update TSF0 for if1
1394 * enable TX BCN report:
1395 * Reg REG_FWHW_TXQ_CTRL_8822B [2] = 1
1396 * Reg REG_BCN_CTRL_8822B[3][5] = 1
1397 * Enable ATIM
1398 * Enable HW seq for BCN
1399 */
1400 /* enable TX BCN report */
1401 /* disable RX BCN report */
1402 val8 = rtw_read8(adapter, REG_FWHW_TXQ_CTRL_8822B);
1403 val8 |= BIT_EN_BCN_TRXRPT_V1_8822B;
1404 val8 &= (~BIT_P0_EN_RXBCN_RPT_8822B);
1405 rtw_write8(adapter, REG_FWHW_TXQ_CTRL_8822B, val8);
1406
1407 /* enable BCN0 Function */
1408 val8 = rtw_read8(adapter, REG_BCN_CTRL_8822B);
1409 val8 |= BIT_EN_BCN_FUNCTION_8822B | BIT_DIS_TSF_UDT_8822B | BIT_P0_EN_TXBCN_RPT_8822B;
1410 rtw_write8(adapter, REG_BCN_CTRL_8822B, val8);
1411
1412 /* Enable ATIM */
1413 val8 = rtw_read8(adapter, REG_DIS_ATIM_8822B);
1414 val8 &= ~BIT_DIS_ATIM_ROOT_8822B;
1415 rtw_write8(adapter, REG_DIS_ATIM_8822B, val8);
1416
1417 /* Enable HW seq for BCN
1418 0x4FC[0]: EN_HWSEQ
1419 0x4FC[1]: EN_HWSEQEXT
1420 According TX desc
1421 */
1422 rtw_write8(adapter, REG_DUMMY_PAGE4_V1_8822B, 0x01);
1423
1424 /* Set RCR */
1425 /* CBSSID_DATA must set to 0, reject ICV_ERR packet */
1426 rtl8822b_rcr_clear(adapter, BIT_CBSSID_DATA_8822B);
1427
1428 /* enable to rx data frame */
1429 rtw_write16(adapter, REG_RXFLTMAP_8822B, 0xFFFF);
1430 /* enable to rx ps-poll */
1431 rtw_write16(adapter, REG_RXFLTMAP1_8822B, 0x0400);
1432
1433 /* Beacon Control related register for first time */
1434 rtw_write8(adapter, REG_BCNDMATIM_8822B, 0x02); /* 2ms */
1435
1436 rtw_write8(adapter, REG_ATIMWND_8822B, 0x0a); /* 10ms */
1437 rtw_write16(adapter, REG_BCNTCFG_8822B, 0x00);
1438 rtw_write16(adapter, REG_TBTT_PROHIBIT_8822B, 0xff04);
1439 rtw_write16(adapter, REG_TSFTR_SYN_OFFSET_8822B, 0x7fff); /* +32767 (~32ms) */
1440
1441 /* reset TSF */
1442 rtw_write8(adapter, REG_DUAL_TSF_RST_8822B, BIT_TSFTR_RST_8822B);
1443
1444 /* SW_BCN_SEL - Port0 */
1445 rtw_hal_set_hwreg(adapter, HW_VAR_DL_BCN_SEL, NULL);
1446
1447 /* select BCN on port 0 */
1448 val8 = rtw_read8(adapter, REG_CCK_CHECK_8822B);
1449 val8 &= ~BIT_BCN_PORT_SEL_8822B;
1450 rtw_write8(adapter, REG_CCK_CHECK_8822B, val8);
1451
1452 #ifdef CONFIG_TSF_RESET_OFFLOAD
1453 /* Reset TSF for STA+AP concurrent mode */
1454 if (rtw_mi_buddy_check_fwstate(adapter, (WIFI_STATION_STATE | WIFI_ASOC_STATE))) {
1455 if (reset_tsf(adapter, HW_PORT0) == _FALSE)
1456 RTW_INFO(FUNC_ADPT_FMT ": ERROR! Reset port0 TSF fail\n",
1457 FUNC_ADPT_ARG(adapter));
1458 }
1459 #endif /* CONFIG_TSF_RESET_OFFLOAD */
1460
1461 break;
1462 }
1463 }
1464
set_opmode_port1(PADAPTER adapter,u8 mode)1465 static void set_opmode_port1(PADAPTER adapter, u8 mode)
1466 {
1467 #ifdef CONFIG_CONCURRENT_MODE
1468 u8 is_ap_exist;
1469 u8 val8;
1470
1471 is_ap_exist = rtw_mi_check_status(adapter, MI_AP_MODE);
1472
1473 /* disable Port1 TSF update */
1474 val8 = rtw_read8(adapter, REG_BCN_CTRL_CLINT0_8822B);
1475 val8 |= BIT_CLI0_DIS_TSF_UDT_8822B;
1476 rtw_write8(adapter, REG_BCN_CTRL_CLINT0_8822B, val8);
1477
1478 Set_MSR(adapter, mode);
1479
1480 RTW_INFO(FUNC_ADPT_FMT ": hw_port(%d) mode=%d\n",
1481 FUNC_ADPT_ARG(adapter), adapter->hw_port, mode);
1482
1483 switch (mode) {
1484 case _HW_STATE_NOLINK_:
1485 case _HW_STATE_STATION_:
1486 if (_FALSE == is_ap_exist) {
1487 rtl8822b_stop_tx_beacon(adapter);
1488 #ifdef CONFIG_PCI_HCI
1489 UpdateInterruptMask8822BE(adapter, 0, 0, RT_BCN_INT_MASKS, 0);
1490 #endif /* CONFIG_PCI_HCI */
1491 }
1492
1493 /* disable beacon function */
1494 val8 = BIT_CLI0_DIS_TSF_UDT_8822B | BIT_CLI0_EN_BCN_FUNCTION_8822B;
1495 rtw_write8(adapter, REG_BCN_CTRL_CLINT0_8822B, val8);
1496
1497 /* clear rx ctrl frame */
1498 rtw_write16(adapter, REG_RXFLTMAP1_8822B, 0);
1499 break;
1500
1501 case _HW_STATE_ADHOC_:
1502 rtl8822b_resume_tx_beacon(adapter);
1503 val8 = BIT_CLI0_DIS_TSF_UDT_8822B | BIT_CLI0_EN_BCN_FUNCTION_8822B;
1504 rtw_write8(adapter, REG_BCN_CTRL_CLINT0_8822B, val8);
1505
1506 /* clear rx ctrl frame */
1507 rtw_write16(adapter, REG_RXFLTMAP1_8822B, 0);
1508 break;
1509
1510 case _HW_STATE_AP_:
1511 #ifdef CONFIG_PCI_HCI
1512 UpdateInterruptMask8822BE(adapter, RT_BCN_INT_MASKS, 0, 0, 0);
1513 #endif /* CONFIG_PCI_HCI */
1514 /* ToDo */
1515 break;
1516 }
1517 #endif /* CONFIG_CONCURRENT_MODE */
1518 }
1519
hw_var_set_opmode(PADAPTER adapter,u8 mode)1520 static void hw_var_set_opmode(PADAPTER adapter, u8 mode)
1521 {
1522 u8 val8;
1523 static u8 isMonitor = _FALSE;
1524
1525
1526 if (isMonitor == _TRUE) {
1527 u32 rcr;
1528 /* reset RCR */
1529 rcr = BIT_APM_8822B
1530 | BIT_AM_8822B
1531 | BIT_AB_8822B
1532 | BIT_CBSSID_DATA_8822B
1533 | BIT_CBSSID_BCN_8822B
1534 | BIT_HTC_LOC_CTRL_8822B
1535 | BIT_VHT_DACK_8822B
1536 | BIT_APP_PHYSTS_8822B
1537 | BIT_APP_ICV_8822B
1538 | BIT_APP_MIC_8822B
1539 ;
1540 rtl8822b_rcr_config(adapter, rcr);
1541 isMonitor = _FALSE;
1542 }
1543
1544 if (mode == _HW_STATE_MONITOR_) {
1545 isMonitor = _TRUE;
1546
1547 Set_MSR(adapter, _HW_STATE_NOLINK_);
1548 set_opmode_monitor(adapter);
1549 return;
1550 }
1551
1552 /* clear crc bit */
1553 if (rtl8822b_rcr_check(adapter, BIT_ACRC32_8822B))
1554 rtl8822b_rcr_clear(adapter, BIT_ACRC32_8822B);
1555
1556 switch (adapter->hw_port) {
1557 case HW_PORT0:
1558 set_opmode_port0(adapter, mode);
1559 break;
1560
1561 case HW_PORT1:
1562 set_opmode_port1(adapter, mode);
1563 break;
1564
1565 default:
1566 break;
1567 }
1568 }
1569
hw_var_set_macaddr(PADAPTER adapter,u8 * val)1570 static void hw_var_set_macaddr(PADAPTER adapter, u8 *val)
1571 {
1572 u8 port;
1573
1574
1575 port = adapter->hw_port;
1576 rtw_halmac_set_mac_address(adapter_to_dvobj(adapter), port, val);
1577 }
1578
hw_var_set_bssid(PADAPTER adapter,u8 * val)1579 static void hw_var_set_bssid(PADAPTER adapter, u8 *val)
1580 {
1581 u8 idx = 0;
1582 u32 reg_bssid;
1583
1584 #ifdef CONFIG_CONCURRENT_MODE
1585 if (adapter->hw_port == HW_PORT1)
1586 reg_bssid = REG_BSSID1_8822B;
1587 else
1588 #endif
1589 reg_bssid = REG_BSSID_8822B;
1590
1591 for (idx = 0; idx < 6; idx++)
1592 rtw_write8(adapter, (reg_bssid + idx), val[idx]);
1593 }
1594
hw_var_set_basic_rate(PADAPTER adapter,u8 * ratetbl)1595 static void hw_var_set_basic_rate(PADAPTER adapter, u8 *ratetbl)
1596 {
1597 #define RATE_1M BIT(0)
1598 #define RATE_2M BIT(1)
1599 #define RATE_5_5M BIT(2)
1600 #define RATE_11M BIT(3)
1601 #define RATE_6M BIT(4)
1602 #define RATE_9M BIT(5)
1603 #define RATE_12M BIT(6)
1604 #define RATE_18M BIT(7)
1605 #define RATE_24M BIT(8)
1606 #define RATE_36M BIT(9)
1607 #define RATE_48M BIT(10)
1608 #define RATE_54M BIT(11)
1609 #define RATE_MCS0 BIT(12)
1610 #define RATE_MCS1 BIT(13)
1611 #define RATE_MCS2 BIT(14)
1612 #define RATE_MCS3 BIT(15)
1613 #define RATE_MCS4 BIT(16)
1614 #define RATE_MCS5 BIT(17)
1615 #define RATE_MCS6 BIT(18)
1616 #define RATE_MCS7 BIT(19)
1617
1618 #define RATES_CCK (RATE_11M | RATE_5_5M | RATE_2M | RATE_1M)
1619 #define RATES_OFDM (RATE_54M | RATE_48M | RATE_36M | RATE_24M | RATE_18M | RATE_12M | RATE_9M | RATE_6M)
1620
1621 struct mlme_ext_info *mlmext_info = &adapter->mlmeextpriv.mlmext_info;
1622 PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
1623 u16 input_b = 0, masked = 0, ioted = 0, BrateCfg = 0;
1624 u16 rrsr_2g_force_mask = RATES_CCK;
1625 u16 rrsr_2g_allow_mask = RATE_24M | RATE_12M | RATE_6M | RATES_CCK;
1626 u16 rrsr_5g_force_mask = RATE_6M;
1627 u16 rrsr_5g_allow_mask = RATES_OFDM;
1628 u32 val32;
1629
1630 HalSetBrateCfg(adapter, ratetbl, &BrateCfg);
1631 input_b = BrateCfg;
1632
1633 /* apply force and allow mask */
1634 if (hal->CurrentBandType == BAND_ON_2_4G) {
1635 BrateCfg |= rrsr_2g_force_mask;
1636 BrateCfg &= rrsr_2g_allow_mask;
1637 } else {
1638 BrateCfg |= rrsr_5g_force_mask;
1639 BrateCfg &= rrsr_5g_allow_mask;
1640 }
1641
1642 masked = BrateCfg;
1643
1644 /* IOT consideration */
1645 if (mlmext_info->assoc_AP_vendor == HT_IOT_PEER_CISCO) {
1646 /* if peer is cisco and didn't use ofdm rate, we enable 6M ack */
1647 if ((BrateCfg & (RATE_24M | RATE_12M | RATE_6M)) == 0)
1648 BrateCfg |= RATE_6M;
1649 }
1650
1651 ioted = BrateCfg;
1652
1653 hal->BasicRateSet = BrateCfg;
1654
1655 RTW_INFO("[HW_VAR_BASIC_RATE] %#x->%#x->%#x\n", input_b, masked, ioted);
1656
1657 /* Set RRSR rate table. */
1658 val32 = rtw_read32(adapter, REG_RRSR_8822B);
1659 val32 &= ~(BIT_MASK_RRSC_BITMAP << BIT_SHIFT_RRSC_BITMAP);
1660 val32 |= BIT_RRSC_BITMAP(BrateCfg);
1661 val32 = rtw_write32(adapter, REG_RRSR_8822B, val32);
1662 }
1663
hw_var_set_bcn_func(PADAPTER adapter,u8 enable)1664 static void hw_var_set_bcn_func(PADAPTER adapter, u8 enable)
1665 {
1666 u32 bcn_ctrl_reg;
1667 u8 val8;
1668
1669 #ifdef CONFIG_CONCURRENT_MODE
1670 if (adapter->hw_port == HW_PORT1)
1671 bcn_ctrl_reg = REG_BCN_CTRL_CLINT0_8822B;
1672 else
1673 #endif
1674 bcn_ctrl_reg = REG_BCN_CTRL_8822B;
1675
1676 if (enable) {
1677 /* enable TX BCN report
1678 * Reg REG_FWHW_TXQ_CTRL_8822B[2] = 1
1679 * Reg REG_BCN_CTRL_8822B[3][5] = 1
1680 */
1681 val8 = rtw_read8(adapter, REG_FWHW_TXQ_CTRL_8822B);
1682 val8 |= BIT_EN_BCN_TRXRPT_V1_8822B;
1683 rtw_write8(adapter, REG_FWHW_TXQ_CTRL_8822B, val8);
1684
1685 if (bcn_ctrl_reg == REG_BCN_CTRL_CLINT0_8822B) {
1686 /* setting port 1 */
1687 val8 = rtw_read8(adapter, REG_BCN_CTRL_8822B);
1688 val8 |= BIT_EN_BCN_FUNCTION_8822B | BIT_P0_EN_TXBCN_RPT_8822B;
1689 rtw_write8(adapter, REG_BCN_CTRL_8822B, val8);
1690
1691 val8 = rtw_read8(adapter, REG_BCN_CTRL_CLINT0_8822B);
1692 val8 |= BIT_CLI0_EN_BCN_FUNCTION_8822B;
1693 rtw_write8(adapter, bcn_ctrl_reg, val8);
1694 } else {
1695 /* setting port 0 */
1696 val8 = BIT_EN_BCN_FUNCTION_8822B | BIT_P0_EN_TXBCN_RPT_8822B;
1697 rtw_write8(adapter, bcn_ctrl_reg, val8);
1698 }
1699 } else {
1700 val8 = rtw_read8(adapter, bcn_ctrl_reg);
1701 val8 &= ~(BIT_EN_BCN_FUNCTION_8822B | BIT_P0_EN_TXBCN_RPT_8822B);
1702 #ifdef CONFIG_BT_COEXIST
1703 /* Always enable port0 beacon function for PSTDMA */
1704 if (GET_HAL_DATA(adapter)->EEPROMBluetoothCoexist) {
1705 if (REG_BCN_CTRL_8822B == bcn_ctrl_reg)
1706 val8 |= BIT_EN_BCN_FUNCTION_8822B;
1707 }
1708 #endif /* CONFIG_BT_COEXIST */
1709 rtw_write8(adapter, bcn_ctrl_reg, val8);
1710 }
1711 }
1712
hw_var_set_correct_tsf(PADAPTER adapter)1713 static void hw_var_set_correct_tsf(PADAPTER adapter)
1714 {
1715 #ifdef CONFIG_MI_WITH_MBSSID_CAM
1716 /* do nothing */
1717 #else /* !CONFIG_MI_WITH_MBSSID_CAM */
1718 u64 tsf;
1719 struct mlme_ext_priv *pmlmeext;
1720 struct mlme_ext_info *pmlmeinfo;
1721
1722
1723 pmlmeext = &adapter->mlmeextpriv;
1724 pmlmeinfo = &pmlmeext->mlmext_info;
1725
1726 tsf = pmlmeext->TSFValue - rtw_modular64(pmlmeext->TSFValue, (pmlmeinfo->bcn_interval * 1024)) - 1024; /* us */
1727
1728 if (((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE)
1729 || ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE))
1730 rtl8822b_stop_tx_beacon(adapter);
1731
1732 rtw_hal_correct_tsf(adapter, adapter->hw_port, tsf);
1733
1734 #ifdef CONFIG_CONCURRENT_MODE
1735 /* Update buddy port's TSF if it is SoftAP for beacon TX issue!*/
1736 if (((pmlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE)
1737 && (rtw_mi_check_status(adapter, MI_AP_MODE) == _TRUE)) {
1738 struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
1739 u32 i;
1740 PADAPTER iface;
1741
1742 for (i = 0; i < dvobj->iface_nums; i++) {
1743 iface = dvobj->padapters[i];
1744 if (!iface)
1745 continue;
1746 if (iface == adapter)
1747 continue;
1748
1749 if ((check_fwstate(&iface->mlmepriv, WIFI_AP_STATE) == _TRUE)
1750 && (check_fwstate(&iface->mlmepriv, WIFI_ASOC_STATE) == _TRUE)) {
1751 rtw_hal_correct_tsf(iface, iface->hw_port, tsf);
1752 #ifdef CONFIG_TSF_RESET_OFFLOAD
1753 if (reset_tsf(iface, iface->hw_port) == _FALSE)
1754 RTW_INFO(FUNC_ADPT_FMT": [ERROR] Reset port%d TSF fail!\n",
1755 FUNC_ADPT_ARG(iface), iface->hw_port);
1756 #endif /* CONFIG_TSF_RESET_OFFLOAD */
1757 }
1758 }
1759 }
1760 #endif /* CONFIG_CONCURRENT_MODE */
1761
1762 if (((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE)
1763 || ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE))
1764 rtl8822b_resume_tx_beacon(adapter);
1765 #endif /* !CONFIG_MI_WITH_MBSSID_CAM */
1766 }
1767
hw_var_set_check_bssid(PADAPTER adapter,u8 enable)1768 static void hw_var_set_check_bssid(PADAPTER adapter, u8 enable)
1769 {
1770 u32 rcr;
1771
1772 rcr = BIT_CBSSID_DATA_8822B | BIT_CBSSID_BCN_8822B;
1773 if (enable)
1774 rtl8822b_rcr_add(adapter, rcr);
1775 else
1776 rtl8822b_rcr_clear(adapter, rcr);
1777
1778 RTW_INFO("%s: [HW_VAR_CHECK_BSSID] 0x%x=0x%x\n", __FUNCTION__,
1779 REG_RCR_8822B, rtw_read32(adapter, REG_RCR_8822B));
1780 }
1781
hw_var_set_mlme_disconnect(PADAPTER adapter)1782 static void hw_var_set_mlme_disconnect(PADAPTER adapter)
1783 {
1784 u8 val8;
1785 u8 ld_sta_num = 0, lg_sta_num = 0;
1786
1787 #ifdef CONFIG_CONCURRENT_MODE
1788 if (rtw_mi_check_status(adapter, MI_LINKED) == _FALSE)
1789 #endif
1790 /* reject all data frames under not link state */
1791 rtw_write16(adapter, REG_RXFLTMAP_8822B, 0);
1792
1793 #ifdef CONFIG_CONCURRENT_MODE
1794 if (adapter->hw_port == HW_PORT1) {
1795 /* reset TSF1(CLINT0) */
1796 rtw_write8(adapter, REG_DUAL_TSF_RST_8822B, BIT_TSFTR_CLI0_RST_8822B);
1797
1798 /* disable update TSF1(CLINT0) */
1799 val8 = rtw_read8(adapter, REG_BCN_CTRL_CLINT0_8822B);
1800 val8 |= BIT_CLI0_DIS_TSF_UDT_8822B;
1801 rtw_write8(adapter, REG_BCN_CTRL_CLINT0_8822B, val8);
1802
1803 /* disable Port1's beacon function */
1804 val8 = rtw_read8(adapter, REG_BCN_CTRL_CLINT0_8822B);
1805 val8 &= ~BIT_CLI0_EN_BCN_FUNCTION_8822B;
1806 rtw_write8(adapter, REG_BCN_CTRL_CLINT0_8822B, val8);
1807 } else
1808 #endif
1809 {
1810 /* reset TSF */
1811 rtw_write8(adapter, REG_DUAL_TSF_RST_8822B, BIT_TSFTR_RST_8822B);
1812
1813 /* disable update TSF */
1814 val8 = rtw_read8(adapter, REG_BCN_CTRL_8822B);
1815 val8 |= BIT_DIS_TSF_UDT_8822B;
1816 rtw_write8(adapter, REG_BCN_CTRL_8822B, val8);
1817 }
1818
1819 rtw_mi_status_no_self(adapter, NULL, &ld_sta_num, &lg_sta_num, NULL, NULL, NULL);
1820
1821 /* clear update TSF only BSSID match for no linked station */
1822 if (ld_sta_num == 0 && lg_sta_num == 0)
1823 rtl8822b_rx_tsf_addr_filter_config(adapter, 0);
1824 }
1825
hw_var_set_mlme_sitesurvey(PADAPTER adapter,u8 enable)1826 static void hw_var_set_mlme_sitesurvey(PADAPTER adapter, u8 enable)
1827 {
1828 struct dvobj_priv *dvobj;
1829 PHAL_DATA_TYPE hal;
1830 struct mlme_priv *pmlmepriv;
1831 PADAPTER iface;
1832 u32 rcr_bit, reg_bcn_ctl;
1833 u16 value_rxfltmap2;
1834 u8 val8, i;
1835
1836
1837 dvobj = adapter_to_dvobj(adapter);
1838 hal = GET_HAL_DATA(adapter);
1839 pmlmepriv = &adapter->mlmepriv;
1840
1841 #ifdef CONFIG_FIND_BEST_CHANNEL
1842 rcr_bit = BIT_CBSSID_BCN_8822B | BIT_CBSSID_DATA_8822B;
1843
1844 /* Receive all data frames */
1845 value_rxfltmap2 = 0xFFFF;
1846 #else /* CONFIG_FIND_BEST_CHANNEL */
1847 rcr_bit = BIT_CBSSID_BCN_8822B;
1848
1849 /* config RCR to receive different BSSID & not to receive data frame */
1850 value_rxfltmap2 = 0;
1851 #endif /* CONFIG_FIND_BEST_CHANNEL */
1852
1853 if (rtw_mi_check_fwstate(adapter, WIFI_AP_STATE))
1854 rcr_bit = BIT_CBSSID_BCN_8822B;
1855 #ifdef CONFIG_TDLS
1856 /* TDLS will clear RCR_CBSSID_DATA bit for connection. */
1857 else if (adapter->tdlsinfo.link_established == _TRUE)
1858 rcr_bit = BIT_CBSSID_BCN_8822B;
1859 #endif /* CONFIG_TDLS */
1860
1861 if (enable) {
1862 /*
1863 * 1. configure REG_RXFLTMAP2
1864 * 2. config RCR to receive different BSSID BCN or probe rsp
1865 */
1866
1867 rtw_write16(adapter, REG_RXFLTMAP_8822B, value_rxfltmap2);
1868
1869 rtl8822b_rcr_clear(adapter, rcr_bit);
1870
1871 /* Save orignal RRSR setting. */
1872 hal->RegRRSR = rtw_read16(adapter, REG_RRSR_8822B);
1873
1874 if (rtw_mi_check_status(adapter, MI_AP_MODE))
1875 rtl8822b_stop_tx_beacon(adapter);
1876 } else {
1877 /* sitesurvey done
1878 * 1. enable rx data frame
1879 * 2. config RCR not to receive different BSSID BCN or probe rsp
1880 */
1881
1882 if (rtw_mi_check_fwstate(adapter, _FW_LINKED | WIFI_AP_STATE))
1883 /* enable to rx data frame */
1884 rtw_write16(adapter, REG_RXFLTMAP_8822B, 0xFFFF);
1885
1886 #ifdef CONFIG_MI_WITH_MBSSID_CAM
1887 rtl8822b_rcr_clear(adapter, BIT_CBSSID_BCN_8822B | BIT_CBSSID_DATA_8822B);
1888 #else /* CONFIG_MI_WITH_MBSSID_CAM */
1889 rtl8822b_rcr_add(adapter, rcr_bit);
1890 #endif /* CONFIG_MI_WITH_MBSSID_CAM */
1891
1892 /* Restore orignal RRSR setting. */
1893 rtw_write16(adapter, REG_RRSR_8822B, hal->RegRRSR);
1894
1895 if (rtw_mi_check_status(adapter, MI_AP_MODE)) {
1896 ResumeTxBeacon(adapter);
1897 rtw_mi_tx_beacon_hdl(adapter);
1898 }
1899 }
1900 }
1901
hw_var_set_mlme_join(PADAPTER adapter,u8 type)1902 static void hw_var_set_mlme_join(PADAPTER adapter, u8 type)
1903 {
1904 u8 val8;
1905 u16 val16;
1906 u32 val32;
1907 u8 RetryLimit;
1908 PHAL_DATA_TYPE hal;
1909 struct mlme_priv *pmlmepriv;
1910
1911 RetryLimit = 0x30;
1912 hal = GET_HAL_DATA(adapter);
1913 pmlmepriv = &adapter->mlmepriv;
1914
1915
1916 #ifdef CONFIG_CONCURRENT_MODE
1917 if (type == 0) {
1918 /* prepare to join */
1919 if (rtw_mi_check_status(adapter, MI_AP_MODE))
1920 rtl8822b_stop_tx_beacon(adapter);
1921
1922 /* enable to rx data frame.Accept all data frame */
1923 rtw_write16(adapter, REG_RXFLTMAP_8822B, 0xFFFF);
1924
1925 #ifdef CONFIG_MI_WITH_MBSSID_CAM
1926 val32 = BIT_CBSSID_DATA_8822B | BIT_CBSSID_BCN_8822B;
1927 rtl8822b_rcr_clear(adapter, val32);
1928 #else /* !CONFIG_MI_WITH_MBSSID_CAM */
1929 if (rtw_mi_check_status(adapter, MI_AP_MODE))
1930 val32 = BIT_CBSSID_BCN_8822B;
1931 else
1932 val32 = BIT_CBSSID_DATA_8822B | BIT_CBSSID_BCN_8822B;
1933 rtl8822b_rcr_add(adapter, val32);
1934 #endif /* !CONFIG_MI_WITH_MBSSID_CAM */
1935
1936 if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE)
1937 RetryLimit = (hal->CustomerID == RT_CID_CCX) ? 7 : 48;
1938 else /* Ad-hoc Mode */
1939 RetryLimit = 0x7;
1940
1941 /*
1942 * for 8822B, must enable BCN function if BIT_CBSSID_BCN_8822B(bit 7) of REG_RCR(0x608) is enable to recv BSSID bcn
1943 */
1944 hw_var_set_bcn_func(adapter, _TRUE);
1945
1946 /* update TSF only BSSID match for station mode */
1947 rtl8822b_rx_tsf_addr_filter_config(adapter, BIT_CHK_TSF_EN_8822B | BIT_CHK_TSF_CBSSID_8822B);
1948 } else if (type == 1) {
1949 /* joinbss_event call back when join res < 0 */
1950 if (rtw_mi_check_status(adapter, MI_LINKED) == _FALSE)
1951 rtw_write16(adapter, REG_RXFLTMAP_8822B, 0x00);
1952
1953 if (rtw_mi_check_status(adapter, MI_AP_MODE)) {
1954 rtl8822b_resume_tx_beacon(adapter);
1955
1956 /* reset TSF 1/2 after resume_tx_beacon */
1957 val8 = BIT_TSFTR_RST_8822B | BIT_TSFTR_CLI0_RST_8822B;
1958 rtw_write8(adapter, REG_DUAL_TSF_RST_8822B, val8);
1959 }
1960 } else if (type == 2) {
1961 /* sta add event callback */
1962
1963 #ifdef CONFIG_MI_WITH_MBSSID_CAM
1964 #else /* !CONFIG_MI_WITH_MBSSID_CAM */
1965 /* enable update TSF */
1966 if (adapter->hw_port == HW_PORT1) {
1967 val8 = rtw_read8(adapter, REG_BCN_CTRL_CLINT0_8822B);
1968 val8 &= ~BIT_DIS_TSF_UDT_8822B;
1969 rtw_write8(adapter, REG_BCN_CTRL_CLINT0_8822B, val8);
1970 } else {
1971 val8 = rtw_read8(adapter, REG_BCN_CTRL_8822B);
1972 val8 &= ~BIT_DIS_TSF_UDT_8822B;
1973 rtw_write8(adapter, REG_BCN_CTRL_8822B, val8);
1974 }
1975 #endif /* !CONFIG_MI_WITH_MBSSID_CAM */
1976
1977 if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE)) {
1978 rtw_write8(adapter, 0x542, 0x02);
1979 RetryLimit = 0x7;
1980 }
1981
1982 if (rtw_mi_check_status(adapter, MI_AP_MODE)) {
1983 rtl8822b_resume_tx_beacon(adapter);
1984
1985 /* reset TSF 1/2 after resume_tx_beacon */
1986 rtw_write8(adapter, REG_DUAL_TSF_RST_8822B, BIT_TSFTR_RST_8822B | BIT_TSFTR_CLI0_RST_8822B);
1987 }
1988 }
1989
1990 val16 = BIT_LRL_8822B(RetryLimit) | BIT_SRL_8822B(RetryLimit);
1991 rtw_write16(adapter, REG_RETRY_LIMIT_8822B, val16);
1992 #else /* !CONFIG_CONCURRENT_MODE */
1993 if (type == 0) {
1994 /* prepare to join */
1995
1996 /* enable to rx data frame.Accept all data frame */
1997 rtw_write16(adapter, REG_RXFLTMAP_8822B, 0xFFFF);
1998
1999 hw_var_set_check_bssid(adapter, !adapter->in_cta_test);
2000
2001 /*
2002 * for 8822B, must enable BCN function if BIT_CBSSID_BCN_8822B(bit 7) of REG_RCR(0x608) is enable to recv BSSID bcn
2003 */
2004 hw_var_set_bcn_func(adapter, _TRUE);
2005
2006 /* update TSF only BSSID match for station mode */
2007 rtl8822b_rx_tsf_addr_filter_config(adapter, BIT_CHK_TSF_EN_8822B | BIT_CHK_TSF_CBSSID_8822B);
2008
2009 if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE)
2010 RetryLimit = (hal->CustomerID == RT_CID_CCX) ? 7 : 48;
2011 else /* Ad-hoc Mode */
2012 RetryLimit = 0x7;
2013 } else if (type == 1) {
2014 /* joinbss_event call back when join res < 0 */
2015 rtw_write16(adapter, REG_RXFLTMAP_8822B, 0x00);
2016 } else if (type == 2) {
2017 /* sta add event callback */
2018
2019 /* enable update TSF */
2020 val8 = rtw_read8(adapter, REG_BCN_CTRL_8822B);
2021 val8 &= ~BIT_DIS_TSF_UDT_8822B;
2022 rtw_write8(adapter, REG_BCN_CTRL_8822B, val8);
2023
2024 if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE))
2025 RetryLimit = 0x7;
2026 }
2027
2028 val16 = BIT_LRL_8822B(RetryLimit) | BIT_SRL_8822B(RetryLimit);
2029 rtw_write16(adapter, REG_RETRY_LIMIT_8822B, val16);
2030 #endif /* !CONFIG_CONCURRENT_MODE */
2031 }
2032
hw_var_set_acm_ctrl(PADAPTER adapter,u8 ctrl)2033 static void hw_var_set_acm_ctrl(PADAPTER adapter, u8 ctrl)
2034 {
2035 u8 hwctrl = 0;
2036
2037 if (ctrl) {
2038 hwctrl |= BIT_ACMHWEN_8822B;
2039
2040 if (ctrl & BIT(1)) /* BE */
2041 hwctrl |= BIT_BEQ_ACM_EN_8822B;
2042 else
2043 hwctrl &= (~BIT_BEQ_ACM_EN_8822B);
2044
2045 if (ctrl & BIT(2)) /* VI */
2046 hwctrl |= BIT_VIQ_ACM_EN_8822B;
2047 else
2048 hwctrl &= (~BIT_VIQ_ACM_EN_8822B);
2049
2050 if (ctrl & BIT(3)) /* VO */
2051 hwctrl |= BIT_VOQ_ACM_EN_8822B;
2052 else
2053 hwctrl &= (~BIT_VOQ_ACM_EN_8822B);
2054 }
2055
2056 RTW_INFO("[HW_VAR_ACM_CTRL] Write 0x%02X\n", hwctrl);
2057 rtw_write8(adapter, REG_ACMHWCTRL_8822B, hwctrl);
2058 }
2059
hw_var_set_rcr_am(PADAPTER adapter,u8 enable)2060 static void hw_var_set_rcr_am(PADAPTER adapter, u8 enable)
2061 {
2062 u32 rcr;
2063
2064 rcr = BIT_AM_8822B;
2065 if (enable)
2066 rtl8822b_rcr_add(adapter, rcr);
2067 else
2068 rtl8822b_rcr_clear(adapter, rcr);
2069
2070 RTW_INFO("%s: [HW_VAR_ON_RCR_AM] RCR(0x%x)=0x%x\n",
2071 __FUNCTION__, REG_RCR_8822B, rtw_read32(adapter, REG_RCR_8822B));
2072 }
2073
hw_var_set_bcn_interval(PADAPTER adapter,u16 bcn_interval)2074 static void hw_var_set_bcn_interval(PADAPTER adapter, u16 bcn_interval)
2075 {
2076 u16 val16 = 0;
2077
2078 #ifdef CONFIG_CONCURRENT_MODE
2079 if (adapter->hw_port == HW_PORT1) {
2080 /* Port 1(clint 0) */
2081 val16 = rtw_read16(adapter, (REG_MBSSID_BCN_SPACE_8822B + 2));
2082 val16 |= (bcn_interval & BIT_MASK_BCN_SPACE_CLINT0_8822B);
2083 rtw_write16(adapter, REG_MBSSID_BCN_SPACE_8822B + 2, val16);
2084 } else
2085 #endif
2086 {
2087 /* Port 0 */
2088 val16 = rtw_read16(adapter, (REG_MBSSID_BCN_SPACE_8822B));
2089 val16 |= (bcn_interval & BIT_MASK_BCN_SPACE0_8822B);
2090 rtw_write16(adapter, REG_MBSSID_BCN_SPACE_8822B, val16);
2091 }
2092
2093 RTW_INFO("%s: [HW_VAR_BEACON_INTERVAL] 0x%x=0x%x\n", __FUNCTION__,
2094 REG_MBSSID_BCN_SPACE_8822B, rtw_read32(adapter, REG_MBSSID_BCN_SPACE_8822B));
2095 }
2096
hw_var_set_sec_dk_cfg(PADAPTER adapter,u8 enable)2097 static void hw_var_set_sec_dk_cfg(PADAPTER adapter, u8 enable)
2098 {
2099 struct security_priv *sec = &adapter->securitypriv;
2100 u8 reg_scr = rtw_read8(adapter, REG_SECCFG_8822B);
2101
2102 if (enable) {
2103 /* Enable default key related setting */
2104 reg_scr |= BIT_TXBCUSEDK_8822B;
2105 if (sec->dot11AuthAlgrthm != dot11AuthAlgrthm_8021X)
2106 reg_scr |= BIT_RXUHUSEDK_8822B | BIT_TXUHUSEDK_8822B;
2107 } else {
2108 /* Disable default key related setting */
2109 reg_scr &= ~(BIT_RXBCUSEDK_8822B | BIT_TXBCUSEDK_8822B | BIT_RXUHUSEDK_8822B | BIT_TXUHUSEDK_8822B);
2110 }
2111
2112 rtw_write8(adapter, REG_SECCFG_8822B, reg_scr);
2113
2114 RTW_INFO("%s: [HW_VAR_SEC_DK_CFG] 0x%x=0x%08x\n", __FUNCTION__,
2115 REG_SECCFG_8822B, rtw_read32(adapter, REG_SECCFG_8822B));
2116 }
2117
hw_var_set_bcn_valid(PADAPTER adapter)2118 static void hw_var_set_bcn_valid(PADAPTER adapter)
2119 {
2120 u8 val8 = 0;
2121
2122 /* only port 0 can TX BCN */
2123 val8 = rtw_read8(adapter, REG_FIFOPAGE_CTRL_2_8822B + 1);
2124 val8 = val8 | BIT(7);
2125 rtw_write8(adapter, REG_FIFOPAGE_CTRL_2_8822B + 1, val8);
2126 }
2127
hw_var_set_cam_empty_entry(PADAPTER adapter,u8 ucIndex)2128 static void hw_var_set_cam_empty_entry(PADAPTER adapter, u8 ucIndex)
2129 {
2130 u8 i;
2131 u32 ulCommand = 0;
2132 u32 ulContent = 0;
2133 u32 ulEncAlgo = CAM_AES;
2134
2135 for (i = 0; i < CAM_CONTENT_COUNT; i++) {
2136 /* filled id in CAM config 2 byte */
2137 if (i == 0)
2138 ulContent |= (ucIndex & 0x03) | ((u16)(ulEncAlgo) << 2);
2139 else
2140 ulContent = 0;
2141
2142 /* polling bit, and No Write enable, and address */
2143 ulCommand = CAM_CONTENT_COUNT * ucIndex + i;
2144 ulCommand |= BIT_SECCAM_POLLING_8822B | BIT_SECCAM_WE_8822B;
2145 /* write content 0 is equall to mark invalid */
2146 rtw_write32(adapter, REG_CAMWRITE_8822B, ulContent);
2147 rtw_write32(adapter, REG_CAMCMD_8822B, ulCommand);
2148 }
2149 }
2150
hw_var_set_ack_preamble(PADAPTER adapter,u8 bShortPreamble)2151 static void hw_var_set_ack_preamble(PADAPTER adapter, u8 bShortPreamble)
2152 {
2153 u8 val8 = 0;
2154
2155
2156 val8 = rtw_read8(adapter, REG_WMAC_TRXPTCL_CTL_8822B + 2);
2157 val8 |= BIT(4) | BIT(5);
2158
2159 if (bShortPreamble)
2160 val8 |= BIT1;
2161 else
2162 val8 &= (~BIT1);
2163
2164 rtw_write8(adapter, REG_WMAC_TRXPTCL_CTL_8822B + 2, val8);
2165 }
2166
hw_var_set_dl_rsvd_page(PADAPTER adapter,u8 mstatus)2167 void hw_var_set_dl_rsvd_page(PADAPTER adapter, u8 mstatus)
2168 {
2169 PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
2170 struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
2171 struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
2172 struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
2173 u8 bcn_valid = _FALSE;
2174 u8 DLBcnCount = 0;
2175 u32 poll = 0;
2176 u8 val8;
2177
2178
2179 RTW_INFO(FUNC_ADPT_FMT ":+ hw_port=%d mstatus(%x)\n",
2180 FUNC_ADPT_ARG(adapter), get_hw_port(adapter), mstatus);
2181
2182 if (mstatus == RT_MEDIA_CONNECT) {
2183 #if 0
2184 u8 bRecover = _FALSE;
2185 #endif
2186 u8 v8;
2187
2188 /* We should set AID, correct TSF, HW seq enable before set JoinBssReport to Fw in 88/92C. */
2189 rtw_write16(adapter, REG_BCN_PSR_RPT_8822B, (0xC000 | pmlmeinfo->aid));
2190
2191 /* Enable SW TX beacon */
2192 v8 = rtw_read8(adapter, REG_CR_8822B + 1);
2193 v8 |= (BIT_ENSWBCN_8822B >> 8);
2194 rtw_write8(adapter, REG_CR_8822B + 1, v8);
2195
2196 /*
2197 * Disable Hw protection for a time which revserd for Hw sending beacon.
2198 * Fix download reserved page packet fail that access collision with the protection time.
2199 */
2200 val8 = rtw_read8(adapter, REG_BCN_CTRL_8822B);
2201 val8 &= ~BIT_EN_BCN_FUNCTION_8822B;
2202 val8 |= BIT_DIS_TSF_UDT_8822B;
2203 rtw_write8(adapter, REG_BCN_CTRL_8822B, val8);
2204
2205 #if 0
2206 /* Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame. */
2207 if (hal->RegFwHwTxQCtrl & BIT(6))
2208 bRecover = _TRUE;
2209
2210 /* To tell Hw the packet is not a real beacon frame. */
2211 val8 = hal->RegFwHwTxQCtrl & ~BIT(6);
2212 rtw_write8(adapter, REG_FWHW_TXQ_CTRL_8822B + 2, val8);
2213 hal->RegFwHwTxQCtrl &= ~BIT(6);
2214 #endif
2215
2216 /* Clear beacon valid check bit. */
2217 rtw_hal_set_hwreg(adapter, HW_VAR_BCN_VALID, NULL);
2218 rtw_hal_set_hwreg(adapter, HW_VAR_DL_BCN_SEL, NULL);
2219
2220 DLBcnCount = 0;
2221 poll = 0;
2222 do {
2223 /* download rsvd page. */
2224 rtw_hal_set_fw_rsvd_page(adapter, 0);
2225 DLBcnCount++;
2226 do {
2227 rtw_yield_os();
2228
2229 /* check rsvd page download OK. */
2230 rtw_hal_get_hwreg(adapter, HW_VAR_BCN_VALID, (u8 *)&bcn_valid);
2231 poll++;
2232 } while (!bcn_valid && (poll % 10) != 0 && !RTW_CANNOT_RUN(adapter));
2233
2234 } while (!bcn_valid && DLBcnCount <= 100 && !RTW_CANNOT_RUN(adapter));
2235
2236 if (RTW_CANNOT_RUN(adapter))
2237 ;
2238 else if (!bcn_valid)
2239 RTW_INFO(FUNC_ADPT_FMT ": DL RSVD page failed! DLBcnCount:%u, poll:%u\n",
2240 FUNC_ADPT_ARG(adapter), DLBcnCount, poll);
2241 else {
2242 struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);
2243
2244 pwrctl->fw_psmode_iface_id = adapter->iface_id;
2245 RTW_INFO(ADPT_FMT ": DL RSVD page success! DLBcnCount:%u, poll:%u\n",
2246 ADPT_ARG(adapter), DLBcnCount, poll);
2247 }
2248
2249 val8 = rtw_read8(adapter, REG_BCN_CTRL_8822B);
2250 val8 |= BIT_EN_BCN_FUNCTION_8822B;
2251 val8 &= ~BIT_DIS_TSF_UDT_8822B;
2252 rtw_write8(adapter, REG_BCN_CTRL_8822B, val8);
2253 #if 0
2254 /*
2255 * To make sure that if there exists an adapter which would like to send beacon.
2256 * If exists, the origianl value of 0x422[6] will be 1, we should check this to
2257 * prevent from setting 0x422[6] to 0 after download reserved page, or it will cause
2258 * the beacon cannot be sent by HW.
2259 */
2260 if (bRecover) {
2261 rtw_write8(adapter, REG_FWHW_TXQ_CTRL_8822B + 2, hal->RegFwHwTxQCtrl | BIT(6));
2262 hal->RegFwHwTxQCtrl |= BIT(6);
2263 }
2264 #endif
2265 #ifndef CONFIG_PCI_HCI
2266 /* Clear CR[8] or beacon packet will not be send to TxBuf anymore. */
2267 v8 = rtw_read8(adapter, REG_CR_8822B + 1);
2268 v8 &= ~BIT(0); /* ~ENSWBCN */
2269 rtw_write8(adapter, REG_CR_8822B + 1, v8);
2270 #endif /* !CONFIG_PCI_HCI */
2271 }
2272 }
2273
hw_var_set_h2c_fw_joinbssrpt(PADAPTER adapter,u8 mstatus)2274 static void hw_var_set_h2c_fw_joinbssrpt(PADAPTER adapter, u8 mstatus)
2275 {
2276 if (mstatus == RT_MEDIA_CONNECT)
2277 hw_var_set_dl_rsvd_page(adapter, RT_MEDIA_CONNECT);
2278 }
2279
2280 /*
2281 * Description: Get the reserved page number in Tx packet buffer.
2282 * Retrun value: the page number.
2283 */
get_txbuffer_rsvdpagenum(PADAPTER adapter,bool wowlan)2284 u8 get_txbuffer_rsvdpagenum(PADAPTER adapter, bool wowlan)
2285 {
2286 u8 RsvdPageNum = HALMAC_RSVD_DRV_PGNUM_8822B;
2287
2288
2289 return RsvdPageNum;
2290 }
2291
2292 /*
2293 * Parameters:
2294 * adapter
2295 * enable _TRUE: enable; _FALSE: disable
2296 */
rx_agg_switch(PADAPTER adapter,u8 enable)2297 static u8 rx_agg_switch(PADAPTER adapter, u8 enable)
2298 {
2299 int err;
2300
2301 err = rtw_halmac_rx_agg_switch(adapter_to_dvobj(adapter), enable);
2302 if (err)
2303 return _FAIL;
2304
2305 return _SUCCESS;
2306 }
2307
hw_var_port_switch_8822b(_adapter * adapter)2308 void hw_var_port_switch_8822b(_adapter *adapter)
2309 {
2310 struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
2311 _adapter *if_p0 = NULL;
2312 _adapter *if_pn = adapter;
2313 u32 bssid_offset = 0;
2314 u8 bssid_p0[6] = {0};
2315 u8 bssid_pn[6] = {0};
2316 u8 tsftr_p0[8] = {0};
2317 u8 tsftr_pn[8] = {0};
2318 u8 vnet_type_p0 = 0;
2319 u8 vnet_type_pn = 0;
2320 u8 vbcn_ctrl_p0= 0;
2321 u8 vbcn_ctrl_pn= 0;
2322 u8 i = 0;
2323 u8 val8 = 0;
2324 u16 bcn_intv_p0 = 0;
2325 u16 bcn_intv_pn = 0;
2326 u32 addr_p0 = 0;
2327 u32 addr_pn = 0;
2328 u8 shift_p0 = 0;
2329 u8 shift_pn = 0;
2330 u16 mask_p0 = 0;
2331 u16 mask_pn = 0;
2332 u32 val32 = 0;
2333
2334 if (if_pn->hw_port == HW_PORT0)
2335 return;
2336
2337 /* Get iface of port-0 */
2338 for (i = 0; i < dvobj->iface_nums; i++) {
2339 if (get_hw_port(dvobj->padapters[i]) == HW_PORT0) {
2340 if_p0 = dvobj->padapters[i];
2341 break;
2342 }
2343 }
2344
2345 if (if_p0 == NULL) {
2346 RTW_ERR("%s port 0 adapter == NULL\n", __func__);
2347 rtw_warn_on(1);
2348 return;
2349 }
2350
2351 /* 1. BCN function */
2352
2353 /* Disable port_0 BCN function */
2354 vbcn_ctrl_p0= rtw_read8(adapter,
2355 port_cfg[if_p0->hw_port].bcn_ctl);
2356
2357 rtw_write8(adapter, port_cfg[if_p0->hw_port].bcn_ctl,
2358 vbcn_ctrl_p0 & ~BIT3);
2359
2360 /* Disable port_n BCN function */
2361 vbcn_ctrl_pn = rtw_read8(adapter,
2362 port_cfg[if_pn->hw_port].bcn_ctl);
2363
2364 rtw_write8(adapter, port_cfg[if_pn->hw_port].bcn_ctl,
2365 vbcn_ctrl_pn & ~BIT3);
2366
2367 /* 2. networt type */
2368 GetHwReg(if_p0, HW_VAR_MEDIA_STATUS, &vnet_type_p0);
2369 GetHwReg(if_pn, HW_VAR_MEDIA_STATUS, &vnet_type_pn);
2370
2371 Set_MSR(if_p0, vnet_type_pn);
2372 Set_MSR(if_pn, vnet_type_p0);
2373
2374 /* 3. BSSID */
2375 if (is_client_associated_to_ap(if_pn)) {
2376 RTW_INFO(ADPT_FMT" is STA mode and linked\n", ADPT_ARG(if_pn));
2377 bssid_offset = port_cfg[if_pn->hw_port].bssid;
2378 for (i = 0; i < 6; i++)
2379 bssid_pn[i] = rtw_read8(if_pn, bssid_offset + i);
2380 }
2381
2382 if (is_client_associated_to_ap(if_p0)) {
2383 RTW_INFO(ADPT_FMT" is STA mode and linked\n", ADPT_ARG(if_p0));
2384 bssid_offset = port_cfg[if_p0->hw_port].bssid;
2385 for (i = 0; i < 6; i++)
2386 bssid_p0[i] = rtw_read8(if_p0, bssid_offset + i);
2387
2388 hw_var_set_bssid(if_pn, bssid_p0);
2389 }
2390
2391 if (is_client_associated_to_ap(if_pn))
2392 hw_var_set_bssid(if_p0, bssid_pn);
2393
2394 /* 4. MAC addr */
2395 hw_var_set_macaddr(if_p0, adapter_mac_addr(if_pn));
2396 hw_var_set_macaddr(if_pn, adapter_mac_addr(if_p0));
2397
2398 /* 5. TSF */
2399 /*0x554[30:28] -BIT_BCN_TIMER_SEL_FWRD*/
2400
2401 /* Read port n TSF */
2402 val8 = rtw_read8(adapter, REG_MBSSID_BCN_SPACE_8822B + 3);
2403 val8 &= 0x8F;
2404 val8 |= if_pn->hw_port << 4;
2405 rtw_write8(adapter, REG_MBSSID_BCN_SPACE_8822B + 3, val8);
2406
2407 for (i = 0; i < 8; i++)
2408 tsftr_pn[i] = rtw_read8(adapter, REG_TSFTR_8822B + i);
2409
2410 /* Read port 0 TSF */
2411 val8 = rtw_read8(adapter, REG_MBSSID_BCN_SPACE_8822B + 3);
2412 val8 &= 0x8F;
2413 val8 |= if_p0->hw_port << 4;
2414 rtw_write8(adapter, REG_MBSSID_BCN_SPACE_8822B + 3, val8);
2415
2416 for (i = 0; i < 8; i++)
2417 tsftr_p0[i] = rtw_read8(adapter, REG_TSFTR_8822B + i);
2418
2419 /* write port n TSF to port 0 */
2420 val8 = rtw_read8(adapter, REG_MBSSID_BCN_SPACE_8822B + 3);
2421 val8 &= 0x8F;
2422 val8 |= if_p0->hw_port << 4; /* to port 0 */
2423 rtw_write8(adapter, REG_MBSSID_BCN_SPACE_8822B + 3, val8);
2424
2425 for (i = 0; i < 8; i++)
2426 rtw_write8(adapter, REG_TSFTR_8822B + i, tsftr_pn[i]);
2427
2428 /* write port 0 TSF to port n */
2429 val8 = rtw_read8(adapter, REG_MBSSID_BCN_SPACE_8822B + 3);
2430 val8 &= 0x8F;
2431 val8 |= if_pn->hw_port << 4; /* to port n */
2432 rtw_write8(adapter, REG_MBSSID_BCN_SPACE_8822B + 3, val8);
2433
2434 for (i = 0; i < 8; i++)
2435 rtw_write8(adapter, REG_TSFTR_8822B + i, tsftr_p0[i]);
2436
2437 /* 6 beacon interval */
2438 addr_pn = port_cfg[if_pn->hw_port].bcn_space;
2439 mask_pn = port_cfg[if_pn->hw_port].bcn_space_mask;
2440 shift_pn = port_cfg[if_pn->hw_port].bcn_space_shift;
2441 val32 = rtw_read32(adapter, addr_pn);
2442 bcn_intv_pn = (val32 >> shift_pn) & mask_pn;
2443
2444 addr_p0 = port_cfg[if_p0->hw_port].bcn_space;
2445 mask_p0 = port_cfg[if_p0->hw_port].bcn_space_mask;
2446 shift_p0 = port_cfg[if_p0->hw_port].bcn_space_shift;
2447 val32 = rtw_read32(adapter, addr_p0);
2448 bcn_intv_p0 = (val32 >> shift_p0) & mask_p0;
2449
2450 val32 |= (bcn_intv_pn & mask_p0) << shift_p0;
2451 rtw_write32(adapter, addr_p0, val32);
2452
2453 val32 |= (bcn_intv_p0 & mask_pn) << shift_pn;
2454 rtw_write32(adapter, addr_pn, val32);
2455
2456 /* 7. BCN ctrl */
2457 rtw_write8(adapter, port_cfg[if_p0->hw_port].bcn_ctl, vbcn_ctrl_pn);
2458 rtw_write8(adapter, port_cfg[if_pn->hw_port].bcn_ctl, vbcn_ctrl_p0);
2459
2460 /*reconfigure*/
2461 if_p0->hw_port = if_pn->hw_port;
2462 if_pn->hw_port = HW_PORT0;
2463 }
2464
rtl8822b_sethwreg(PADAPTER adapter,u8 variable,u8 * val)2465 void rtl8822b_sethwreg(PADAPTER adapter, u8 variable, u8 *val)
2466 {
2467 PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
2468 u8 val8;
2469 u16 val16;
2470 u32 val32;
2471
2472
2473 switch (variable) {
2474 /*
2475 case HW_VAR_MEDIA_STATUS:
2476 break;
2477 */
2478 case HW_VAR_SET_OPMODE:
2479 hw_var_set_opmode(adapter, *val);
2480 break;
2481
2482 case HW_VAR_MAC_ADDR:
2483 hw_var_set_macaddr(adapter, val);
2484 break;
2485
2486 case HW_VAR_BSSID:
2487 hw_var_set_bssid(adapter, val);
2488 break;
2489 /*
2490 case HW_VAR_INIT_RTS_RATE:
2491 break;
2492 */
2493 case HW_VAR_BASIC_RATE:
2494 hw_var_set_basic_rate(adapter, val);
2495 break;
2496
2497 case HW_VAR_TXPAUSE:
2498 rtw_write8(adapter, REG_TXPAUSE_8822B, *val);
2499 break;
2500
2501 case HW_VAR_BCN_FUNC:
2502 hw_var_set_bcn_func(adapter, *val);
2503 break;
2504
2505 case HW_VAR_CORRECT_TSF:
2506 hw_var_set_correct_tsf(adapter);
2507 break;
2508
2509 case HW_VAR_CHECK_BSSID:
2510 hw_var_set_check_bssid(adapter, *val);
2511 break;
2512
2513 case HW_VAR_MLME_DISCONNECT:
2514 hw_var_set_mlme_disconnect(adapter);
2515 break;
2516
2517 case HW_VAR_MLME_SITESURVEY:
2518 hw_var_set_mlme_sitesurvey(adapter, *val);
2519 #ifdef CONFIG_BT_COEXIST
2520 if (hal->EEPROMBluetoothCoexist)
2521 rtw_btcoex_ScanNotify(adapter, *val ? _TRUE : _FALSE);
2522 #endif
2523 break;
2524
2525 case HW_VAR_MLME_JOIN:
2526 hw_var_set_mlme_join(adapter, *val);
2527
2528 #ifdef CONFIG_BT_COEXIST
2529 if (hal->EEPROMBluetoothCoexist) {
2530 switch (*val) {
2531 case 0:
2532 /* Notify coex. mechanism before join */
2533 rtw_btcoex_ConnectNotify(adapter, _TRUE);
2534 break;
2535 case 1:
2536 case 2:
2537 /* Notify coex. mechanism after join, whether successful or failed */
2538 rtw_btcoex_ConnectNotify(adapter, _FALSE);
2539 break;
2540 }
2541 }
2542 #endif /* CONFIG_BT_COEXIST */
2543 break;
2544
2545 case HW_VAR_ON_RCR_AM:
2546 hw_var_set_rcr_am(adapter, 1);
2547 break;
2548
2549 case HW_VAR_OFF_RCR_AM:
2550 hw_var_set_rcr_am(adapter, 0);
2551 break;
2552
2553 case HW_VAR_BEACON_INTERVAL:
2554 hw_var_set_bcn_interval(adapter, *(u16 *)val);
2555 break;
2556
2557 case HW_VAR_SLOT_TIME:
2558 rtw_write8(adapter, REG_SLOT_8822B, *val);
2559 break;
2560
2561 case HW_VAR_RESP_SIFS:
2562 /* RESP_SIFS for CCK */
2563 rtw_write8(adapter, REG_RESP_SIFS_CCK_8822B, val[0]);
2564 rtw_write8(adapter, REG_RESP_SIFS_CCK_8822B + 1, val[1]);
2565 /* RESP_SIFS for OFDM */
2566 rtw_write8(adapter, REG_RESP_SIFS_OFDM_8822B, val[2]);
2567 rtw_write8(adapter, REG_RESP_SIFS_OFDM_8822B + 1, val[3]);
2568 break;
2569
2570 case HW_VAR_ACK_PREAMBLE:
2571 hw_var_set_ack_preamble(adapter, *val);
2572 break;
2573
2574 /*
2575 case HW_VAR_SEC_CFG:
2576 follow hal_com.c
2577 break;
2578 */
2579
2580 case HW_VAR_SEC_DK_CFG:
2581 if (val)
2582 hw_var_set_sec_dk_cfg(adapter, _TRUE);
2583 else
2584 hw_var_set_sec_dk_cfg(adapter, _FALSE);
2585 break;
2586
2587 case HW_VAR_BCN_VALID:
2588 hw_var_set_bcn_valid(adapter);
2589 break;
2590 /*
2591 case HW_VAR_RF_TYPE:
2592 break;
2593 */
2594 case HW_VAR_CAM_EMPTY_ENTRY:
2595 hw_var_set_cam_empty_entry(adapter, *val);
2596 break;
2597
2598 case HW_VAR_CAM_INVALID_ALL:
2599 val32 = BIT_SECCAM_POLLING_8822B | BIT_SECCAM_CLR_8822B;
2600 rtw_write32(adapter, REG_CAMCMD_8822B, val32);
2601 break;
2602
2603 case HW_VAR_AC_PARAM_VO:
2604 rtw_write32(adapter, REG_EDCA_VO_PARAM_8822B, *(u32 *)val);
2605 break;
2606
2607 case HW_VAR_AC_PARAM_VI:
2608 rtw_write32(adapter, REG_EDCA_VI_PARAM_8822B, *(u32 *)val);
2609 break;
2610
2611 case HW_VAR_AC_PARAM_BE:
2612 hal->AcParam_BE = *(u32 *)val;
2613 rtw_write32(adapter, REG_EDCA_BE_PARAM_8822B, *(u32 *)val);
2614 break;
2615
2616 case HW_VAR_AC_PARAM_BK:
2617 rtw_write32(adapter, REG_EDCA_BK_PARAM_8822B, *(u32 *)val);
2618 break;
2619
2620 case HW_VAR_ACM_CTRL:
2621 hw_var_set_acm_ctrl(adapter, *val);
2622 break;
2623 /*
2624 case HW_VAR_AMPDU_MIN_SPACE:
2625 break;
2626 */
2627 case HW_VAR_AMPDU_FACTOR: {
2628 u32 AMPDULen = *val; /* enum AGGRE_SIZE */
2629
2630 AMPDULen = (0x2000 << AMPDULen) - 1;
2631 rtw_write32(adapter, REG_AMPDU_MAX_LENGTH_8822B, AMPDULen);
2632 }
2633 break;
2634
2635 case HW_VAR_RXDMA_AGG_PG_TH:
2636 /*
2637 * TH=1 => invalidate RX DMA aggregation
2638 * TH=0 => validate RX DMA aggregation, use init value.
2639 */
2640 if (*val == 0)
2641 /* enable RXDMA aggregation */
2642 rx_agg_switch(adapter, _TRUE);
2643 else
2644 /* disable RXDMA aggregation */
2645 rx_agg_switch(adapter, _FALSE);
2646 break;
2647 /*
2648 case HW_VAR_SET_RPWM:
2649 case HW_VAR_CPWM:
2650 break;
2651 */
2652 case HW_VAR_H2C_FW_PWRMODE:
2653 rtl8822b_set_FwPwrMode_cmd(adapter, *val);
2654 break;
2655 /*
2656 case HW_VAR_H2C_PS_TUNE_PARAM:
2657 break;
2658 */
2659 case HW_VAR_H2C_FW_JOINBSSRPT:
2660 hw_var_set_h2c_fw_joinbssrpt(adapter, *val);
2661 break;
2662 /*
2663 case HW_VAR_FWLPS_RF_ON:
2664 break;
2665 */
2666 #ifdef CONFIG_P2P_PS
2667 case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
2668 rtl8822b_set_p2p_ps_offload_cmd(adapter, *val);
2669 break;
2670 #endif
2671 /*
2672 case HW_VAR_TRIGGER_GPIO_0:
2673 case HW_VAR_BT_SET_COEXIST:
2674 case HW_VAR_BT_ISSUE_DELBA:
2675 case HW_VAR_SWITCH_EPHY_WoWLAN:
2676 case HW_VAR_EFUSE_USAGE:
2677 case HW_VAR_EFUSE_BYTES:
2678 case HW_VAR_EFUSE_BT_USAGE:
2679 case HW_VAR_EFUSE_BT_BYTES:
2680 break;
2681 */
2682 case HW_VAR_FIFO_CLEARN_UP: {
2683 struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
2684 u8 trycnt = 100;
2685
2686 /* pause tx */
2687 rtw_write8(adapter, REG_TXPAUSE_8822B, 0xff);
2688
2689 /* keep sn */
2690 adapter->xmitpriv.nqos_ssn = rtw_read16(adapter, REG_HW_SEQ2_8822B);
2691
2692 if (pwrpriv->bkeepfwalive != _TRUE) {
2693 /* RX DMA stop */
2694 val32 = rtw_read32(adapter, REG_RXPKT_NUM_8822B);
2695 val32 |= BIT_RW_RELEASE_EN;
2696 rtw_write32(adapter, REG_RXPKT_NUM_8822B, val32);
2697 do {
2698 val32 = rtw_read32(adapter, REG_RXPKT_NUM_8822B);
2699 val32 &= BIT_RXDMA_IDLE_8822B;
2700 if (val32)
2701 break;
2702
2703 RTW_INFO("[HW_VAR_FIFO_CLEARN_UP] val=%x times:%d\n", val32, trycnt);
2704 } while (--trycnt);
2705 if (trycnt == 0)
2706 RTW_INFO("[HW_VAR_FIFO_CLEARN_UP] Stop RX DMA failed!\n");
2707 #if 0
2708 /* RQPN Load 0 */
2709 rtw_write16(adapter, REG_RQPN_NPQ, 0);
2710 rtw_write32(adapter, REG_RQPN, 0x80000000);
2711 rtw_mdelay_os(2);
2712 #endif
2713 }
2714 }
2715 break;
2716
2717 case HW_VAR_RESTORE_HW_SEQ:
2718 /* restore Sequence No. */
2719 rtw_write8(adapter, REG_HW_SEQ2_8822B, adapter->xmitpriv.nqos_ssn);
2720 break;
2721
2722 case HW_VAR_CHECK_TXBUF: {
2723 u16 rtylmtorg;
2724 u8 RetryLimit = 0x01;
2725 u32 start, passtime;
2726 u32 timelmt = 2000; /* ms */
2727 u32 waittime = 10; /* ms */
2728 u32 high, low, normal, extra, publc;
2729 u16 rsvd, available;
2730 u8 empty;
2731
2732
2733 rtylmtorg = rtw_read16(adapter, REG_RETRY_LIMIT_8822B);
2734
2735 val16 = BIT_LRL_8822B(RetryLimit) | BIT_SRL_8822B(RetryLimit);
2736 rtw_write16(adapter, REG_RETRY_LIMIT_8822B, val16);
2737
2738 /* Check TX FIFO empty or not */
2739 empty = _FALSE;
2740 high = 0;
2741 low = 0;
2742 normal = 0;
2743 extra = 0;
2744 publc = 0;
2745 start = rtw_get_current_time();
2746 while ((rtw_get_passing_time_ms(start) < timelmt)
2747 && !RTW_CANNOT_RUN(adapter)) {
2748 high = rtw_read32(adapter, REG_FIFOPAGE_INFO_1_8822B);
2749 low = rtw_read32(adapter, REG_FIFOPAGE_INFO_2_8822B);
2750 normal = rtw_read32(adapter, REG_FIFOPAGE_INFO_3_8822B);
2751 extra = rtw_read32(adapter, REG_FIFOPAGE_INFO_4_8822B);
2752 publc = rtw_read32(adapter, REG_FIFOPAGE_INFO_5_8822B);
2753
2754 rsvd = BIT_GET_HPQ_V1_8822B(high);
2755 available = BIT_GET_HPQ_AVAL_PG_V1_8822B(high);
2756 if (rsvd != available) {
2757 rtw_msleep_os(waittime);
2758 continue;
2759 }
2760
2761 rsvd = BIT_GET_LPQ_V1_8822B(low);
2762 available = BIT_GET_LPQ_AVAL_PG_V1_8822B(low);
2763 if (rsvd != available) {
2764 rtw_msleep_os(waittime);
2765 continue;
2766 }
2767
2768 rsvd = BIT_GET_NPQ_V1_8822B(normal);
2769 available = BIT_GET_NPQ_AVAL_PG_V1_8822B(normal);
2770 if (rsvd != available) {
2771 rtw_msleep_os(waittime);
2772 continue;
2773 }
2774
2775 rsvd = BIT_GET_EXQ_V1_8822B(extra);
2776 available = BIT_GET_EXQ_AVAL_PG_V1_8822B(extra);
2777 if (rsvd != available) {
2778 rtw_msleep_os(waittime);
2779 continue;
2780 }
2781
2782 rsvd = BIT_GET_PUBQ_V1_8822B(publc);
2783 available = BIT_GET_PUBQ_AVAL_PG_V1_8822B(publc);
2784 if (rsvd != available) {
2785 rtw_msleep_os(waittime);
2786 continue;
2787 }
2788
2789 empty = _TRUE;
2790 break;
2791 }
2792
2793 passtime = rtw_get_passing_time_ms(start);
2794 if (_TRUE == empty)
2795 RTW_INFO("[HW_VAR_CHECK_TXBUF] Empty in %d ms\n", passtime);
2796 else if (RTW_CANNOT_RUN(adapter))
2797 RTW_INFO("[HW_VAR_CHECK_TXBUF] bDriverStopped or bSurpriseRemoved\n");
2798 else {
2799 RTW_PRINT("[HW_VAR_CHECK_TXBUF] NOT empty in %d ms\n", passtime);
2800 RTW_PRINT("[HW_VAR_CHECK_TXBUF] 0x230=0x%08x 0x234=0x%08x 0x238=0x%08x 0x23c=0x%08x 0x240=0x%08x\n",
2801 high, low, normal, extra, publc);
2802 }
2803
2804 rtw_write16(adapter, REG_RETRY_LIMIT_8822B, rtylmtorg);
2805 }
2806 break;
2807 /*
2808 case HW_VAR_PCIE_STOP_TX_DMA:
2809 break;
2810 */
2811 case HW_VAR_APFM_ON_MAC:
2812 hal->bMacPwrCtrlOn = *val;
2813 RTW_INFO("[HW_VAR_APFM_ON_MAC] bMacPwrCtrlOn=%d\n", hal->bMacPwrCtrlOn);
2814 break;
2815 /*
2816 case HW_VAR_HCI_SUS_STATE:
2817 #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
2818 case HW_VAR_WOWLAN:
2819 case HW_VAR_WAKEUP_REASON:
2820 case HW_VAR_RPWM_TOG:
2821 #endif
2822 break;
2823 */
2824 #ifdef CONFIG_GPIO_WAKEUP
2825 case HW_SET_GPIO_WL_CTRL: {
2826 u8 enable = *val;
2827 u8 shift = 2;
2828 u32 addr;
2829 u8 bit_en;
2830
2831 addr = REG_LED_CFG_8822B + shift;
2832 bit_en = BIT_GPIO13_14_WL_CTRL_EN_8822B >> (shift * 8);
2833
2834 val8 = rtw_read8(adapter, addr);
2835
2836 if (enable == _TRUE) {
2837 if (val8 & bit_en) {
2838 val8 &= ~bit_en;
2839 rtw_write8(adapter, addr, val8);
2840 }
2841 } else {
2842 if (!(val8 & bit_en)) {
2843 val8 |= bit_en;
2844 rtw_write8(adapter, addr, val8);
2845 }
2846
2847 }
2848 RTW_INFO("[HW_SET_GPIO_WL_CTRL] 0x%02X=0x%02X\n",
2849 addr, rtw_read8(adapter, addr));
2850 }
2851 break;
2852 #endif
2853 /*
2854 case HW_VAR_SYS_CLKR:
2855 break;
2856 */
2857 case HW_VAR_NAV_UPPER: {
2858 #define HAL_NAV_UPPER_UNIT 128 /* micro-second */
2859 u32 usNavUpper = *(u32 *)val;
2860
2861 if (usNavUpper > HAL_NAV_UPPER_UNIT * 0xFF) {
2862 RTW_INFO(FUNC_ADPT_FMT ": [HW_VAR_NAV_UPPER] value(0x%08X us) is larger than (%d * 0xFF)!!!\n",
2863 FUNC_ADPT_ARG(adapter), usNavUpper, HAL_NAV_UPPER_UNIT);
2864 break;
2865 }
2866
2867 usNavUpper = (usNavUpper + HAL_NAV_UPPER_UNIT - 1) / HAL_NAV_UPPER_UNIT;
2868 rtw_write8(adapter, REG_NAV_CTRL_8822B + 2, (u8)usNavUpper);
2869 }
2870 break;
2871
2872 /*
2873 case HW_VAR_C2H_HANDLE:
2874 case HW_VAR_RPT_TIMER_SETTING:
2875 case HW_VAR_TX_RPT_MAX_MACID:
2876 case HW_VAR_CHK_HI_QUEUE_EMPTY:
2877 break;
2878 */
2879 case HW_VAR_DL_BCN_SEL:
2880 #ifdef CONFIG_CONCURRENT_MODE
2881 if (adapter->hw_port == HW_PORT1) {
2882 /* Port1 */
2883 /* ToDo */
2884 } else
2885 #endif /* CONFIG_CONCURRENT_MODE */
2886 {
2887 /* Port0 */
2888 /* ToDo */
2889 }
2890 break;
2891 /*
2892 case HW_VAR_AMPDU_MAX_TIME:
2893 case HW_VAR_WIRELESS_MODE:
2894 case HW_VAR_USB_MODE:
2895 */
2896 case HW_VAR_PORT_SWITCH:
2897 hw_var_port_switch_8822b(adapter);
2898 break;
2899
2900 case HW_VAR_DO_IQK:
2901 if (*val)
2902 hal->bNeedIQK = _TRUE;
2903 else
2904 hal->bNeedIQK = _FALSE;
2905 break;
2906
2907 case HW_VAR_DM_IN_LPS:
2908 rtl8822b_phy_haldm_in_lps(adapter);
2909 break;
2910 /*
2911 case HW_VAR_SET_REQ_FW_PS:
2912 case HW_VAR_FW_PS_STATE:
2913 break;
2914 */
2915 #ifdef CONFIG_BEAMFORMING
2916 case HW_VAR_SOUNDING_ENTER:
2917 rtl8822b_phy_sounding_enter(adapter, (struct sta_info*)val);
2918 break;
2919
2920 case HW_VAR_SOUNDING_LEAVE:
2921 rtl8822b_phy_sounding_leave(adapter, val);
2922 break;
2923 /*
2924 case HW_VAR_SOUNDING_RATE:
2925 case HW_VAR_SOUNDING_STATUS:
2926 case HW_VAR_SOUNDING_FW_NDPA:
2927 case HW_VAR_SOUNDING_CLK:
2928 break;
2929 */
2930 case HW_VAR_SOUNDING_SET_GID_TABLE:
2931 rtl8822b_phy_sounding_set_gid_table(adapter, (struct beamformer_entry*)val);
2932 break;
2933 #endif /* CONFIG_BEAMFORMING */
2934 /*
2935 case HW_VAR_HW_REG_TIMER_INIT:
2936 case HW_VAR_HW_REG_TIMER_RESTART:
2937 case HW_VAR_HW_REG_TIMER_START:
2938 case HW_VAR_HW_REG_TIMER_STOP:
2939 break;
2940 */
2941 case HW_VAR_DL_RSVD_PAGE:
2942 #ifdef CONFIG_BT_COEXIST
2943 if (check_fwstate(&adapter->mlmepriv, WIFI_AP_STATE) == _TRUE)
2944 rtl8822b_download_BTCoex_AP_mode_rsvd_page(adapter);
2945 #endif
2946 break;
2947 /*
2948 case HW_VAR_MACID_LINK:
2949 case HW_VAR_MACID_NOLINK:
2950 break;
2951 */
2952 case HW_VAR_MACID_SLEEP: {
2953 u32 reg_macid_sleep;
2954 u8 bit_shift;
2955 u8 id = *(u8 *)val;
2956
2957 if (id < 32) {
2958 reg_macid_sleep = REG_MACID_SLEEP_8822B;
2959 bit_shift = id;
2960 } else if (id < 64) {
2961 reg_macid_sleep = REG_MACID_SLEEP1_8822B;
2962 bit_shift = id - 32;
2963 } else if (id < 96) {
2964 reg_macid_sleep = REG_MACID_SLEEP2_8822B;
2965 bit_shift = id - 64;
2966 } else if (id < 128) {
2967 reg_macid_sleep = REG_MACID_SLEEP3_8822B;
2968 bit_shift = id - 96;
2969 } else {
2970 rtw_warn_on(1);
2971 break;
2972 }
2973
2974 val32 = rtw_read32(adapter, reg_macid_sleep);
2975 RTW_INFO(FUNC_ADPT_FMT ": [HW_VAR_MACID_SLEEP] macid=%d, org reg_0x%03x=0x%08X\n",
2976 FUNC_ADPT_ARG(adapter), id, reg_macid_sleep, val32);
2977
2978 if (val32 & BIT(bit_shift))
2979 break;
2980
2981 val32 |= BIT(bit_shift);
2982 rtw_write32(adapter, reg_macid_sleep, val32);
2983 }
2984 break;
2985
2986 case HW_VAR_MACID_WAKEUP: {
2987 u32 reg_macid_sleep;
2988 u8 bit_shift;
2989 u8 id = *(u8 *)val;
2990
2991 if (id < 32) {
2992 reg_macid_sleep = REG_MACID_SLEEP_8822B;
2993 bit_shift = id;
2994 } else if (id < 64) {
2995 reg_macid_sleep = REG_MACID_SLEEP1_8822B;
2996 bit_shift = id - 32;
2997 } else if (id < 96) {
2998 reg_macid_sleep = REG_MACID_SLEEP2_8822B;
2999 bit_shift = id - 64;
3000 } else if (id < 128) {
3001 reg_macid_sleep = REG_MACID_SLEEP3_8822B;
3002 bit_shift = id - 96;
3003 } else {
3004 rtw_warn_on(1);
3005 break;
3006 }
3007
3008 val32 = rtw_read32(adapter, reg_macid_sleep);
3009 RTW_INFO(FUNC_ADPT_FMT ": [HW_VAR_MACID_WAKEUP] macid=%d, org reg_0x%03x=0x%08X\n",
3010 FUNC_ADPT_ARG(adapter), id, reg_macid_sleep, val32);
3011
3012 if (!(val32 & BIT(bit_shift)))
3013 break;
3014
3015 val32 &= ~BIT(bit_shift);
3016 rtw_write32(adapter, reg_macid_sleep, val32);
3017 }
3018 break;
3019 /*
3020 case HW_VAR_DUMP_MAC_QUEUE_INFO:
3021 case HW_VAR_ASIX_IOT:
3022 #ifdef CONFIG_MBSSID_CAM
3023 case HW_VAR_MBSSID_CAM_WRITE:
3024 case HW_VAR_MBSSID_CAM_CLEAR:
3025 case HW_VAR_RCR_MBSSID_EN:
3026 #endif
3027 case HW_VAR_EN_HW_UPDATE_TSF:
3028 case HW_VAR_CH_SW_NEED_TO_TAKE_CARE_IQK_INFO:
3029 case HW_VAR_CH_SW_IQK_INFO_BACKUP:
3030 case HW_VAR_CH_SW_IQK_INFO_RESTORE:
3031 break;
3032 */
3033 #ifdef CONFIG_TDLS
3034 case HW_VAR_TDLS_WRCR:
3035 rtl8822b_rcr_clear(adapter, BIT_CBSSID_DATA_8822B);
3036 break;
3037
3038 case HW_VAR_TDLS_RS_RCR:
3039 rtl8822b_rcr_add(adapter, BIT_CBSSID_DATA_8822B);
3040 break;
3041 /*
3042 #ifdef CONFIG_TDLS_CH_SW
3043 case HW_VAR_TDLS_BCN_EARLY_C2H_RPT:
3044 break;
3045 #endif
3046 */
3047 #endif
3048
3049 default:
3050 SetHwReg(adapter, variable, val);
3051 break;
3052 }
3053 }
3054
3055 struct qinfo {
3056 u32 head:8;
3057 u32 pkt_num:7;
3058 u32 tail:8;
3059 u32 ac:2;
3060 u32 macid:7;
3061 };
3062
3063 struct bcn_qinfo {
3064 u16 head:8;
3065 u16 pkt_num:8;
3066 };
3067
dump_qinfo(void * sel,struct qinfo * info,const char * tag)3068 static void dump_qinfo(void *sel, struct qinfo *info, const char *tag)
3069 {
3070 RTW_PRINT_SEL(sel, "%shead:0x%02x, tail:0x%02x, pkt_num:%u, macid:%u, ac:%u\n",
3071 tag ? tag : "", info->head, info->tail, info->pkt_num, info->macid, info->ac);
3072 }
3073
dump_bcn_qinfo(void * sel,struct bcn_qinfo * info,const char * tag)3074 static void dump_bcn_qinfo(void *sel, struct bcn_qinfo *info, const char *tag)
3075 {
3076 RTW_PRINT_SEL(sel, "%shead:0x%02x, pkt_num:%u\n",
3077 tag ? tag : "", info->head, info->pkt_num);
3078 }
3079
dump_mac_qinfo(void * sel,_adapter * adapter)3080 static void dump_mac_qinfo(void *sel, _adapter *adapter)
3081 {
3082 u32 q0_info;
3083 u32 q1_info;
3084 u32 q2_info;
3085 u32 q3_info;
3086 u32 q4_info;
3087 u32 q5_info;
3088 u32 q6_info;
3089 u32 q7_info;
3090 u32 mg_q_info;
3091 u32 hi_q_info;
3092 u16 bcn_q_info;
3093
3094 q0_info = rtw_read32(adapter, REG_Q0_INFO_8822B);
3095 q1_info = rtw_read32(adapter, REG_Q1_INFO_8822B);
3096 q2_info = rtw_read32(adapter, REG_Q2_INFO_8822B);
3097 q3_info = rtw_read32(adapter, REG_Q3_INFO_8822B);
3098 q4_info = rtw_read32(adapter, REG_Q4_INFO_8822B);
3099 q5_info = rtw_read32(adapter, REG_Q5_INFO_8822B);
3100 q6_info = rtw_read32(adapter, REG_Q6_INFO_8822B);
3101 q7_info = rtw_read32(adapter, REG_Q7_INFO_8822B);
3102 mg_q_info = rtw_read32(adapter, REG_MGQ_INFO_8822B);
3103 hi_q_info = rtw_read32(adapter, REG_HIQ_INFO_8822B);
3104 bcn_q_info = rtw_read16(adapter, REG_BCNQ_INFO_8822B);
3105
3106 dump_qinfo(sel, (struct qinfo *)&q0_info, "Q0 ");
3107 dump_qinfo(sel, (struct qinfo *)&q1_info, "Q1 ");
3108 dump_qinfo(sel, (struct qinfo *)&q2_info, "Q2 ");
3109 dump_qinfo(sel, (struct qinfo *)&q3_info, "Q3 ");
3110 dump_qinfo(sel, (struct qinfo *)&q4_info, "Q4 ");
3111 dump_qinfo(sel, (struct qinfo *)&q5_info, "Q5 ");
3112 dump_qinfo(sel, (struct qinfo *)&q6_info, "Q6 ");
3113 dump_qinfo(sel, (struct qinfo *)&q7_info, "Q7 ");
3114 dump_qinfo(sel, (struct qinfo *)&mg_q_info, "MG ");
3115 dump_qinfo(sel, (struct qinfo *)&hi_q_info, "HI ");
3116 dump_bcn_qinfo(sel, (struct bcn_qinfo *)&bcn_q_info, "BCN ");
3117 }
3118
hw_var_get_bcn_valid(PADAPTER adapter)3119 static u8 hw_var_get_bcn_valid(PADAPTER adapter)
3120 {
3121 u8 val8 = 0;
3122 u8 ret = _FALSE;
3123
3124 /* only port 0 can TX BCN */
3125 val8 = rtw_read8(adapter, REG_FIFOPAGE_CTRL_2_8822B + 1);
3126 ret = (BIT(7) & val8) ? _TRUE : _FALSE;
3127
3128 return ret;
3129 }
3130
rtl8822b_gethwreg(PADAPTER adapter,u8 variable,u8 * val)3131 void rtl8822b_gethwreg(PADAPTER adapter, u8 variable, u8 *val)
3132 {
3133 PHAL_DATA_TYPE hal;
3134 u8 val8;
3135 u16 val16;
3136 u32 val32;
3137
3138
3139 hal = GET_HAL_DATA(adapter);
3140
3141 switch (variable) {
3142 /*
3143 case HW_VAR_MEDIA_STATUS:
3144 case HW_VAR_SET_OPMODE:
3145 case HW_VAR_MAC_ADDR:
3146 case HW_VAR_BSSID:
3147 case HW_VAR_INIT_RTS_RATE:
3148 case HW_VAR_BASIC_RATE:
3149 break;
3150 */
3151 case HW_VAR_TXPAUSE:
3152 *val = rtw_read8(adapter, REG_TXPAUSE_8822B);
3153 break;
3154 /*
3155 case HW_VAR_BCN_FUNC:
3156 case HW_VAR_CORRECT_TSF:
3157 case HW_VAR_CHECK_BSSID:
3158 case HW_VAR_MLME_DISCONNECT:
3159 case HW_VAR_MLME_SITESURVEY:
3160 case HW_VAR_MLME_JOIN:
3161 case HW_VAR_ON_RCR_AM:
3162 case HW_VAR_OFF_RCR_AM:
3163 case HW_VAR_BEACON_INTERVAL:
3164 case HW_VAR_SLOT_TIME:
3165 case HW_VAR_RESP_SIFS:
3166 case HW_VAR_ACK_PREAMBLE:
3167 case HW_VAR_SEC_CFG:
3168 case HW_VAR_SEC_DK_CFG:
3169 break;
3170 */
3171 case HW_VAR_BCN_VALID:
3172 *val = hw_var_get_bcn_valid(adapter);
3173 break;
3174 /*
3175 case HW_VAR_RF_TYPE:
3176 case HW_VAR_CAM_EMPTY_ENTRY:
3177 case HW_VAR_CAM_INVALID_ALL:
3178 case HW_VAR_AC_PARAM_VO:
3179 case HW_VAR_AC_PARAM_VI:
3180 case HW_VAR_AC_PARAM_BE:
3181 case HW_VAR_AC_PARAM_BK:
3182 case HW_VAR_ACM_CTRL:
3183 case HW_VAR_AMPDU_MIN_SPACE:
3184 case HW_VAR_AMPDU_FACTOR:
3185 case HW_VAR_RXDMA_AGG_PG_TH:
3186 case HW_VAR_SET_RPWM:
3187 case HW_VAR_CPWM:
3188 case HW_VAR_H2C_FW_PWRMODE:
3189 case HW_VAR_H2C_PS_TUNE_PARAM:
3190 case HW_VAR_H2C_FW_JOINBSSRPT:
3191 break;
3192 */
3193 case HW_VAR_FWLPS_RF_ON:
3194 /* When we halt NIC, we should check if FW LPS is leave. */
3195 if (rtw_is_surprise_removed(adapter) ||
3196 (adapter_to_pwrctl(adapter)->rf_pwrstate == rf_off)) {
3197 /*
3198 * If it is in HW/SW Radio OFF or IPS state,
3199 * we do not check Fw LPS Leave,
3200 * because Fw is unload.
3201 */
3202 *val = _TRUE;
3203 } else {
3204 rtl8822b_rcr_get(adapter, &val32);
3205 val32 &= (BIT_UC_MD_EN_8822B | BIT_BC_MD_EN_8822B | BIT_TIM_PARSER_EN_8822B);
3206 if (val32)
3207 *val = _FALSE;
3208 else
3209 *val = _TRUE;
3210 }
3211 break;
3212 /*
3213 case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
3214 case HW_VAR_TRIGGER_GPIO_0:
3215 case HW_VAR_BT_SET_COEXIST:
3216 case HW_VAR_BT_ISSUE_DELBA:
3217 case HW_VAR_SWITCH_EPHY_WoWLAN:
3218 case HW_VAR_EFUSE_USAGE:
3219 case HW_VAR_EFUSE_BYTES:
3220 case HW_VAR_EFUSE_BT_USAGE:
3221 case HW_VAR_EFUSE_BT_BYTES:
3222 case HW_VAR_FIFO_CLEARN_UP:
3223 case HW_VAR_RESTORE_HW_SEQ:
3224 case HW_VAR_CHECK_TXBUF:
3225 case HW_VAR_PCIE_STOP_TX_DMA:
3226 break;
3227 */
3228 case HW_VAR_APFM_ON_MAC:
3229 *val = hal->bMacPwrCtrlOn;
3230 break;
3231 /*
3232 case HW_VAR_HCI_SUS_STATE:
3233 break;
3234 */
3235 #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
3236 /*
3237 case HW_VAR_WOWLAN:
3238 break;
3239 */
3240 case HW_VAR_WAKEUP_REASON:
3241 rtw_halmac_get_wow_reason(adapter_to_dvobj(adapter), val);
3242 break;
3243 /*
3244 case HW_VAR_RPWM_TOG:
3245 break;
3246 */
3247 #endif
3248 /*
3249 #ifdef CONFIG_GPIO_WAKEUP
3250 case HW_SET_GPIO_WL_CTRL:
3251 break;
3252 #endif
3253 */
3254 case HW_VAR_SYS_CLKR:
3255 *val = rtw_read8(adapter, REG_SYS_CLK_CTRL_8822B);
3256 break;
3257 /*
3258 case HW_VAR_NAV_UPPER:
3259 case HW_VAR_C2H_HANDLE:
3260 case HW_VAR_RPT_TIMER_SETTING:
3261 case HW_VAR_TX_RPT_MAX_MACID:
3262 break;
3263 */
3264 case HW_VAR_CHK_HI_QUEUE_EMPTY:
3265 val16 = rtw_read16(adapter, REG_TXPKT_EMPTY_8822B);
3266 *val = (val16 & BIT_HQQ_EMPTY_8822B) ? _TRUE : _FALSE;
3267 break;
3268 /*
3269 case HW_VAR_DL_BCN_SEL:
3270 case HW_VAR_AMPDU_MAX_TIME:
3271 case HW_VAR_WIRELESS_MODE:
3272 case HW_VAR_USB_MODE:
3273 case HW_VAR_PORT_SWITCH:
3274 case HW_VAR_DO_IQK:
3275 case HW_VAR_DM_IN_LPS:
3276 case HW_VAR_SET_REQ_FW_PS:
3277 case HW_VAR_FW_PS_STATE:
3278 case HW_VAR_SOUNDING_ENTER:
3279 case HW_VAR_SOUNDING_LEAVE:
3280 case HW_VAR_SOUNDING_RATE:
3281 case HW_VAR_SOUNDING_STATUS:
3282 case HW_VAR_SOUNDING_FW_NDPA:
3283 case HW_VAR_SOUNDING_CLK:
3284 case HW_VAR_HW_REG_TIMER_INIT:
3285 case HW_VAR_HW_REG_TIMER_RESTART:
3286 case HW_VAR_HW_REG_TIMER_START:
3287 case HW_VAR_HW_REG_TIMER_STOP:
3288 case HW_VAR_DL_RSVD_PAGE:
3289 case HW_VAR_MACID_LINK:
3290 case HW_VAR_MACID_NOLINK:
3291 case HW_VAR_MACID_SLEEP:
3292 case HW_VAR_MACID_WAKEUP:
3293 break;
3294 */
3295 case HW_VAR_DUMP_MAC_QUEUE_INFO:
3296 dump_mac_qinfo(val, adapter);
3297 break;
3298 /*
3299 case HW_VAR_ASIX_IOT:
3300 #ifdef CONFIG_MBSSID_CAM
3301 case HW_VAR_MBSSID_CAM_WRITE:
3302 case HW_VAR_MBSSID_CAM_CLEAR:
3303 case HW_VAR_RCR_MBSSID_EN:
3304 #endif
3305 case HW_VAR_EN_HW_UPDATE_TSF:
3306 case HW_VAR_CH_SW_NEED_TO_TAKE_CARE_IQK_INFO:
3307 case HW_VAR_CH_SW_IQK_INFO_BACKUP:
3308 case HW_VAR_CH_SW_IQK_INFO_RESTORE:
3309 #ifdef CONFIG_TDLS
3310 case HW_VAR_TDLS_WRCR:
3311 case HW_VAR_TDLS_RS_RCR:
3312 #ifdef CONFIG_TDLS_CH_SW
3313 case HW_VAR_TDLS_BCN_EARLY_C2H_RPT:
3314 #endif
3315 #endif
3316 break;
3317 */
3318 default:
3319 GetHwReg(adapter, variable, val);
3320 break;
3321 }
3322 }
3323
rtl8822b_sethwregwithbuf(PADAPTER adapter,u8 variable,u8 * pbuf,int len)3324 void rtl8822b_sethwregwithbuf(PADAPTER adapter, u8 variable, u8 *pbuf, int len)
3325 {
3326 PHAL_DATA_TYPE hal;
3327
3328
3329 hal = GET_HAL_DATA(adapter);
3330
3331 switch (variable) {
3332 case HW_VAR_C2H_HANDLE:
3333 rtl8822b_c2h_handler(adapter, pbuf, len);
3334 break;
3335
3336 default:
3337 break;
3338 }
3339 }
3340
3341 /*
3342 * Description:
3343 * Change default setting of specified variable.
3344 */
rtl8822b_sethaldefvar(PADAPTER adapter,HAL_DEF_VARIABLE variable,void * pval)3345 u8 rtl8822b_sethaldefvar(PADAPTER adapter, HAL_DEF_VARIABLE variable, void *pval)
3346 {
3347 PHAL_DATA_TYPE hal;
3348 u8 bResult;
3349
3350
3351 hal = GET_HAL_DATA(adapter);
3352 bResult = _SUCCESS;
3353
3354 switch (variable) {
3355 /*
3356 case HAL_DEF_UNDERCORATEDSMOOTHEDPWDB:
3357 case HAL_DEF_IS_SUPPORT_ANT_DIV:
3358 case HAL_DEF_DRVINFO_SZ:
3359 case HAL_DEF_MAX_RECVBUF_SZ:
3360 case HAL_DEF_RX_PACKET_OFFSET:
3361 case HAL_DEF_RX_DMA_SZ_WOW:
3362 case HAL_DEF_RX_DMA_SZ:
3363 case HAL_DEF_RX_PAGE_SIZE:
3364 case HAL_DEF_DBG_DUMP_RXPKT:
3365 case HAL_DEF_RA_DECISION_RATE:
3366 case HAL_DEF_RA_SGI:
3367 case HAL_DEF_PT_PWR_STATUS:
3368 case HAL_DEF_TX_LDPC:
3369 case HAL_DEF_RX_LDPC:
3370 case HAL_DEF_TX_STBC:
3371 case HAL_DEF_RX_STBC:
3372 case HAL_DEF_EXPLICIT_BEAMFORMER:
3373 case HAL_DEF_EXPLICIT_BEAMFORMEE:
3374 case HAL_DEF_VHT_MU_BEAMFORMER:
3375 case HAL_DEF_VHT_MU_BEAMFORMEE:
3376 case HAL_DEF_BEAMFORMER_CAP:
3377 case HAL_DEF_BEAMFORMEE_CAP:
3378 case HW_VAR_MAX_RX_AMPDU_FACTOR:
3379 case HW_DEF_RA_INFO_DUMP:
3380 case HAL_DEF_DBG_DUMP_TXPKT:
3381 case HAL_DEF_TX_PAGE_SIZE:
3382 case HAL_DEF_TX_PAGE_BOUNDARY:
3383 case HAL_DEF_TX_PAGE_BOUNDARY_WOWLAN:
3384 case HAL_DEF_ANT_DETECT:
3385 case HAL_DEF_PCI_SUUPORT_L1_BACKDOOR:
3386 case HAL_DEF_PCI_AMD_L1_SUPPORT:
3387 case HAL_DEF_PCI_ASPM_OSC:
3388 case HAL_DEF_MACID_SLEEP:
3389 case HAL_DEF_DBG_DIS_PWT:
3390 case HAL_DEF_EFUSE_USAGE:
3391 case HAL_DEF_EFUSE_BYTES:
3392 case HW_VAR_BEST_AMPDU_DENSITY:
3393 break;
3394 */
3395 default:
3396 bResult = SetHalDefVar(adapter, variable, pval);
3397 break;
3398 }
3399
3400 return bResult;
3401 }
3402
3403 /*
3404 * Description:
3405 * Query setting of specified variable.
3406 */
rtl8822b_gethaldefvar(PADAPTER adapter,HAL_DEF_VARIABLE variable,void * pval)3407 u8 rtl8822b_gethaldefvar(PADAPTER adapter, HAL_DEF_VARIABLE variable, void *pval)
3408 {
3409 PHAL_DATA_TYPE hal;
3410 struct dvobj_priv *d;
3411 u8 bResult;
3412 u8 val8;
3413
3414
3415 d = adapter_to_dvobj(adapter);
3416 hal = GET_HAL_DATA(adapter);
3417 bResult = _SUCCESS;
3418
3419 switch (variable) {
3420 /*
3421 case HAL_DEF_UNDERCORATEDSMOOTHEDPWDB:
3422 break;
3423 */
3424 case HAL_DEF_IS_SUPPORT_ANT_DIV:
3425 #ifdef CONFIG_ANTENNA_DIVERSITY
3426 *(u8 *)pval = _TRUE;
3427 #else
3428 *(u8 *)pval = _FALSE;
3429 #endif
3430 break;
3431
3432 case HAL_DEF_MAX_RECVBUF_SZ:
3433 *((u32 *)pval) = HALMAC_RX_FIFO_SIZE_8822B;
3434 break;
3435
3436 case HAL_DEF_RX_PACKET_OFFSET:
3437 rtw_halmac_get_drv_info_sz(d, &val8);
3438 *((u32 *)pval) = HALMAC_RX_DESC_SIZE_8822B + val8;
3439 break;
3440 /*
3441 case HAL_DEF_DRVINFO_SZ:
3442 case HAL_DEF_RX_DMA_SZ_WOW:
3443 case HAL_DEF_RX_DMA_SZ:
3444 case HAL_DEF_RX_PAGE_SIZE:
3445 case HAL_DEF_DBG_DUMP_RXPKT:
3446 case HAL_DEF_RA_DECISION_RATE:
3447 case HAL_DEF_RA_SGI:
3448 break;
3449 */
3450 /* only for 8188E */
3451 case HAL_DEF_PT_PWR_STATUS:
3452 break;
3453
3454 case HAL_DEF_TX_LDPC:
3455 case HAL_DEF_RX_LDPC:
3456 *(u8 *)pval = _TRUE;
3457 break;
3458
3459 /* support 1T STBC under 2TX */
3460 case HAL_DEF_TX_STBC:
3461 if (hal->rf_type == RF_1T2R || hal->rf_type == RF_1T1R)
3462 *(u8 *)pval = 0;
3463 else
3464 *(u8 *)pval = 1;
3465 break;
3466
3467 /* support 1RX for STBC */
3468 case HAL_DEF_RX_STBC:
3469 *(u8 *)pval = 1;
3470 break;
3471
3472 /* support Explicit TxBF for HT/VHT */
3473 case HAL_DEF_EXPLICIT_BEAMFORMER:
3474 case HAL_DEF_EXPLICIT_BEAMFORMEE:
3475 case HAL_DEF_VHT_MU_BEAMFORMER:
3476 case HAL_DEF_VHT_MU_BEAMFORMEE:
3477 *(u8 *)pval = _TRUE;
3478 break;
3479
3480 case HAL_DEF_BEAMFORMER_CAP:
3481 val8 = 0;
3482 rtw_hal_get_hwreg(adapter, HW_VAR_RF_TYPE, &val8);
3483 switch (val8) {
3484 case RF_1T1R:
3485 case RF_1T2R:
3486 *(u8 *)pval = 0;
3487 break;
3488 default:
3489 case RF_2T2R:
3490 *(u8 *)pval = 1;
3491 break;
3492 }
3493 break;
3494
3495 case HAL_DEF_BEAMFORMEE_CAP:
3496 *(u8 *)pval = 3;
3497 break;
3498
3499 case HW_VAR_MAX_RX_AMPDU_FACTOR:
3500 /* 8822B RX FIFO is 24KB */
3501 *(HT_CAP_AMPDU_FACTOR *)pval = MAX_AMPDU_FACTOR_16K;
3502 break;
3503
3504 case HW_DEF_RA_INFO_DUMP: {
3505 #if 0
3506 u8 mac_id = *(u8 *)pval;
3507 u32 cmd;
3508 u32 ra_info1, ra_info2;
3509 u32 rate_mask1, rate_mask2;
3510 u8 curr_tx_rate, curr_tx_sgi, hight_rate, lowest_rate;
3511
3512 RTW_INFO("============ RA status check Mac_id:%d ===================\n", mac_id);
3513
3514 cmd = 0x40000100 | mac_id;
3515 rtw_write32(adapter, REG_HMEBOX_DBG_2_8723B, cmd);
3516 rtw_msleep_os(10);
3517 ra_info1 = rtw_read32(adapter, 0x2F0);
3518 curr_tx_rate = ra_info1 & 0x7F;
3519 curr_tx_sgi = (ra_info1 >> 7) & 0x01;
3520 RTW_INFO("[ ra_info1:0x%08x ] =>cur_tx_rate=%s, cur_sgi:%d, PWRSTS=0x%02x\n",
3521 ra_info1,
3522 HDATA_RATE(curr_tx_rate),
3523 curr_tx_sgi,
3524 (ra_info1 >> 8) & 0x07);
3525
3526 cmd = 0x40000400 | mac_id;
3527 rtw_write32(adapter, REG_HMEBOX_DBG_2_8723B, cmd);
3528 rtw_msleep_os(10);
3529 ra_info1 = rtw_read32(adapter, 0x2F0);
3530 ra_info2 = rtw_read32(adapter, 0x2F4);
3531 rate_mask1 = rtw_read32(adapter, 0x2F8);
3532 rate_mask2 = rtw_read32(adapter, 0x2FC);
3533 hight_rate = ra_info2 & 0xFF;
3534 lowest_rate = (ra_info2 >> 8) & 0xFF;
3535
3536 RTW_INFO("[ ra_info1:0x%08x ] =>RSSI=%d, BW_setting=0x%02x, DISRA=0x%02x, VHT_EN=0x%02x\n",
3537 ra_info1,
3538 ra_info1 & 0xFF,
3539 (ra_info1 >> 8) & 0xFF,
3540 (ra_info1 >> 16) & 0xFF,
3541 (ra_info1 >> 24) & 0xFF);
3542
3543 RTW_INFO("[ ra_info2:0x%08x ] =>hight_rate=%s, lowest_rate=%s, SGI=0x%02x, RateID=%d\n",
3544 ra_info2,
3545 HDATA_RATE(hight_rate),
3546 HDATA_RATE(lowest_rate),
3547 (ra_info2 >> 16) & 0xFF,
3548 (ra_info2 >> 24) & 0xFF);
3549
3550 RTW_INFO("rate_mask2=0x%08x, rate_mask1=0x%08x\n", rate_mask2, rate_mask1);
3551 #endif
3552 }
3553 break;
3554 /*
3555 case HAL_DEF_DBG_DUMP_TXPKT:
3556 break;
3557 */
3558 case HAL_DEF_TX_PAGE_SIZE:
3559 *(u32 *)pval = HALMAC_TX_PAGE_SIZE_8822B;
3560 break;
3561 /*
3562 case HAL_DEF_TX_PAGE_BOUNDARY:
3563 case HAL_DEF_TX_PAGE_BOUNDARY_WOWLAN:
3564 case HAL_DEF_ANT_DETECT:
3565 case HAL_DEF_PCI_SUUPORT_L1_BACKDOOR:
3566 case HAL_DEF_PCI_AMD_L1_SUPPORT:
3567 case HAL_DEF_PCI_ASPM_OSC:
3568 break;
3569 */
3570 case HAL_DEF_MACID_SLEEP:
3571 *(u8 *)pval = _TRUE; /* support macid sleep */
3572 break;
3573 /*
3574 case HAL_DEF_DBG_DIS_PWT:
3575 case HAL_DEF_EFUSE_USAGE:
3576 case HAL_DEF_EFUSE_BYTES:
3577 break;
3578 */
3579 case HW_VAR_BEST_AMPDU_DENSITY:
3580 *((u32 *)pval) = AMPDU_DENSITY_VALUE_4;
3581 break;
3582
3583 default:
3584 bResult = GetHalDefVar(adapter, variable, pval);
3585 break;
3586 }
3587
3588 return bResult;
3589 }
3590
3591 #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
3592 /*
3593 * Description: Prepare some information to Fw for WoWLAN.
3594 * (1) Download wowlan Fw.
3595 * (2) Download RSVD page packets.
3596 * (3) Enable AP offload if needed.
3597 */
SetFwRelatedForWoWLAN(PADAPTER adapter,u8 bHostIsGoingtoSleep)3598 static void SetFwRelatedForWoWLAN(PADAPTER adapter, u8 bHostIsGoingtoSleep)
3599 {
3600 u8 status = _FAIL;
3601 PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
3602 u8 bRecover = _FALSE;
3603
3604 /*
3605 * 1. Before WoWLAN we need to re-download WoWLAN Fw.
3606 */
3607 status = rtl8723b_FirmwareDownload(adapter, bHostIsGoingtoSleep);
3608 if (status != _SUCCESS) {
3609 RTW_INFO("%s: Re-Download Firmware failed!!\n", __FUNCTION__);
3610 return;
3611 }
3612 RTW_INFO("%s: Re-Download Firmware Success !!\n", , __FUNCTION__);
3613
3614 /*
3615 * 2. Re-Init the variables about Fw related setting.
3616 */
3617 rtl8723b_InitializeFirmwareVars(adapter);
3618 }
3619 #endif /* CONFIG_WOWLAN || CONFIG_AP_WOWLAN */
3620
rtl8822b_fill_txdesc_sectype(struct pkt_attrib * pattrib,u8 * ptxdesc)3621 void rtl8822b_fill_txdesc_sectype(struct pkt_attrib *pattrib, u8 *ptxdesc)
3622 {
3623 if ((pattrib->encrypt > 0) && !pattrib->bswenc) {
3624 /* SEC_TYPE : 0:NO_ENC,1:WEP40/TKIP,2:WAPI,3:AES */
3625 switch (pattrib->encrypt) {
3626 case _WEP40_:
3627 case _WEP104_:
3628 case _TKIP_:
3629 case _TKIP_WTMIC_:
3630 SET_TX_DESC_SEC_TYPE_8822B(ptxdesc, 0x1);
3631 break;
3632 #ifdef CONFIG_WAPI_SUPPORT
3633 case _SMS4_:
3634 SET_TX_DESC_SEC_TYPE_8822B(ptxdesc, 0x2);
3635 break;
3636 #endif
3637 case _AES_:
3638 SET_TX_DESC_SEC_TYPE_8822B(ptxdesc, 0x3);
3639 break;
3640 case _NO_PRIVACY_:
3641 default:
3642 SET_TX_DESC_SEC_TYPE_8822B(ptxdesc, 0x0);
3643 break;
3644 }
3645 }
3646 }
3647
rtl8822b_fill_txdesc_vcs(PADAPTER adapter,struct pkt_attrib * pattrib,u8 * ptxdesc)3648 void rtl8822b_fill_txdesc_vcs(PADAPTER adapter, struct pkt_attrib *pattrib, u8 *ptxdesc)
3649 {
3650 struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
3651 struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
3652
3653
3654 if (pattrib->vcs_mode) {
3655 switch (pattrib->vcs_mode) {
3656 case RTS_CTS:
3657 SET_TX_DESC_RTSEN_8822B(ptxdesc, 1);
3658 break;
3659 case CTS_TO_SELF:
3660 SET_TX_DESC_CTS2SELF_8822B(ptxdesc, 1);
3661 break;
3662 case NONE_VCS:
3663 default:
3664 break;
3665 }
3666
3667 if (pmlmeinfo->preamble_mode == PREAMBLE_SHORT)
3668 SET_TX_DESC_RTS_SHORT_8822B(ptxdesc, 1);
3669
3670 /* RTS Rate=24M */
3671 SET_TX_DESC_RTSRATE_8822B(ptxdesc, 0x8);
3672
3673 /* compatibility for MCC consideration, use pmlmeext->cur_channel */
3674 if (pmlmeext->cur_channel > 14)
3675 /* RTS retry to rate OFDM 6M for 5G */
3676 SET_TX_DESC_RTS_RTY_LOWEST_RATE_8822B(ptxdesc, 4);
3677 else
3678 /* RTS retry to rate CCK 1M for 2.4G */
3679 SET_TX_DESC_RTS_RTY_LOWEST_RATE_8822B(ptxdesc, 0);
3680 }
3681 }
3682
rtl8822b_bw_mapping(PADAPTER adapter,struct pkt_attrib * pattrib)3683 u8 rtl8822b_bw_mapping(PADAPTER adapter, struct pkt_attrib *pattrib)
3684 {
3685 u8 BWSettingOfDesc = 0;
3686 PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
3687
3688
3689 if (hal->CurrentChannelBW == CHANNEL_WIDTH_80) {
3690 if (pattrib->bwmode == CHANNEL_WIDTH_80)
3691 BWSettingOfDesc = 2;
3692 else if (pattrib->bwmode == CHANNEL_WIDTH_40)
3693 BWSettingOfDesc = 1;
3694 else
3695 BWSettingOfDesc = 0;
3696 } else if (hal->CurrentChannelBW == CHANNEL_WIDTH_40) {
3697 if ((pattrib->bwmode == CHANNEL_WIDTH_40) || (pattrib->bwmode == CHANNEL_WIDTH_80))
3698 BWSettingOfDesc = 1;
3699 else
3700 BWSettingOfDesc = 0;
3701 } else
3702 BWSettingOfDesc = 0;
3703
3704 return BWSettingOfDesc;
3705 }
3706
rtl8822b_sc_mapping(PADAPTER adapter,struct pkt_attrib * pattrib)3707 u8 rtl8822b_sc_mapping(PADAPTER adapter, struct pkt_attrib *pattrib)
3708 {
3709 u8 SCSettingOfDesc = 0;
3710 PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
3711
3712
3713 if (hal->CurrentChannelBW == CHANNEL_WIDTH_80) {
3714 if (pattrib->bwmode == CHANNEL_WIDTH_80)
3715 SCSettingOfDesc = VHT_DATA_SC_DONOT_CARE;
3716 else if (pattrib->bwmode == CHANNEL_WIDTH_40) {
3717 if (hal->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)
3718 SCSettingOfDesc = VHT_DATA_SC_40_LOWER_OF_80MHZ;
3719 else if (hal->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)
3720 SCSettingOfDesc = VHT_DATA_SC_40_UPPER_OF_80MHZ;
3721 else
3722 RTW_INFO("SCMapping: DONOT CARE Mode Setting\n");
3723 } else {
3724 if ((hal->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) && (hal->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER))
3725 SCSettingOfDesc = VHT_DATA_SC_20_LOWEST_OF_80MHZ;
3726 else if ((hal->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) && (hal->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER))
3727 SCSettingOfDesc = VHT_DATA_SC_20_LOWER_OF_80MHZ;
3728 else if ((hal->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) && (hal->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER))
3729 SCSettingOfDesc = VHT_DATA_SC_20_UPPER_OF_80MHZ;
3730 else if ((hal->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) && (hal->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER))
3731 SCSettingOfDesc = VHT_DATA_SC_20_UPPERST_OF_80MHZ;
3732 else
3733 RTW_INFO("SCMapping: DONOT CARE Mode Setting\n");
3734 }
3735 } else if (hal->CurrentChannelBW == CHANNEL_WIDTH_40) {
3736 if (pattrib->bwmode == CHANNEL_WIDTH_40)
3737 SCSettingOfDesc = VHT_DATA_SC_DONOT_CARE;
3738 else if (pattrib->bwmode == CHANNEL_WIDTH_20) {
3739 if (hal->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)
3740 SCSettingOfDesc = VHT_DATA_SC_20_UPPER_OF_80MHZ;
3741 else if (hal->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)
3742 SCSettingOfDesc = VHT_DATA_SC_20_LOWER_OF_80MHZ;
3743 else
3744 SCSettingOfDesc = VHT_DATA_SC_DONOT_CARE;
3745 }
3746 } else
3747 SCSettingOfDesc = VHT_DATA_SC_DONOT_CARE;
3748
3749 return SCSettingOfDesc;
3750 }
3751
rtl8822b_fill_txdesc_phy(PADAPTER adapter,struct pkt_attrib * pattrib,u8 * ptxdesc)3752 void rtl8822b_fill_txdesc_phy(PADAPTER adapter, struct pkt_attrib *pattrib, u8 *ptxdesc)
3753 {
3754 if (pattrib->ht_en) {
3755 /* Set Bandwidth and sub-channel settings. */
3756 SET_TX_DESC_DATA_BW_8822B(ptxdesc, rtl8822b_bw_mapping(adapter, pattrib));
3757 SET_TX_DESC_DATA_SC_8822B(ptxdesc, rtl8822b_sc_mapping(adapter, pattrib));
3758 }
3759 }
3760
3761 #ifdef CONFIG_CONCURRENT_MODE
rtl8822b_fill_txdesc_force_bmc_camid(struct pkt_attrib * pattrib,u8 * ptxdesc)3762 void rtl8822b_fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc)
3763 {
3764 if ((pattrib->encrypt > 0) && (!pattrib->bswenc)
3765 && (pattrib->bmc_camid != INVALID_SEC_MAC_CAM_ID)) {
3766 SET_TX_DESC_EN_DESC_ID_8822B(ptxdesc, 1);
3767 SET_TX_DESC_MACID_8822B(ptxdesc, pattrib->bmc_camid);
3768 }
3769 }
3770 #endif
3771
rtl8822b_cal_txdesc_chksum(PADAPTER adapter,u8 * ptxdesc)3772 void rtl8822b_cal_txdesc_chksum(PADAPTER adapter, u8 *ptxdesc)
3773 {
3774 PHALMAC_ADAPTER halmac;
3775 PHALMAC_API api;
3776
3777
3778 halmac = adapter_to_halmac(adapter);
3779 api = HALMAC_GET_API(halmac);
3780
3781 api->halmac_fill_txdesc_checksum(halmac, ptxdesc);
3782 }
3783
3784
3785 #ifdef CONFIG_MP_INCLUDED
rtl8822b_prepare_mp_txdesc(PADAPTER adapter,struct mp_priv * pmp_priv)3786 void rtl8822b_prepare_mp_txdesc(PADAPTER adapter, struct mp_priv *pmp_priv)
3787 {
3788 u8 *desc;
3789 struct pkt_attrib *attrib;
3790 u32 pkt_size;
3791 s32 bmcast;
3792 u8 data_rate, pwr_status, offset;
3793
3794
3795 desc = pmp_priv->tx.desc;
3796 attrib = &pmp_priv->tx.attrib;
3797 pkt_size = attrib->last_txcmdsz;
3798 bmcast = IS_MCAST(attrib->ra);
3799
3800 SET_TX_DESC_LS_8822B(desc, 1);
3801 SET_TX_DESC_TXPKTSIZE_8822B(desc, pkt_size);
3802
3803 offset = HALMAC_TX_DESC_SIZE_8822B;
3804 SET_TX_DESC_OFFSET_8822B(desc, offset);
3805 #if defined(CONFIG_PCI_HCI)
3806 SET_TX_DESC_PKT_OFFSET_8822B(desc, 0); /* 8822BE pkt_offset is 0 */
3807 #else
3808 SET_TX_DESC_PKT_OFFSET_8822B(desc, 1);
3809 #endif
3810
3811 if (bmcast)
3812 SET_TX_DESC_BMC_8822B(desc, 1);
3813
3814 SET_TX_DESC_MACID_8822B(desc, attrib->mac_id);
3815 SET_TX_DESC_RATE_ID_8822B(desc, attrib->raid);
3816 SET_TX_DESC_QSEL_8822B(desc, attrib->qsel);
3817
3818 if (pmp_priv->preamble)
3819 SET_TX_DESC_DATA_SHORT_8822B(desc, 1);
3820
3821 if (!attrib->qos_en)
3822 SET_TX_DESC_EN_HWSEQ_8822B(desc, 1);
3823 else
3824 SET_TX_DESC_SW_SEQ_8822B(desc, attrib->seqnum);
3825
3826 if (pmp_priv->bandwidth <= CHANNEL_WIDTH_160)
3827 SET_TX_DESC_DATA_BW_8822B(desc, pmp_priv->bandwidth);
3828 else {
3829 RTW_INFO("%s: <ERROR> unknown bandwidth %d, use 20M\n",
3830 __FUNCTION__, pmp_priv->bandwidth);
3831 SET_TX_DESC_DATA_BW_8822B(desc, CHANNEL_WIDTH_20);
3832 }
3833
3834 SET_TX_DESC_DISDATAFB_8822B(desc, 1);
3835 SET_TX_DESC_USE_RATE_8822B(desc, 1);
3836 SET_TX_DESC_DATARATE_8822B(desc, pmp_priv->rateidx);
3837 }
3838 #endif /* CONFIG_MP_INCLUDED */
3839
fill_default_txdesc(struct xmit_frame * pxmitframe,u8 * pbuf)3840 static void fill_default_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf)
3841 {
3842 PADAPTER adapter;
3843 PHAL_DATA_TYPE hal;
3844 struct mlme_ext_priv *pmlmeext;
3845 struct mlme_ext_info *pmlmeinfo;
3846 struct pkt_attrib *pattrib;
3847 s32 bmcst;
3848
3849
3850 _rtw_memset(pbuf, 0, HALMAC_TX_DESC_SIZE_8822B);
3851
3852 adapter = pxmitframe->padapter;
3853 hal = GET_HAL_DATA(adapter);
3854 pmlmeext = &adapter->mlmeextpriv;
3855 pmlmeinfo = &(pmlmeext->mlmext_info);
3856
3857 pattrib = &pxmitframe->attrib;
3858 bmcst = IS_MCAST(pattrib->ra);
3859
3860 if (pxmitframe->frame_tag == DATA_FRAMETAG) {
3861 u8 drv_userate = 0;
3862
3863 SET_TX_DESC_MACID_8822B(pbuf, pattrib->mac_id);
3864 SET_TX_DESC_RATE_ID_8822B(pbuf, pattrib->raid);
3865 SET_TX_DESC_QSEL_8822B(pbuf, pattrib->qsel);
3866 SET_TX_DESC_SW_SEQ_8822B(pbuf, pattrib->seqnum);
3867
3868 rtl8822b_fill_txdesc_sectype(pattrib, pbuf);
3869 rtl8822b_fill_txdesc_vcs(adapter, pattrib, pbuf);
3870
3871 #ifdef CONFIG_CONCURRENT_MODE
3872 if (bmcst)
3873 rtl8822b_fill_txdesc_force_bmc_camid(pattrib, pbuf);
3874 #endif
3875
3876 #ifdef CONFIG_P2P
3877 if (!rtw_p2p_chk_state(&adapter->wdinfo, P2P_STATE_NONE)) {
3878 if (pattrib->icmp_pkt == 1 && adapter->registrypriv.wifi_spec == 1)
3879 drv_userate = 1;
3880 }
3881 #endif
3882
3883 if ((pattrib->ether_type != 0x888e) &&
3884 (pattrib->ether_type != 0x0806) &&
3885 (pattrib->ether_type != 0x88B4) &&
3886 (pattrib->dhcp_pkt != 1) &&
3887 (drv_userate != 1)
3888 #ifdef CONFIG_AUTO_AP_MODE
3889 && (pattrib->pctrl != _TRUE)
3890 #endif
3891 ) {
3892 /* Non EAP & ARP & DHCP type data packet */
3893
3894 if (pattrib->ampdu_en == _TRUE) {
3895 SET_TX_DESC_AGG_EN_8822B(pbuf, 1);
3896 SET_TX_DESC_MAX_AGG_NUM_8822B(pbuf, 0x1F);
3897 SET_TX_DESC_AMPDU_DENSITY_8822B(pbuf, pattrib->ampdu_spacing);
3898 } else
3899 SET_TX_DESC_BK_8822B(pbuf, 1);
3900
3901 rtl8822b_fill_txdesc_phy(adapter, pattrib, pbuf);
3902
3903 /* compatibility for MCC consideration, use pmlmeext->cur_channel */
3904 if (pmlmeext->cur_channel > 14)
3905 /* for 5G, OFDM 6M */
3906 SET_TX_DESC_DATA_RTY_LOWEST_RATE_8822B(pbuf, 4);
3907 else
3908 /* for 2.4G, CCK 1M */
3909 SET_TX_DESC_DATA_RTY_LOWEST_RATE_8822B(pbuf, 0);
3910
3911 if (hal->fw_ractrl == _FALSE) {
3912 SET_TX_DESC_USE_RATE_8822B(pbuf, 1);
3913
3914 if (hal->INIDATA_RATE[pattrib->mac_id] & BIT(7))
3915 SET_TX_DESC_DATA_SHORT_8822B(pbuf, 1);
3916
3917 SET_TX_DESC_DATARATE_8822B(pbuf, hal->INIDATA_RATE[pattrib->mac_id] & 0x7F);
3918 }
3919
3920 /* modify data rate by iwpriv */
3921 if (adapter->fix_rate != 0xFF) {
3922 SET_TX_DESC_USE_RATE_8822B(pbuf, 1);
3923 if (adapter->fix_rate & BIT(7))
3924 SET_TX_DESC_DATA_SHORT_8822B(pbuf, 1);
3925 SET_TX_DESC_DATARATE_8822B(pbuf, adapter->fix_rate & 0x7F);
3926 if (!adapter->data_fb)
3927 SET_TX_DESC_DISDATAFB_8822B(pbuf, 1);
3928 }
3929
3930 if (pattrib->ldpc)
3931 SET_TX_DESC_DATA_LDPC_8822B(pbuf, 1);
3932 if (pattrib->stbc)
3933 SET_TX_DESC_DATA_STBC_8822B(pbuf, 1);
3934
3935 #ifdef CONFIG_CMCC_TEST
3936 SET_TX_DESC_DATA_SHORT_8822B(pbuf, 1); /* use cck short premble */
3937 #endif
3938 } else {
3939 /*
3940 * EAP data packet and ARP packet.
3941 * Use the 1M data rate to send the EAP/ARP packet.
3942 * This will maybe make the handshake smooth.
3943 */
3944
3945 SET_TX_DESC_BK_8822B(pbuf, 1);
3946 SET_TX_DESC_USE_RATE_8822B(pbuf, 1);
3947 if (pmlmeinfo->preamble_mode == PREAMBLE_SHORT)
3948 SET_TX_DESC_DATA_SHORT_8822B(pbuf, 1);
3949 SET_TX_DESC_DATARATE_8822B(pbuf, MRateToHwRate(pmlmeext->tx_rate));
3950
3951 RTW_INFO(FUNC_ADPT_FMT ": SP Packet(0x%04X) rate=0x%x\n",
3952 FUNC_ADPT_ARG(adapter), pattrib->ether_type, MRateToHwRate(pmlmeext->tx_rate));
3953 }
3954
3955 #if defined(CONFIG_USB_TX_AGGREGATION) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
3956 SET_TX_DESC_DMA_TXAGG_NUM_8822B(pbuf, pxmitframe->agg_num);
3957 #endif
3958
3959 #ifdef CONFIG_TDLS
3960 #ifdef CONFIG_XMIT_ACK
3961 /* CCX-TXRPT ack for xmit mgmt frames. */
3962 if (pxmitframe->ack_report) {
3963 #ifdef DBG_CCX
3964 RTW_INFO("%s set spe_rpt\n", __func__);
3965 #endif
3966 SET_TX_DESC_SPE_RPT_8822B(pbuf, 1);
3967 SET_TX_DESC_SW_DEFINE_8822B(pbuf, (u8)(GET_PRIMARY_ADAPTER(adapter)->xmitpriv.seq_no));
3968 }
3969 #endif /* CONFIG_XMIT_ACK */
3970 #endif
3971 } else if (pxmitframe->frame_tag == MGNT_FRAMETAG) {
3972 SET_TX_DESC_MACID_8822B(pbuf, pattrib->mac_id);
3973 SET_TX_DESC_QSEL_8822B(pbuf, pattrib->qsel);
3974 SET_TX_DESC_RATE_ID_8822B(pbuf, pattrib->raid);
3975 SET_TX_DESC_SW_SEQ_8822B(pbuf, pattrib->seqnum);
3976 SET_TX_DESC_USE_RATE_8822B(pbuf, 1);
3977
3978 SET_TX_DESC_MBSSID_8822B(pbuf, pattrib->mbssid & 0xF);
3979
3980 #ifdef CONFIG_INTEL_PROXIM
3981 if ((adapter->proximity.proxim_on == _TRUE)
3982 && (pattrib->intel_proxim == _TRUE)) {
3983 RTW_INFO("%s: pattrib->rate=%d\n", __FUNCTION__, pattrib->rate);
3984 SET_TX_DESC_DATARATE_8822B(pbuf, pattrib->rate);
3985 } else
3986 #endif
3987 {
3988 SET_TX_DESC_DATARATE_8822B(pbuf, MRateToHwRate(pmlmeext->tx_rate));
3989 }
3990
3991 #ifdef CONFIG_XMIT_ACK
3992 /* CCX-TXRPT ack for xmit mgmt frames. */
3993 if (pxmitframe->ack_report) {
3994 #ifdef DBG_CCX
3995 RTW_INFO("%s set spe_rpt\n", __FUNCTION__);
3996 #endif
3997 SET_TX_DESC_SPE_RPT_8822B(pbuf, 1);
3998 SET_TX_DESC_SW_DEFINE_8822B(pbuf, (u8)(GET_PRIMARY_ADAPTER(adapter)->xmitpriv.seq_no));
3999 }
4000 #endif /* CONFIG_XMIT_ACK */
4001 } else if (pxmitframe->frame_tag == TXAGG_FRAMETAG)
4002 RTW_INFO("%s: TXAGG_FRAMETAG\n", __FUNCTION__);
4003 #ifdef CONFIG_MP_INCLUDED
4004 else if (pxmitframe->frame_tag == MP_FRAMETAG) {
4005 RTW_INFO("%s: MP_FRAMETAG\n", __FUNCTION__);
4006 fill_txdesc_for_mp(adapter, pbuf);
4007 }
4008 #endif
4009 else {
4010 RTW_INFO("%s: frame_tag=0x%x\n", __FUNCTION__, pxmitframe->frame_tag);
4011
4012 SET_TX_DESC_MACID_8822B(pbuf, pattrib->mac_id);
4013 SET_TX_DESC_RATE_ID_8822B(pbuf, pattrib->raid);
4014 SET_TX_DESC_QSEL_8822B(pbuf, pattrib->qsel);
4015 SET_TX_DESC_SW_SEQ_8822B(pbuf, pattrib->seqnum);
4016 SET_TX_DESC_USE_RATE_8822B(pbuf, 1);
4017 SET_TX_DESC_DATARATE_8822B(pbuf, MRateToHwRate(pmlmeext->tx_rate));
4018 }
4019
4020 SET_TX_DESC_TXPKTSIZE_8822B(pbuf, pattrib->last_txcmdsz);
4021
4022 {
4023 u8 pkt_offset, offset;
4024
4025 pkt_offset = 0;
4026 offset = HALMAC_TX_DESC_SIZE_8822B;
4027 #ifdef CONFIG_USB_HCI
4028 pkt_offset = pxmitframe->pkt_offset;
4029 offset += (pxmitframe->pkt_offset >> 3);
4030 #endif /* CONFIG_USB_HCI */
4031
4032 #ifdef CONFIG_TX_EARLY_MODE
4033 if (pxmitframe->frame_tag == DATA_FRAMETAG) {
4034 pkt_offset = 1;
4035 offset += EARLY_MODE_INFO_SIZE;
4036 }
4037 #endif /* CONFIG_TX_EARLY_MODE */
4038
4039 SET_TX_DESC_PKT_OFFSET_8822B(pbuf, pkt_offset);
4040 SET_TX_DESC_OFFSET_8822B(pbuf, offset);
4041 }
4042
4043 if (bmcst)
4044 SET_TX_DESC_BMC_8822B(pbuf, 1);
4045
4046 /*
4047 * 2009.11.05. tynli_test. Suggested by SD4 Filen for FW LPS.
4048 * (1) The sequence number of each non-Qos frame / broadcast / multicast /
4049 * mgnt frame should be controlled by Hw because Fw will also send null data
4050 * which we cannot control when Fw LPS enable.
4051 * --> default enable non-Qos data sequense number. 2010.06.23. by tynli.
4052 * (2) Enable HW SEQ control for beacon packet, because we use Hw beacon.
4053 * (3) Use HW Qos SEQ to control the seq num of Ext port non-Qos packets.
4054 * 2010.06.23. Added by tynli.
4055 */
4056 if (!pattrib->qos_en)
4057 SET_TX_DESC_EN_HWSEQ_8822B(pbuf, 1);
4058
4059 #ifdef CONFIG_BEAMFORMING
4060 SET_TX_DESC_G_ID_8822B(pbuf, pattrib->txbf_g_id);
4061 SET_TX_DESC_P_AID_8822B(pbuf, pattrib->txbf_p_aid);
4062 #endif /* CONFIG_BEAMFORMING */
4063 }
4064
4065 /*
4066 * Description:
4067 *
4068 * Parameters:
4069 * pxmitframe xmitframe
4070 * pbuf where to fill tx desc
4071 */
rtl8822b_update_txdesc(struct xmit_frame * pxmitframe,u8 * pbuf)4072 void rtl8822b_update_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf)
4073 {
4074 fill_default_txdesc(pxmitframe, pbuf);
4075
4076 #ifdef CONFIG_ANTENNA_DIVERSITY
4077 ODM_SetTxAntByTxInfo(&GET_HAL_DATA(pxmitframe->adapter)->odmpriv, pbuf, pxmitframe->attrib.mac_id);
4078 #endif /* CONFIG_ANTENNA_DIVERSITY */
4079
4080 rtl8822b_cal_txdesc_chksum(pxmitframe->padapter, pbuf);
4081 }
4082
4083 /*
4084 * Description:
4085 * In normal chip, we should send some packet to HW which will be used by FW
4086 * in FW LPS mode.
4087 * The function is to fill the Tx descriptor of this packets,
4088 * then FW can tell HW to send these packet directly.
4089 */
fill_fake_txdesc(PADAPTER adapter,u8 * pDesc,u32 BufferLen,u8 IsPsPoll,u8 IsBTQosNull,u8 bDataFrame)4090 static void fill_fake_txdesc(PADAPTER adapter, u8 *pDesc, u32 BufferLen,
4091 u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame)
4092 {
4093 /* Clear all status */
4094 _rtw_memset(pDesc, 0, HALMAC_TX_DESC_SIZE_8822B);
4095
4096 SET_TX_DESC_LS_8822B(pDesc, 1);
4097
4098 SET_TX_DESC_OFFSET_8822B(pDesc, HALMAC_TX_DESC_SIZE_8822B);
4099
4100 SET_TX_DESC_TXPKTSIZE_8822B(pDesc, BufferLen);
4101 SET_TX_DESC_QSEL_8822B(pDesc, QSLT_MGNT); /* Fixed queue of Mgnt queue */
4102
4103 /* Set NAVUSEHDR to prevent Ps-poll AId filed to be changed to error vlaue by HW */
4104 if (_TRUE == IsPsPoll)
4105 SET_TX_DESC_NAVUSEHDR_8822B(pDesc, 1);
4106 else {
4107 SET_TX_DESC_EN_HWSEQ_8822B(pDesc, 1);
4108 SET_TX_DESC_HW_SSN_SEL_8822B(pDesc, 0);
4109 }
4110
4111 if (_TRUE == IsBTQosNull)
4112 SET_TX_DESC_BT_NULL_8822B(pDesc, 1);
4113
4114 SET_TX_DESC_USE_RATE_8822B(pDesc, 1);
4115 SET_TX_DESC_DATARATE_8822B(pDesc, DESC_RATE1M);
4116
4117 /*
4118 * Encrypt the data frame if under security mode excepct null data.
4119 */
4120 if (_TRUE == bDataFrame) {
4121 u32 EncAlg;
4122
4123 EncAlg = adapter->securitypriv.dot11PrivacyAlgrthm;
4124 switch (EncAlg) {
4125 case _NO_PRIVACY_:
4126 SET_TX_DESC_SEC_TYPE_8822B(pDesc, 0x0);
4127 break;
4128 case _WEP40_:
4129 case _WEP104_:
4130 case _TKIP_:
4131 SET_TX_DESC_SEC_TYPE_8822B(pDesc, 0x1);
4132 break;
4133 case _SMS4_:
4134 SET_TX_DESC_SEC_TYPE_8822B(pDesc, 0x2);
4135 break;
4136 case _AES_:
4137 SET_TX_DESC_SEC_TYPE_8822B(pDesc, 0x3);
4138 break;
4139 default:
4140 SET_TX_DESC_SEC_TYPE_8822B(pDesc, 0x0);
4141 break;
4142 }
4143 }
4144
4145 #if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
4146 /*
4147 * USB interface drop packet if the checksum of descriptor isn't correct.
4148 * Using this checksum can let hardware recovery from packet bulk out error (e.g. Cancel URC, Bulk out error.).
4149 */
4150 rtl8822b_cal_txdesc_chksum(adapter, pDesc);
4151 #endif
4152 }
4153
rtl8822b_dbg_dump_tx_desc(PADAPTER adapter,int frame_tag,u8 * ptxdesc)4154 void rtl8822b_dbg_dump_tx_desc(PADAPTER adapter, int frame_tag, u8 *ptxdesc)
4155 {
4156 u8 bDumpTxPkt;
4157 u8 bDumpTxDesc = _FALSE;
4158
4159
4160 rtw_hal_get_def_var(adapter, HAL_DEF_DBG_DUMP_TXPKT, &bDumpTxPkt);
4161
4162 /* 1 for data frame, 2 for mgnt frame */
4163 if (bDumpTxPkt == 1) {
4164 RTW_INFO("dump tx_desc for data frame\n");
4165 if ((frame_tag & 0x0f) == DATA_FRAMETAG)
4166 bDumpTxDesc = _TRUE;
4167 } else if (bDumpTxPkt == 2) {
4168 RTW_INFO("dump tx_desc for mgnt frame\n");
4169 if ((frame_tag & 0x0f) == MGNT_FRAMETAG)
4170 bDumpTxDesc = _TRUE;
4171 }
4172
4173 /* 8822B TX SIZE = 48(HALMAC_TX_DESC_SIZE_8822B) */
4174 if (_TRUE == bDumpTxDesc) {
4175 RTW_INFO("=====================================\n");
4176 RTW_INFO("Offset00(0x%08x)\n", *((u32 *)(ptxdesc)));
4177 RTW_INFO("Offset04(0x%08x)\n", *((u32 *)(ptxdesc + 4)));
4178 RTW_INFO("Offset08(0x%08x)\n", *((u32 *)(ptxdesc + 8)));
4179 RTW_INFO("Offset12(0x%08x)\n", *((u32 *)(ptxdesc + 12)));
4180 RTW_INFO("Offset16(0x%08x)\n", *((u32 *)(ptxdesc + 16)));
4181 RTW_INFO("Offset20(0x%08x)\n", *((u32 *)(ptxdesc + 20)));
4182 RTW_INFO("Offset24(0x%08x)\n", *((u32 *)(ptxdesc + 24)));
4183 RTW_INFO("Offset28(0x%08x)\n", *((u32 *)(ptxdesc + 28)));
4184 RTW_INFO("Offset32(0x%08x)\n", *((u32 *)(ptxdesc + 32)));
4185 RTW_INFO("Offset36(0x%08x)\n", *((u32 *)(ptxdesc + 36)));
4186 RTW_INFO("Offset40(0x%08x)\n", *((u32 *)(ptxdesc + 40)));
4187 RTW_INFO("Offset44(0x%08x)\n", *((u32 *)(ptxdesc + 44)));
4188 RTW_INFO("=====================================\n");
4189 }
4190 }
4191
rtl8822b_rxdesc2attribute(struct rx_pkt_attrib * a,u8 * desc)4192 void rtl8822b_rxdesc2attribute(struct rx_pkt_attrib *a, u8 *desc)
4193 {
4194 _rtw_memset(a, 0, sizeof(struct rx_pkt_attrib));
4195
4196 a->pkt_len = (u16)GET_RX_DESC_PKT_LEN_8822B(desc);
4197 a->pkt_rpt_type = GET_RX_DESC_C2H_8822B(desc) ? C2H_PACKET : NORMAL_RX;
4198
4199 if (a->pkt_rpt_type == NORMAL_RX) {
4200 a->crc_err = (u8)GET_RX_DESC_CRC32_8822B(desc);
4201 a->icv_err = (u8)GET_RX_DESC_ICV_ERR_8822B(desc);
4202 a->drvinfo_sz = (u8)GET_RX_DESC_DRV_INFO_SIZE_8822B(desc) << 3;
4203 a->encrypt = (u8)GET_RX_DESC_SECURITY_8822B(desc);
4204 a->qos = (u8)GET_RX_DESC_QOS_8822B(desc);
4205 a->shift_sz = (u8)GET_RX_DESC_SHIFT_8822B(desc);
4206 a->physt = (u8)GET_RX_DESC_PHYST_8822B(desc);
4207 a->bdecrypted = (u8)GET_RX_DESC_SWDEC_8822B(desc) ? 0 : 1;
4208
4209 a->priority = (u8)GET_RX_DESC_TID_8822B(desc);
4210 a->amsdu = (u8)GET_RX_DESC_AMSDU_8822B(desc);
4211 a->mdata = (u8)GET_RX_DESC_MD_8822B(desc);
4212 a->mfrag = (u8)GET_RX_DESC_MF_8822B(desc);
4213
4214 a->seq_num = (u16)GET_RX_DESC_SEQ_8822B(desc);
4215 a->frag_num = (u8)GET_RX_DESC_FRAG_8822B(desc);
4216
4217 a->data_rate = (u8)GET_RX_DESC_RX_RATE_8822B(desc);
4218 }
4219 }
4220
rtl8822b_query_rx_desc(union recv_frame * precvframe,u8 * pdesc)4221 void rtl8822b_query_rx_desc(union recv_frame *precvframe, u8 *pdesc)
4222 {
4223 rtl8822b_rxdesc2attribute(&precvframe->u.hdr.attrib, pdesc);
4224 }
4225
rtl8822b_set_hal_ops(PADAPTER adapter)4226 void rtl8822b_set_hal_ops(PADAPTER adapter)
4227 {
4228 struct hal_com_data *hal;
4229 struct hal_ops *ops;
4230
4231
4232 ops = &adapter->HalFunc;
4233 hal = GET_HAL_DATA(adapter);
4234
4235 /*
4236 * Initialize hal_com_data variables
4237 */
4238 hal->tx_pa_bias_a = 0xFF;
4239 hal->tx_pa_bias_b = 0xFF;
4240
4241 /*
4242 * Initialize operation callback functions
4243 */
4244 /*** initialize section ***/
4245 ops->read_chip_version = read_chip_version;
4246 /*
4247 ops->init_default_value = NULL;
4248 ops->intf_chip_configure = NULL;
4249 */
4250 ops->read_adapter_info = rtl8822b_read_efuse;
4251 ops->hal_power_on = rtl8822b_power_on;
4252 ops->hal_power_off = rtl8822b_power_off;
4253 ops->hal_init = rtl8822b_init;
4254 ops->hal_deinit = rtl8822b_deinit;
4255 ops->dm_init = rtl8822b_phy_init_dm_priv;
4256 ops->dm_deinit = rtl8822b_phy_deinit_dm_priv;
4257
4258 /*** xmit section ***/
4259 /*
4260 ops->init_xmit_priv = NULL;
4261 ops->free_xmit_priv = NULL;
4262 ops->hal_xmit = NULL;
4263 ops->mgnt_xmit = NULL;
4264 ops->hal_xmitframe_enqueue = NULL;
4265 #ifdef CONFIG_XMIT_THREAD_MODE
4266 ops->xmit_thread_handler = NULL;
4267 #endif
4268 */
4269 ops->run_thread = rtl8822b_run_thread;
4270 ops->cancel_thread = rtl8822b_cancel_thread;
4271
4272 /*** recv section ***/
4273 /*
4274 ops->init_recv_priv = NULL;
4275 ops->free_recv_priv = NULL;
4276 #if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI)
4277 ops->inirp_init = NULL;
4278 ops->inirp_deinit = NULL;
4279 #endif
4280 */
4281 /*** interrupt hdl section ***/
4282 /*
4283 ops->enable_interrupt = NULL;
4284 ops->disable_interrupt = NULL;
4285 */
4286 ops->check_ips_status = check_ips_status;
4287 /*
4288 #if defined(CONFIG_PCI_HCI)
4289 ops->interrupt_handler = NULL;
4290 #endif
4291 #if defined(CONFIG_USB_HCI) && defined(CONFIG_SUPPORT_USB_INT)
4292 ops->interrupt_handler = NULL;
4293 #endif
4294 #if defined(CONFIG_PCI_HCI)
4295 ops->irp_reset = NULL;
4296 #endif
4297 */
4298
4299 /*** DM section ***/
4300 /*
4301 ops->InitSwLeds = NULL;
4302 ops->DeInitSwLeds = NULL;
4303 */
4304 ops->set_bwmode_handler = rtl8822b_set_bw_mode;
4305 ops->set_channel_handler = rtl8822b_set_channel;
4306 ops->set_chnl_bw_handler = rtl8822b_set_channel_bw;
4307
4308 ops->set_tx_power_level_handler = rtl8822b_set_tx_power_level;
4309 ops->get_tx_power_level_handler = rtl8822b_get_tx_power_level;
4310
4311 ops->set_tx_power_index_handler = rtl8822b_set_tx_power_index;
4312 ops->get_tx_power_index_handler = rtl8822b_get_tx_power_index;
4313
4314 ops->hal_dm_watchdog = rtl8822b_phy_haldm_watchdog;
4315 #ifdef CONFIG_LPS_LCLK_WD_TIMER
4316 ops->hal_dm_watchdog_in_lps = rtl8822b_phy_haldm_watchdog_in_lps;
4317 #endif
4318
4319 ops->SetHwRegHandler = rtl8822b_sethwreg;
4320 ops->GetHwRegHandler = rtl8822b_gethwreg;
4321 ops->SetHwRegHandlerWithBuf = rtl8822b_sethwregwithbuf;
4322 ops->GetHalDefVarHandler = rtl8822b_gethaldefvar;
4323 ops->SetHalDefVarHandler = rtl8822b_sethaldefvar;
4324
4325 ops->GetHalODMVarHandler = GetHalODMVar;
4326 ops->SetHalODMVarHandler = SetHalODMVar;
4327
4328 ops->UpdateRAMaskHandler = update_ra_mask;
4329 ops->SetBeaconRelatedRegistersHandler = set_beacon_related_registers;
4330
4331 ops->Add_RateATid = add_rateatid;
4332 /*
4333 ops->interface_ps_func = NULL;
4334 */
4335 ops->read_bbreg = rtl8822b_read_bb_reg;
4336 ops->write_bbreg = rtl8822b_write_bb_reg;
4337 ops->read_rfreg = rtl8822b_read_rf_reg;
4338 ops->write_rfreg = rtl8822b_write_rf_reg;
4339
4340 #ifdef CONFIG_HOSTAPD_MLME
4341 /*
4342 ops->hostap_mgnt_xmit_entry = NULL;
4343 */
4344 #endif
4345 /*
4346 ops->EfusePowerSwitch = NULL;
4347 ops->BTEfusePowerSwitch = NULL;
4348 ops->ReadEFuse = NULL;
4349 ops->EFUSEGetEfuseDefinition = NULL;
4350 ops->EfuseGetCurrentSize = NULL;
4351 ops->Efuse_PgPacketRead = NULL;
4352 ops->Efuse_PgPacketWrite = NULL;
4353 ops->Efuse_WordEnableDataWrite = NULL;
4354 ops->Efuse_PgPacketWrite_BT = NULL;
4355 */
4356 #ifdef DBG_CONFIG_ERROR_DETECT
4357 ops->sreset_init_value = sreset_init_value;
4358 ops->sreset_reset_value = sreset_reset_value;
4359 ops->silentreset = sreset_reset;
4360 ops->sreset_xmit_status_check = xmit_status_check;
4361 ops->sreset_linked_status_check = linked_status_check;
4362 ops->sreset_get_wifi_status = sreset_get_wifi_status;
4363 ops->sreset_inprogress = sreset_inprogress;
4364 #endif /* DBG_CONFIG_ERROR_DETECT */
4365
4366 #ifdef CONFIG_IOL
4367 /*
4368 ops->IOL_exec_cmds_sync = NULL;
4369 */
4370 #endif
4371
4372 ops->hal_notch_filter = rtl8822b_notch_filter_switch;
4373 /*
4374 ops->c2h_handler = NULL;
4375 */
4376 ops->c2h_id_filter_ccx = c2h_id_filter_ccx_8822b;
4377 ops->fill_h2c_cmd = rtl8822b_fillh2ccmd;
4378 ops->fill_fake_txdesc = fill_fake_txdesc;
4379 ops->fw_dl = rtl8822b_fw_dl;
4380
4381 #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) || defined(CONFIG_PCI_HCI)
4382 /*
4383 ops->clear_interrupt = NULL;
4384 */
4385 #endif
4386
4387 ops->hal_get_tx_buff_rsvd_page_num = get_txbuffer_rsvdpagenum;
4388
4389 #ifdef CONFIG_GPIO_API
4390 /*
4391 ops->update_hisr_hsisr_ind = NULL;
4392 */
4393 #endif
4394
4395 ops->fw_correct_bcn = rtl8822b_fw_update_beacon_cmd;
4396
4397 /* HALMAC related functions */
4398 ops->init_mac_register = rtl8822b_phy_init_mac_register;
4399 ops->init_phy = rtl8822b_phy_init;
4400 ops->reqtxrpt = rtl8822b_req_txrpt_cmd;
4401 }
4402