1 /******************************************************************************
2 *
3 * Copyright(c) 2015 - 2016 Realtek Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 *
19 ******************************************************************************/
20 #define _RTL8822B_PHY_C_
21
22 #include <hal_data.h> /* HAL_DATA_TYPE */
23 #include "../hal_halmac.h" /* rtw_halmac_phy_power_switch() */
24 #include "rtl8822b.h"
25
26
27 /*
28 * Description:
29 * Initialize Register definition offset for Radio Path A/B/C/D
30 * The initialization value is constant and it should never be changes
31 */
bb_rf_register_definition(PADAPTER adapter)32 static void bb_rf_register_definition(PADAPTER adapter)
33 {
34 PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
35
36
37 /* RF Interface Sowrtware Control */
38 hal->PHYRegDef[ODM_RF_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW;
39 hal->PHYRegDef[ODM_RF_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW;
40
41 /* RF Interface Output (and Enable) */
42 hal->PHYRegDef[ODM_RF_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE;
43 hal->PHYRegDef[ODM_RF_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE;
44
45 /* RF Interface (Output and) Enable */
46 hal->PHYRegDef[ODM_RF_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE;
47 hal->PHYRegDef[ODM_RF_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE;
48
49 hal->PHYRegDef[ODM_RF_PATH_A].rf3wireOffset = rA_LSSIWrite_Jaguar;
50 hal->PHYRegDef[ODM_RF_PATH_B].rf3wireOffset = rB_LSSIWrite_Jaguar;
51
52 hal->PHYRegDef[ODM_RF_PATH_A].rfHSSIPara2 = rHSSIRead_Jaguar;
53 hal->PHYRegDef[ODM_RF_PATH_B].rfHSSIPara2 = rHSSIRead_Jaguar;
54
55 /* Tranceiver Readback LSSI/HSPI mode */
56 hal->PHYRegDef[ODM_RF_PATH_A].rfLSSIReadBack = rA_SIRead_Jaguar;
57 hal->PHYRegDef[ODM_RF_PATH_B].rfLSSIReadBack = rB_SIRead_Jaguar;
58 hal->PHYRegDef[ODM_RF_PATH_A].rfLSSIReadBackPi = rA_PIRead_Jaguar;
59 hal->PHYRegDef[ODM_RF_PATH_B].rfLSSIReadBackPi = rB_PIRead_Jaguar;
60 }
61
62 /*
63 * Description:
64 * Initialize MAC registers
65 *
66 * Return:
67 * _TRUE Success
68 * _FALSE Fail
69 */
rtl8822b_phy_init_mac_register(PADAPTER adapter)70 u8 rtl8822b_phy_init_mac_register(PADAPTER adapter)
71 {
72 PHAL_DATA_TYPE hal;
73 u8 regfile[] = RTL8822B_PHY_MACREG;
74 u8 ret = _TRUE;
75 int res;
76 HAL_STATUS status;
77
78
79 hal = GET_HAL_DATA(adapter);
80
81 ret = _FALSE;
82 #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
83 res = phy_ConfigMACWithParaFile(adapter, regfile);
84 if (_SUCCESS == res)
85 ret = _TRUE;
86 #endif /* CONFIG_LOAD_PHY_PARA_FROM_FILE */
87 if (_FALSE == ret) {
88 status = ODM_ConfigMACWithHeaderFile(&hal->odmpriv);
89 if (HAL_STATUS_SUCCESS == status)
90 ret = _TRUE;
91 }
92 if (_FALSE == ret)
93 RTW_INFO("%s: Write MAC Reg Fail!!", __FUNCTION__);
94
95 return ret;
96 }
97
_init_bb_reg(PADAPTER Adapter)98 static u8 _init_bb_reg(PADAPTER Adapter)
99 {
100 PHAL_DATA_TYPE hal = GET_HAL_DATA(Adapter);
101 u8 regfile[] = RTL8822B_PHY_REG;
102 u8 agcfile[] = RTL8822B_AGC_TAB;
103 u8 regfile_mp[] = RTL8822B_PHY_REG_MP;
104 u8 ret = _TRUE;
105 int res;
106 HAL_STATUS status;
107
108
109 /*
110 * 1. Read PHY_REG.TXT BB INIT!!
111 */
112 ret = _FALSE;
113 #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
114 res = phy_ConfigBBWithParaFile(Adapter, regfile, CONFIG_BB_PHY_REG);
115 if (_SUCCESS == res)
116 ret = _TRUE;
117 #endif
118 if (_FALSE == ret) {
119 status = ODM_ConfigBBWithHeaderFile(&hal->odmpriv, CONFIG_BB_PHY_REG);
120 if (HAL_STATUS_SUCCESS == status)
121 ret = _TRUE;
122 }
123 if (_FALSE == ret) {
124 RTW_INFO("%s: Write BB Reg Fail!!", __FUNCTION__);
125 goto exit;
126 }
127
128 #if 0 /* No parameter with MP using currently by BB@Stanley. */
129 /*#ifdef CONFIG_MP_INCLUDED*/
130 if (Adapter->registrypriv.mp_mode == 1) {
131 /*
132 * 1.1 Read PHY_REG_MP.TXT BB INIT!!
133 */
134 ret = _FALSE;
135 #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
136 res = phy_ConfigBBWithMpParaFile(Adapter, regfile_mp);
137 if (_SUCCESS == res)
138 ret = _TRUE;
139 #endif
140 if (_FALSE == ret) {
141 status = ODM_ConfigBBWithHeaderFile(&hal->odmpriv, CONFIG_BB_PHY_REG_MP);
142 if (HAL_STATUS_SUCCESS == status)
143 ret = _TRUE;
144 }
145 if (_FALSE == ret) {
146 RTW_INFO("%s: Write BB Reg MP Fail!!", __FUNCTION__);
147 goto exit;
148 }
149 }
150 #endif /* CONFIG_MP_INCLUDED */
151
152 /*
153 * 2. Read BB AGC table Initialization
154 */
155 ret = _FALSE;
156 #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
157 res = phy_ConfigBBWithParaFile(Adapter, agcfile, CONFIG_BB_AGC_TAB);
158 if (_SUCCESS == res)
159 ret = _TRUE;
160 #endif
161 if (_FALSE == ret) {
162 status = ODM_ConfigBBWithHeaderFile(&hal->odmpriv, CONFIG_BB_AGC_TAB);
163 if (HAL_STATUS_SUCCESS == status)
164 ret = _TRUE;
165 }
166 if (_FALSE == ret) {
167 RTW_INFO("%s: Write AGC Table Fail!\n", __FUNCTION__);
168 goto exit;
169 }
170
171 exit:
172 return ret;
173 }
174
init_bb_reg(PADAPTER adapter)175 static u8 init_bb_reg(PADAPTER adapter)
176 {
177 u8 ret = _TRUE;
178 PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
179
180
181 /*
182 * Config BB and AGC
183 */
184 ret = _init_bb_reg(adapter);
185
186 hal_set_crystal_cap(adapter, hal->CrystalCap);
187
188 return ret;
189 }
190
_init_rf_reg(PADAPTER adapter)191 static u8 _init_rf_reg(PADAPTER adapter)
192 {
193 u8 path, phydm_path;
194 PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
195 u8 regfile_a[] = RTL8822B_PHY_RADIO_A;
196 u8 regfile_b[] = RTL8822B_PHY_RADIO_B;
197 u8 *regfile;
198 u8 txpwrtrackfile[] = RTL8822B_TXPWR_TRACK;
199 HAL_STATUS status;
200 int res;
201 u8 ret = _TRUE;
202
203
204 /*
205 * Initialize RF
206 */
207 for (path = 0; path < hal->NumTotalRFPath; path++) {
208 /* Initialize RF from configuration file */
209 switch (path) {
210 case RF_PATH_A:
211 phydm_path = ODM_RF_PATH_A;
212 regfile = regfile_a;
213 break;
214
215 case RF_PATH_B:
216 phydm_path = ODM_RF_PATH_B;
217 regfile = regfile_b;
218 break;
219
220 default:
221 RTW_INFO("%s: [WARN] Unknown path=%d, skip!\n", __FUNCTION__, path);
222 continue;
223 }
224
225 ret = _FALSE;
226 #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
227 res = PHY_ConfigRFWithParaFile(adapter, regfile, phydm_path);
228 if (_SUCCESS == res)
229 ret = _TRUE;
230 #endif
231 if (_FALSE == ret) {
232 status = ODM_ConfigRFWithHeaderFile(&hal->odmpriv, CONFIG_RF_RADIO, (ODM_RF_RADIO_PATH_E)phydm_path);
233 if (HAL_STATUS_SUCCESS != status)
234 goto exit;
235 ret = _TRUE;
236 }
237 }
238
239 /*
240 * Configuration of Tx Power Tracking
241 */
242 ret = _FALSE;
243 #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
244 res = PHY_ConfigRFWithTxPwrTrackParaFile(adapter, txpwrtrackfile);
245 if (_SUCCESS == res)
246 ret = _TRUE;
247 #endif
248 if (_FALSE == ret) {
249 status = ODM_ConfigRFWithTxPwrTrackHeaderFile(&hal->odmpriv);
250 if (HAL_STATUS_SUCCESS != status) {
251 RTW_INFO("%s: Write PwrTrack Table Fail!\n", __FUNCTION__);
252 goto exit;
253 }
254 ret = _TRUE;
255 }
256
257 exit:
258 return ret;
259 }
260
init_rf_reg(PADAPTER adapter)261 static u8 init_rf_reg(PADAPTER adapter)
262 {
263 u8 ret = _TRUE;
264
265
266 ret = _init_rf_reg(adapter);
267
268 return ret;
269 }
270
271 /*
272 * Description:
273 * Initialize PHY(BB/RF) related functions
274 *
275 * Return:
276 * _TRUE Success
277 * _FALSE Fail
278 */
rtl8822b_phy_init(PADAPTER adapter)279 u8 rtl8822b_phy_init(PADAPTER adapter)
280 {
281 PHAL_DATA_TYPE hal;
282 PDM_ODM_T phydm;
283 u8 rf_type;
284 ODM_RF_PATH_E txpath, rxpath;
285 BOOLEAN tx2path;
286 u8 ok = _TRUE;
287 BOOLEAN ret;
288
289
290 hal = GET_HAL_DATA(adapter);
291 phydm = &hal->odmpriv;
292
293 bb_rf_register_definition(adapter);
294
295 rtw_halmac_phy_power_switch(adapter_to_dvobj(adapter), _TRUE);
296
297 ret = config_phydm_parameter_init(phydm, ODM_PRE_SETTING);
298 if (FALSE == ret)
299 return _FALSE;
300
301 ok = init_bb_reg(adapter);
302 if (_FALSE == ok)
303 return _FALSE;
304 ok = init_rf_reg(adapter);
305 if (_FALSE == ok)
306 return _FALSE;
307
308 ret = config_phydm_parameter_init(phydm, ODM_POST_SETTING);
309 if (FALSE == ret)
310 return _FALSE;
311
312 rf_type = RF_2T2R;
313 rtw_hal_get_hwreg(adapter, HW_VAR_RF_TYPE, (u8 *)&rf_type);
314 switch (rf_type) {
315 case RF_1T1R:
316 txpath = ODM_RF_A;
317 rxpath = ODM_RF_A;
318 break;
319 case RF_1T2R:
320 txpath = ODM_RF_A;
321 rxpath = ODM_RF_A | ODM_RF_B;
322 break;
323 default:
324 case RF_2T2R:
325 txpath = ODM_RF_A | ODM_RF_B;
326 rxpath = ODM_RF_A | ODM_RF_B;
327 break;
328 }
329 tx2path = FALSE;
330 ret = config_phydm_trx_mode_8822b(phydm, txpath, rxpath, tx2path);
331 if (FALSE == ret)
332 return _FALSE;
333
334 return _TRUE;
335 }
336
dm_CheckProtection(PADAPTER adapter)337 static void dm_CheckProtection(PADAPTER adapter)
338 {
339 }
340
dm_CheckStatistics(PADAPTER adapter)341 static void dm_CheckStatistics(PADAPTER adapter)
342 {
343 }
344
345 #ifdef CONFIG_SUPPORT_HW_WPS_PBC
dm_CheckPbcGPIO(PADAPTER adapter)346 static void dm_CheckPbcGPIO(PADAPTER adapter)
347 {
348 u8 tmp1byte;
349 u8 bPbcPressed = _FALSE;
350
351 if (!adapter->registrypriv.hw_wps_pbc)
352 return;
353
354 #ifdef CONFIG_USB_HCI
355 tmp1byte = rtw_read8(adapter, GPIO_IO_SEL);
356 tmp1byte |= (HAL_8192C_HW_GPIO_WPS_BIT);
357 rtw_write8(adapter, GPIO_IO_SEL, tmp1byte); /* enable GPIO[2] as output mode */
358
359 tmp1byte &= ~(HAL_8192C_HW_GPIO_WPS_BIT);
360 rtw_write8(adapter, GPIO_IN, tmp1byte); /* reset the floating voltage level */
361
362 tmp1byte = rtw_read8(adapter, GPIO_IO_SEL);
363 tmp1byte &= ~(HAL_8192C_HW_GPIO_WPS_BIT);
364 rtw_write8(adapter, GPIO_IO_SEL, tmp1byte); /* enable GPIO[2] as input mode */
365
366 tmp1byte = rtw_read8(adapter, GPIO_IN);
367 if (tmp1byte == 0xff)
368 return;
369
370 if (tmp1byte & HAL_8192C_HW_GPIO_WPS_BIT)
371 bPbcPressed = _TRUE;
372 #else
373 tmp1byte = rtw_read8(adapter, GPIO_IN);
374
375 if ((tmp1byte == 0xff) || adapter->init_adpt_in_progress)
376 return;
377
378 if ((tmp1byte & HAL_8192C_HW_GPIO_WPS_BIT) == 0)
379 bPbcPressed = _TRUE;
380 #endif
381
382 if (_TRUE == bPbcPressed) {
383 /*
384 * Here we only set bPbcPressed to true
385 * After trigger PBC, the variable will be set to false
386 */
387 RTW_INFO("CheckPbcGPIO - PBC is pressed\n");
388 rtw_request_wps_pbc_event(adapter);
389 }
390 }
391 #endif /* CONFIG_SUPPORT_HW_WPS_PBC */
392
393
394 #ifdef CONFIG_PCI_HCI
395 /*
396 * Description:
397 * Perform interrupt migration dynamically to reduce CPU utilization.
398 *
399 * Assumption:
400 * 1. Do not enable migration under WIFI test.
401 */
dm_InterruptMigration(PADAPTER adapter)402 void dm_InterruptMigration(PADAPTER adapter)
403 {
404 PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
405 struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
406 BOOLEAN bCurrentIntMt, bCurrentACIntDisable;
407 BOOLEAN IntMtToSet = _FALSE;
408 BOOLEAN ACIntToSet = _FALSE;
409
410
411 /* Retrieve current interrupt migration and Tx four ACs IMR settings first. */
412 bCurrentIntMt = hal->bInterruptMigration;
413 bCurrentACIntDisable = hal->bDisableTxInt;
414
415 /*
416 * <Roger_Notes> Currently we use busy traffic for reference instead of RxIntOK counts to prevent non-linear Rx statistics
417 * when interrupt migration is set before. 2010.03.05.
418 */
419 if (!adapter->registrypriv.wifi_spec
420 && (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)
421 && pmlmepriv->LinkDetectInfo.bHigherBusyTraffic) {
422 IntMtToSet = _TRUE;
423
424 /* To check whether we should disable Tx interrupt or not. */
425 if (pmlmepriv->LinkDetectInfo.bHigherBusyRxTraffic)
426 ACIntToSet = _TRUE;
427 }
428
429 /* Update current settings. */
430 if (bCurrentIntMt != IntMtToSet) {
431 RTW_INFO("%s: Update interrupt migration(%d)\n", __FUNCTION__, IntMtToSet);
432 if (IntMtToSet) {
433 /*
434 * <Roger_Notes> Set interrupt migration timer and corresponging Tx/Rx counter.
435 * timer 25ns*0xfa0=100us for 0xf packets.
436 * 2010.03.05.
437 */
438 rtw_write32(adapter, REG_INT_MIG, 0xff000fa0); /* 0x306:Rx, 0x307:Tx */
439 hal->bInterruptMigration = IntMtToSet;
440 } else {
441 /* Reset all interrupt migration settings. */
442 rtw_write32(adapter, REG_INT_MIG, 0);
443 hal->bInterruptMigration = IntMtToSet;
444 }
445 }
446 }
447 #endif /* CONFIG_PCI_HCI */
448
449 /*
450 * ============================================================
451 * functions
452 * ============================================================
453 */
init_phydm_cominfo(PADAPTER adapter)454 static void init_phydm_cominfo(PADAPTER adapter)
455 {
456 PHAL_DATA_TYPE hal;
457 PDM_ODM_T pDM_Odm;
458 u32 SupportAbility = 0;
459 u8 cut_ver = ODM_CUT_A, fab_ver = ODM_TSMC;
460
461
462 hal = GET_HAL_DATA(adapter);
463 pDM_Odm = &hal->odmpriv;
464
465 Init_ODM_ComInfo(adapter);
466
467 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_PACKAGE_TYPE, hal->PackageType);
468 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_IC_TYPE, ODM_RTL8822B);
469
470 if (IS_CHIP_VENDOR_TSMC(hal->VersionID))
471 fab_ver = ODM_TSMC;
472 else if (IS_CHIP_VENDOR_UMC(hal->VersionID))
473 fab_ver = ODM_UMC;
474 else if (IS_CHIP_VENDOR_SMIC(hal->VersionID))
475 fab_ver = ODM_UMC + 1;
476 else
477 RTW_INFO("%s: unknown fab_ver=%d !!\n",
478 __FUNCTION__, GET_CVID_MANUFACTUER(hal->VersionID));
479
480 if (IS_A_CUT(hal->VersionID))
481 cut_ver = ODM_CUT_A;
482 else if (IS_B_CUT(hal->VersionID))
483 cut_ver = ODM_CUT_B;
484 else if (IS_C_CUT(hal->VersionID))
485 cut_ver = ODM_CUT_C;
486 else if (IS_D_CUT(hal->VersionID))
487 cut_ver = ODM_CUT_D;
488 else if (IS_E_CUT(hal->VersionID))
489 cut_ver = ODM_CUT_E;
490 else if (IS_F_CUT(hal->VersionID))
491 cut_ver = ODM_CUT_F;
492 else if (IS_I_CUT(hal->VersionID))
493 cut_ver = ODM_CUT_I;
494 else if (IS_J_CUT(hal->VersionID))
495 cut_ver = ODM_CUT_J;
496 else if (IS_K_CUT(hal->VersionID))
497 cut_ver = ODM_CUT_K;
498 else
499 RTW_INFO("%s: unknown cut_ver=%d !!\n",
500 __FUNCTION__, GET_CVID_CUT_VERSION(hal->VersionID));
501
502 RTW_INFO("%s: fab_ver=%d cut_ver=%d\n", __FUNCTION__, fab_ver, cut_ver);
503 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_FAB_VER, fab_ver);
504 ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_CUT_VER, cut_ver);
505
506 #ifdef CONFIG_DISABLE_ODM
507 SupportAbility = 0;
508 #else /* !CONFIG_DISABLE_ODM */
509 SupportAbility = ODM_RF_CALIBRATION | ODM_RF_TX_PWR_TRACK;
510 #endif /* !CONFIG_DISABLE_ODM */
511 ODM_CmnInfoUpdate(pDM_Odm, ODM_CMNINFO_ABILITY, SupportAbility);
512 }
513
update_phydm_cominfo(PADAPTER adapter)514 static void update_phydm_cominfo(PADAPTER adapter)
515 {
516 PHAL_DATA_TYPE hal;
517 PDM_ODM_T pDM_Odm;
518 u32 SupportAbility = 0;
519
520
521 hal = GET_HAL_DATA(adapter);
522 pDM_Odm = &hal->odmpriv;
523
524 SupportAbility = 0
525 | ODM_BB_DIG
526 | ODM_BB_RA_MASK
527 | ODM_BB_DYNAMIC_TXPWR
528 | ODM_BB_FA_CNT
529 | ODM_BB_RSSI_MONITOR
530 | ODM_BB_CCK_PD
531 /* | ODM_BB_PWR_SAVE*/
532 | ODM_BB_CFO_TRACKING
533 | ODM_MAC_EDCA_TURBO
534 | ODM_RF_TX_PWR_TRACK
535 | ODM_RF_CALIBRATION
536 | ODM_BB_NHM_CNT
537 /* | ODM_BB_PWR_TRAIN*/
538 ;
539
540 if (rtw_odm_adaptivity_needed(adapter) == _TRUE)
541 SupportAbility |= ODM_BB_ADAPTIVITY;
542
543 #ifdef CONFIG_ANTENNA_DIVERSITY
544 if (hal->AntDivCfg)
545 SupportAbility |= ODM_BB_ANT_DIV;
546 #endif /* CONFIG_ANTENNA_DIVERSITY */
547
548 #ifdef CONFIG_MP_INCLUDED
549 if (adapter->registrypriv.mp_mode == 1) {
550 SupportAbility = 0
551 | ODM_RF_CALIBRATION
552 | ODM_RF_TX_PWR_TRACK
553 ;
554 }
555 #endif /* CONFIG_MP_INCLUDED */
556
557 #ifdef CONFIG_DISABLE_ODM
558 SupportAbility = 0;
559 #endif /* CONFIG_DISABLE_ODM */
560
561 ODM_CmnInfoUpdate(pDM_Odm, ODM_CMNINFO_ABILITY, SupportAbility);
562 }
563
_pa_bias_paser(u8 shift,u8 * minus,u8 * val)564 static void _pa_bias_paser(u8 shift, u8 *minus, u8 *val)
565 {
566 shift &= 0xF;
567 #if 0
568 /* Skip 0x8(-4) */
569 if ((shift == 0x8) || (shift > 0x9))
570 shift = 0;
571 #endif
572
573 /*
574 * BIT 0 is sign bit,
575 * 1 for positive, 0 for negative
576 */
577 *minus = (shift & BIT(0)) ? 0 : 1;
578 /* BIT 1~3 are value */
579 *val = (shift & 0xE) >> 1;
580 }
581
582 /*
583 * Description:
584 * Access TX PA Bias according to 0x3D8[3:0] or 0x3D7[3:0]
585 *
586 * Return:
587 * Value between 0~7.
588 */
_pa_bias_adjust(u8 bias,u8 minus,u8 val)589 static u8 _pa_bias_adjust(u8 bias, u8 minus, u8 val)
590 {
591 s8 tmp = bias;
592
593
594 if (minus)
595 tmp -= val;
596 else
597 tmp += val;
598
599 if (tmp < 0)
600 return 0;
601 if (tmp > 7)
602 return 7;
603 return (u8)tmp;
604 }
605
_pa_bias_calibration(PADAPTER adapter,enum _ODM_RF_RADIO_PATH path,u8 shift)606 static void _pa_bias_calibration(PADAPTER adapter, enum _ODM_RF_RADIO_PATH path, u8 shift)
607 {
608 u32 rf_reg18_offset[12] = {
609 0X10124,
610 0X10524,
611 0X10924,
612 0X10D24,
613 0X30164,
614 0X30564,
615 0X30964,
616 0X30D64,
617 0X50195,
618 0X50595,
619 0X50995,
620 0X50D95
621 };
622 u8 offset;
623 u32 bias_org, bias_new;
624 u8 val8;
625 u8 minus = 0;
626 u8 val = 0;
627
628
629 _pa_bias_paser(shift, &minus, &val);
630 RTW_INFO("%s: RF-%u bias shift %s%u\n", __FUNCTION__, path, minus?"-":"+", val);
631 if (!val)
632 return;
633
634 rtw_hal_write_rfreg(adapter, path, 0xEF, 0xFFFFF, 0x200);
635
636 /* Set 12 sets of TxA value */
637 for (offset = 0; offset < 12; offset++) {
638 /* Read TX PA Bias Table default value */
639 rtw_hal_write_rfreg(adapter, path, 0x18, 0xFFFFF, rf_reg18_offset[offset]);
640 bias_org = rtw_hal_read_rfreg(adapter, path, 0x61, 0xFFFFF);
641 val8 = bias_org & 0xF;
642 val8 = _pa_bias_adjust(val8, minus, val);
643 bias_new = (bias_org & 0xFF0) | val8;
644 bias_new |= (offset << 12);
645 rtw_hal_write_rfreg(adapter, path, 0x30, 0xFFFFF, bias_new);
646 }
647
648 rtw_hal_write_rfreg(adapter, path, 0xEF, 0xFFFFF, 0x0);
649 }
650
pa_bias_calibration(PADAPTER adapter)651 static void pa_bias_calibration(PADAPTER adapter)
652 {
653 struct hal_com_data *hal;
654 u32 rf_reg18_a, rf_reg18_b;
655 u32 time;
656
657
658 hal = GET_HAL_DATA(adapter);
659 if (0xFF == hal->tx_pa_bias_a)
660 return;
661
662 time = rtw_get_current_time();
663
664 /* Save RF register 0x18 */
665 rf_reg18_a = rtw_hal_read_rfreg(adapter, ODM_RF_PATH_A, 0x18, 0xFFFFF);
666 rf_reg18_b = rtw_hal_read_rfreg(adapter, ODM_RF_PATH_B, 0x18, 0xFFFFF);
667
668 _pa_bias_calibration(adapter, ODM_RF_PATH_A, hal->tx_pa_bias_a);
669 _pa_bias_calibration(adapter, ODM_RF_PATH_B, hal->tx_pa_bias_b);
670
671 /* Restore RF register 0x18 */
672 rtw_hal_write_rfreg(adapter, ODM_RF_PATH_A, 0x18, 0xFFFFF, rf_reg18_a);
673 rtw_hal_write_rfreg(adapter, ODM_RF_PATH_B, 0x18, 0xFFFFF, rf_reg18_b);
674
675 RTW_INFO("%s: done! cost %u ms\n", __FUNCTION__, rtw_get_passing_time_ms(time));
676 }
677
rtl8822b_phy_init_dm_priv(PADAPTER adapter)678 void rtl8822b_phy_init_dm_priv(PADAPTER adapter)
679 {
680 PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
681 PDM_ODM_T podmpriv = &hal->odmpriv;
682
683
684 /*
685 * Call this before other phydm functions
686 * to guarantee debug messages of phydm would be printed.
687 */
688
689 init_phydm_cominfo(adapter);
690 ODM_InitAllTimers(podmpriv);
691 PHYDM_InitDebugSetting(podmpriv);
692 }
693
rtl8822b_phy_deinit_dm_priv(PADAPTER adapter)694 void rtl8822b_phy_deinit_dm_priv(PADAPTER adapter)
695 {
696 PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
697 PDM_ODM_T podmpriv = &hal->odmpriv;
698
699
700 ODM_CancelAllTimers(podmpriv);
701 }
702
rtl8822b_phy_init_haldm(PADAPTER adapter)703 void rtl8822b_phy_init_haldm(PADAPTER adapter)
704 {
705 PHAL_DATA_TYPE hal;
706 PDM_ODM_T pDM_Odm;
707
708
709 hal = GET_HAL_DATA(adapter);
710 pDM_Odm = &hal->odmpriv;
711
712 hal->DM_Type = DM_Type_ByDriver;
713
714 update_phydm_cominfo(adapter);
715
716 ODM_DMInit(pDM_Odm);
717
718 pa_bias_calibration(adapter);
719 }
720
check_rxfifo_full(PADAPTER adapter)721 static void check_rxfifo_full(PADAPTER adapter)
722 {
723 struct dvobj_priv *psdpriv = adapter->dvobj;
724 struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
725 HAL_DATA_TYPE *hal = GET_HAL_DATA(adapter);
726 struct registry_priv *regsty = &adapter->registrypriv;
727 u8 val8 = 0;
728
729 if (regsty->check_hw_status == 1) {
730 /* switch counter to RX fifo */
731 val8 = rtw_read8(adapter, REG_RXERR_RPT_8822B + 3);
732 rtw_write8(adapter, REG_RXERR_RPT_8822B + 3, (val8 | 0xa0));
733
734 pdbgpriv->dbg_rx_fifo_last_overflow = pdbgpriv->dbg_rx_fifo_curr_overflow;
735 pdbgpriv->dbg_rx_fifo_curr_overflow = rtw_read16(adapter, REG_RXERR_RPT_8822B);
736 pdbgpriv->dbg_rx_fifo_diff_overflow =
737 pdbgpriv->dbg_rx_fifo_curr_overflow - pdbgpriv->dbg_rx_fifo_last_overflow;
738 }
739 }
740
rtl8822b_phy_haldm_watchdog(PADAPTER adapter)741 void rtl8822b_phy_haldm_watchdog(PADAPTER adapter)
742 {
743 BOOLEAN bFwCurrentInPSMode = _FALSE;
744 BOOLEAN bFwPSAwake = _TRUE;
745 PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
746
747
748 #ifdef CONFIG_MP_INCLUDED
749 /* for MP power tracking */
750 if ((adapter->registrypriv.mp_mode == 1)
751 && (adapter->mppriv.mp_dm == 0))
752 return;
753 #endif /* CONFIG_MP_INCLUDED */
754
755 if (!rtw_is_hw_init_completed(adapter))
756 goto skip_dm;
757
758 #ifdef CONFIG_LPS
759 bFwCurrentInPSMode = adapter_to_pwrctl(adapter)->bFwCurrentInPSMode;
760 rtw_hal_get_hwreg(adapter, HW_VAR_FWLPS_RF_ON, (u8 *)&bFwPSAwake);
761 #endif /* CONFIG_LPS */
762
763 #ifdef CONFIG_P2P_PS
764 /*
765 * Fw is under p2p powersaving mode, driver should stop dynamic mechanism.
766 */
767 if (adapter->wdinfo.p2p_ps_mode)
768 bFwPSAwake = _FALSE;
769 #endif /* CONFIG_P2P */
770
771 if ((rtw_is_hw_init_completed(adapter))
772 && ((!bFwCurrentInPSMode) && bFwPSAwake)) {
773
774 /* check rx fifo */
775 check_rxfifo_full(adapter);
776 /*
777 * Dynamically switch RTS/CTS protection.
778 */
779 dm_CheckProtection(adapter);
780 }
781
782 /* PHYDM */
783 if (rtw_is_hw_init_completed(adapter)) {
784 u8 bLinked = _FALSE;
785 u8 bsta_state = _FALSE;
786 u8 bBtDisabled = _TRUE;
787
788 if (rtw_mi_check_status(adapter, MI_ASSOC)) {
789 bLinked = _TRUE;
790 if (rtw_mi_check_status(adapter, MI_STA_LINKED))
791 bsta_state = _TRUE;
792 }
793
794 ODM_CmnInfoUpdate(&hal->odmpriv, ODM_CMNINFO_LINK, bLinked);
795 ODM_CmnInfoUpdate(&hal->odmpriv, ODM_CMNINFO_STATION_STATE, bsta_state);
796
797 #ifdef CONFIG_BT_COEXIST
798 bBtDisabled = rtw_btcoex_IsBtDisabled(adapter);
799 #endif /* CONFIG_BT_COEXIST */
800 ODM_CmnInfoUpdate(&hal->odmpriv, ODM_CMNINFO_BT_ENABLED, ((bBtDisabled == _TRUE) ? _FALSE : _TRUE));
801
802 ODM_DMWatchdog(&hal->odmpriv);
803 }
804
805 skip_dm:
806 /*
807 * Check GPIO to determine current RF on/off and Pbc status.
808 * Check Hardware Radio ON/OFF or not
809 */
810 #ifdef CONFIG_SUPPORT_HW_WPS_PBC
811 dm_CheckPbcGPIO(adapter);
812 #else /* !CONFIG_SUPPORT_HW_WPS_PBC */
813 return;
814 #endif /* !CONFIG_SUPPORT_HW_WPS_PBC */
815 }
816
rtl8822b_phy_haldm_in_lps(PADAPTER adapter)817 void rtl8822b_phy_haldm_in_lps(PADAPTER adapter)
818 {
819 u32 PWDB_rssi = 0;
820 struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
821 PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
822 PDM_ODM_T pDM_Odm = &hal->odmpriv;
823 pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable;
824 struct sta_priv *pstapriv = &adapter->stapriv;
825 struct sta_info *psta = NULL;
826
827
828 RTW_INFO("%s: RSSI_Min=%d\n", __FUNCTION__, pDM_Odm->RSSI_Min);
829
830 /* update IGI */
831 ODM_Write_DIG(pDM_Odm, pDM_Odm->RSSI_Min);
832
833 /* set rssi to fw */
834 psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv));
835 if (psta && (psta->rssi_stat.UndecoratedSmoothedPWDB > 0)) {
836 PWDB_rssi = (psta->mac_id | (psta->rssi_stat.UndecoratedSmoothedPWDB << 16));
837 rtl8822b_set_FwRssiSetting_cmd(adapter, (u8 *)&PWDB_rssi);
838 }
839 }
840
rtl8822b_phy_haldm_watchdog_in_lps(PADAPTER adapter)841 void rtl8822b_phy_haldm_watchdog_in_lps(PADAPTER adapter)
842 {
843 u8 bLinked = _FALSE;
844 PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
845 struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
846 PDM_ODM_T pDM_Odm = &hal->odmpriv;
847 pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable;
848 struct sta_priv *pstapriv = &adapter->stapriv;
849 struct sta_info *psta = NULL;
850
851 if (!rtw_is_hw_init_completed(adapter))
852 goto skip_lps_dm;
853
854 if (rtw_mi_check_status(adapter, MI_ASSOC))
855 bLinked = _TRUE;
856
857 ODM_CmnInfoUpdate(&hal->odmpriv, ODM_CMNINFO_LINK, bLinked);
858
859 if (bLinked == _FALSE)
860 goto skip_lps_dm;
861
862 if (!(pDM_Odm->SupportAbility & ODM_BB_RSSI_MONITOR))
863 goto skip_lps_dm;
864
865 /* Do DIG by RSSI In LPS-32K */
866
867 /* 1. Find MIN-RSSI */
868 psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv));
869 if (psta == NULL)
870 goto skip_lps_dm;
871
872 hal->EntryMinUndecoratedSmoothedPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB;
873
874 RTW_INFO("CurIGValue=%d, EntryMinUndecoratedSmoothedPWDB=%d\n",
875 pDM_DigTable->CurIGValue, hal->EntryMinUndecoratedSmoothedPWDB);
876
877 if (hal->EntryMinUndecoratedSmoothedPWDB <= 0)
878 goto skip_lps_dm;
879
880 hal->MinUndecoratedPWDBForDM = hal->EntryMinUndecoratedSmoothedPWDB;
881
882 pDM_Odm->RSSI_Min = hal->MinUndecoratedPWDBForDM;
883
884 #ifdef CONFIG_LPS
885 if ((pDM_DigTable->CurIGValue > pDM_Odm->RSSI_Min + 5)
886 || (pDM_DigTable->CurIGValue < pDM_Odm->RSSI_Min - 5))
887 rtw_dm_in_lps_wk_cmd(adapter);
888 #endif
889
890 skip_lps_dm:
891 return;
892 }
893
phy_calculatebitshift(u32 mask)894 static u32 phy_calculatebitshift(u32 mask)
895 {
896 u32 i;
897
898
899 for (i = 0; i <= 31; i++)
900 if (mask & BIT(i))
901 break;
902
903 return i;
904 }
905
rtl8822b_read_bb_reg(PADAPTER adapter,u32 addr,u32 mask)906 u32 rtl8822b_read_bb_reg(PADAPTER adapter, u32 addr, u32 mask)
907 {
908 u32 val = 0, val_org, shift;
909
910
911 #if (DISABLE_BB_RF == 1)
912 return 0;
913 #endif
914
915 val_org = rtw_read32(adapter, addr);
916 shift = phy_calculatebitshift(mask);
917 val = (val_org & mask) >> shift;
918
919 return val;
920 }
921
rtl8822b_write_bb_reg(PADAPTER adapter,u32 addr,u32 mask,u32 val)922 void rtl8822b_write_bb_reg(PADAPTER adapter, u32 addr, u32 mask, u32 val)
923 {
924 u32 val_org, shift;
925
926
927 #if (DISABLE_BB_RF == 1)
928 return;
929 #endif
930
931 if (mask != 0xFFFFFFFF) {
932 /* not "double word" write */
933 val_org = rtw_read32(adapter, addr);
934 shift = phy_calculatebitshift(mask);
935 val = ((val_org & (~mask)) | ((val << shift) & mask));
936 }
937
938 rtw_write32(adapter, addr, val);
939 }
940
rtl8822b_read_rf_reg(PADAPTER adapter,u8 path,u32 addr,u32 mask)941 u32 rtl8822b_read_rf_reg(PADAPTER adapter, u8 path, u32 addr, u32 mask)
942 {
943 PHAL_DATA_TYPE hal;
944 PDM_ODM_T phydm;
945 u32 val;
946
947
948 hal = GET_HAL_DATA(adapter);
949 phydm = &hal->odmpriv;
950
951 val = config_phydm_read_rf_reg_8822b(phydm, path, addr, mask);
952 if (!config_phydm_read_rf_check_8822b(val))
953 RTW_INFO(FUNC_ADPT_FMT ": read RF reg path=%d addr=0x%x mask=0x%x FAIL!\n",
954 FUNC_ADPT_ARG(adapter), path, addr, mask);
955
956 return val;
957 }
958
rtl8822b_write_rf_reg(PADAPTER adapter,u8 path,u32 addr,u32 mask,u32 val)959 void rtl8822b_write_rf_reg(PADAPTER adapter, u8 path, u32 addr, u32 mask, u32 val)
960 {
961 PHAL_DATA_TYPE hal;
962 PDM_ODM_T phydm;
963 u8 ret;
964
965
966 hal = GET_HAL_DATA(adapter);
967 phydm = &hal->odmpriv;
968
969 ret = config_phydm_write_rf_reg_8822b(phydm, path, addr, mask, val);
970 if (_FALSE == ret)
971 RTW_INFO(FUNC_ADPT_FMT ": write RF reg path=%d addr=0x%x mask=0x%x val=0x%x FAIL!\n",
972 FUNC_ADPT_ARG(adapter), path, addr, mask, val);
973 }
974
set_tx_power_level_by_path(PADAPTER adapter,u8 channel,u8 path)975 static void set_tx_power_level_by_path(PADAPTER adapter, u8 channel, u8 path)
976 {
977 PHY_SetTxPowerIndexByRateSection(adapter, path, channel, CCK);
978 PHY_SetTxPowerIndexByRateSection(adapter, path, channel, OFDM);
979 PHY_SetTxPowerIndexByRateSection(adapter, path, channel, HT_MCS0_MCS7);
980 PHY_SetTxPowerIndexByRateSection(adapter, path, channel, HT_MCS8_MCS15);
981 PHY_SetTxPowerIndexByRateSection(adapter, path, channel, VHT_1SSMCS0_1SSMCS9);
982 PHY_SetTxPowerIndexByRateSection(adapter, path, channel, VHT_2SSMCS0_2SSMCS9);
983 }
984
rtl8822b_set_tx_power_level(PADAPTER adapter,u8 channel)985 void rtl8822b_set_tx_power_level(PADAPTER adapter, u8 channel)
986 {
987 PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
988 PDM_ODM_T phydm;
989 pFAT_T pDM_FatTable;
990 u8 path = ODM_RF_PATH_A;
991
992
993 hal = GET_HAL_DATA(adapter);
994 phydm = &hal->odmpriv;
995 pDM_FatTable = &phydm->DM_FatTable;
996
997 if (hal->AntDivCfg) {
998 /* antenna diversity Enable */
999 path = (pDM_FatTable->RxIdleAnt == MAIN_ANT) ? ODM_RF_PATH_A : ODM_RF_PATH_B;
1000 set_tx_power_level_by_path(adapter, channel, path);
1001 } else {
1002 /* antenna diversity disable */
1003 for (path = ODM_RF_PATH_A; path < hal->NumTotalRFPath; ++path)
1004 set_tx_power_level_by_path(adapter, channel, path);
1005 }
1006 }
1007
rtl8822b_get_tx_power_level(PADAPTER adapter,s32 * power)1008 void rtl8822b_get_tx_power_level(PADAPTER adapter, s32 *power)
1009 {
1010 }
1011
1012 /*
1013 * Parameters:
1014 * padatper
1015 * powerindex power index for rate
1016 * rfpath Antenna(RF) path, type "enum _ODM_RF_RADIO_PATH"
1017 * rate data rate, type "enum MGN_RATE"
1018 */
rtl8822b_set_tx_power_index(PADAPTER adapter,u32 powerindex,u8 rfpath,u8 rate)1019 void rtl8822b_set_tx_power_index(PADAPTER adapter, u32 powerindex, u8 rfpath, u8 rate)
1020 {
1021 PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
1022 PDM_ODM_T phydm = &hal->odmpriv;
1023 u8 shift = 0;
1024 static u32 index = 0;
1025
1026
1027 rate = PHY_GetRateIndexOfTxPowerByRate(rate);
1028
1029 /*
1030 * For 8822B, phydm api use 4 bytes txagc value
1031 * driver must combine every four 1 byte to one 4 byte and send to phydm api
1032 */
1033 shift = rate % 4;
1034 index |= ((powerindex & 0xff) << (shift * 8));
1035
1036 if (shift == 3) {
1037 rate = rate - 3;
1038
1039 if (!config_phydm_write_txagc_8822b(phydm, index, rfpath, rate)) {
1040 RTW_INFO("%s(index:%d, rfpath:%d, rate:0x%02x, disable api:%d) fail\n",
1041 __FUNCTION__, index, rfpath, rate, phydm->bDisablePhyApi);
1042
1043 rtw_warn_on(1);
1044 }
1045 index = 0;
1046 }
1047 }
1048
rtl8822b_phy_get_current_tx_num(PADAPTER adapter,u8 rate)1049 static u8 rtl8822b_phy_get_current_tx_num(PADAPTER adapter, u8 rate)
1050 {
1051 u8 tx_num = 0;
1052
1053 if ((rate >= MGN_MCS8 && rate <= MGN_MCS15) ||
1054 (rate >= MGN_VHT2SS_MCS0 && rate <= MGN_VHT2SS_MCS9))
1055 tx_num = RF_2TX;
1056 else
1057 tx_num = RF_1TX;
1058
1059 return tx_num;
1060 }
1061
1062 /*
1063 * Parameters:
1064 * padatper
1065 * rfpath Antenna(RF) path, type "enum _ODM_RF_RADIO_PATH"
1066 * rate data rate, type "enum MGN_RATE"
1067 * bandwidth Bandwidth, type "enum _CHANNEL_WIDTH"
1068 * channel Channel number
1069 *
1070 * Rteurn:
1071 * tx_power power index for rate
1072 */
rtl8822b_get_tx_power_index(PADAPTER adapter,u8 rfpath,u8 rate,u8 bandwidth,u8 channel)1073 u8 rtl8822b_get_tx_power_index(PADAPTER adapter, u8 rfpath, u8 rate, u8 bandwidth, u8 channel)
1074 {
1075 PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
1076 s8 power_diff_by_rate = 0;
1077 s8 tx_power = 0, limit = 0;
1078 u8 tx_num = rtl8822b_phy_get_current_tx_num(adapter, rate);
1079 u8 bIn24G = _FALSE;
1080
1081
1082 tx_power = (s8) PHY_GetTxPowerIndexBase(adapter, rfpath, rate, bandwidth, channel, &bIn24G);
1083
1084 power_diff_by_rate = PHY_GetTxPowerByRate(adapter, (u8)(!bIn24G), rfpath, tx_num, rate);
1085
1086 limit = PHY_GetTxPowerLimit(adapter, adapter->registrypriv.RegPwrTblSel, (BAND_TYPE)(!bIn24G),
1087 hal->CurrentChannelBW, rfpath, rate, hal->CurrentChannel);
1088
1089 power_diff_by_rate = power_diff_by_rate > limit ? limit : power_diff_by_rate;
1090
1091 tx_power += power_diff_by_rate;
1092
1093 #if 0
1094 #if CCX_SUPPORT
1095 CCX_CellPowerLimit(pAdapter, Channel, Rate, (u8 *)&txPower);
1096 #endif
1097 #endif
1098
1099 if (tx_power > MAX_POWER_INDEX)
1100 tx_power = MAX_POWER_INDEX;
1101
1102 return tx_power;
1103 }
1104
1105 /*
1106 * Description:
1107 * Check need to switch band or not
1108 * Parameters:
1109 * channelToSW channel wiii be switch to
1110 * Return:
1111 * _TRUE need to switch band
1112 * _FALSE not need to switch band
1113 */
need_switch_band(PADAPTER adapter,u8 channelToSW)1114 static u8 need_switch_band(PADAPTER adapter, u8 channelToSW)
1115 {
1116 u8 u1tmp = 0;
1117 u8 ret_value = _TRUE;
1118 u8 Band = BAND_ON_5G, BandToSW = BAND_ON_5G;
1119 PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
1120
1121 Band = hal->CurrentBandType;
1122
1123 /* Use current swich channel to judge Band Type and switch Band if need */
1124 if (channelToSW > 14)
1125 BandToSW = BAND_ON_5G;
1126 else
1127 BandToSW = BAND_ON_2_4G;
1128
1129 if (BandToSW != Band) {
1130 /* record current band type for other hal use */
1131 hal->CurrentBandType = (BAND_TYPE)BandToSW;
1132 ret_value = _TRUE;
1133 } else
1134 ret_value = _FALSE;
1135
1136 return ret_value;
1137 }
1138
get_pri_ch_id(PADAPTER adapter)1139 static u8 get_pri_ch_id(PADAPTER adapter)
1140 {
1141 u8 pri_ch_idx = 0;
1142 PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
1143
1144 if (hal->CurrentChannelBW == CHANNEL_WIDTH_80) {
1145 /* primary channel is at lower subband of 80MHz & 40MHz */
1146 if ((hal->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) && (hal->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER))
1147 pri_ch_idx = VHT_DATA_SC_20_LOWEST_OF_80MHZ;
1148 /* primary channel is at lower subband of 80MHz & upper subband of 40MHz */
1149 else if ((hal->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) && (hal->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER))
1150 pri_ch_idx = VHT_DATA_SC_20_LOWER_OF_80MHZ;
1151 /* primary channel is at upper subband of 80MHz & lower subband of 40MHz */
1152 else if ((hal->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) && (hal->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER))
1153 pri_ch_idx = VHT_DATA_SC_20_UPPER_OF_80MHZ;
1154 /* primary channel is at upper subband of 80MHz & upper subband of 40MHz */
1155 else if ((hal->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) && (hal->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER))
1156 pri_ch_idx = VHT_DATA_SC_20_UPPERST_OF_80MHZ;
1157 else {
1158 if (hal->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)
1159 pri_ch_idx = VHT_DATA_SC_40_LOWER_OF_80MHZ;
1160 else if (hal->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)
1161 pri_ch_idx = VHT_DATA_SC_40_UPPER_OF_80MHZ;
1162 else
1163 RTW_INFO("SCMapping: DONOT CARE Mode Setting\n");
1164 }
1165 } else if (hal->CurrentChannelBW == CHANNEL_WIDTH_40) {
1166 /* primary channel is at upper subband of 40MHz */
1167 if (hal->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)
1168 pri_ch_idx = VHT_DATA_SC_20_UPPER_OF_80MHZ;
1169 /* primary channel is at lower subband of 40MHz */
1170 else if (hal->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)
1171 pri_ch_idx = VHT_DATA_SC_20_LOWER_OF_80MHZ;
1172 else
1173 RTW_INFO("SCMapping: DONOT CARE Mode Setting\n");
1174 }
1175
1176 return pri_ch_idx;
1177 }
1178
mac_switch_bandwidth(PADAPTER adapter,u8 pri_ch_idx)1179 static void mac_switch_bandwidth(PADAPTER adapter, u8 pri_ch_idx)
1180 {
1181 u8 channel = 0, bw = 0;
1182 PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
1183 int err;
1184
1185 channel = hal->CurrentChannel;
1186 bw = hal->CurrentChannelBW;
1187 err = rtw_halmac_set_bandwidth(adapter_to_dvobj(adapter), channel, pri_ch_idx, bw);
1188 if (err) {
1189 RTW_INFO(FUNC_ADPT_FMT ": (channel=%d, pri_ch_idx=%d, bw=%d) fail\n",
1190 FUNC_ADPT_ARG(adapter), channel, pri_ch_idx, bw);
1191 }
1192 }
1193
1194 /*
1195 * Description:
1196 * Set channel & bandwidth & offset
1197 */
rtl8822b_switch_chnl_and_set_bw(PADAPTER adapter)1198 void rtl8822b_switch_chnl_and_set_bw(PADAPTER adapter)
1199 {
1200 PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
1201 PDM_ODM_T pDM_Odm = &hal->odmpriv;
1202 u8 center_ch = 0, ret = 0;
1203
1204 if (adapter->bNotifyChannelChange) {
1205 RTW_INFO("[%s] bSwChnl=%d, ch=%d, bSetChnlBW=%d, bw=%d\n",
1206 __FUNCTION__,
1207 hal->bSwChnl,
1208 hal->CurrentChannel,
1209 hal->bSetChnlBW,
1210 hal->CurrentChannelBW);
1211 }
1212
1213 if (RTW_CANNOT_RUN(adapter)) {
1214 hal->bSwChnlAndSetBWInProgress = _FALSE;
1215 return;
1216 }
1217
1218 /* set channel & Bandwidth register */
1219 /* 1. set switch band register if need to switch band */
1220 if (need_switch_band(adapter, hal->CurrentChannel) == _TRUE) {
1221 #ifdef CONFIG_BT_COEXIST
1222 if (hal->EEPROMBluetoothCoexist) {
1223 struct mlme_ext_priv *mlmeext;
1224
1225 /* switch band under site survey or not, must notify to BT COEX */
1226 mlmeext = &adapter->mlmeextpriv;
1227 if (mlmeext_scan_state(mlmeext) != SCAN_DISABLE)
1228 rtw_btcoex_switchband_notify(_TRUE, hal->CurrentBandType);
1229 else
1230 rtw_btcoex_switchband_notify(_FALSE, hal->CurrentBandType);
1231 }
1232 #endif /* CONFIG_BT_COEXIST */
1233
1234 /* hal->CurrentChannel is center channel of pmlmeext->cur_channel(primary channel) */
1235 ret = config_phydm_switch_band_8822b(pDM_Odm, hal->CurrentChannel);
1236
1237 if (!ret) {
1238 RTW_INFO("%s: config_phydm_switch_band_8822b fail\n", __FUNCTION__);
1239 rtw_warn_on(1);
1240 return;
1241 }
1242
1243 /* <2016/03/09> ** This Setting is for MP Driver Only*/
1244 #ifdef CONFIG_MP_INCLUDED
1245 if (adapter->registrypriv.mp_mode == _TRUE) {
1246 /* <2016/02/25, VincentL> Add for 8822B Antenna Binding between "2.4G-WiFi"
1247 And between "5G-BT", Suggested by RF SzuyiTsai*/
1248 if (hal->CurrentChannel <= 14) /* 2.4G*/
1249 PHY_SetRFPathSwitch_8822B(adapter, 1); /*To WiFi-2.4G*/
1250 else /* 5G */
1251 PHY_SetRFPathSwitch_8822B(adapter, 0); /*To BT-5G*/
1252 }
1253 #endif
1254
1255 }
1256
1257 /* 2. set channel register */
1258 if (hal->bSwChnl) {
1259 ret = config_phydm_switch_channel_8822b(pDM_Odm, hal->CurrentChannel);
1260 hal->bSwChnl = _FALSE;
1261
1262 if (!ret) {
1263 RTW_INFO("%s: config_phydm_switch_channel_8822b fail\n", __FUNCTION__);
1264 rtw_warn_on(1);
1265 return;
1266 }
1267 }
1268
1269 /* 3. set Bandwidth register */
1270 if (hal->bSetChnlBW) {
1271 /* get primary channel index */
1272 u8 pri_ch_idx = get_pri_ch_id(adapter);
1273
1274 /* 3.1 set MAC register */
1275 mac_switch_bandwidth(adapter, pri_ch_idx);
1276
1277 /* 3.2 set BB/RF registet */
1278 ret = config_phydm_switch_bandwidth_8822b(pDM_Odm, pri_ch_idx, hal->CurrentChannelBW);
1279 hal->bSetChnlBW = _FALSE;
1280
1281 if (!ret) {
1282 RTW_INFO("%s: config_phydm_switch_bandwidth_8822b fail\n", __FUNCTION__);
1283 rtw_warn_on(1);
1284 return;
1285 }
1286 }
1287
1288 /* TX Power Setting */
1289 ODM_ClearTxPowerTrackingState(pDM_Odm);
1290 rtw_hal_set_tx_power_level(adapter, hal->CurrentChannel);
1291
1292 /* IQK */
1293 if ((hal->bNeedIQK == _TRUE)
1294 || (adapter->registrypriv.mp_mode == 1)) {
1295 PHY_IQCalibrate_8822B(pDM_Odm, _FALSE);
1296 hal->bNeedIQK = _FALSE;
1297 }
1298 }
1299
1300 /*
1301 * Description:
1302 * Store channel setting to hal date
1303 * Parameters:
1304 * bSwitchChannel swith channel or not
1305 * bSetBandWidth set band or not
1306 * ChannelNum center channel
1307 * ChnlWidth bandwidth
1308 * ChnlOffsetOf40MHz channel offset for 40MHz Bandwidth
1309 * ChnlOffsetOf80MHz channel offset for 80MHz Bandwidth
1310 * CenterFrequencyIndex1 center channel index
1311 */
1312
rtl8822b_handle_sw_chnl_and_set_bw(PADAPTER Adapter,u8 bSwitchChannel,u8 bSetBandWidth,u8 ChannelNum,CHANNEL_WIDTH ChnlWidth,u8 ChnlOffsetOf40MHz,u8 ChnlOffsetOf80MHz,u8 CenterFrequencyIndex1)1313 void rtl8822b_handle_sw_chnl_and_set_bw(
1314 PADAPTER Adapter, u8 bSwitchChannel, u8 bSetBandWidth,
1315 u8 ChannelNum, CHANNEL_WIDTH ChnlWidth, u8 ChnlOffsetOf40MHz,
1316 u8 ChnlOffsetOf80MHz, u8 CenterFrequencyIndex1)
1317 {
1318 PADAPTER pDefAdapter = GetDefaultAdapter(Adapter);
1319 PHAL_DATA_TYPE hal = GET_HAL_DATA(pDefAdapter);
1320 u8 tmpChannel = hal->CurrentChannel;
1321 CHANNEL_WIDTH tmpBW = hal->CurrentChannelBW;
1322 u8 tmpnCur40MhzPrimeSC = hal->nCur40MhzPrimeSC;
1323 u8 tmpnCur80MhzPrimeSC = hal->nCur80MhzPrimeSC;
1324 u8 tmpCenterFrequencyIndex1 = hal->CurrentCenterFrequencyIndex1;
1325 struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv;
1326
1327
1328 /* check swchnl or setbw */
1329 if (!bSwitchChannel && !bSetBandWidth) {
1330 RTW_INFO("%s: not switch channel and not set bandwidth\n", __FUNCTION__);
1331 return;
1332 }
1333
1334 /* skip switch channel operation for current channel & ChannelNum(will be switch) are the same */
1335 if (bSwitchChannel) {
1336 if (hal->CurrentChannel != ChannelNum) {
1337 if (HAL_IsLegalChannel(Adapter, ChannelNum))
1338 hal->bSwChnl = _TRUE;
1339 else
1340 return;
1341 }
1342 }
1343
1344 /* check set BandWidth */
1345 if (bSetBandWidth) {
1346 /* initial channel bw setting */
1347 if (hal->bChnlBWInitialized == _FALSE) {
1348 hal->bChnlBWInitialized = _TRUE;
1349 hal->bSetChnlBW = _TRUE;
1350 } else if ((hal->CurrentChannelBW != ChnlWidth) || /* check whether need set band or not */
1351 (hal->nCur40MhzPrimeSC != ChnlOffsetOf40MHz) ||
1352 (hal->nCur80MhzPrimeSC != ChnlOffsetOf80MHz) ||
1353 (hal->CurrentCenterFrequencyIndex1 != CenterFrequencyIndex1))
1354 hal->bSetChnlBW = _TRUE;
1355 }
1356
1357 /* return if not need set bandwidth nor channel after check*/
1358 if (!hal->bSetChnlBW && !hal->bSwChnl)
1359 return;
1360
1361 /* set channel number to hal data */
1362 if (hal->bSwChnl) {
1363 hal->CurrentChannel = ChannelNum;
1364 hal->CurrentCenterFrequencyIndex1 = ChannelNum;
1365 }
1366
1367 /* set bandwidth info to hal data */
1368 if (hal->bSetChnlBW) {
1369 hal->CurrentChannelBW = ChnlWidth;
1370 hal->nCur40MhzPrimeSC = ChnlOffsetOf40MHz;
1371 hal->nCur80MhzPrimeSC = ChnlOffsetOf80MHz;
1372 hal->CurrentCenterFrequencyIndex1 = CenterFrequencyIndex1;
1373 }
1374
1375 /* switch channel & bandwidth */
1376 if (!RTW_CANNOT_RUN(Adapter))
1377 rtl8822b_switch_chnl_and_set_bw(Adapter);
1378 else {
1379 if (hal->bSwChnl) {
1380 hal->CurrentChannel = tmpChannel;
1381 hal->CurrentCenterFrequencyIndex1 = tmpChannel;
1382 }
1383
1384 if (hal->bSetChnlBW) {
1385 hal->CurrentChannelBW = tmpBW;
1386 hal->nCur40MhzPrimeSC = tmpnCur40MhzPrimeSC;
1387 hal->nCur80MhzPrimeSC = tmpnCur80MhzPrimeSC;
1388 hal->CurrentCenterFrequencyIndex1 = tmpCenterFrequencyIndex1;
1389 }
1390 }
1391 }
1392
1393 /*
1394 * Description:
1395 * Change bandwidth, current channel is the same
1396 * Parameters:
1397 * bw bandwidth
1398 * offset channel offset for 40MHz or 80MHz Bandwidth according to bw
1399 */
rtl8822b_set_bw_mode(PADAPTER adapter,CHANNEL_WIDTH bw,u8 offset)1400 void rtl8822b_set_bw_mode(PADAPTER adapter, CHANNEL_WIDTH bw, u8 offset)
1401 {
1402 PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
1403
1404 rtl8822b_handle_sw_chnl_and_set_bw(adapter, _FALSE, _TRUE, hal->CurrentChannel, bw, offset, offset, hal->CurrentChannel);
1405 }
1406
1407 /*
1408 * Description:
1409 * Change channel, and bandwidth & offset are not changed
1410 * Parameters:
1411 * center_ch center channel
1412 */
rtl8822b_set_channel(PADAPTER adapter,u8 center_ch)1413 void rtl8822b_set_channel(PADAPTER adapter, u8 center_ch)
1414 {
1415 PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
1416
1417 rtl8822b_handle_sw_chnl_and_set_bw(adapter, _TRUE, _FALSE, center_ch, 0, 0, 0, center_ch);
1418 }
1419
1420 /*
1421 * Description:
1422 * Change channel, bandwidth & offset
1423 * Parameters:
1424 * center_ch center channel
1425 * bw bandwidth
1426 * offset40 channel offset for 40MHz Bandwidth
1427 * offset80 channel offset for 80MHz Bandwidth
1428 */
rtl8822b_set_channel_bw(PADAPTER adapter,u8 center_ch,CHANNEL_WIDTH bw,u8 offset40,u8 offset80)1429 void rtl8822b_set_channel_bw(PADAPTER adapter, u8 center_ch, CHANNEL_WIDTH bw, u8 offset40, u8 offset80)
1430 {
1431 rtl8822b_handle_sw_chnl_and_set_bw(adapter, _TRUE, _TRUE, center_ch, bw, offset40, offset80, center_ch);
1432 }
1433
rtl8822b_notch_filter_switch(PADAPTER adapter,bool enable)1434 void rtl8822b_notch_filter_switch(PADAPTER adapter, bool enable)
1435 {
1436 if (enable)
1437 RTW_INFO("%s: Enable notch filter\n", __FUNCTION__);
1438 else
1439 RTW_INFO("%s: Disable notch filter\n", __FUNCTION__);
1440 }
1441
1442 #ifdef CONFIG_MP_INCLUDED
1443 /*
1444 * Description:
1445 * Config RF path
1446 *
1447 * Parameters:
1448 * adapter pointer of struct _ADAPTER
1449 */
rtl8822b_mp_config_rfpath(PADAPTER adapter)1450 void rtl8822b_mp_config_rfpath(PADAPTER adapter)
1451 {
1452 PHAL_DATA_TYPE hal;
1453 PMPT_CONTEXT mpt;
1454 ANTENNA_PATH anttx, antrx;
1455 ODM_RF_PATH_E rxant;
1456
1457
1458 hal = GET_HAL_DATA(adapter);
1459 mpt = &adapter->mppriv.MptCtx;
1460 anttx = hal->AntennaTxPath;
1461 antrx = hal->AntennaRxPath;
1462 hal->antenna_test = _TRUE;
1463 RTW_INFO("+Config RF Path, tx=0x%x rx=0x%x\n", anttx, antrx);
1464
1465 switch (anttx) {
1466 case ANTENNA_A:
1467 mpt->MptRfPath = ODM_RF_A;
1468 break;
1469 case ANTENNA_B:
1470 mpt->MptRfPath = ODM_RF_B;
1471 break;
1472 case ANTENNA_AB:
1473 default:
1474 mpt->MptRfPath = ODM_RF_A | ODM_RF_B;
1475 break;
1476 }
1477
1478 switch (antrx) {
1479 case ANTENNA_A:
1480 rxant = ODM_RF_A;
1481 break;
1482 case ANTENNA_B:
1483 rxant = ODM_RF_B;
1484 break;
1485 case ANTENNA_AB:
1486 default:
1487 rxant = ODM_RF_A | ODM_RF_B;
1488 break;
1489 }
1490
1491 config_phydm_trx_mode_8822b(GET_PDM_ODM(adapter), mpt->MptRfPath, rxant, FALSE);
1492
1493 RTW_INFO("-Config RF Path Finish\n");
1494 }
1495 #endif /* CONFIG_MP_INCLUDED */
1496
1497 #ifdef CONFIG_BEAMFORMING
rtl8822b_phy_init_beamforming(PADAPTER adapter)1498 void rtl8822b_phy_init_beamforming(PADAPTER adapter)
1499 {
1500 u8 v8;
1501 u32 v32;
1502
1503 v32 = rtw_read32(adapter, 0x14c0);
1504 /* Enable P1 aggr new packet according to P0 transfer time */
1505 v32 |= BIT(16);
1506 /* MU Retry Limit */
1507 v32 = (v32 & 0xFFFF0FFF) | 0xA000;
1508 /*Disable Tx MU-MIMO until sounding done*/
1509 v32 &= ~BIT(7);
1510 /* Clear validity of MU STAs */
1511 v32 &= 0xFFFFFFC0;
1512 rtw_write32(adapter, 0x14C0, v32);
1513
1514 /* MU-MIMO Option as default value */
1515 rtw_write8(adapter, 0x167C, 0x70);
1516 /*MU-MIMO Control as default value*/
1517 rtw_write16(adapter, 0x1680, 0);
1518
1519 /* Set MU NDPA rate & BW source */
1520 /* 0x42C[30] = 1 (0: from Tx desc, 1: from 0x45F) */
1521 v8 = rtw_read8(adapter, REG_TXBF_CTRL_8822B);
1522 v8 |= BIT(6);
1523 rtw_write8(adapter, REG_TXBF_CTRL_8822B, v8);
1524 /* 0x45F[7:0] = 0x10 (Rate=OFDM_6M, BW20) */
1525 rtw_write8(adapter, REG_NDPA_OPT_CTRL_8822B, 0x10);
1526
1527 /* Temp Settings */
1528 /* STA2's CSI rate is fixed at 6M */
1529 v8 = rtw_read8(adapter, 0x6DF);
1530 v8 = (v8 & 0xC0) | 0x4;
1531 rtw_write8(adapter, 0x6DF, v8);
1532 /* Grouping bitmap parameters */
1533 rtw_write32(adapter, 0x1C94, 0xAFFFAFFF);
1534 }
1535
_setbeamformrfmode(PADAPTER adapter,u8 cnt_bfee_su,u8 cnt_bfee_mu,u8 idx)1536 static void _setbeamformrfmode(PADAPTER adapter, u8 cnt_bfee_su, u8 cnt_bfee_mu, u8 idx)
1537 {
1538 BEAMFORMING_CAP bf_cap = BEAMFORMING_CAP_NONE;
1539
1540
1541 if (GET_RF_TYPE(adapter) == RF_1T1R)
1542 return;
1543
1544 /* RF Mode table write enable */
1545 PHY_SetRFReg(adapter, ODM_RF_PATH_A, RF_WeLut_Jaguar, 0x80000, 0x1);
1546 PHY_SetRFReg(adapter, ODM_RF_PATH_B, RF_WeLut_Jaguar, 0x80000, 0x1);
1547
1548 if (cnt_bfee_su || cnt_bfee_mu) {
1549 /* Path_A */
1550 /* Select RX mode */
1551 PHY_SetRFReg(adapter, ODM_RF_PATH_A, RF_ModeTableAddr, 0xfffff, 0x18000);
1552 /* Set Table data */
1553 PHY_SetRFReg(adapter, ODM_RF_PATH_A, RF_ModeTableData0, 0xfffff, 0xBE77F);
1554 /* Enable TXIQGEN in RX mode */
1555 PHY_SetRFReg(adapter, ODM_RF_PATH_A, RF_ModeTableData1, 0xfffff, 0x226BF);
1556 /* Path_B */
1557 /* Select RX mode */
1558 PHY_SetRFReg(adapter, ODM_RF_PATH_B, RF_ModeTableAddr, 0xfffff, 0x18000);
1559 /* Set Table data */
1560 PHY_SetRFReg(adapter, ODM_RF_PATH_B, RF_ModeTableData0, 0xfffff, 0xBE77F);
1561 /* Enable TXIQGEN in RX mode */
1562 PHY_SetRFReg(adapter, ODM_RF_PATH_B, RF_ModeTableData1, 0xfffff, 0x226BF);
1563
1564 /* Enable TXIQGEN in RX mode */
1565 PHY_SetRFReg(adapter, ODM_RF_PATH_A, RF_ModeTableData1, 0xfffff, 0xE26BF);
1566 }
1567
1568 /* RF Mode table write disable */
1569 PHY_SetRFReg(adapter, ODM_RF_PATH_A, RF_WeLut_Jaguar, 0x80000, 0x0);
1570 PHY_SetRFReg(adapter, ODM_RF_PATH_B, RF_WeLut_Jaguar, 0x80000, 0x0);
1571
1572 if (cnt_bfee_su) {
1573 /* enable BB TxBF ant mapping register */
1574 PHY_SetBBReg(adapter, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(28)|BIT(29), 0x2);
1575
1576 if (idx == 0) {
1577 /* Nsts = 2, AB */
1578 PHY_SetBBReg(adapter, REG_BB_TXBF_ANT_SET_BF0_8822B, 0xffff, 0x0433);
1579 PHY_SetBBReg(adapter, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x043);
1580 /*PHY_SetBBReg(adapter, REG_BB_TX_PATH_SEL_2_8822B, bMaskLWord, 0x430);*/
1581
1582 } else { /* idx = 1 */
1583 PHY_SetBBReg(adapter, REG_BB_TXBF_ANT_SET_BF1_8822B, 0xffff, 0x0433);
1584 PHY_SetBBReg(adapter, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x043);
1585 /*PHY_SetBBReg(adapter, REG_BB_TX_PATH_SEL_2_8822B, bMaskLWord, 0x430;*/
1586 }
1587 } else {
1588 PHY_SetBBReg(adapter, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x1); /* 1SS by path-A */
1589 PHY_SetBBReg(adapter, REG_BB_TX_PATH_SEL_2_8822B, bMaskLWord, 0x430); /* 2SS by path-A,B */
1590 }
1591
1592 if (cnt_bfee_mu) {
1593 /* MU STAs share the common setting */
1594 PHY_SetBBReg(adapter, REG_BB_TXBF_ANT_SET_BF1_8822B, BIT(31), 1);
1595 PHY_SetBBReg(adapter, REG_BB_TXBF_ANT_SET_BF1_8822B, 0xffff, 0x0433);
1596 PHY_SetBBReg(adapter, REG_BB_TX_PATH_SEL_1_8822B, 0xfff00000, 0x043);
1597 }
1598 }
1599
_get_txbf_nrx(PADAPTER adapter)1600 static u8 _get_txbf_nrx(PADAPTER adapter)
1601 {
1602 u8 rf;
1603 u8 nrx = 0;
1604
1605
1606 rtw_hal_get_hwreg(adapter, HW_VAR_RF_TYPE, &rf);
1607 switch (rf) {
1608 case RF_1T1R:
1609 nrx = 0;
1610 break;
1611 default:
1612 case RF_1T2R:
1613 case RF_2T2R:
1614 nrx = 1;
1615 break;
1616 }
1617
1618 return nrx;
1619 }
1620
1621 typedef enum _HW_CFG_SOUNDING_TYPE {
1622 HW_CFG_SOUNDING_TYPE_SOUNDDOWN,
1623 HW_CFG_SOUNDING_TYPE_LEAVE,
1624 HW_CFG_SOUNDING_TYPE_RESET,
1625 HW_CFG_SOUNDING_TYPE_MAX
1626 } HW_CFG_SOUNDING_TYPE, *PHW_CFG_SOUNDING_TYPE;
1627
_config_sounding(PADAPTER adapter,struct beamformee_entry * entry,u8 mu_sounding,HW_CFG_SOUNDING_TYPE cfg_type)1628 static void _config_sounding(PADAPTER adapter, struct beamformee_entry *entry, u8 mu_sounding, HW_CFG_SOUNDING_TYPE cfg_type)
1629 {
1630 struct mlme_priv *mlme;
1631 struct beamforming_info *bf_info;
1632 u8 su_cnt, mu_cnt;
1633 u16 BeamCtrlVal;
1634 u32 BeamCtrlReg;
1635 u8 is_bitmap_ready = _FALSE;
1636 u16 bitmap;
1637 u8 gid, i, j, count = 0;
1638 u8 id1, id0;
1639 u32 gid_valid[6] = {0};
1640 u32 val32;
1641
1642
1643 mlme = &adapter->mlmepriv;
1644 bf_info = GET_BEAMFORM_INFO(adapter);
1645
1646 if (cfg_type == HW_CFG_SOUNDING_TYPE_RESET) {
1647 RTW_INFO("%s: HW_CFG_SOUNDING_TYPE_RESET\n", __FUNCTION__);
1648
1649 rtw_write8(adapter, REG_TXBF_CTRL_8822B+3, 0);
1650
1651 /* Clear all MU entry table */
1652 for (i = 0; i < MAX_BEAMFORMEE_ENTRY_NUM; i++) {
1653 entry = &bf_info->bfee_entry[i];
1654 for (i = 0; i < 8; i++)
1655 entry->gid_valid[i] = 0;
1656 }
1657
1658 val32 = rtw_read32(adapter, 0x14C0);
1659 for (i = 0; i < 6; i++) {
1660 val32 &= ~(BIT(8)|BIT(9)|BIT(10));
1661 val32 |= ((i<<8) & (BIT(8)|BIT(9)|BIT(10)));
1662 rtw_write32(adapter, 0x14C0, val32);
1663 /* set MU STA gid valid table */
1664 rtw_write32(adapter, 0x14C4, 0);
1665 }
1666
1667 /* Disable TxMU PPDU */
1668 val32 &= ~BIT(7);
1669 rtw_write32(adapter, 0x14C0, val32);
1670 } else {
1671 if (_FALSE == mu_sounding) {
1672 /* SU sounding */
1673 if ((check_fwstate(mlme, WIFI_ADHOC_STATE) == _TRUE)
1674 || (check_fwstate(mlme, WIFI_ADHOC_MASTER_STATE) == _TRUE))
1675 BeamCtrlVal = entry->mac_id;
1676 else
1677 BeamCtrlVal = entry->p_aid;
1678
1679 if (entry->su_reg_index == 0) {
1680 BeamCtrlReg = REG_TXBF_CTRL_8822B;
1681 } else {
1682 BeamCtrlReg = REG_TXBF_CTRL_8822B+2;
1683 BeamCtrlVal |= ((BIT_R_EN_NDPA_INT_8822B | BIT_USE_NDPA_PARAMETER_8822B | BIT_R_ENABLE_NDPA_8822B) >> 16);
1684 }
1685
1686 /* Current BFee sound down */
1687 if (entry->bDeleteSounding
1688 || (cfg_type == HW_CFG_SOUNDING_TYPE_LEAVE)) {
1689 RTW_INFO("%s: SU HW_CFG_SOUNDING_TYPE_LEAVE\n", __FUNCTION__);
1690 RTW_INFO("%s: Don't apply Vmatrix\n", __FUNCTION__);
1691 BeamCtrlVal &= ~(BIT(9)|BIT(10)|BIT(11));
1692 } else {
1693 if (entry->sound_bw == CHANNEL_WIDTH_20)
1694 BeamCtrlVal |= BIT(9);
1695 else if (entry->sound_bw == CHANNEL_WIDTH_40)
1696 BeamCtrlVal |= (BIT(9)|BIT(10));
1697 else if (entry->sound_bw == CHANNEL_WIDTH_80)
1698 BeamCtrlVal |= (BIT(9)|BIT(10)|BIT(11));
1699 }
1700
1701 rtw_write16(adapter, BeamCtrlReg, BeamCtrlVal);
1702 } else {
1703 /* MU sounding */
1704 if (cfg_type == HW_CFG_SOUNDING_TYPE_LEAVE) {
1705 RTW_INFO("%s: MU HW_CFG_SOUNDING_TYPE_LEAVE\n", __FUNCTION__);
1706
1707 /* Clear the entry table */
1708 val32 = rtw_read32(adapter, 0x14C0);
1709 if (TEST_FLAG(entry->cap, BEAMFORMEE_CAP_VHT_MU)) {
1710 for (i = 0; i < 8; i++)
1711 entry->gid_valid[i] = 0;
1712
1713 val32 &= ~(BIT(8)|BIT(9)|BIT(10));
1714 val32 |= ((i<<8) & (BIT(8)|BIT(9)|BIT(10)));
1715 rtw_write32(adapter, 0x14C0, val32);
1716 /* Set MU STA gid valid table */
1717 rtw_write32(adapter, 0x14C4, 0);
1718 } else {
1719 RTW_ERR("%s: ERROR! It is not an MU BFee entry!!\n", __FUNCTION__);
1720 }
1721
1722 if (bf_info->beamformee_su_cnt == 0) {
1723 /* Disable TxMU PPDU */
1724 val32 &= ~BIT(7);
1725 rtw_write32(adapter, 0x14C0, val32);
1726 }
1727 } else if (cfg_type == HW_CFG_SOUNDING_TYPE_SOUNDDOWN) {
1728 RTW_INFO("%s: MU HW_CFG_SOUNDING_TYPE_SOUNDDOWN\n", __FUNCTION__);
1729
1730 /* Update all MU entry table */
1731 do {
1732 /* Check BB GID bitmap ready */
1733 val32 = PHY_QueryBBReg(adapter, 0xF4C, 0xFFFF0000);
1734
1735 is_bitmap_ready = (val32 & BIT(15)) ? _TRUE : _FALSE;
1736 count++;
1737 rtw_udelay_os(5);
1738 } while ((_FALSE == is_bitmap_ready) && (count < 100));
1739
1740 bitmap = (u16)(val32 & 0x3FFF);
1741
1742 for (i = 0; i < 15; i++) {
1743 if (i < 5) {/*bit0~4*/
1744 id0 = 0;
1745 id1 = (u8)(i + 1);
1746 } else if (i < 9) { /*bit5~8*/
1747 id0 = 1;
1748 id1 = (u8)(i - 3);
1749 } else if (i < 12) { /*bit9~11*/
1750 id0 = 2;
1751 id1 = (u8)(i - 6);
1752 } else if (i < 14) { /*bit12~13*/
1753 id0 = 3;
1754 id1 = (u8)(i - 8);
1755 } else { /*bit14*/
1756 id0 = 4;
1757 id1 = (u8)(i - 9);
1758 }
1759 if (bitmap & BIT(i)) {
1760 /*Pair 1*/
1761 gid = (i << 1) + 1;
1762 gid_valid[id0] |= (BIT(gid));
1763 gid_valid[id1] |= (BIT(gid));
1764 /*Pair 2*/
1765 gid += 1;
1766 gid_valid[id0] |= (BIT(gid));
1767 gid_valid[id1] |= (BIT(gid));
1768 } else {
1769 /*Pair 1*/
1770 gid = (i << 1) + 1;
1771 gid_valid[id0] &= ~(BIT(gid));
1772 gid_valid[id1] &= ~(BIT(gid));
1773 /*Pair 2*/
1774 gid += 1;
1775 gid_valid[id0] &= ~(BIT(gid));
1776 gid_valid[id1] &= ~(BIT(gid));
1777 }
1778 }
1779
1780 for (i = 0; i < MAX_BEAMFORMEE_ENTRY_NUM; i++) {
1781 entry = &bf_info->bfee_entry[i];
1782 if (TEST_FLAG(entry->cap, BEAMFORMEE_CAP_VHT_MU)
1783 && (entry->mu_reg_index < 6)) {
1784 val32 = gid_valid[entry->mu_reg_index];
1785 for (j = 0; j < 4; j++) {
1786 entry->gid_valid[j] = (u8)(val32 & 0xFF);
1787 val32 >>= 8;
1788 }
1789 }
1790 }
1791
1792 val32 = rtw_read32(adapter, 0x14C0);
1793 for (i = 0; i < 6; i++) {
1794 val32 &= ~(BIT8|BIT9|BIT10);
1795 val32 |= ((i<<8) & (BIT8|BIT9|BIT10));
1796 rtw_write32(adapter, 0x14C0, val32);
1797 /* Set MU STA gid valid table */
1798 rtw_write32(adapter, 0x14C4, gid_valid[i]);
1799 }
1800
1801 /* Enable TxMU PPDU */
1802 val32 |= BIT(7);
1803 rtw_write32(adapter, 0x14C0, val32);
1804 }
1805 }
1806 }
1807 }
1808
rtl8822b_phy_sounding_enter(PADAPTER adapter,struct sta_info * sta)1809 void rtl8822b_phy_sounding_enter(PADAPTER adapter, struct sta_info *sta)
1810 {
1811 PHAL_DATA_TYPE hal;
1812 struct mlme_priv *mlme;
1813 struct beamforming_info *bf_info;
1814 struct beamformer_entry *bfer;
1815 struct beamformee_entry *bfee;
1816 u8 cnt_bfee_su = 0, cnt_bfee_mu = 0;
1817 u8 i = 0, idx;
1818 u32 csi_param;
1819 u16 p_aid = 0;
1820 /* MU */
1821 u8 nc_index = 0, nr_index = 0, grouping = 0, codebookinfo = 0, coefficientsize = 0;
1822 u32 gid_valid = 0, user_position_l = 0, user_position_h = 0;
1823 u32 mu_reg[6] = {0x1684, 0x1686, 0x1688, 0x168A, 0x168C, 0x168E};
1824 /* General */
1825 u8 val8;
1826 u16 val16;
1827 u32 val32;
1828
1829
1830 RTW_INFO("+%s\n", __FUNCTION__);
1831
1832 hal = GET_HAL_DATA(adapter);
1833 mlme = &adapter->mlmepriv;
1834 bf_info = GET_BEAMFORM_INFO(adapter);
1835
1836 bfee = beamforming_get_bfee_entry_by_addr(adapter, sta->hwaddr);
1837 bfer = beamforming_get_bfer_entry_by_addr(adapter, sta->hwaddr);
1838
1839 if (bfer) {
1840 bfer->state = BEAMFORM_ENTRY_HW_STATE_ADDING;
1841
1842 if (TEST_FLAG(bfer->cap, BEAMFORMER_CAP_VHT_MU)) {
1843 /* Config MU BFer entry */
1844 RTW_INFO("%s: Config MU BFer entry HW setting\n", __FUNCTION__);
1845
1846 /* Reset GID table */
1847 for (i = 0; i < 8; i++)
1848 bfer->gid_valid[i] = 0;
1849 for (i = 0; i < 16; i++)
1850 bfer->user_position[i] = 0;
1851
1852 /* Sounding protocol control */
1853 rtw_write8(adapter, REG_SND_PTCL_CTRL_8822B, 0xDB);
1854
1855 /* MAC address */
1856 for (i = 0; i < ETH_ALEN; i++)
1857 rtw_write8(adapter, REG_ASSOCIATED_BFMER0_INFO_8822B+i, bfer->mac_addr[i]);
1858
1859 /* Set partial AID */
1860 rtw_write16(adapter, REG_ASSOCIATED_BFMER0_INFO_8822B+6, bfer->p_aid);
1861
1862 /*
1863 * Fill our AID to 0x1680[11:0] and
1864 * [13:12] = 2b'00, BF report segement select to 3895 bytes
1865 */
1866 val16 = rtw_read16(adapter, 0x1680);
1867 val16 &= ~0x3FFF;
1868 val16 |= (bfer->aid & 0xFFF);
1869 rtw_write16(adapter, 0x1680, val16);
1870
1871 /* Set 80us for leaving ndp_rx_standby_state */
1872 rtw_write8(adapter, 0x71B, 0x50);
1873
1874 /* Set 0x6A0[14] = 1 to accept action_no_ack */
1875 val8 = rtw_read8(adapter, REG_RXFLTMAP0_8822B+1);
1876 val8 |= 0x40;
1877 rtw_write8(adapter, REG_RXFLTMAP0_8822B+1, val8);
1878
1879 /* Set 0x6A2[5:4] = 1 to NDPA and BF report poll */
1880 val8 = rtw_read8(adapter, REG_RXFLTMAP1_8822B);
1881 val8 |= 0x30;
1882 rtw_write8(adapter, REG_RXFLTMAP1_8822B, val8);
1883
1884 /* CSI report parameters of Beamformer */
1885 nc_index = _get_txbf_nrx(adapter);
1886 /*
1887 * 0x718[7] = 1 use Nsts
1888 * 0x718[7] = 0 use reg setting
1889 * As Bfee, we use Nsts, so nr_index don't care
1890 */
1891 nr_index = 1;
1892 grouping = 0; /* no grouping */
1893 codebookinfo = 1; /* 7 bit for psi, 9 bit for phi */
1894 coefficientsize = 0; /* This is nothing really matter */
1895 csi_param = (u16)((coefficientsize<<10)|(codebookinfo<<8)|(grouping<<6)|(nr_index<<3)|(nc_index));
1896 rtw_write16(adapter, REG_TX_CSI_RPT_PARAM_BW20_8822B, csi_param);
1897 RTW_INFO("%s: nc=%d nr=%d group=%d codebookinfo=%d coefficientsize=%d\n",
1898 __FUNCTION__, nc_index, nr_index, grouping, codebookinfo, coefficientsize);
1899 RTW_INFO("%s: csi=0x%04x\n", __FUNCTION__, csi_param);
1900
1901 /*for B-Cut*/
1902 PHY_SetBBReg(adapter, REG_RXFLTMAP0_8822B, BIT(20), 0);
1903 PHY_SetBBReg(adapter, REG_RXFLTMAP3_8822B, BIT(20), 0);
1904 } else if (TEST_FLAG(bfer->cap, BEAMFORMER_CAP_VHT_SU|BEAMFORMER_CAP_HT_EXPLICIT)) {
1905 /* Config SU BFer entry */
1906 RTW_INFO("%s: Config SU BFer entry HW setting.\n", __FUNCTION__);
1907
1908 /* Sounding protocol control */
1909 rtw_write8(adapter, REG_SND_PTCL_CTRL_8822B, 0xDB);
1910
1911 /* MAC address/Partial AID of Beamformer */
1912 if (bfer->su_reg_index == 0)
1913 for (i = 0; i < 6; i++)
1914 rtw_write8(adapter, (REG_ASSOCIATED_BFMER0_INFO_8822B+i), bfer->mac_addr[i]);
1915 else
1916 for (i = 0; i < 6; i++)
1917 rtw_write8(adapter, (REG_ASSOCIATED_BFMER1_INFO_8822B+i), bfer->mac_addr[i]);
1918
1919 /* CSI report parameters of Beamformer */
1920 nc_index = _get_txbf_nrx(adapter);
1921 /*
1922 * 0x718[7] = 1 use Nsts
1923 * 0x718[7] = 0 use reg setting
1924 * As Bfee, we use Nsts, so nr_index don't care
1925 */
1926 nr_index = bfer->NumofSoundingDim;
1927
1928 grouping = 0;
1929
1930 /* for ac = 1, for n = 3 */
1931 if (TEST_FLAG(bfer->cap, BEAMFORMER_CAP_VHT_SU))
1932 codebookinfo = 1;
1933 else if (TEST_FLAG(bfer->cap, BEAMFORMER_CAP_HT_EXPLICIT))
1934 codebookinfo = 3;
1935
1936 coefficientsize = 3;
1937
1938 csi_param = (u16)((coefficientsize<<10)|(codebookinfo<<8)|(grouping<<6)|(nr_index<<3)|(nc_index));
1939
1940 if (bfer->su_reg_index == 0)
1941 rtw_write16(adapter, REG_TX_CSI_RPT_PARAM_BW20_8822B, csi_param);
1942 else
1943 rtw_write16(adapter, REG_TX_CSI_RPT_PARAM_BW20_8822B+2, csi_param);
1944 /* ndp_rx_standby_timer */
1945 rtw_write8(adapter, REG_SND_PTCL_CTRL_8822B+3, 0x70);
1946 }
1947
1948 bfer->state = BEAMFORM_ENTRY_HW_STATE_ADDED;
1949 }
1950
1951 if (bfee) {
1952 bfee->state = BEAMFORM_ENTRY_HW_STATE_ADDING;
1953
1954 if (TEST_FLAG(bfee->cap, BEAMFORMEE_CAP_VHT_MU)) {
1955 idx = bfee->mu_reg_index;
1956 /* User position table */
1957 switch (idx) {
1958 case 0:
1959 gid_valid = 0x7fe;
1960 user_position_l = 0x111110;
1961 user_position_h = 0x0;
1962 break;
1963 case 1:
1964 gid_valid = 0x7f806;
1965 user_position_l = 0x11000004;
1966 user_position_h = 0x11;
1967 break;
1968 case 2:
1969 gid_valid = 0x1f81818;
1970 user_position_l = 0x400040;
1971 user_position_h = 0x11100;
1972 break;
1973 case 3:
1974 gid_valid = 0x1e186060;
1975 user_position_l = 0x4000400;
1976 user_position_h = 0x1100040;
1977 break;
1978 case 4:
1979 gid_valid = 0x66618180;
1980 user_position_l = 0x40004000;
1981 user_position_h = 0x10040400;
1982 break;
1983 case 5:
1984 gid_valid = 0x79860600;
1985 user_position_l = 0x40000;
1986 user_position_h = 0x4404004;
1987 break;
1988 }
1989
1990 for (i = 0; i < 8; i++) {
1991 if (i < 4) {
1992 bfee->gid_valid[i] = (u8)(gid_valid & 0xFF);
1993 gid_valid = (gid_valid >> 8);
1994 } else
1995 bfee->gid_valid[i] = 0;
1996 }
1997 for (i = 0; i < 16; i++) {
1998 if (i < 4)
1999 bfee->user_position[i] = (u8)((user_position_l >> (i*8)) & 0xFF);
2000 else if (i < 8)
2001 bfee->user_position[i] = (u8)((user_position_h >> ((i-4)*8)) & 0xFF);
2002 else
2003 bfee->user_position[i] = 0;
2004 }
2005
2006 /* Sounding protocol control */
2007 rtw_write8(adapter, REG_SND_PTCL_CTRL_8822B, 0xDB);
2008
2009 /* select MU STA table */
2010 val32 = rtw_read32(adapter, 0x14C0);
2011 val32 &= ~(BIT(8)|BIT(9)|BIT(10));
2012 val32 |= (idx << 8) & (BIT(8)|BIT(9)|BIT(10));
2013 rtw_write32(adapter, 0x14C0, val32);
2014
2015 /* Reset gid_valid table */
2016 rtw_write32(adapter, 0x14C4, 0);
2017 rtw_write32(adapter, 0x14C8 , user_position_l);
2018 rtw_write32(adapter, 0x14CC , user_position_h);
2019
2020 /* set validity of MU STAs */
2021 val32 &= 0xFFFFFFC0;
2022 val32 |= bf_info->beamformee_mu_reg_maping & 0x3F;
2023 rtw_write32(adapter, 0x14C0, val32);
2024
2025 RTW_INFO("%s: RegMUTxCtrl=0x%x, user_position_l=0x%x, user_position_h=0x%x\n",
2026 __FUNCTION__, val32, user_position_l, user_position_h);
2027
2028 val16 = rtw_read16(adapter, mu_reg[idx]);
2029 val16 &= 0xFE00; /* Clear PAID */
2030 val16 |= BIT(9); /* Enable MU BFee */
2031 val16 |= bfee->p_aid;
2032 rtw_write16(adapter, mu_reg[idx], val16);
2033 RTW_INFO("%s: Write mu_reg 0x%x = 0x%x\n",
2034 __FUNCTION__, mu_reg[idx], val16);
2035
2036 /* 0x42C[30] = 1 (0: from Tx desc, 1: from 0x45F) */
2037 val8 = rtw_read8(adapter, REG_TXBF_CTRL_8822B+3);
2038 val8 |= 0xD0; /* Set bit 28, 30, 31 to 3b'111 */
2039 rtw_write8(adapter, REG_TXBF_CTRL_8822B+3, val8);
2040 /* Set NDPA to 6M*/
2041 rtw_write8(adapter, REG_NDPA_RATE_8822B, 0x4); /* 6M */
2042
2043 val8 = rtw_read8(adapter, REG_NDPA_OPT_CTRL_8822B);
2044 val8 &= 0xFC; /* Clear bit 0, 1 */
2045 rtw_write8(adapter, REG_NDPA_OPT_CTRL_8822B, val8);
2046
2047 val32 = rtw_read32(adapter, REG_SND_PTCL_CTRL_8822B);
2048 val32 = ((val32 & 0xFF0000FF) | 0x020200); /* Set [23:8] to 0x0202 */
2049 rtw_write32(adapter, REG_SND_PTCL_CTRL_8822B, val32);
2050
2051 /* Set 0x6A0[14] = 1 to accept action_no_ack */
2052 val8 = rtw_read8(adapter, REG_RXFLTMAP0_8822B+1);
2053 val8 |= 0x40;
2054 rtw_write8(adapter, REG_RXFLTMAP0_8822B+1, val8);
2055 /* End of MAC registers setting */
2056
2057 _setbeamformrfmode(adapter, bf_info->beamformee_su_cnt, bf_info->beamformee_mu_cnt, 0);
2058
2059 /* <tynli_mark> <TODO> Need to set timer 2015.12.23 */
2060 /* Special for plugfest */
2061 rtw_mdelay_os(50); /* wait for 4-way handshake ending */
2062 beamforming_send_vht_gid_mgnt_packet(adapter, bfee);
2063
2064 #if 1 /* Fix rate. <tynli_note> Do we need to keep this action? */
2065 /* Set Ctrl Info */
2066 rtw_write16(adapter, 0x140, 0x660);
2067
2068 /* Reset Ctrl Info */
2069 val32 = 0x8000 + 32 * bfee->mac_id;
2070 for (i = 0; i < 8; i++)
2071 rtw_write32(adapter, val32 + i*4, 0);
2072
2073 rtw_write32(adapter, val32, (idx + 1) << 16);
2074 rtw_write8(adapter, 0x81, 0x80); /* RPTBUF ready */
2075
2076 RTW_INFO("%s: mac_id=%d, ctrl_info_offset=0x%x, mu_reg_index=%x\n",
2077 __FUNCTION__, bfee->mac_id, val32, idx);
2078 #endif
2079 } else if (TEST_FLAG(bfee->cap, BEAMFORMEE_CAP_VHT_SU|BEAMFORMEE_CAP_HT_EXPLICIT)) {
2080 RTW_INFO("%s: Config SU BFee entry HW setting\n", __FUNCTION__);
2081
2082 idx = bfee->su_reg_index;
2083
2084 if ((check_fwstate(mlme, WIFI_ADHOC_STATE) == _TRUE)
2085 || (check_fwstate(mlme, WIFI_ADHOC_MASTER_STATE) == _TRUE))
2086 p_aid = bfee->mac_id;
2087 else
2088 p_aid = bfee->p_aid;
2089
2090 _setbeamformrfmode(adapter, bf_info->beamformee_su_cnt, bf_info->beamformee_mu_cnt, idx);
2091
2092 /* P_AID of Beamformee & enable NDPA transmission & enable NDPA interrupt */
2093 if (idx == 0) {
2094 rtw_write16(adapter, REG_TXBF_CTRL_8822B, p_aid);
2095 val8 = rtw_read8(adapter, REG_TXBF_CTRL_8822B+3);
2096 val8 |= ((BIT_R_EN_NDPA_INT_8822B | BIT_USE_NDPA_PARAMETER_8822B | BIT_R_ENABLE_NDPA_8822B) >> 24);
2097 rtw_write8(adapter, REG_TXBF_CTRL_8822B+3, val8);
2098 } else {
2099 val16 = p_aid;
2100 val16 |= ((BIT_R_EN_NDPA_INT_8822B | BIT_USE_NDPA_PARAMETER_8822B | BIT_R_ENABLE_NDPA_8822B) >> 16);
2101 rtw_write16(adapter, REG_TXBF_CTRL_8822B+2, val16);
2102 }
2103
2104 /* CSI report parameters of Beamformee */
2105 if (idx == 0) {
2106 /* Get BIT24 & BIT(25)=BIT_TXUSER_ID1_8822B */
2107 val8 = rtw_read8(adapter, REG_ASSOCIATED_BFMEE_SEL_8822B+3) & 0x3;
2108 val8 |= 0x60;
2109 rtw_write8(adapter, REG_ASSOCIATED_BFMEE_SEL_8822B+3, val8);
2110
2111 val16 = p_aid | BIT_TXUSER_ID0_8822B;
2112 rtw_write16(adapter, REG_ASSOCIATED_BFMEE_SEL_8822B, val16);
2113 } else {
2114 /* Set BIT(25)=BIT_TXUSER_ID1_8822B */
2115 val16 = p_aid | 0xE200;
2116 rtw_write16(adapter, REG_ASSOCIATED_BFMEE_SEL_8822B+2, val16);
2117 }
2118 }
2119
2120 bfee->state = BEAMFORM_ENTRY_HW_STATE_ADDED;
2121 }
2122
2123 RTW_INFO("-%s\n", __FUNCTION__);
2124 }
2125
rtl8822b_phy_sounding_leave(PADAPTER adapter,u8 * addr)2126 void rtl8822b_phy_sounding_leave(PADAPTER adapter, u8 *addr)
2127 {
2128 PHAL_DATA_TYPE hal;
2129 struct beamforming_info *bf_info;
2130 struct beamformer_entry *bfer_entry;
2131 struct beamformee_entry *bfee_entry;
2132 u8 cnt_bfee_su = 0, cnt_bfee_mu = 0;
2133 u8 i = 0, idx;
2134 u16 p_aid = 0;
2135 /* MU */
2136 u32 gid_valid, user_position_l, user_position_h;
2137 u32 mu_reg[6] = {0x1684, 0x1686, 0x1688, 0x168a, 0x168c, 0x168e};
2138 /* General */
2139 u8 val8;
2140 u16 val16;
2141 u32 val32;
2142
2143
2144 RTW_INFO("+%s\n", __FUNCTION__);
2145
2146 hal = GET_HAL_DATA(adapter);
2147 bf_info = GET_BEAMFORM_INFO(adapter);
2148
2149 bfee_entry = beamforming_get_bfee_entry_by_addr(adapter, addr);
2150 bfer_entry = beamforming_get_bfer_entry_by_addr(adapter, addr);
2151
2152 /* Clear P_AID of Beamformee */
2153 /* Clear MAC address of Beamformer */
2154 /* Clear Associated Bfmee Sel */
2155 if (bfer_entry) {
2156 bfer_entry->state = BEAMFORM_ENTRY_HW_STATE_DELETING;
2157
2158 rtw_write8(adapter, REG_SND_PTCL_CTRL_8822B, 0xD8);
2159
2160 if (TEST_FLAG(bfer_entry->cap, BEAMFORMER_CAP_VHT_MU)) {
2161 /* MU BFer entry */
2162 /* Clear validity of MU STA0 and MU STA1*/
2163 val32 = rtw_read32(adapter, 0x14C0);
2164 val32 &= 0xFFFFFFC0;
2165 rtw_write32(adapter, 0x14C0, val32);
2166
2167 RTW_INFO("%s: Clear MU BFer entry HW setting\n", __FUNCTION__);
2168 } else if (TEST_FLAG(bfer_entry->cap, BEAMFORMEE_CAP_VHT_SU|BEAMFORMEE_CAP_HT_EXPLICIT)) {
2169 /* SU BFer entry */
2170 idx = bfer_entry->su_reg_index;
2171 if (idx == 0) {
2172 rtw_write32(adapter, REG_ASSOCIATED_BFMER0_INFO_8822B, 0);
2173 rtw_write16(adapter, REG_ASSOCIATED_BFMER0_INFO_8822B+4, 0);
2174 rtw_write16(adapter, REG_TX_CSI_RPT_PARAM_BW20_8822B, 0);
2175 } else {
2176 rtw_write32(adapter, REG_ASSOCIATED_BFMER1_INFO_8822B, 0);
2177 rtw_write16(adapter, REG_ASSOCIATED_BFMER1_INFO_8822B+4, 0);
2178 rtw_write16(adapter, REG_TX_CSI_RPT_PARAM_BW20_8822B+2, 0);
2179 }
2180
2181 bf_info->beamformer_su_reg_maping &= ~BIT(idx);
2182 bfer_entry->su_reg_index = 0xFF;
2183
2184 RTW_INFO("%s: Clear SU BFer entry HW setting\n", __FUNCTION__);
2185 }
2186
2187 bfer_entry->used = _FALSE;
2188 bfer_entry->state = BEAMFORM_ENTRY_HW_STATE_NONE;
2189 bfer_entry->cap = BEAMFORMING_CAP_NONE;
2190 }
2191
2192 if (bfee_entry) {
2193 bfee_entry->state = BEAMFORM_ENTRY_HW_STATE_DELETING;
2194
2195 _setbeamformrfmode(adapter, bf_info->beamformee_su_cnt, bf_info->beamformee_mu_cnt, bfee_entry->su_reg_index);
2196
2197 if (TEST_FLAG(bfee_entry->cap, BEAMFORMER_CAP_VHT_MU)) {
2198 /*MU BFee */
2199 idx = bfee_entry->mu_reg_index;
2200
2201 /* Disable sending NDPA & BF-rpt-poll to this BFee */
2202 rtw_write16(adapter, mu_reg[idx] , 0);
2203 /* Set validity of MU STA */
2204 val32 = rtw_read32(adapter, 0x14C0);
2205 val32 &= ~(BIT(idx));
2206 rtw_write32(adapter, 0x14C0, val32);
2207
2208 /* Force disable sounding config */
2209 _config_sounding(adapter, bfee_entry, _TRUE, HW_CFG_SOUNDING_TYPE_LEAVE);
2210
2211 bf_info->beamformee_mu_reg_maping &= ~BIT(idx);
2212 bfee_entry->mu_reg_index = 0xFF;
2213
2214 RTW_INFO("%s: Clear MU BFee entry HW setting\n", __FUNCTION__);
2215 } else if (TEST_FLAG(bfee_entry->cap, BEAMFORMER_CAP_VHT_SU|BEAMFORMER_CAP_HT_EXPLICIT)) {
2216 /* SU BFee */
2217 idx = bfee_entry->su_reg_index;
2218
2219 if (idx == 0) {
2220 rtw_write16(adapter, REG_TXBF_CTRL_8822B, 0x0);
2221 val8 = rtw_read8(adapter, REG_TXBF_CTRL_8822B+3);
2222 val8 |= ((BIT_R_EN_NDPA_INT_8822B | BIT_USE_NDPA_PARAMETER_8822B | BIT_R_ENABLE_NDPA_8822B) >> 24);
2223 rtw_write8(adapter, REG_TXBF_CTRL_8822B+3, val8);
2224 rtw_write16(adapter, REG_ASSOCIATED_BFMEE_SEL_8822B, 0);
2225 } else {
2226 val16 = 0x0;
2227 val16 |= ((BIT_R_EN_NDPA_INT_8822B | BIT_USE_NDPA_PARAMETER_8822B | BIT_R_ENABLE_NDPA_8822B) >> 16);
2228 rtw_write16(adapter, REG_TXBF_CTRL_8822B+2, val16);
2229
2230 val16 = rtw_read16(adapter, REG_ASSOCIATED_BFMEE_SEL_8822B+2);
2231 val16 &= 0x60;
2232 rtw_write16(adapter, REG_ASSOCIATED_BFMEE_SEL_8822B+2, val16);
2233 }
2234
2235 /* Force disable sounding config */
2236 _config_sounding(adapter, bfee_entry, _FALSE, HW_CFG_SOUNDING_TYPE_LEAVE);
2237
2238 bf_info->beamformee_su_reg_maping &= ~BIT(idx);
2239 bfee_entry->su_reg_index = 0xFF;
2240
2241 RTW_INFO("%s: Clear SU BFee entry HW setting\n", __FUNCTION__);
2242 }
2243 }
2244
2245 RTW_INFO("-%s\n", __FUNCTION__);
2246 }
2247
rtl8822b_phy_sounding_set_gid_table(PADAPTER adapter,struct beamformer_entry * bfer)2248 void rtl8822b_phy_sounding_set_gid_table(PADAPTER adapter, struct beamformer_entry *bfer)
2249 {
2250 struct beamforming_info *bf_info;
2251 u32 beamctrlreg;
2252 u16 beamctrlval;
2253 /* MU */
2254 u32 gid_valid, user_position_l, user_position_h;
2255 u32 mu_reg[6] = {0x1684, 0x1686, 0x1688, 0x168a, 0x168c, 0x168e};
2256 /* General */
2257 u8 val8;
2258 u16 val16;
2259 u32 val32;
2260 int i;
2261
2262
2263 bf_info = GET_BEAMFORM_INFO(adapter);
2264
2265 /* For GID 0~31 */
2266 gid_valid = 0;
2267 user_position_l = 0;
2268 user_position_h = 0;
2269 for (i = 0; i < 4; i++)
2270 gid_valid |= (bfer->gid_valid[i] << (i << 3));
2271 for (i = 0; i < 8; i++) {
2272 if (i < 4)
2273 user_position_l |= (bfer->user_position[i] << (i << 3));
2274 else
2275 user_position_h |= (bfer->user_position[i] << ((i - 4) << 3));
2276 }
2277 /* select MU STA0 table */
2278 val32 = rtw_read32(adapter, 0x14C0);
2279 val32 &= ~(BIT(8)|BIT(9)|BIT(10));
2280 rtw_write32(adapter, 0x14C0, val32);
2281 rtw_write32(adapter, 0x14C4, gid_valid);
2282 rtw_write32(adapter, 0x14C8, user_position_l);
2283 rtw_write32(adapter, 0x14CC, user_position_h);
2284
2285 RTW_INFO("%s: STA0: gid_valid=0x%x, user_position_l=0x%x, user_position_h=0x%x\n",
2286 __FUNCTION__, gid_valid, user_position_l, user_position_h);
2287
2288 /* For GID 32~64 */
2289 gid_valid = 0;
2290 user_position_l = 0;
2291 user_position_h = 0;
2292 for (i = 4; i < 8; i++)
2293 gid_valid |= (bfer->gid_valid[i] << ((i - 4)<<3));
2294 for (i = 8; i < 16; i++) {
2295 if (i < 12)
2296 user_position_l |= (bfer->user_position[i] << ((i - 8) << 3));
2297 else
2298 user_position_h |= (bfer->user_position[i] << ((i - 12) << 3));
2299 }
2300 /* select MU STA1 table */
2301 val32 = rtw_read32(adapter, 0x14C0);
2302 val32 &= ~(BIT(8)|BIT(9)|BIT(10));
2303 val32 |= BIT(8);
2304 rtw_write32(adapter, 0x14C0, val32);
2305 rtw_write32(adapter, 0x14C4, gid_valid);
2306 rtw_write32(adapter, 0x14C8, user_position_l);
2307 rtw_write32(adapter, 0x14CC, user_position_h);
2308
2309 RTW_INFO("%s: STA1: gid_valid=0x%x, user_position_l=0x%x, user_position_h=0x%x\n",
2310 __FUNCTION__, gid_valid, user_position_l, user_position_h);
2311
2312 /* Set validity of MU STA0 and MU STA1 */
2313 val32 = rtw_read32(adapter, 0x14C0);
2314 val32 &= 0xFFFFFFC0;
2315 val32 |= 0x3; /* STA0, STA1 */
2316 rtw_write32(adapter, 0x14C0, val32);
2317 }
2318 #endif /* CONFIG_BEAMFORMING */
2319
2320