1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 *****************************************************************************/
15 #define _SDIO_HALINIT_C_
16
17 #include <rtl8703b_hal.h>
18 #include "hal_com_h2c.h"
19
20 /*
21 * Description:
22 * Call power on sequence to enable card
23 *
24 * Return:
25 * _SUCCESS enable success
26 * _FAIL enable fail
27 */
CardEnable(PADAPTER padapter)28 static u8 CardEnable(PADAPTER padapter)
29 {
30 u8 bMacPwrCtrlOn;
31 u8 ret = _FAIL;
32
33
34 bMacPwrCtrlOn = _FALSE;
35 rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
36 if (bMacPwrCtrlOn == _FALSE) {
37 /* RSV_CTRL 0x1C[7:0] = 0x00 */
38 /* unlock ISO/CLK/Power control register */
39 rtw_write8(padapter, REG_RSV_CTRL, 0x0);
40
41 ret = HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, rtl8703B_card_enable_flow);
42 if (ret == _SUCCESS) {
43 u8 bMacPwrCtrlOn = _TRUE;
44 rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
45 }
46 } else
47 ret = _SUCCESS;
48
49 return ret;
50 }
51
52 /* static */
_InitPowerOn_8703BS(PADAPTER padapter)53 u32 _InitPowerOn_8703BS(PADAPTER padapter)
54 {
55 u8 value8;
56 u16 value16;
57 u32 value32;
58 u8 ret;
59 u8 pwron_chk_cnt = 0;
60 /* u8 bMacPwrCtrlOn; */
61
62 _init_power_on:
63
64 #if 1
65 /* all of these MUST be configured before power on */
66 #ifdef CONFIG_XTAL_26M
67 /* Config PLL Reference CLK, */
68 /* Change crystal to 26M, APLL_FREF_SEL = 4b'0101 */
69 /* APLL_FREF_SEL[0]=1b'1 */
70 value8 = rtw_read8(padapter, REG_AFE_PLL_CTRL);
71 value8 |= BIT(2);
72 rtw_write8(padapter, REG_AFE_PLL_CTRL, value8);
73 /* APLL_FREF_SEL[2:1]=2b'10 */
74 value8 = rtw_read8(padapter, REG_AFE_CTRL_4_8703B + 1);
75 value8 &= ~(BIT(1) | BIT(0));
76 value8 |= BIT(1);
77 rtw_write16(padapter, REG_AFE_CTRL_4_8703B + 1, value8);
78 /* APLL_FREF_SEL[3]=1b'0 */
79 value8 = rtw_read8(padapter, REG_AFE_CTRL_4_8703B);
80 value8 &= ~BIT(7);
81 rtw_write16(padapter, REG_AFE_CTRL_4_8703B, value8);
82 #endif /* CONFIG_XTAL_26M */
83
84 #ifdef CONFIG_EXT_CLK
85 /* Use external crystal(XTAL) */
86 value8 = rtw_read8(padapter, REG_PAD_CTRL1_8703B + 2);
87 value8 |= BIT(7);
88 rtw_write8(padapter, REG_PAD_CTRL1_8703B + 2, value8);
89
90 /* CLK_REQ High active or Low Active */
91 /* Request GPIO polarity: */
92 /* 0: low active */
93 /* 1: high active */
94 value8 = rtw_read8(padapter, REG_MULTI_FUNC_CTRL + 1);
95 value8 |= BIT(5);
96 rtw_write8(padapter, REG_MULTI_FUNC_CTRL + 1, value8);
97 #endif /* CONFIG_EXT_CLK */
98 #endif /* all of these MUST be configured before power on */
99
100 /* only cmd52 can be used before power on(card enable) */
101 ret = CardEnable(padapter);
102 if (ret == _FALSE) {
103 return _FAIL;
104 }
105
106 /* Radio-Off Pin Trigger */
107 value8 = rtw_read8(padapter, REG_GPIO_INTM + 1);
108 value8 |= BIT(1); /* Enable falling edge triggering interrupt */
109 rtw_write8(padapter, REG_GPIO_INTM + 1, value8);
110 value8 = rtw_read8(padapter, REG_GPIO_IO_SEL_2 + 1);
111 value8 |= BIT(1);
112 rtw_write8(padapter, REG_GPIO_IO_SEL_2 + 1, value8);
113
114 /* Enable power down and GPIO interrupt */
115 value16 = rtw_read16(padapter, REG_APS_FSMCO);
116 value16 |= EnPDN; /* Enable HW power down and RF on */
117 rtw_write16(padapter, REG_APS_FSMCO, value16);
118
119 /* Enable CMD53 R/W Operation
120 * bMacPwrCtrlOn = _TRUE;
121 * rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn); */
122
123 rtw_write8(padapter, REG_CR, 0x00);
124 /* Enable MAC DMA/WMAC/SCHEDULE/SEC block */
125 value16 = rtw_read16(padapter, REG_CR);
126 value16 |= (HCI_TXDMA_EN | HCI_RXDMA_EN | TXDMA_EN | RXDMA_EN
127 | PROTOCOL_EN | SCHEDULE_EN | ENSEC | CALTMR_EN);
128 rtw_write16(padapter, REG_CR, value16);
129
130
131 /* PowerOnCheck() */
132 ret = sdio_power_on_check(padapter);
133 pwron_chk_cnt++;
134 if (_FAIL == ret) {
135 if (pwron_chk_cnt > 1) {
136 RTW_INFO("Failed to init Power On!\n");
137 return _FAIL;
138 }
139 RTW_INFO("Power on Fail! do it again\n");
140 goto _init_power_on;
141 }
142
143 return _SUCCESS;
144 }
145 #ifdef CONFIG_SDIO_TX_ENABLE_AVAL_INT
146 /* Tx Page FIFO threshold */
_init_available_page_threshold(PADAPTER padapter,u8 numHQ,u8 numNQ,u8 numLQ,u8 numPubQ)147 static void _init_available_page_threshold(PADAPTER padapter, u8 numHQ, u8 numNQ, u8 numLQ, u8 numPubQ)
148 {
149 u16 HQ_threshold, NQ_threshold, LQ_threshold;
150
151 HQ_threshold = (numPubQ + numHQ + 1) >> 1;
152 HQ_threshold |= (HQ_threshold << 8);
153
154 NQ_threshold = (numPubQ + numNQ + 1) >> 1;
155 NQ_threshold |= (NQ_threshold << 8);
156
157 LQ_threshold = (numPubQ + numLQ + 1) >> 1;
158 LQ_threshold |= (LQ_threshold << 8);
159
160 rtw_write16(padapter, 0x218, HQ_threshold);
161 rtw_write16(padapter, 0x21A, NQ_threshold);
162 rtw_write16(padapter, 0x21C, LQ_threshold);
163 RTW_INFO("%s(): Enable Tx FIFO Page Threshold H:0x%x,N:0x%x,L:0x%x\n", __FUNCTION__, HQ_threshold, NQ_threshold, LQ_threshold);
164 }
165 #endif
_InitQueueReservedPage(PADAPTER padapter)166 static void _InitQueueReservedPage(PADAPTER padapter)
167 {
168 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
169 struct registry_priv *pregistrypriv = &padapter->registrypriv;
170 u32 outEPNum = (u32)pHalData->OutEpNumber;
171 u32 numHQ = 0;
172 u32 numLQ = 0;
173 u32 numNQ = 0;
174 u32 numPubQ;
175 u32 value32;
176 u8 value8;
177 BOOLEAN bWiFiConfig = pregistrypriv->wifi_spec;
178
179 if (pHalData->OutEpQueueSel & TX_SELE_HQ)
180 numHQ = bWiFiConfig ? WMM_NORMAL_PAGE_NUM_HPQ_8703B : NORMAL_PAGE_NUM_HPQ_8703B;
181
182 if (pHalData->OutEpQueueSel & TX_SELE_LQ)
183 numLQ = bWiFiConfig ? WMM_NORMAL_PAGE_NUM_LPQ_8703B : NORMAL_PAGE_NUM_LPQ_8703B;
184
185 /* NOTE: This step shall be proceed before writting REG_RQPN. */
186 if (pHalData->OutEpQueueSel & TX_SELE_NQ)
187 numNQ = bWiFiConfig ? WMM_NORMAL_PAGE_NUM_NPQ_8703B : NORMAL_PAGE_NUM_NPQ_8703B;
188
189 numPubQ = TX_TOTAL_PAGE_NUMBER_8703B - numHQ - numLQ - numNQ;
190
191 value8 = (u8)_NPQ(numNQ);
192 rtw_write8(padapter, REG_RQPN_NPQ, value8);
193
194 /* TX DMA */
195 value32 = _HPQ(numHQ) | _LPQ(numLQ) | _PUBQ(numPubQ) | LD_RQPN;
196 rtw_write32(padapter, REG_RQPN, value32);
197
198 rtw_hal_set_sdio_tx_max_length(padapter, numHQ, numNQ, numLQ, numPubQ, SDIO_TX_DIV_NUM);
199
200 #ifdef CONFIG_SDIO_TX_ENABLE_AVAL_INT
201 _init_available_page_threshold(padapter, numHQ, numNQ, numLQ, numPubQ);
202 #endif
203 }
204
_InitTxBufferBoundary(PADAPTER padapter)205 static void _InitTxBufferBoundary(PADAPTER padapter)
206 {
207 struct registry_priv *pregistrypriv = &padapter->registrypriv;
208 #ifdef CONFIG_CONCURRENT_MODE
209 u8 val8;
210 #endif /* CONFIG_CONCURRENT_MODE */
211
212 /* u16 txdmactrl; */
213 u8 txpktbuf_bndy;
214
215 if (!pregistrypriv->wifi_spec)
216 txpktbuf_bndy = TX_PAGE_BOUNDARY_8703B;
217 else {
218 /* for WMM */
219 txpktbuf_bndy = WMM_NORMAL_TX_PAGE_BOUNDARY_8703B;
220 }
221
222 rtw_write8(padapter, REG_TXPKTBUF_BCNQ_BDNY_8703B, txpktbuf_bndy);
223 rtw_write8(padapter, REG_TXPKTBUF_MGQ_BDNY_8703B, txpktbuf_bndy);
224 rtw_write8(padapter, REG_TXPKTBUF_WMAC_LBK_BF_HD_8703B, txpktbuf_bndy);
225 rtw_write8(padapter, REG_TRXFF_BNDY, txpktbuf_bndy);
226 rtw_write8(padapter, REG_TDECTRL + 1, txpktbuf_bndy);
227
228 #ifdef CONFIG_CONCURRENT_MODE
229 val8 = txpktbuf_bndy + BCNQ_PAGE_NUM_8703B + WOWLAN_PAGE_NUM_8703B;
230 rtw_write8(padapter, REG_BCNQ1_BDNY, val8);
231 rtw_write8(padapter, REG_DWBCN1_CTRL_8703B + 1, val8); /* BCN1_HEAD */
232
233 val8 = rtw_read8(padapter, REG_DWBCN1_CTRL_8703B + 2);
234 val8 |= BIT(1); /* BIT1- BIT_SW_BCN_SEL_EN */
235 rtw_write8(padapter, REG_DWBCN1_CTRL_8703B + 2, val8);
236 #endif /* CONFIG_CONCURRENT_MODE */
237 }
238
239 static void
_InitNormalChipRegPriority(PADAPTER Adapter,u16 beQ,u16 bkQ,u16 viQ,u16 voQ,u16 mgtQ,u16 hiQ)240 _InitNormalChipRegPriority(
241 PADAPTER Adapter,
242 u16 beQ,
243 u16 bkQ,
244 u16 viQ,
245 u16 voQ,
246 u16 mgtQ,
247 u16 hiQ
248 )
249 {
250 u16 value16 = (rtw_read16(Adapter, REG_TRXDMA_CTRL) & 0x7);
251
252 value16 |= _TXDMA_BEQ_MAP(beQ) | _TXDMA_BKQ_MAP(bkQ) |
253 _TXDMA_VIQ_MAP(viQ) | _TXDMA_VOQ_MAP(voQ) |
254 _TXDMA_MGQ_MAP(mgtQ) | _TXDMA_HIQ_MAP(hiQ);
255
256 rtw_write16(Adapter, REG_TRXDMA_CTRL, value16);
257 }
258
259 static void
_InitNormalChipOneOutEpPriority(PADAPTER Adapter)260 _InitNormalChipOneOutEpPriority(
261 PADAPTER Adapter
262 )
263 {
264 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
265
266 u16 value = 0;
267 switch (pHalData->OutEpQueueSel) {
268 case TX_SELE_HQ:
269 value = QUEUE_HIGH;
270 break;
271 case TX_SELE_LQ:
272 value = QUEUE_LOW;
273 break;
274 case TX_SELE_NQ:
275 value = QUEUE_NORMAL;
276 break;
277 default:
278 /* RT_ASSERT(FALSE,("Shall not reach here!\n")); */
279 break;
280 }
281
282 _InitNormalChipRegPriority(Adapter,
283 value,
284 value,
285 value,
286 value,
287 value,
288 value
289 );
290
291 }
292
293 static void
_InitNormalChipTwoOutEpPriority(PADAPTER Adapter)294 _InitNormalChipTwoOutEpPriority(
295 PADAPTER Adapter
296 )
297 {
298 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
299 struct registry_priv *pregistrypriv = &Adapter->registrypriv;
300 u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
301
302
303 u16 valueHi = 0;
304 u16 valueLow = 0;
305
306 switch (pHalData->OutEpQueueSel) {
307 case (TX_SELE_HQ | TX_SELE_LQ):
308 valueHi = QUEUE_HIGH;
309 valueLow = QUEUE_LOW;
310 break;
311 case (TX_SELE_NQ | TX_SELE_LQ):
312 valueHi = QUEUE_NORMAL;
313 valueLow = QUEUE_LOW;
314 break;
315 case (TX_SELE_HQ | TX_SELE_NQ):
316 valueHi = QUEUE_HIGH;
317 valueLow = QUEUE_NORMAL;
318 break;
319 default:
320 /* RT_ASSERT(FALSE,("Shall not reach here!\n")); */
321 break;
322 }
323
324 if (!pregistrypriv->wifi_spec) {
325 beQ = valueLow;
326 bkQ = valueLow;
327 viQ = valueHi;
328 voQ = valueHi;
329 mgtQ = valueHi;
330 hiQ = valueHi;
331 } else { /* for WMM ,CONFIG_OUT_EP_WIFI_MODE */
332 beQ = valueLow;
333 bkQ = valueHi;
334 viQ = valueHi;
335 voQ = valueLow;
336 mgtQ = valueHi;
337 hiQ = valueHi;
338 }
339
340 _InitNormalChipRegPriority(Adapter, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
341
342 }
343
344 static void
_InitNormalChipThreeOutEpPriority(PADAPTER padapter)345 _InitNormalChipThreeOutEpPriority(
346 PADAPTER padapter
347 )
348 {
349 struct registry_priv *pregistrypriv = &padapter->registrypriv;
350 u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
351
352 if (!pregistrypriv->wifi_spec) { /* typical setting */
353 beQ = QUEUE_LOW;
354 bkQ = QUEUE_LOW;
355 viQ = QUEUE_NORMAL;
356 voQ = QUEUE_HIGH;
357 mgtQ = QUEUE_HIGH;
358 hiQ = QUEUE_HIGH;
359 } else { /* for WMM */
360 beQ = QUEUE_LOW;
361 bkQ = QUEUE_NORMAL;
362 viQ = QUEUE_NORMAL;
363 voQ = QUEUE_HIGH;
364 mgtQ = QUEUE_HIGH;
365 hiQ = QUEUE_HIGH;
366 }
367 _InitNormalChipRegPriority(padapter, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
368 }
369
370 static void
_InitNormalChipQueuePriority(PADAPTER Adapter)371 _InitNormalChipQueuePriority(
372 PADAPTER Adapter
373 )
374 {
375 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
376
377 switch (pHalData->OutEpNumber) {
378 case 1:
379 _InitNormalChipOneOutEpPriority(Adapter);
380 break;
381 case 2:
382 _InitNormalChipTwoOutEpPriority(Adapter);
383 break;
384 case 3:
385 _InitNormalChipThreeOutEpPriority(Adapter);
386 break;
387 default:
388 /* RT_ASSERT(FALSE,("Shall not reach here!\n")); */
389 break;
390 }
391
392
393 }
394
_InitQueuePriority(PADAPTER padapter)395 static void _InitQueuePriority(PADAPTER padapter)
396 {
397 _InitNormalChipQueuePriority(padapter);
398 }
399
_InitPageBoundary(PADAPTER padapter)400 static void _InitPageBoundary(PADAPTER padapter)
401 {
402 /* RX Page Boundary */
403 u16 rxff_bndy = RX_DMA_BOUNDARY_8703B;
404
405 rtw_write16(padapter, (REG_TRXFF_BNDY + 2), rxff_bndy);
406 }
407
_InitTransferPageSize(PADAPTER padapter)408 static void _InitTransferPageSize(PADAPTER padapter)
409 {
410 /* Tx page size is always 128. */
411
412 u8 value8;
413 value8 = _PSRX(PBP_128) | _PSTX(PBP_128);
414 rtw_write8(padapter, REG_PBP, value8);
415 }
416
_InitDriverInfoSize(PADAPTER padapter,u8 drvInfoSize)417 void _InitDriverInfoSize(PADAPTER padapter, u8 drvInfoSize)
418 {
419 rtw_write8(padapter, REG_RX_DRVINFO_SZ, drvInfoSize);
420 }
421
_InitNetworkType(PADAPTER padapter)422 void _InitNetworkType(PADAPTER padapter)
423 {
424 u32 value32;
425
426 value32 = rtw_read32(padapter, REG_CR);
427
428 /* TODO: use the other function to set network type
429 * value32 = (value32 & ~MASK_NETTYPE) | _NETTYPE(NT_LINK_AD_HOC); */
430 value32 = (value32 & ~MASK_NETTYPE) | _NETTYPE(NT_LINK_AP);
431
432 rtw_write32(padapter, REG_CR, value32);
433 }
434
_InitWMACSetting(PADAPTER padapter)435 void _InitWMACSetting(PADAPTER padapter)
436 {
437 PHAL_DATA_TYPE pHalData;
438 u16 value16;
439 u32 rcr;
440
441 pHalData = GET_HAL_DATA(padapter);
442
443 rcr = 0
444 | RCR_APM | RCR_AM | RCR_AB
445 | RCR_CBSSID_DATA | RCR_CBSSID_BCN | RCR_AMF
446 | RCR_HTC_LOC_CTRL
447 | RCR_APP_PHYST_RXFF | RCR_APP_ICV | RCR_APP_MIC
448 #ifdef CONFIG_MAC_LOOPBACK_DRIVER
449 | RCR_AAP
450 | RCR_ADD3 | RCR_APWRMGT | RCR_ACRC32 | RCR_ADF
451 #endif
452 ;
453 rtw_hal_set_hwreg(padapter, HW_VAR_RCR, (u8 *)&rcr);
454
455 /* Accept all multicast address */
456 rtw_write32(padapter, REG_MAR, 0xFFFFFFFF);
457 rtw_write32(padapter, REG_MAR + 4, 0xFFFFFFFF);
458
459 /* Accept all data frames */
460 value16 = 0xFFFF;
461 rtw_write16(padapter, REG_RXFLTMAP2, value16);
462
463 /* 2010.09.08 hpfan */
464 /* Since ADF is removed from RCR, ps-poll will not be indicate to driver, */
465 /* RxFilterMap should mask ps-poll to gurantee AP mode can rx ps-poll. */
466 value16 = 0x400;
467 rtw_write16(padapter, REG_RXFLTMAP1, value16);
468
469 /* Accept all management frames */
470 value16 = 0xFFFF;
471 rtw_write16(padapter, REG_RXFLTMAP0, value16);
472 }
473
_InitAdaptiveCtrl(PADAPTER padapter)474 void _InitAdaptiveCtrl(PADAPTER padapter)
475 {
476 u16 value16;
477 u32 value32;
478
479 /* Response Rate Set */
480 value32 = rtw_read32(padapter, REG_RRSR);
481 value32 &= ~RATE_BITMAP_ALL;
482 value32 |= RATE_RRSR_CCK_ONLY_1M;
483
484 rtw_phydm_set_rrsr(padapter, value32, TRUE);
485
486
487 /* CF-END Threshold */
488 /* m_spIoBase->rtw_write8(REG_CFEND_TH, 0x1); */
489
490 /* SIFS (used in NAV) */
491 value16 = _SPEC_SIFS_CCK(0x10) | _SPEC_SIFS_OFDM(0x10);
492 rtw_write16(padapter, REG_SPEC_SIFS, value16);
493
494 /* Retry Limit */
495 value16 = BIT_LRL(RL_VAL_STA) | BIT_SRL(RL_VAL_STA);
496 rtw_write16(padapter, REG_RETRY_LIMIT, value16);
497 }
498
_InitEDCA(PADAPTER padapter)499 void _InitEDCA(PADAPTER padapter)
500 {
501 /* Set Spec SIFS (used in NAV) */
502 rtw_write16(padapter, REG_SPEC_SIFS, 0x100a);
503 rtw_write16(padapter, REG_MAC_SPEC_SIFS, 0x100a);
504
505 /* Set SIFS for CCK */
506 rtw_write16(padapter, REG_SIFS_CTX, 0x100a);
507
508 /* Set SIFS for OFDM */
509 rtw_write16(padapter, REG_SIFS_TRX, 0x100a);
510
511 /* TXOP */
512 rtw_write32(padapter, REG_EDCA_BE_PARAM, 0x005EA42B);
513 rtw_write32(padapter, REG_EDCA_BK_PARAM, 0x0000A44F);
514 rtw_write32(padapter, REG_EDCA_VI_PARAM, 0x005EA324);
515 rtw_write32(padapter, REG_EDCA_VO_PARAM, 0x002FA226);
516 }
517
_InitRetryFunction(PADAPTER padapter)518 void _InitRetryFunction(PADAPTER padapter)
519 {
520 u8 value8;
521
522 value8 = rtw_read8(padapter, REG_FWHW_TXQ_CTRL);
523 value8 |= EN_AMPDU_RTY_NEW;
524 rtw_write8(padapter, REG_FWHW_TXQ_CTRL, value8);
525
526 /* Set ACK timeout */
527 rtw_write8(padapter, REG_ACKTO, 0x40);
528 }
529
HalRxAggr8703BSdio(PADAPTER padapter)530 static void HalRxAggr8703BSdio(PADAPTER padapter)
531 {
532 struct registry_priv *pregistrypriv;
533 u8 valueDMATimeout;
534 u8 valueDMAPageCount;
535
536
537 pregistrypriv = &padapter->registrypriv;
538
539 if (pregistrypriv->wifi_spec) {
540 /* 2010.04.27 hpfan */
541 /* Adjust RxAggrTimeout to close to zero disable RxAggr, suggested by designer */
542 /* Timeout value is calculated by 34 / (2^n) */
543 valueDMATimeout = 0x06;
544 valueDMAPageCount = 0x06;
545 } else {
546 /* 20130530, Isaac@SD1 suggest 3 kinds of parameter */
547 #if 1
548 /* TX/RX Balance */
549 valueDMATimeout = 0x06;
550 valueDMAPageCount = 0x06;
551 #endif
552 #if 0
553 /* TX/RX Balance, but TCP ack may be late */
554 valueDMATimeout = 0x16;
555 valueDMAPageCount = 0x06;
556 #endif
557 #if 0
558 /* RX Best */
559 valueDMATimeout = 0x16;
560 valueDMAPageCount = 0x08;
561 #endif
562 }
563
564 #ifdef CONFIG_DONT_CARE_TP
565 valueDMATimeout = 0x0f;
566 valueDMAPageCount = 0x04; /* RxAggUpthreshold = [4]*1K bytes+1.5k. since RxAggUpthreshold+SzAmsdu(3839)<MaxRxBuffSize(8k), MaxvalueDMAPageCount=4. */
567 #endif
568 rtw_write8(padapter, REG_RXDMA_AGG_PG_TH + 1, valueDMATimeout);
569 rtw_write8(padapter, REG_RXDMA_AGG_PG_TH, valueDMAPageCount);
570 }
571
sdio_AggSettingRxUpdate(PADAPTER padapter)572 void sdio_AggSettingRxUpdate(PADAPTER padapter)
573 {
574 HAL_DATA_TYPE *pHalData;
575 u8 valueDMA;
576 u8 valueRxAggCtrl = 0;
577 u8 aggBurstNum = 3; /* 0:1, 1:2, 2:3, 3:4 */
578 u8 aggBurstSize = 0; /* 0:1K, 1:512Byte, 2:256Byte... */
579
580 pHalData = GET_HAL_DATA(padapter);
581
582 valueDMA = rtw_read8(padapter, REG_TRXDMA_CTRL);
583 valueDMA |= RXDMA_AGG_EN;
584 rtw_write8(padapter, REG_TRXDMA_CTRL, valueDMA);
585
586 valueRxAggCtrl |= RXDMA_AGG_MODE_EN;
587 valueRxAggCtrl |= ((aggBurstNum << 2) & 0x0C);
588 valueRxAggCtrl |= ((aggBurstSize << 4) & 0x30);
589 rtw_write8(padapter, REG_RXDMA_MODE_CTRL_8703B, valueRxAggCtrl);/* RxAggLowThresh = 4*1K */
590 }
591
_initSdioAggregationSetting(PADAPTER padapter)592 void _initSdioAggregationSetting(PADAPTER padapter)
593 {
594 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
595
596 /* Tx aggregation setting
597 * sdio_AggSettingTxUpdate(padapter); */
598
599 /* Rx aggregation setting */
600 HalRxAggr8703BSdio(padapter);
601
602 sdio_AggSettingRxUpdate(padapter);
603 }
604 #if 0
605 static void _RXAggrSwitch(PADAPTER padapter, u8 enable)
606 {
607 PHAL_DATA_TYPE pHalData;
608 u8 valueDMA;
609 u8 valueRxAggCtrl;
610
611
612 pHalData = GET_HAL_DATA(padapter);
613
614 valueDMA = rtw_read8(padapter, REG_TRXDMA_CTRL);
615 valueRxAggCtrl = rtw_read8(padapter, REG_RXDMA_MODE_CTRL_8703B);
616
617 if (_TRUE == enable) {
618 valueDMA |= RXDMA_AGG_EN;
619 valueRxAggCtrl |= RXDMA_AGG_MODE_EN;
620 } else {
621 valueDMA &= ~RXDMA_AGG_EN;
622 valueRxAggCtrl &= ~RXDMA_AGG_MODE_EN;
623 }
624
625 rtw_write8(padapter, REG_TRXDMA_CTRL, valueDMA);
626 rtw_write8(padapter, REG_RXDMA_MODE_CTRL_8703B, valueRxAggCtrl);
627 }
628 #endif
_InitInterrupt(PADAPTER padapter)629 void _InitInterrupt(PADAPTER padapter)
630 {
631 /* HISR - turn all off */
632 rtw_write32(padapter, REG_HISR, 0);
633
634 /* HIMR - turn all off */
635 rtw_write32(padapter, REG_HIMR, 0);
636
637 /* */
638 /* Initialize and enable SDIO Host Interrupt. */
639 /* */
640 InitInterrupt8703BSdio(padapter);
641
642 /* */
643 /* Initialize system Host Interrupt. */
644 /* */
645 InitSysInterrupt8703BSdio(padapter);
646 }
647
_InitRDGSetting(PADAPTER padapter)648 void _InitRDGSetting(PADAPTER padapter)
649 {
650 rtw_write8(padapter, REG_RD_CTRL, 0xFF);
651 rtw_write16(padapter, REG_RD_NAV_NXT, 0x200);
652 rtw_write8(padapter, REG_RD_RESP_PKT_TH, 0x05);
653 }
654
_InitRFType(PADAPTER padapter)655 static void _InitRFType(PADAPTER padapter)
656 {
657 struct registry_priv *pregpriv = &padapter->registrypriv;
658 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
659
660 #if DISABLE_BB_RF
661 pHalData->rf_chip = RF_PSEUDO_11N;
662 return;
663 #endif
664 pHalData->rf_chip = RF_6052;
665
666 RTW_INFO("Set RF Chip ID to RF_6052 and RF type to %d.\n", pHalData->rf_type);
667 }
668
669 /* Set CCK and OFDM Block "ON" */
670 #if 0
671 static void _BBTurnOnBlock(PADAPTER padapter)
672 {
673 #if (DISABLE_BB_RF)
674 return;
675 #endif
676
677 phy_set_bb_reg(padapter, rFPGA0_RFMOD, bCCKEn, 0x1);
678 phy_set_bb_reg(padapter, rFPGA0_RFMOD, bOFDMEn, 0x1);
679 }
680 #endif
681
_InitBBRegBackup_8703BS(PADAPTER Adapter)682 void _InitBBRegBackup_8703BS(PADAPTER Adapter)
683 {
684 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
685
686 /* For Channel 1~11 (Default Value)*/
687 pHalData->RegForRecover[0].offset = rCCK0_TxFilter2;
688 pHalData->RegForRecover[0].value = phy_query_bb_reg(Adapter, pHalData->RegForRecover[0].offset, bMaskDWord);
689
690 pHalData->RegForRecover[1].offset = rCCK0_DebugPort;
691 pHalData->RegForRecover[1].value = phy_query_bb_reg(Adapter, pHalData->RegForRecover[1].offset, bMaskDWord);
692
693 /* For 20 MHz (Default Value)*/
694 pHalData->RegForRecover[2].offset = rBBrx_DFIR;
695 pHalData->RegForRecover[2].value = phy_query_bb_reg(Adapter, pHalData->RegForRecover[2].offset, bMaskDWord);
696
697 pHalData->RegForRecover[3].offset = rOFDM0_XATxAFE;
698 pHalData->RegForRecover[3].value = phy_query_bb_reg(Adapter, pHalData->RegForRecover[3].offset, bMaskDWord);
699
700 pHalData->RegForRecover[4].offset = 0x1E;
701 pHalData->RegForRecover[4].value = phy_query_rf_reg(Adapter, RF_PATH_A, pHalData->RegForRecover[4].offset, bRFRegOffsetMask);
702 }
703
704 /*
705 * 2010/08/09 MH Add for power down check.
706 * */
HalDetectPwrDownMode(PADAPTER Adapter)707 static BOOLEAN HalDetectPwrDownMode(PADAPTER Adapter)
708 {
709 u8 tmpvalue;
710 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
711 struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(Adapter);
712
713
714 EFUSE_ShadowRead(Adapter, 1, EEPROM_FEATURE_OPTION_8703B, (u32 *)&tmpvalue);
715
716 /* 2010/08/25 MH INF priority > PDN Efuse value. */
717 if (tmpvalue & BIT4 && pwrctrlpriv->reg_pdnmode)
718 pHalData->pwrdown = _TRUE;
719 else
720 pHalData->pwrdown = _FALSE;
721
722 RTW_INFO("HalDetectPwrDownMode(): PDN=%d\n", pHalData->pwrdown);
723
724 return pHalData->pwrdown;
725 } /* HalDetectPwrDownMode */
726
rtl8703bs_hal_init(PADAPTER padapter)727 static u32 rtl8703bs_hal_init(PADAPTER padapter)
728 {
729 s32 ret;
730 PHAL_DATA_TYPE pHalData;
731 struct pwrctrl_priv *pwrctrlpriv;
732 struct registry_priv *pregistrypriv;
733 struct sreset_priv *psrtpriv;
734 struct dvobj_priv *psdpriv = padapter->dvobj;
735 struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
736 rt_rf_power_state eRfPowerStateToSet;
737 u32 NavUpper = WiFiNavUpperUs;
738 u8 u1bTmp;
739 u16 value16;
740 u8 typeid;
741 u32 u4Tmp;
742
743 pHalData = GET_HAL_DATA(padapter);
744 psrtpriv = &pHalData->srestpriv;
745 pwrctrlpriv = adapter_to_pwrctl(padapter);
746 pregistrypriv = &padapter->registrypriv;
747
748 #ifdef CONFIG_SWLPS_IN_IPS
749 if (adapter_to_pwrctl(padapter)->bips_processing == _TRUE) {
750 u8 val8, bMacPwrCtrlOn = _TRUE;
751
752 RTW_INFO("%s: run LPS flow in IPS\n", __FUNCTION__);
753
754 /* ser rpwm */
755 val8 = rtw_read8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1);
756 val8 &= 0x80;
757 val8 += 0x80;
758 val8 |= BIT(6);
759 rtw_write8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1, val8);
760
761 adapter_to_pwrctl(padapter)->tog = (val8 + 0x80) & 0x80;
762
763 rtw_mdelay_os(5); /* wait set rpwm already */
764
765 ret = HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, rtl8703B_leave_swlps_flow);
766 if (ret == _FALSE) {
767 RTW_INFO("%s: run LPS flow in IPS fail!\n", __FUNCTION__);
768 return _FAIL;
769 }
770
771 rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
772
773 pHalData->LastHMEBoxNum = 0;
774
775 #ifdef CONFIG_BT_COEXIST
776 rtw_btcoex_HAL_Initialize(padapter, _FALSE);
777 #else
778 rtw_btcoex_HAL_Initialize(padapter, _TRUE);
779 #endif /* CONFIG_BT_COEXIST */
780
781 return _SUCCESS;
782 }
783 #elif defined(CONFIG_FWLPS_IN_IPS)
784 if (adapter_to_pwrctl(padapter)->bips_processing == _TRUE && psrtpriv->silent_reset_inprogress == _FALSE
785 && adapter_to_pwrctl(padapter)->pre_ips_type == 0) {
786 systime start_time;
787 u8 cpwm_orig, cpwm_now;
788 u8 val8, bMacPwrCtrlOn = _TRUE;
789
790 RTW_INFO("%s: Leaving IPS in FWLPS state\n", __FUNCTION__);
791
792 /* for polling cpwm */
793 cpwm_orig = 0;
794 rtw_hal_get_hwreg(padapter, HW_VAR_CPWM, &cpwm_orig);
795
796 /* ser rpwm */
797 val8 = rtw_read8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1);
798 val8 &= 0x80;
799 val8 += 0x80;
800 val8 |= BIT(6);
801 rtw_write8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1, val8);
802 RTW_INFO("%s: write rpwm=%02x\n", __FUNCTION__, val8);
803 adapter_to_pwrctl(padapter)->tog = (val8 + 0x80) & 0x80;
804
805 /* do polling cpwm */
806 start_time = rtw_get_current_time();
807 do {
808
809 rtw_mdelay_os(1);
810
811 rtw_hal_get_hwreg(padapter, HW_VAR_CPWM, &cpwm_now);
812 if ((cpwm_orig ^ cpwm_now) & 0x80) {
813 #ifdef DBG_CHECK_FW_PS_STATE
814 RTW_INFO("%s: polling cpwm ok when leaving IPS in FWLPS state, cpwm_orig=%02x, cpwm_now=%02x, 0x100=0x%x\n"
815 , __FUNCTION__, cpwm_orig, cpwm_now, rtw_read8(padapter, REG_CR));
816 #endif /* DBG_CHECK_FW_PS_STATE */
817 break;
818 }
819
820 if (rtw_get_passing_time_ms(start_time) > 100) {
821 RTW_INFO("%s: polling cpwm timeout when leaving IPS in FWLPS state\n", __FUNCTION__);
822 break;
823 }
824 } while (1);
825
826 rtl8703b_set_FwPwrModeInIPS_cmd(padapter, 0);
827
828 rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
829
830 #ifdef CONFIG_BT_COEXIST
831 rtw_btcoex_HAL_Initialize(padapter, _FALSE);
832 #else
833 rtw_btcoex_HAL_Initialize(padapter, _TRUE);
834 #endif /* CONFIG_BT_COEXIST */
835
836 #ifdef DBG_CHECK_FW_PS_STATE
837 if (rtw_fw_ps_state(padapter) == _FAIL) {
838 RTW_INFO("after hal init, fw ps state in 32k\n");
839 pdbgpriv->dbg_ips_drvopen_fail_cnt++;
840 }
841 #endif /* DBG_CHECK_FW_PS_STATE */
842 return _SUCCESS;
843 }
844 #endif /* CONFIG_SWLPS_IN_IPS */
845
846 /* Disable Interrupt first.
847 * rtw_hal_disable_interrupt(padapter); */
848
849 if (rtw_read8(padapter, REG_MCUFWDL) == 0xc6)
850 RTW_INFO("FW exist before power on!!\n");
851 else
852 RTW_INFO("FW does not exist before power on!!\n");
853 #ifdef DBG_CHECK_FW_PS_STATE
854 if (rtw_fw_ps_state(padapter) == _FAIL) {
855 RTW_INFO("check fw_ps_state fail before PowerOn!\n");
856 pdbgpriv->dbg_ips_drvopen_fail_cnt++;
857 }
858 #endif
859 ret = rtw_hal_power_on(padapter);
860 if (_FAIL == ret) {
861 return _FAIL;
862 }
863 RTW_INFO("Power on ok!\n");
864 #ifdef DBG_CHECK_FW_PS_STATE
865 if (rtw_fw_ps_state(padapter) == _FAIL) {
866 RTW_INFO("check fw_ps_state fail after PowerOn!\n");
867 pdbgpriv->dbg_ips_drvopen_fail_cnt++;
868 }
869 #endif
870
871 rtw_write8(padapter, REG_EARLY_MODE_CONTROL, 0);
872
873 if (padapter->registrypriv.mp_mode == 0) {
874 ret = rtl8703b_FirmwareDownload(padapter, _FALSE);
875 if (ret != _SUCCESS) {
876 pHalData->bFWReady = _FALSE;
877 pHalData->fw_ractrl = _FALSE;
878 return ret;
879 } else {
880 pHalData->bFWReady = _TRUE;
881 pHalData->fw_ractrl = _TRUE;
882 }
883 }
884
885 /* SIC_Init(padapter); */
886
887 if (pwrctrlpriv->reg_rfoff == _TRUE)
888 pwrctrlpriv->rf_pwrstate = rf_off;
889
890 /* 2010/08/09 MH We need to check if we need to turnon or off RF after detecting */
891 /* HW GPIO pin. Before PHY_RFConfig8192C. */
892 HalDetectPwrDownMode(padapter);
893
894 /* Set RF type for BB/RF configuration */
895 _InitRFType(padapter);
896
897 /* Save target channel */
898 /* <Roger_Notes> Current Channel will be updated again later. */
899 pHalData->current_channel = 6;
900
901 #if (HAL_MAC_ENABLE == 1)
902 ret = PHY_MACConfig8703B(padapter);
903 if (ret != _SUCCESS) {
904 return ret;
905 }
906 #endif
907 /* */
908 /* d. Initialize BB related configurations. */
909 /* */
910 #if (HAL_BB_ENABLE == 1)
911 ret = PHY_BBConfig8703B(padapter);
912 if (ret != _SUCCESS) {
913 return ret;
914 }
915
916 #endif
917
918 /* If RF is on, we need to init RF. Otherwise, skip the procedure. */
919 /* We need to follow SU method to change the RF cfg.txt. Default disable RF TX/RX mode. */
920 /* if(pHalData->eRFPowerState == eRfOn) */
921 {
922 #if (HAL_RF_ENABLE == 1)
923 ret = PHY_RFConfig8703B(padapter);
924 if (ret != _SUCCESS) {
925 return ret;
926 }
927 #endif
928 }
929
930 _InitBBRegBackup_8703BS(padapter);
931
932 _InitMacAPLLSetting_8703B(padapter);
933
934 /* */
935 /* Joseph Note: Keep RfRegChnlVal for later use. */
936 /* */
937 pHalData->RfRegChnlVal[0] = phy_query_rf_reg(padapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask);
938 pHalData->RfRegChnlVal[1] = phy_query_rf_reg(padapter, RF_PATH_B, RF_CHNLBW, bRFRegOffsetMask);
939
940 #if 0
941 /* Specially add for FWDL by Tx pkt write. Reset Tx/Rx DMA since the Tx boundary setting
942 is changed during FW download */
943 rtw_write8(padapter, REG_CR, 0x00);
944 rtw_write8(padapter, REG_CR, 0xFF);
945 #endif
946
947 /* if (!pHalData->bMACFuncEnable) { */
948 _InitQueueReservedPage(padapter);
949 _InitTxBufferBoundary(padapter);
950
951 /* init LLT after tx buffer boundary is defined */
952 ret = rtl8703b_InitLLTTable(padapter);
953 if (_SUCCESS != ret) {
954 RTW_INFO("%s: Failed to init LLT Table!\n", __FUNCTION__);
955 return _FAIL;
956 }
957 /* } */
958 _InitQueuePriority(padapter);
959 _InitPageBoundary(padapter);
960 _InitTransferPageSize(padapter);
961
962 /* Get Rx PHY status in order to report RSSI and others. */
963 _InitDriverInfoSize(padapter, DRVINFO_SZ);
964 _InitNetworkType(padapter);
965 _InitWMACSetting(padapter);
966 _InitAdaptiveCtrl(padapter);
967 _InitEDCA(padapter);
968 _InitRetryFunction(padapter);
969 _initSdioAggregationSetting(padapter);
970
971 rtl8703b_InitBeaconParameters(padapter);
972 rtl8703b_InitBeaconMaxError(padapter, _TRUE);
973 _InitInterrupt(padapter);
974 _InitBurstPktLen_8703BS(padapter);
975
976 #if 0
977 /* 8703B new ADD */
978 _InitLTECoex_8703BS(padapter);
979 #endif
980
981 /* YJ,TODO */
982 rtw_write8(padapter, REG_SECONDARY_CCA_CTRL_8703B, 0x3); /* CCA */
983 rtw_write8(padapter, 0x976, 0); /* hpfan_todo: 2nd CCA related */
984
985 invalidate_cam_all(padapter);
986
987 rtw_hal_set_chnl_bw(padapter, padapter->registrypriv.channel,
988 CHANNEL_WIDTH_20, HAL_PRIME_CHNL_OFFSET_DONT_CARE, HAL_PRIME_CHNL_OFFSET_DONT_CARE);
989
990 rtl8703b_InitAntenna_Selection(padapter);
991
992 /* */
993 /* Disable BAR, suggested by Scott */
994 /* 2010.04.09 add by hpfan */
995 /* */
996 rtw_write32(padapter, REG_BAR_MODE_CTRL, 0x0201ffff);
997
998 /* HW SEQ CTRL */
999 /* set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM. */
1000 rtw_write8(padapter, REG_HWSEQ_CTRL, 0xFF);
1001
1002
1003 #ifdef CONFIG_MAC_LOOPBACK_DRIVER
1004 u1bTmp = rtw_read8(padapter, REG_SYS_FUNC_EN);
1005 u1bTmp &= ~(FEN_BBRSTB | FEN_BB_GLB_RSTn);
1006 rtw_write8(padapter, REG_SYS_FUNC_EN, u1bTmp);
1007
1008 rtw_write8(padapter, REG_RD_CTRL, 0x0F);
1009 rtw_write8(padapter, REG_RD_CTRL + 1, 0xCF);
1010 rtw_write8(padapter, REG_TXPKTBUF_WMAC_LBK_BF_HD, 0x80);
1011 rtw_write32(padapter, REG_CR, 0x0b0202ff);
1012 #endif
1013
1014 /* */
1015 /* Configure SDIO TxRx Control to enable Rx DMA timer masking. */
1016 /* 2010.02.24. */
1017 /* */
1018 rtw_write32(padapter, SDIO_LOCAL_BASE | SDIO_REG_TX_CTRL, 0);
1019
1020
1021 rtl8703b_InitHalDm(padapter);
1022
1023 /* dbg_print("pHalData->DefaultTxPwrDbm = %d\n", pHalData->DefaultTxPwrDbm); */
1024
1025 /* if(pHalData->SwBeaconType < HAL92CSDIO_DEFAULT_BEACON_TYPE) */ /* The lowest Beacon Type that HW can support */
1026 /* pHalData->SwBeaconType = HAL92CSDIO_DEFAULT_BEACON_TYPE; */
1027
1028 /* */
1029 /* Update current Tx FIFO page status. */
1030 /* */
1031 HalQueryTxBufferStatus8703BSdio(padapter);
1032 HalQueryTxOQTBufferStatus8703BSdio(padapter);
1033 pHalData->SdioTxOQTMaxFreeSpace = pHalData->SdioTxOQTFreeSpace;
1034
1035 /* Enable MACTXEN/MACRXEN block */
1036 u1bTmp = rtw_read8(padapter, REG_CR);
1037 u1bTmp |= (MACTXEN | MACRXEN);
1038 rtw_write8(padapter, REG_CR, u1bTmp);
1039
1040 rtw_hal_set_hwreg(padapter, HW_VAR_NAV_UPPER, (u8 *)&NavUpper);
1041
1042 #ifdef CONFIG_XMIT_ACK
1043 /* ack for xmit mgmt frames. */
1044 rtw_write32(padapter, REG_FWHW_TXQ_CTRL, rtw_read32(padapter, REG_FWHW_TXQ_CTRL) | BIT(12));
1045 #endif /* CONFIG_XMIT_ACK */
1046
1047 /* pHalData->PreRpwmVal = SdioLocalCmd52Read1Byte(padapter, SDIO_REG_HRPWM1) & 0x80; */
1048
1049 #if (MP_DRIVER == 1)
1050 if (padapter->registrypriv.mp_mode == 1) {
1051 padapter->mppriv.channel = pHalData->current_channel;
1052 MPT_InitializeAdapter(padapter, padapter->mppriv.channel);
1053 } else
1054 #endif /* #if (MP_DRIVER == 1) */
1055 {
1056 pwrctrlpriv->rf_pwrstate = rf_on;
1057
1058 /*phy_lc_calibrate_8703b(&pHalData->odmpriv);*/
1059 halrf_lck_trigger(&pHalData->odmpriv);
1060
1061 pHalData->neediqk_24g = _TRUE;
1062
1063 odm_txpowertracking_check(&pHalData->odmpriv);
1064 }
1065
1066 #ifdef CONFIG_BT_COEXIST
1067 /* Init BT hw config.*/
1068 if (padapter->registrypriv.mp_mode == 1)
1069 rtw_btcoex_HAL_Initialize(padapter, _TRUE);
1070 else
1071 rtw_btcoex_HAL_Initialize(padapter, _FALSE);
1072 #endif
1073
1074
1075 return _SUCCESS;
1076 }
1077
CardDisableRTL8703BSdio(PADAPTER padapter)1078 static void CardDisableRTL8703BSdio(PADAPTER padapter)
1079 {
1080 u8 u1bTmp;
1081 u16 u2bTmp;
1082 u32 u4bTmp;
1083 u8 bMacPwrCtrlOn;
1084 u8 ret = _FAIL;
1085
1086 /* Run LPS WL RFOFF flow */
1087 ret = HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, rtl8703B_enter_lps_flow);
1088 if (ret == _FAIL)
1089 RTW_ERR("%s: run RF OFF flow fail!\n", __func__);
1090
1091 /* ==== Reset digital sequence ====== */
1092
1093 u1bTmp = rtw_read8(padapter, REG_MCUFWDL);
1094 if ((u1bTmp & RAM_DL_SEL) && GET_HAL_DATA(padapter)->bFWReady) /* 8051 RAM code */
1095 rtl8703b_FirmwareSelfReset(padapter);
1096
1097 /* Reset MCU 0x2[10]=0. Suggested by Filen. 2011.01.26. by tynli. */
1098 u1bTmp = rtw_read8(padapter, REG_SYS_FUNC_EN + 1);
1099 u1bTmp &= ~BIT(2); /* 0x2[10], FEN_CPUEN */
1100 rtw_write8(padapter, REG_SYS_FUNC_EN + 1, u1bTmp);
1101
1102 /* MCUFWDL 0x80[1:0]=0 */
1103 /* reset MCU ready status */
1104 rtw_write8(padapter, REG_MCUFWDL, 0);
1105
1106 /* Reset MCU IO Wrapper, added by Roger, 2011.08.30 */
1107 u1bTmp = rtw_read8(padapter, REG_RSV_CTRL + 1);
1108 u1bTmp &= ~BIT(0);
1109 rtw_write8(padapter, REG_RSV_CTRL + 1, u1bTmp);
1110 u1bTmp = rtw_read8(padapter, REG_RSV_CTRL + 1);
1111 u1bTmp |= BIT(0);
1112 rtw_write8(padapter, REG_RSV_CTRL + 1, u1bTmp);
1113
1114 /* ==== Reset digital sequence end ====== */
1115
1116 bMacPwrCtrlOn = _FALSE; /* Disable CMD53 R/W */
1117 ret = _FALSE;
1118 rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
1119 ret = HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, rtl8703B_card_disable_flow);
1120 if (ret == _FALSE)
1121 RTW_ERR("%s: run CARD DISABLE flow fail!\n", __func__);
1122
1123 GET_HAL_DATA(padapter)->bFWReady = _FALSE;
1124 }
1125
rtl8703bs_hal_deinit(PADAPTER padapter)1126 static u32 rtl8703bs_hal_deinit(PADAPTER padapter)
1127 {
1128 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
1129 struct sreset_priv *psrtpriv = &pHalData->srestpriv;
1130 struct dvobj_priv *psdpriv = padapter->dvobj;
1131 struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
1132
1133 #ifdef CONFIG_MP_INCLUDED
1134 if (padapter->registrypriv.mp_mode == 1)
1135 MPT_DeInitAdapter(padapter);
1136 #endif
1137
1138 if (rtw_is_hw_init_completed(padapter)) {
1139 #ifdef CONFIG_SWLPS_IN_IPS
1140 if (adapter_to_pwrctl(padapter)->bips_processing == _TRUE) {
1141 u8 bMacPwrCtrlOn;
1142 u8 ret = _TRUE;
1143
1144 RTW_INFO("%s: run LPS flow in IPS\n", __FUNCTION__);
1145
1146 rtw_write32(padapter, 0x130, 0x0);
1147 rtw_write32(padapter, 0x138, 0x100);
1148 rtw_write8(padapter, 0x13d, 0x1);
1149
1150
1151 bMacPwrCtrlOn = _FALSE; /* Disable CMD53 R/W */
1152 rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
1153
1154 ret = HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, rtl8703B_enter_swlps_flow);
1155 if (ret == _FALSE) {
1156 RTW_INFO("%s: run LPS flow in IPS fail!\n", __FUNCTION__);
1157 return _FAIL;
1158 }
1159 } else
1160 #elif defined(CONFIG_FWLPS_IN_IPS)
1161 if (adapter_to_pwrctl(padapter)->bips_processing == _TRUE && psrtpriv->silent_reset_inprogress == _FALSE) {
1162 if (padapter->netif_up == _TRUE) {
1163 int cnt = 0;
1164 u8 val8 = 0;
1165
1166 RTW_INFO("%s: issue H2C to FW when entering IPS\n", __FUNCTION__);
1167
1168 rtl8703b_set_FwPwrModeInIPS_cmd(padapter, 0x1);
1169 /* poll 0x1cc to make sure H2C command already finished by FW; MAC_0x1cc=0 means H2C done by FW. */
1170 do {
1171 val8 = rtw_read8(padapter, REG_HMETFR);
1172 cnt++;
1173 RTW_INFO("%s polling REG_HMETFR=0x%x, cnt=%d\n", __FUNCTION__, val8, cnt);
1174 rtw_mdelay_os(10);
1175 } while (cnt < 100 && (val8 != 0));
1176 /* H2C done, enter 32k */
1177 if (val8 == 0) {
1178 /* ser rpwm to enter 32k */
1179 val8 = rtw_read8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1);
1180 val8 += 0x80;
1181 val8 |= BIT(0);
1182 rtw_write8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1, val8);
1183 RTW_INFO("%s: write rpwm=%02x\n", __FUNCTION__, val8);
1184 adapter_to_pwrctl(padapter)->tog = (val8 + 0x80) & 0x80;
1185 cnt = val8 = 0;
1186 do {
1187 val8 = rtw_read8(padapter, REG_CR);
1188 cnt++;
1189 RTW_INFO("%s polling 0x100=0x%x, cnt=%d\n", __FUNCTION__, val8, cnt);
1190 rtw_mdelay_os(10);
1191 } while (cnt < 100 && (val8 != 0xEA));
1192 #ifdef DBG_CHECK_FW_PS_STATE
1193 if (val8 != 0xEA)
1194 RTW_INFO("MAC_1C0=%08x, MAC_1C4=%08x, MAC_1C8=%08x, MAC_1CC=%08x\n", rtw_read32(padapter, 0x1c0), rtw_read32(padapter, 0x1c4)
1195 , rtw_read32(padapter, 0x1c8), rtw_read32(padapter, 0x1cc));
1196 #endif /* DBG_CHECK_FW_PS_STATE */
1197 } else {
1198 RTW_INFO("MAC_1C0=%08x, MAC_1C4=%08x, MAC_1C8=%08x, MAC_1CC=%08x\n", rtw_read32(padapter, 0x1c0), rtw_read32(padapter, 0x1c4)
1199 , rtw_read32(padapter, 0x1c8), rtw_read32(padapter, 0x1cc));
1200 }
1201
1202 RTW_INFO("polling done when entering IPS, check result : 0x100=0x%x, cnt=%d, MAC_1cc=0x%02x\n"
1203 , rtw_read8(padapter, REG_CR), cnt, rtw_read8(padapter, REG_HMETFR));
1204
1205 adapter_to_pwrctl(padapter)->pre_ips_type = 0;
1206
1207 } else {
1208 pdbgpriv->dbg_carddisable_cnt++;
1209 #ifdef DBG_CHECK_FW_PS_STATE
1210 if (rtw_fw_ps_state(padapter) == _FAIL) {
1211 RTW_INFO("card disable should leave 32k\n");
1212 pdbgpriv->dbg_carddisable_error_cnt++;
1213 }
1214 #endif /* DBG_CHECK_FW_PS_STATE */
1215 rtw_hal_power_off(padapter);
1216
1217 adapter_to_pwrctl(padapter)->pre_ips_type = 1;
1218 }
1219
1220 } else
1221 #endif /* CONFIG_SWLPS_IN_IPS */
1222 {
1223 pdbgpriv->dbg_carddisable_cnt++;
1224 #ifdef DBG_CHECK_FW_PS_STATE
1225 if (rtw_fw_ps_state(padapter) == _FAIL) {
1226 RTW_INFO("card disable should leave 32k\n");
1227 pdbgpriv->dbg_carddisable_error_cnt++;
1228 }
1229 #endif /* DBG_CHECK_FW_PS_STATE */
1230 rtw_hal_power_off(padapter);
1231 }
1232 } else
1233 pdbgpriv->dbg_deinit_fail_cnt++;
1234
1235 return _SUCCESS;
1236 }
rtl8703bs_init_default_value(PADAPTER padapter)1237 static void rtl8703bs_init_default_value(PADAPTER padapter)
1238 {
1239 PHAL_DATA_TYPE pHalData;
1240
1241
1242 pHalData = GET_HAL_DATA(padapter);
1243
1244 rtl8703b_init_default_value(padapter);
1245
1246 /* interface related variable */
1247 pHalData->SdioRxFIFOCnt = 0;
1248 }
1249
rtl8703bs_interface_configure(PADAPTER padapter)1250 static void rtl8703bs_interface_configure(PADAPTER padapter)
1251 {
1252 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
1253 struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
1254 struct registry_priv *pregistrypriv = &padapter->registrypriv;
1255 BOOLEAN bWiFiConfig = pregistrypriv->wifi_spec;
1256
1257
1258 pdvobjpriv->RtOutPipe[0] = WLAN_TX_HIQ_DEVICE_ID;
1259 pdvobjpriv->RtOutPipe[1] = WLAN_TX_MIQ_DEVICE_ID;
1260 pdvobjpriv->RtOutPipe[2] = WLAN_TX_LOQ_DEVICE_ID;
1261
1262 if (bWiFiConfig)
1263 pHalData->OutEpNumber = 2;
1264 else
1265 pHalData->OutEpNumber = SDIO_MAX_TX_QUEUE;
1266
1267 switch (pHalData->OutEpNumber) {
1268 case 3:
1269 pHalData->OutEpQueueSel = TX_SELE_HQ | TX_SELE_LQ | TX_SELE_NQ;
1270 break;
1271 case 2:
1272 pHalData->OutEpQueueSel = TX_SELE_HQ | TX_SELE_NQ;
1273 break;
1274 case 1:
1275 pHalData->OutEpQueueSel = TX_SELE_HQ;
1276 break;
1277 default:
1278 break;
1279 }
1280
1281 Hal_MappingOutPipe(padapter, pHalData->OutEpNumber);
1282 }
1283
1284 /*
1285 * Description:
1286 * We should set Efuse cell selection to WiFi cell in default.
1287 *
1288 * Assumption:
1289 * PASSIVE_LEVEL
1290 *
1291 * Added by Roger, 2010.11.23.
1292 * */
1293 static void
_EfuseCellSel(PADAPTER padapter)1294 _EfuseCellSel(
1295 PADAPTER padapter
1296 )
1297 {
1298 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
1299
1300 u32 value32;
1301
1302 /* if(INCLUDE_MULTI_FUNC_BT(padapter)) */
1303 {
1304 value32 = rtw_read32(padapter, EFUSE_TEST);
1305 value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0);
1306 rtw_write32(padapter, EFUSE_TEST, value32);
1307 }
1308 }
1309
1310 static void
_ReadRFType(PADAPTER Adapter)1311 _ReadRFType(
1312 PADAPTER Adapter
1313 )
1314 {
1315 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
1316
1317 #if DISABLE_BB_RF
1318 pHalData->rf_chip = RF_PSEUDO_11N;
1319 #else
1320 pHalData->rf_chip = RF_6052;
1321 #endif
1322 }
1323
1324 static u8
_ReadEfuseInfo8703BS(PADAPTER padapter)1325 _ReadEfuseInfo8703BS(
1326 PADAPTER padapter
1327 )
1328 {
1329 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
1330 u8 *hwinfo = NULL;
1331 u8 ret = _FAIL;
1332
1333 /* */
1334 /* This part read and parse the eeprom/efuse content */
1335 /* */
1336
1337 if (sizeof(pHalData->efuse_eeprom_data) < HWSET_MAX_SIZE_8703B)
1338 RTW_INFO("[WARNING] size of efuse_eeprom_data is less than HWSET_MAX_SIZE_8703B!\n");
1339
1340 hwinfo = pHalData->efuse_eeprom_data;
1341
1342 Hal_InitPGData(padapter, hwinfo);
1343
1344 Hal_EfuseParseIDCode(padapter, hwinfo);
1345 Hal_EfuseParseEEPROMVer_8703B(padapter, hwinfo, pHalData->bautoload_fail_flag);
1346 hal_config_macaddr(padapter, pHalData->bautoload_fail_flag);
1347 Hal_EfuseParseTxPowerInfo_8703B(padapter, hwinfo, pHalData->bautoload_fail_flag);
1348 Hal_EfuseParseBoardType_8703B(padapter, hwinfo, pHalData->bautoload_fail_flag);
1349
1350 /* */
1351 /* Read Bluetooth co-exist and initialize */
1352 /* */
1353 Hal_EfuseParseBTCoexistInfo_8703B(padapter, hwinfo, pHalData->bautoload_fail_flag);
1354 Hal_EfuseParseChnlPlan_8703B(padapter, hwinfo, pHalData->bautoload_fail_flag);
1355 Hal_EfuseParseXtal_8703B(padapter, hwinfo, pHalData->bautoload_fail_flag);
1356 Hal_EfuseParseThermalMeter_8703B(padapter, hwinfo, pHalData->bautoload_fail_flag);
1357 Hal_EfuseParseAntennaDiversity_8703B(padapter, hwinfo, pHalData->bautoload_fail_flag);
1358 Hal_EfuseParseCustomerID_8703B(padapter, hwinfo, pHalData->bautoload_fail_flag);
1359
1360 Hal_EfuseParseVoltage_8703B(padapter, hwinfo, pHalData->bautoload_fail_flag);
1361
1362 #ifdef CONFIG_WOWLAN
1363 Hal_DetectWoWMode(padapter);
1364 #endif
1365
1366 Hal_ReadRFGainOffset(padapter, hwinfo, pHalData->bautoload_fail_flag);
1367
1368 /* set coex. ant info once efuse parsing is done */
1369 rtw_btcoex_set_ant_info(padapter);
1370
1371 if (hal_read_mac_hidden_rpt(padapter) != _SUCCESS)
1372 goto exit;
1373
1374 ret = _SUCCESS;
1375
1376 exit:
1377 return ret;
1378 }
1379
_ReadPROMContent(PADAPTER padapter)1380 static u8 _ReadPROMContent(
1381 PADAPTER padapter
1382 )
1383 {
1384 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
1385 u8 eeValue;
1386 u8 ret = _FAIL;
1387
1388 eeValue = rtw_read8(padapter, REG_9346CR);
1389 /* To check system boot selection. */
1390 pHalData->EepromOrEfuse = (eeValue & BOOT_FROM_EEPROM) ? _TRUE : _FALSE;
1391 pHalData->bautoload_fail_flag = (eeValue & EEPROM_EN) ? _FALSE : _TRUE;
1392
1393
1394 /* pHalData->EEType = IS_BOOT_FROM_EEPROM(Adapter) ? EEPROM_93C46 : EEPROM_BOOT_EFUSE; */
1395
1396 if (_ReadEfuseInfo8703BS(padapter) != _SUCCESS)
1397 goto exit;
1398
1399 ret = _SUCCESS;
1400
1401 exit:
1402 return ret;
1403 }
1404
1405 static void
_InitOtherVariable(PADAPTER Adapter)1406 _InitOtherVariable(
1407 PADAPTER Adapter
1408 )
1409 {
1410 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
1411
1412
1413 /* if(Adapter->bInHctTest){ */
1414 /* pMgntInfo->PowerSaveControl.bInactivePs = FALSE; */
1415 /* pMgntInfo->PowerSaveControl.bIPSModeBackup = FALSE; */
1416 /* pMgntInfo->PowerSaveControl.bLeisurePs = FALSE; */
1417 /* pMgntInfo->keepAliveLevel = 0; */
1418 /* } */
1419
1420
1421
1422 }
1423
1424 /*
1425 * Description:
1426 * Read HW adapter information by E-Fuse or EEPROM according CR9346 reported.
1427 *
1428 * Assumption:
1429 * PASSIVE_LEVEL (SDIO interface)
1430 *
1431 * */
ReadAdapterInfo8703BS(PADAPTER padapter)1432 static u8 ReadAdapterInfo8703BS(PADAPTER padapter)
1433 {
1434 u8 ret = _FAIL;
1435 u8 val8;
1436
1437 val8 = rtw_read8(padapter, 0x4e);
1438 RTW_INFO("%s, 0x4e=0x%x\n", __func__, val8);
1439 val8 |= BIT(6);
1440 rtw_write8(padapter, 0x4e, val8);
1441
1442 /* Read EEPROM size before call any EEPROM function */
1443 padapter->EepromAddressSize = GetEEPROMSize8703B(padapter);
1444
1445 _EfuseCellSel(padapter);
1446 _ReadRFType(padapter);
1447 if (_ReadPROMContent(padapter) != _SUCCESS)
1448 goto exit;
1449
1450 _InitOtherVariable(padapter);
1451
1452 #ifdef CONFIG_PLATFORM_INTEL_BYT
1453 { /* for BT, let BT can control ANT when wifi disable */
1454 u32 val32;
1455 RTW_INFO("%s, 0x4c=0x%x\n", __func__, rtw_read32(padapter, 0x4c));
1456 val32 = rtw_read32(padapter, 0x64);
1457 RTW_INFO("%s, 0x64=0x%x\n", __func__, val32);
1458 val32 |= BIT(13);
1459 rtw_write32(padapter, 0x64, val32);
1460 RTW_INFO("%s, 0x64=0x%x\n", __func__, rtw_read32(padapter, 0x64));
1461 }
1462 #endif /* CONFIG_PLATFORM_INTEL_BYT */
1463
1464 ret = _SUCCESS;
1465
1466 exit:
1467 return ret;
1468 }
1469
1470 /*
1471 * If variable not handled here,
1472 * some variables will be processed in SetHwReg8703B()
1473 */
SetHwReg8703BS(PADAPTER padapter,u8 variable,u8 * val)1474 u8 SetHwReg8703BS(PADAPTER padapter, u8 variable, u8 *val)
1475 {
1476 PHAL_DATA_TYPE pHalData;
1477 u8 ret = _SUCCESS;
1478 u8 val8;
1479
1480
1481 pHalData = GET_HAL_DATA(padapter);
1482
1483 switch (variable) {
1484 case HW_VAR_SET_RPWM:
1485 /* rpwm value only use BIT0(clock bit) ,BIT6(Ack bit), and BIT7(Toggle bit) */
1486 /* BIT0 value - 1: 32k, 0:40MHz. */
1487 /* BIT6 value - 1: report cpwm value after success set, 0:do not report. */
1488 /* BIT7 value - Toggle bit change. */
1489 {
1490 val8 = *val;
1491 val8 &= 0xC1;
1492 rtw_write8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1, val8);
1493 }
1494 break;
1495 case HW_VAR_SET_REQ_FW_PS:
1496 /* 1. driver write 0x8f[4]=1 */ { /* request fw ps state (only can write bit4) */
1497 u8 req_fw_ps = 0;
1498 req_fw_ps = rtw_read8(padapter, 0x8f);
1499 req_fw_ps |= 0x10;
1500 rtw_write8(padapter, 0x8f, req_fw_ps);
1501 }
1502 break;
1503 case HW_VAR_RXDMA_AGG_PG_TH:
1504 #if 0
1505 val8 = *val;
1506
1507 /* TH=1 => invalidate RX DMA aggregation */
1508 /* TH=0 => validate RX DMA aggregation, use init value. */
1509 if (val8 == 0) {
1510 /* enable RXDMA aggregation */
1511 /* _RXAggrSwitch(padapter, _TRUE); */
1512 } else {
1513 /* disable RXDMA aggregation */
1514 /* _RXAggrSwitch(padapter, _FALSE); */
1515 }
1516 #endif
1517 break;
1518 default:
1519 ret = SetHwReg8703B(padapter, variable, val);
1520 break;
1521 }
1522
1523 return ret;
1524 }
1525
1526 /*
1527 * If variable not handled here,
1528 * some variables will be processed in GetHwReg8703B()
1529 */
GetHwReg8703BS(PADAPTER padapter,u8 variable,u8 * val)1530 void GetHwReg8703BS(PADAPTER padapter, u8 variable, u8 *val)
1531 {
1532 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
1533
1534
1535 switch (variable) {
1536 case HW_VAR_CPWM:
1537 *val = rtw_read8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HCPWM1_8703B);
1538 break;
1539
1540 case HW_VAR_FW_PS_STATE: {
1541 /* 3. read dword 0x88 */ /* driver read fw ps state */
1542 *((u16 *)val) = rtw_read16(padapter, 0x88);
1543 }
1544 break;
1545 default:
1546 GetHwReg8703B(padapter, variable, val);
1547 break;
1548 }
1549
1550 }
1551
1552 /*
1553 * Description:
1554 * Query setting of specified variable.
1555 * */
1556 u8
GetHalDefVar8703BSDIO(PADAPTER Adapter,HAL_DEF_VARIABLE eVariable,void * pValue)1557 GetHalDefVar8703BSDIO(
1558 PADAPTER Adapter,
1559 HAL_DEF_VARIABLE eVariable,
1560 void *pValue
1561 )
1562 {
1563 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
1564 u8 bResult = _SUCCESS;
1565
1566 switch (eVariable) {
1567 case HAL_DEF_IS_SUPPORT_ANT_DIV:
1568 #ifdef CONFIG_ANTENNA_DIVERSITY
1569 *((u8 *)pValue) = _FALSE;
1570 #endif
1571 break;
1572
1573 case HW_VAR_MAX_RX_AMPDU_FACTOR:
1574 /* Stanley@BB.SD3 suggests 16K can get stable performance */
1575 /* coding by Lucas@20130730 */
1576 *(HT_CAP_AMPDU_FACTOR *)pValue = MAX_AMPDU_FACTOR_16K;
1577 break;
1578 default:
1579 bResult = GetHalDefVar8703B(Adapter, eVariable, pValue);
1580 break;
1581 }
1582
1583 return bResult;
1584 }
1585
1586 /*
1587 * Description:
1588 * Change default setting of specified variable.
1589 * */
1590 u8
SetHalDefVar8703BSDIO(PADAPTER Adapter,HAL_DEF_VARIABLE eVariable,void * pValue)1591 SetHalDefVar8703BSDIO(
1592 PADAPTER Adapter,
1593 HAL_DEF_VARIABLE eVariable,
1594 void *pValue
1595 )
1596 {
1597 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
1598 u8 bResult = _SUCCESS;
1599
1600 switch (eVariable) {
1601 default:
1602 bResult = SetHalDefVar8703B(Adapter, eVariable, pValue);
1603 break;
1604 }
1605
1606 return bResult;
1607 }
1608
rtl8703bs_set_hal_ops(PADAPTER padapter)1609 void rtl8703bs_set_hal_ops(PADAPTER padapter)
1610 {
1611 struct hal_ops *pHalFunc = &padapter->hal_func;
1612
1613
1614 rtl8703b_set_hal_ops(pHalFunc);
1615
1616 pHalFunc->hal_power_on = &_InitPowerOn_8703BS;
1617 pHalFunc->hal_power_off = &CardDisableRTL8703BSdio;
1618
1619
1620 pHalFunc->hal_init = &rtl8703bs_hal_init;
1621 pHalFunc->hal_deinit = &rtl8703bs_hal_deinit;
1622
1623 pHalFunc->init_xmit_priv = &rtl8703bs_init_xmit_priv;
1624 pHalFunc->free_xmit_priv = &rtl8703bs_free_xmit_priv;
1625
1626 pHalFunc->init_recv_priv = &rtl8703bs_init_recv_priv;
1627 pHalFunc->free_recv_priv = &rtl8703bs_free_recv_priv;
1628 #ifdef CONFIG_RECV_THREAD_MODE
1629 pHalFunc->recv_hdl = rtl8703bs_recv_hdl;
1630 #endif /* CONFIG_RECV_THREAD_MODE */
1631 #ifdef CONFIG_RTW_SW_LED
1632 pHalFunc->InitSwLeds = &rtl8703bs_InitSwLeds;
1633 pHalFunc->DeInitSwLeds = &rtl8703bs_DeInitSwLeds;
1634 #endif
1635 pHalFunc->init_default_value = &rtl8703bs_init_default_value;
1636 pHalFunc->intf_chip_configure = &rtl8703bs_interface_configure;
1637 pHalFunc->read_adapter_info = &ReadAdapterInfo8703BS;
1638
1639 pHalFunc->enable_interrupt = &EnableInterrupt8703BSdio;
1640 pHalFunc->disable_interrupt = &DisableInterrupt8703BSdio;
1641 pHalFunc->check_ips_status = &CheckIPSStatus;
1642 #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
1643 pHalFunc->clear_interrupt = &ClearInterrupt8703BSdio;
1644 #endif
1645 pHalFunc->set_hw_reg_handler = &SetHwReg8703BS;
1646 pHalFunc->GetHwRegHandler = &GetHwReg8703BS;
1647 pHalFunc->get_hal_def_var_handler = &GetHalDefVar8703BSDIO;
1648 pHalFunc->SetHalDefVarHandler = &SetHalDefVar8703BSDIO;
1649
1650 pHalFunc->hal_xmit = &rtl8703bs_hal_xmit;
1651 pHalFunc->mgnt_xmit = &rtl8703bs_mgnt_xmit;
1652 #ifdef CONFIG_RTW_MGMT_QUEUE
1653 pHalFunc->hal_mgmt_xmitframe_enqueue = &rtl8703bs_hal_mgmt_xmitframe_enqueue;
1654 #endif
1655 pHalFunc->hal_xmitframe_enqueue = &rtl8703bs_hal_xmitframe_enqueue;
1656
1657 #ifdef CONFIG_HOSTAPD_MLME
1658 pHalFunc->hostap_mgnt_xmit_entry = NULL;
1659 #endif
1660
1661 #if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST)
1662 pHalFunc->hal_init_checkbthang_workqueue = &rtl8703bs_init_checkbthang_workqueue;
1663 pHalFunc->hal_free_checkbthang_workqueue = &rtl8703bs_free_checkbthang_workqueue;
1664 pHalFunc->hal_cancle_checkbthang_workqueue = &rtl8703bs_cancle_checkbthang_workqueue;
1665 pHalFunc->hal_checke_bt_hang = &rtl8703bs_hal_check_bt_hang;
1666 #endif
1667
1668 }
1669