1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 *****************************************************************************/
15 #define _HAL_INIT_C_
16
17 #include <rtl8703b_hal.h>
18 #include "hal_com_h2c.h"
19 #include <hal_com.h>
20 #include "hal8703b_fw.h"
21 #define FW_DOWNLOAD_SIZE_8703B 8192
22
23 static void
_FWDownloadEnable(PADAPTER padapter,BOOLEAN enable)24 _FWDownloadEnable(
25 PADAPTER padapter,
26 BOOLEAN enable
27 )
28 {
29 u8 tmp, count = 0;
30
31 if (enable) {
32 /* 8051 enable */
33 tmp = rtw_read8(padapter, REG_SYS_FUNC_EN + 1);
34 rtw_write8(padapter, REG_SYS_FUNC_EN + 1, tmp | 0x04);
35
36 tmp = rtw_read8(padapter, REG_MCUFWDL);
37 rtw_write8(padapter, REG_MCUFWDL, tmp | 0x01);
38
39 do {
40 tmp = rtw_read8(padapter, REG_MCUFWDL);
41 if (tmp & 0x01)
42 break;
43 rtw_write8(padapter, REG_MCUFWDL, tmp | 0x01);
44 rtw_msleep_os(1);
45 } while (count++ < 100);
46 if (count > 0)
47 RTW_INFO("%s: !!!!!!!!Write 0x80 Fail!: count = %d\n", __func__, count);
48
49 /* 8051 reset */
50 tmp = rtw_read8(padapter, REG_MCUFWDL + 2);
51 rtw_write8(padapter, REG_MCUFWDL + 2, tmp & 0xf7);
52 } else {
53 /* MCU firmware download disable. */
54 tmp = rtw_read8(padapter, REG_MCUFWDL);
55 rtw_write8(padapter, REG_MCUFWDL, tmp & 0xfe);
56 }
57 }
58
59 static int
_BlockWrite(PADAPTER padapter,void * buffer,u32 buffSize)60 _BlockWrite(
61 PADAPTER padapter,
62 void *buffer,
63 u32 buffSize
64 )
65 {
66 int ret = _SUCCESS;
67
68 u32 blockSize_p1 = 4; /* (Default) Phase #1 : PCI muse use 4-byte write to download FW */
69 u32 blockSize_p2 = 8; /* Phase #2 : Use 8-byte, if Phase#1 use big size to write FW. */
70 u32 blockSize_p3 = 1; /* Phase #3 : Use 1-byte, the remnant of FW image. */
71 u32 blockCount_p1 = 0, blockCount_p2 = 0, blockCount_p3 = 0;
72 u32 remainSize_p1 = 0, remainSize_p2 = 0;
73 u8 *bufferPtr = (u8 *)buffer;
74 u32 i = 0, offset = 0;
75 #ifdef CONFIG_PCI_HCI
76 u8 remainFW[4] = {0, 0, 0, 0};
77 u8 *p = NULL;
78 #endif
79
80 #ifdef CONFIG_USB_HCI
81 blockSize_p1 = 254;
82 #endif
83
84 /* printk("====>%s %d\n", __func__, __LINE__); */
85
86 /* 3 Phase #1 */
87 blockCount_p1 = buffSize / blockSize_p1;
88 remainSize_p1 = buffSize % blockSize_p1;
89
90
91
92 for (i = 0; i < blockCount_p1; i++) {
93 #ifdef CONFIG_USB_HCI
94 ret = rtw_writeN(padapter, (FW_8703B_START_ADDRESS + i * blockSize_p1), blockSize_p1, (bufferPtr + i * blockSize_p1));
95 #else
96 ret = rtw_write32(padapter, (FW_8703B_START_ADDRESS + i * blockSize_p1), le32_to_cpu(*((u32 *)(bufferPtr + i * blockSize_p1))));
97 #endif
98 if (ret == _FAIL) {
99 printk("====>%s %d i:%d\n", __func__, __LINE__, i);
100 goto exit;
101 }
102 }
103
104 #ifdef CONFIG_PCI_HCI
105 p = (u8 *)((u32 *)(bufferPtr + blockCount_p1 * blockSize_p1));
106 if (remainSize_p1) {
107 switch (remainSize_p1) {
108 case 0:
109 break;
110 case 3:
111 remainFW[2] = *(p + 2);
112 case 2:
113 remainFW[1] = *(p + 1);
114 case 1:
115 remainFW[0] = *(p);
116 ret = rtw_write32(padapter, (FW_8703B_START_ADDRESS + blockCount_p1 * blockSize_p1),
117 le32_to_cpu(*(u32 *)remainFW));
118 }
119 return ret;
120 }
121 #endif
122
123 /* 3 Phase #2 */
124 if (remainSize_p1) {
125 offset = blockCount_p1 * blockSize_p1;
126
127 blockCount_p2 = remainSize_p1 / blockSize_p2;
128 remainSize_p2 = remainSize_p1 % blockSize_p2;
129
130
131
132 #ifdef CONFIG_USB_HCI
133 for (i = 0; i < blockCount_p2; i++) {
134 ret = rtw_writeN(padapter, (FW_8703B_START_ADDRESS + offset + i * blockSize_p2), blockSize_p2, (bufferPtr + offset + i * blockSize_p2));
135
136 if (ret == _FAIL)
137 goto exit;
138 }
139 #endif
140 }
141
142 /* 3 Phase #3 */
143 if (remainSize_p2) {
144 offset = (blockCount_p1 * blockSize_p1) + (blockCount_p2 * blockSize_p2);
145
146 blockCount_p3 = remainSize_p2 / blockSize_p3;
147
148
149 for (i = 0 ; i < blockCount_p3 ; i++) {
150 ret = rtw_write8(padapter, (FW_8703B_START_ADDRESS + offset + i), *(bufferPtr + offset + i));
151
152 if (ret == _FAIL) {
153 printk("====>%s %d i:%d\n", __func__, __LINE__, i);
154 goto exit;
155 }
156 }
157 }
158 exit:
159 return ret;
160 }
161
162 static int
_PageWrite(PADAPTER padapter,u32 page,void * buffer,u32 size)163 _PageWrite(
164 PADAPTER padapter,
165 u32 page,
166 void *buffer,
167 u32 size
168 )
169 {
170 u8 value8;
171 u8 u8Page = (u8)(page & 0x07) ;
172
173 value8 = (rtw_read8(padapter, REG_MCUFWDL + 2) & 0xF8) | u8Page ;
174 rtw_write8(padapter, REG_MCUFWDL + 2, value8);
175
176 return _BlockWrite(padapter, buffer, size);
177 }
178 #ifdef CONFIG_PCI_HCI
179 static void
_FillDummy(u8 * pFwBuf,u32 * pFwLen)180 _FillDummy(
181 u8 *pFwBuf,
182 u32 *pFwLen
183 )
184 {
185 u32 FwLen = *pFwLen;
186 u8 remain = (u8)(FwLen % 4);
187 remain = (remain == 0) ? 0 : (4 - remain);
188
189 while (remain > 0) {
190 pFwBuf[FwLen] = 0;
191 FwLen++;
192 remain--;
193 }
194
195 *pFwLen = FwLen;
196 }
197 #endif
198 static int
_WriteFW(PADAPTER padapter,void * buffer,u32 size)199 _WriteFW(
200 PADAPTER padapter,
201 void *buffer,
202 u32 size
203 )
204 {
205 /* Since we need dynamic decide method of dwonload fw, so we call this function to get chip version. */
206 int ret = _SUCCESS;
207 u32 pageNums, remainSize ;
208 u32 page, offset;
209 u8 *bufferPtr = (u8 *)buffer;
210
211 #ifdef CONFIG_PCI_HCI
212 /* 20100120 Joseph: Add for 88CE normal chip. */
213 /* Fill in zero to make firmware image to dword alignment. */
214 _FillDummy(bufferPtr, &size);
215 #endif
216
217 pageNums = size / MAX_DLFW_PAGE_SIZE ;
218 /* RT_ASSERT((pageNums <= 4), ("Page numbers should not greater then 4\n")); */
219 remainSize = size % MAX_DLFW_PAGE_SIZE;
220
221 for (page = 0; page < pageNums; page++) {
222 offset = page * MAX_DLFW_PAGE_SIZE;
223 ret = _PageWrite(padapter, page, bufferPtr + offset, MAX_DLFW_PAGE_SIZE);
224
225 if (ret == _FAIL) {
226 printk("====>%s %d\n", __func__, __LINE__);
227 goto exit;
228 }
229 }
230 if (remainSize) {
231 offset = pageNums * MAX_DLFW_PAGE_SIZE;
232 page = pageNums;
233 ret = _PageWrite(padapter, page, bufferPtr + offset, remainSize);
234
235 if (ret == _FAIL) {
236 printk("====>%s %d\n", __func__, __LINE__);
237 goto exit;
238 }
239 }
240
241 exit:
242 return ret;
243 }
244
_8051Reset8703(PADAPTER padapter)245 void _8051Reset8703(PADAPTER padapter)
246 {
247 u8 cpu_rst;
248 u8 io_rst;
249
250 #if 0
251 io_rst = rtw_read8(padapter, REG_RSV_CTRL);
252 rtw_write8(padapter, REG_RSV_CTRL, io_rst & (~BIT1));
253 #endif
254
255 /* Reset 8051(WLMCU) IO wrapper */
256 /* 0x1c[8] = 0 */
257 /* Suggested by Isaac@SD1 and Gimmy@SD1, coding by Lucas@20130624 */
258 io_rst = rtw_read8(padapter, REG_RSV_CTRL + 1);
259 io_rst &= ~BIT(0);
260 rtw_write8(padapter, REG_RSV_CTRL + 1, io_rst);
261
262 cpu_rst = rtw_read8(padapter, REG_SYS_FUNC_EN + 1);
263 cpu_rst &= ~BIT(2);
264 rtw_write8(padapter, REG_SYS_FUNC_EN + 1, cpu_rst);
265
266 #if 0
267 io_rst = rtw_read8(padapter, REG_RSV_CTRL);
268 rtw_write8(padapter, REG_RSV_CTRL, io_rst & (~BIT1));
269 #endif
270
271 /* Enable 8051 IO wrapper */
272 /* 0x1c[8] = 1 */
273 io_rst = rtw_read8(padapter, REG_RSV_CTRL + 1);
274 io_rst |= BIT(0);
275 rtw_write8(padapter, REG_RSV_CTRL + 1, io_rst);
276
277 cpu_rst = rtw_read8(padapter, REG_SYS_FUNC_EN + 1);
278 cpu_rst |= BIT(2);
279 rtw_write8(padapter, REG_SYS_FUNC_EN + 1, cpu_rst);
280
281 RTW_INFO("%s: Finish\n", __FUNCTION__);
282 }
283
polling_fwdl_chksum(_adapter * adapter,u32 min_cnt,u32 timeout_ms)284 static s32 polling_fwdl_chksum(_adapter *adapter, u32 min_cnt, u32 timeout_ms)
285 {
286 s32 ret = _FAIL;
287 u32 value32;
288 systime start = rtw_get_current_time();
289 u32 cnt = 0;
290
291 /* polling CheckSum report */
292 do {
293 cnt++;
294 value32 = rtw_read32(adapter, REG_MCUFWDL);
295 if (value32 & FWDL_ChkSum_rpt || RTW_CANNOT_IO(adapter))
296 break;
297 rtw_yield_os();
298 } while (rtw_get_passing_time_ms(start) < timeout_ms || cnt < min_cnt);
299
300 if (!(value32 & FWDL_ChkSum_rpt))
301 goto exit;
302
303 if (rtw_fwdl_test_trigger_chksum_fail())
304 goto exit;
305
306 ret = _SUCCESS;
307
308 exit:
309 RTW_INFO("%s: Checksum report %s! (%u, %dms), REG_MCUFWDL:0x%08x\n", __FUNCTION__
310 , (ret == _SUCCESS) ? "OK" : "Fail", cnt, rtw_get_passing_time_ms(start), value32);
311
312 return ret;
313 }
314
_FWFreeToGo(_adapter * adapter,u32 min_cnt,u32 timeout_ms)315 static s32 _FWFreeToGo(_adapter *adapter, u32 min_cnt, u32 timeout_ms)
316 {
317 s32 ret = _FAIL;
318 u32 value32;
319 systime start = rtw_get_current_time();
320 u32 cnt = 0;
321 u32 value_to_check = 0;
322 u32 value_expected = (MCUFWDL_RDY | FWDL_ChkSum_rpt | WINTINI_RDY | RAM_DL_SEL);
323
324 value32 = rtw_read32(adapter, REG_MCUFWDL);
325 value32 |= MCUFWDL_RDY;
326 value32 &= ~WINTINI_RDY;
327 rtw_write32(adapter, REG_MCUFWDL, value32);
328
329 _8051Reset8703(adapter);
330
331 /* polling for FW ready */
332 do {
333 cnt++;
334 value32 = rtw_read32(adapter, REG_MCUFWDL);
335 value_to_check = value32 & value_expected;
336 if ((value_to_check == value_expected) || RTW_CANNOT_IO(adapter))
337 break;
338 rtw_yield_os();
339 } while (rtw_get_passing_time_ms(start) < timeout_ms || cnt < min_cnt);
340
341 if (value_to_check != value_expected)
342 goto exit;
343
344 if (rtw_fwdl_test_trigger_wintint_rdy_fail())
345 goto exit;
346
347 ret = _SUCCESS;
348
349 exit:
350 RTW_INFO("%s: Polling FW ready %s! (%u, %dms), REG_MCUFWDL:0x%08x\n", __FUNCTION__
351 , (ret == _SUCCESS) ? "OK" : "Fail", cnt, rtw_get_passing_time_ms(start), value32);
352
353 return ret;
354 }
355
356 #define IS_FW_81xxC(padapter) (((GET_HAL_DATA(padapter))->FirmwareSignature & 0xFFF0) == 0x88C0)
357
rtl8703b_FirmwareSelfReset(PADAPTER padapter)358 void rtl8703b_FirmwareSelfReset(PADAPTER padapter)
359 {
360 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
361 u8 u1bTmp;
362 u8 Delay = 100;
363
364 if (!(IS_FW_81xxC(padapter) &&
365 ((pHalData->firmware_version < 0x21) ||
366 (pHalData->firmware_version == 0x21 &&
367 pHalData->firmware_sub_version < 0x01)))) { /* after 88C Fw v33.1 */
368 /* 0x1cf=0x20. Inform 8051 to reset. 2009.12.25. tynli_test */
369 rtw_write8(padapter, REG_HMETFR + 3, 0x20);
370
371 u1bTmp = rtw_read8(padapter, REG_SYS_FUNC_EN + 1);
372 while (u1bTmp & BIT2) {
373 Delay--;
374 if (Delay == 0)
375 break;
376 rtw_udelay_os(50);
377 u1bTmp = rtw_read8(padapter, REG_SYS_FUNC_EN + 1);
378 }
379
380 if (Delay == 0) {
381 /* force firmware reset */
382 u1bTmp = rtw_read8(padapter, REG_SYS_FUNC_EN + 1);
383 rtw_write8(padapter, REG_SYS_FUNC_EN + 1, u1bTmp & (~BIT2));
384 }
385 }
386 }
387
388 #ifdef CONFIG_FILE_FWIMG
389 extern char *rtw_fw_file_path;
390 extern char *rtw_fw_wow_file_path;
391 #ifdef CONFIG_MP_INCLUDED
392 extern char *rtw_fw_mp_bt_file_path;
393 #endif /* CONFIG_MP_INCLUDED */
394 u8 FwBuffer[FW_8703B_SIZE];
395 #endif /* CONFIG_FILE_FWIMG */
396
397 #ifdef CONFIG_MP_INCLUDED
_WriteBTFWtoTxPktBuf8703B(PADAPTER Adapter,void * buffer,u32 FwBufLen,u8 times)398 int _WriteBTFWtoTxPktBuf8703B(
399 PADAPTER Adapter,
400 void *buffer,
401 u32 FwBufLen,
402 u8 times
403 )
404 {
405 int rtStatus = _SUCCESS;
406 /* u32 value32; */
407 /* u8 numHQ, numLQ, numPubQ; */ /* , txpktbuf_bndy; */
408 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
409 /* PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); */
410 u8 BcnValidReg;
411 u8 count = 0, DLBcnCount = 0;
412 u8 *FwbufferPtr = (u8 *)buffer;
413 /* PRT_TCB pTcb, ptempTcb; */
414 /* PRT_TX_LOCAL_BUFFER pBuf; */
415
416 u8 *ReservedPagePacket = NULL;
417 u8 *pGenBufReservedPagePacket = NULL;
418 u32 TotalPktLen, txpktbuf_bndy;
419 /* u8 tmpReg422; */
420 /* u8 u1bTmp; */
421 u8 *pframe;
422 struct xmit_priv *pxmitpriv = &(Adapter->xmitpriv);
423 struct xmit_frame *pmgntframe;
424 struct pkt_attrib *pattrib;
425 u8 txdesc_offset = TXDESC_OFFSET;
426 u8 val8, RegFwHwTxQCtrl;
427 #ifdef CONFIG_PCI_HCI
428 u8 u1bTmp;
429 #endif
430
431 #if 1/* #ifdef CONFIG_PCI_HCI */
432 TotalPktLen = FwBufLen;
433 #else
434 TotalPktLen = FwBufLen + pHalData->HWDescHeadLength;
435 #endif
436
437 if ((TotalPktLen + TXDESC_OFFSET) > MAX_CMDBUF_SZ) {
438 RTW_INFO(" WARNING %s => Total packet len = %d > MAX_CMDBUF_SZ:%d\n"
439 , __FUNCTION__, (TotalPktLen + TXDESC_OFFSET), MAX_CMDBUF_SZ);
440 return _FAIL;
441 }
442
443 pGenBufReservedPagePacket = rtw_zmalloc(TotalPktLen);/* GetGenTempBuffer (Adapter, TotalPktLen); */
444 if (!pGenBufReservedPagePacket)
445 return _FAIL;
446
447 ReservedPagePacket = (u8 *)pGenBufReservedPagePacket;
448
449 _rtw_memset(ReservedPagePacket, 0, TotalPktLen);
450
451 #if 1/* #ifdef CONFIG_PCI_HCI */
452 _rtw_memcpy(ReservedPagePacket, FwbufferPtr, FwBufLen);
453
454 #else
455 PlatformMoveMemory(ReservedPagePacket + Adapter->HWDescHeadLength , FwbufferPtr, FwBufLen);
456 #endif
457
458 /* --------------------------------------------------------- */
459 /* 1. Pause BCN */
460 /* --------------------------------------------------------- */
461 /* Set REG_CR bit 8. DMA beacon by SW. */
462 #ifdef CONFIG_PCI_HCI
463 u1bTmp = PlatformEFIORead1Byte(Adapter, REG_CR + 1);
464 PlatformEFIOWrite1Byte(Adapter, REG_CR + 1, (u1bTmp | BIT0));
465 #else
466 /* Remove for temparaily because of the code on v2002 is not sync to MERGE_TMEP for USB/SDIO. */
467 /* De not remove this part on MERGE_TEMP. by tynli. */
468 #endif
469
470 /* Disable Hw protection for a time which revserd for Hw sending beacon. */
471 /* Fix download reserved page packet fail that access collision with the protection time. */
472 /* 2010.05.11. Added by tynli. */
473 val8 = rtw_read8(Adapter, REG_BCN_CTRL);
474 val8 &= ~EN_BCN_FUNCTION;
475 val8 |= DIS_TSF_UDT;
476 rtw_write8(Adapter, REG_BCN_CTRL, val8);
477
478 #if 0/* #ifdef CONFIG_PCI_HCI */
479 tmpReg422 = PlatformEFIORead1Byte(Adapter, REG_FWHW_TXQ_CTRL + 2);
480 if (tmpReg422 & BIT6)
481 bRecover = TRUE;
482 PlatformEFIOWrite1Byte(Adapter, REG_FWHW_TXQ_CTRL + 2, tmpReg422 & (~BIT6));
483 #else
484 /* Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame. */
485 RegFwHwTxQCtrl = PlatformEFIORead1Byte(Adapter, REG_FWHW_TXQ_CTRL + 2);
486 PlatformEFIOWrite1Byte(Adapter, REG_FWHW_TXQ_CTRL + 2, RegFwHwTxQCtrl & (~BIT6));
487 #endif
488
489 /* --------------------------------------------------------- */
490 /* 2. Adjust LLT table to an even boundary. */
491 /* --------------------------------------------------------- */
492 #if 0/* #ifdef CONFIG_SDIO_HCI */
493 txpktbuf_bndy = 10; /* rsvd page start address should be an even value. */
494 rtStatus = InitLLTTable8703BS(Adapter, txpktbuf_bndy);
495 if (RT_STATUS_SUCCESS != rtStatus) {
496 RTW_INFO("_CheckWLANFwPatchBTFwReady_8703B(): Failed to init LLT!\n");
497 return RT_STATUS_FAILURE;
498 }
499
500 /* Init Tx boundary. */
501 PlatformEFIOWrite1Byte(Adapter, REG_DWBCN0_CTRL_8703B + 1, (u8)txpktbuf_bndy);
502 #endif
503
504
505 /* --------------------------------------------------------- */
506 /* 3. Write Fw to Tx packet buffer by reseverd page. */
507 /* --------------------------------------------------------- */
508 do {
509 /* download rsvd page. */
510 /* Clear beacon valid check bit. */
511 BcnValidReg = PlatformEFIORead1Byte(Adapter, REG_TDECTRL + 2);
512 PlatformEFIOWrite1Byte(Adapter, REG_TDECTRL + 2, BcnValidReg & (~BIT(0)));
513
514 /* BT patch is big, we should set 0x209 < 0x40 suggested from Gimmy */
515
516 PlatformEFIOWrite1Byte(Adapter, REG_TDECTRL + 1, (0x90 - 0x20 * (times - 1)));
517 RTW_INFO("0x209:0x%x\n", PlatformEFIORead1Byte(Adapter, REG_TDECTRL + 1));
518
519 #if 0
520 /* Acquice TX spin lock before GetFwBuf and send the packet to prevent system deadlock. */
521 /* Advertised by Roger. Added by tynli. 2010.02.22. */
522 PlatformAcquireSpinLock(Adapter, RT_TX_SPINLOCK);
523 if (MgntGetFWBuffer(Adapter, &pTcb, &pBuf)) {
524 PlatformMoveMemory(pBuf->Buffer.VirtualAddress, ReservedPagePacket, TotalPktLen);
525 CmdSendPacket(Adapter, pTcb, pBuf, TotalPktLen, DESC_PACKET_TYPE_NORMAL, FALSE);
526 } else
527 dbgdump("SetFwRsvdPagePkt(): MgntGetFWBuffer FAIL!!!!!!!!.\n");
528 PlatformReleaseSpinLock(Adapter, RT_TX_SPINLOCK);
529 #else
530 /*---------------------------------------------------------
531 tx reserved_page_packet
532 ----------------------------------------------------------*/
533 pmgntframe = rtw_alloc_cmdxmitframe(pxmitpriv);
534 if (pmgntframe == NULL) {
535 rtStatus = _FAIL;
536 goto exit;
537 }
538 /* update attribute */
539 pattrib = &pmgntframe->attrib;
540 update_mgntframe_attrib(Adapter, pattrib);
541
542 pattrib->qsel = QSLT_BEACON;
543 pattrib->pktlen = pattrib->last_txcmdsz = FwBufLen ;
544
545 /* _rtw_memset(pmgntframe->buf_addr, 0, TotalPktLen+txdesc_size); */
546 /* pmgntframe->buf_addr = ReservedPagePacket ; */
547
548 _rtw_memcpy((u8 *)(pmgntframe->buf_addr + txdesc_offset), ReservedPagePacket, FwBufLen);
549 RTW_INFO("[%d]===>TotalPktLen + TXDESC_OFFSET TotalPacketLen:%d\n", DLBcnCount, (FwBufLen + txdesc_offset));
550
551 #ifdef CONFIG_PCI_HCI
552 dump_mgntframe(Adapter, pmgntframe);
553 #else
554 dump_mgntframe_and_wait(Adapter, pmgntframe, 100);
555 #endif
556
557 #endif
558 #if 1
559 /* check rsvd page download OK. */
560 BcnValidReg = PlatformEFIORead1Byte(Adapter, REG_TDECTRL + 2);
561 while (!(BcnValidReg & BIT(0)) && count < 200) {
562 count++;
563 /* PlatformSleepUs(10); */
564 rtw_msleep_os(1);
565 BcnValidReg = PlatformEFIORead1Byte(Adapter, REG_TDECTRL + 2);
566 }
567 DLBcnCount++;
568 /* RTW_INFO("##0x208:%08x,0x210=%08x\n",PlatformEFIORead4Byte(Adapter, REG_TDECTRL),PlatformEFIORead4Byte(Adapter, 0x210)); */
569
570 PlatformEFIOWrite1Byte(Adapter, REG_TDECTRL + 2, BcnValidReg);
571
572 } while ((!(BcnValidReg & BIT(0))) && DLBcnCount < 5);
573
574
575 #endif
576 if (DLBcnCount >= 5) {
577 RTW_INFO(" check rsvd page download OK DLBcnCount =%d\n", DLBcnCount);
578 rtStatus = _FAIL;
579 goto exit;
580 }
581
582 if (!(BcnValidReg & BIT(0))) {
583 RTW_INFO("_WriteFWtoTxPktBuf(): 1 Download RSVD page failed!\n");
584 rtStatus = _FAIL;
585 goto exit;
586 }
587
588 /* --------------------------------------------------------- */
589 /* 4. Set Tx boundary to the initial value */
590 /* --------------------------------------------------------- */
591
592
593 /* --------------------------------------------------------- */
594 /* 5. Reset beacon setting to the initial value. */
595 /* After _CheckWLANFwPatchBTFwReady(). */
596 /* --------------------------------------------------------- */
597
598 exit:
599
600 if (pGenBufReservedPagePacket) {
601 RTW_INFO("_WriteBTFWtoTxPktBuf8703B => rtw_mfree pGenBufReservedPagePacket!\n");
602 rtw_mfree((u8 *)pGenBufReservedPagePacket, TotalPktLen);
603 }
604 return rtStatus;
605 }
606
607
608
609 /*
610 * Description: Determine the contents of H2C BT_FW_PATCH Command sent to FW.
611 * 2011.10.20 by tynli
612 * */
613 void
SetFwBTFwPatchCmd(PADAPTER Adapter,u16 FwSize)614 SetFwBTFwPatchCmd(
615 PADAPTER Adapter,
616 u16 FwSize
617 )
618 {
619 u8 u1BTFwPatchParm[H2C_BT_FW_PATCH_LEN] = {0};
620 u8 addr0 = 0;
621 u8 addr1 = 0xa0;
622 u8 addr2 = 0x10;
623 u8 addr3 = 0x80;
624
625
626 SET_8703B_H2CCMD_BT_FW_PATCH_SIZE(u1BTFwPatchParm, FwSize);
627 SET_8703B_H2CCMD_BT_FW_PATCH_ADDR0(u1BTFwPatchParm, addr0);
628 SET_8703B_H2CCMD_BT_FW_PATCH_ADDR1(u1BTFwPatchParm, addr1);
629 SET_8703B_H2CCMD_BT_FW_PATCH_ADDR2(u1BTFwPatchParm, addr2);
630 SET_8703B_H2CCMD_BT_FW_PATCH_ADDR3(u1BTFwPatchParm, addr3);
631
632 FillH2CCmd8703B(Adapter, H2C_8703B_BT_FW_PATCH, H2C_BT_FW_PATCH_LEN, u1BTFwPatchParm);
633
634 }
635
636 void
SetFwBTPwrCmd(PADAPTER Adapter,u8 PwrIdx)637 SetFwBTPwrCmd(
638 PADAPTER Adapter,
639 u8 PwrIdx
640 )
641 {
642 u8 u1BTPwrIdxParm[H2C_FORCE_BT_TXPWR_LEN] = {0};
643
644 SET_8703B_H2CCMD_BT_PWR_IDX(u1BTPwrIdxParm, PwrIdx);
645
646
647 FillH2CCmd8703B(Adapter, H2C_8703B_FORCE_BT_TXPWR, H2C_FORCE_BT_TXPWR_LEN, u1BTPwrIdxParm);
648 }
649
650 /*
651 * Description: WLAN Fw will write BT Fw to BT XRAM and signal driver.
652 *
653 * 2011.10.20. by tynli.
654 * */
655 int
_CheckWLANFwPatchBTFwReady(PADAPTER Adapter,BOOLEAN bRecover)656 _CheckWLANFwPatchBTFwReady(
657 PADAPTER Adapter,
658 BOOLEAN bRecover
659 )
660 {
661 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
662 u32 count = 0;
663 u8 u1bTmp;
664 int ret = _FAIL;
665
666 /* --------------------------------------------------------- */
667 /* Check if BT FW patch procedure is ready. */
668 /* --------------------------------------------------------- */
669 do {
670 u1bTmp = PlatformEFIORead1Byte(Adapter, REG_HMEBOX_DBG_0_8703B);
671 if ((u1bTmp & BIT6) || (u1bTmp & BIT7)) {
672 ret = _SUCCESS;
673 break;
674 }
675
676 count++;
677 rtw_msleep_os(50); /* 50ms */
678 } while (!((u1bTmp & BIT6) || (u1bTmp & BIT7)) && count < 50);
679
680
681
682
683 /* --------------------------------------------------------- */
684 /* Reset beacon setting to the initial value. */
685 /* --------------------------------------------------------- */
686 #if 0/* #ifdef CONFIG_PCI_HCI */
687 if (LLT_table_init(Adapter, FALSE, 0) == RT_STATUS_FAILURE) {
688 dbgdump("Init self define for BT Fw patch LLT table fail.\n");
689 /* return RT_STATUS_FAILURE; */
690 }
691 #endif
692 u1bTmp = rtw_read8(Adapter, REG_BCN_CTRL);
693 u1bTmp |= EN_BCN_FUNCTION;
694 u1bTmp &= ~DIS_TSF_UDT;
695 rtw_write8(Adapter, REG_BCN_CTRL, u1bTmp);
696
697 /* To make sure that if there exists an adapter which would like to send beacon. */
698 /* If exists, the origianl value of 0x422[6] will be 1, we should check this to */
699 /* prevent from setting 0x422[6] to 0 after download reserved page, or it will cause */
700 /* the beacon cannot be sent by HW. */
701 /* 2010.06.23. Added by tynli. */
702 if (bRecover) {
703 u1bTmp = PlatformEFIORead1Byte(Adapter, REG_FWHW_TXQ_CTRL + 2);
704 PlatformEFIOWrite1Byte(Adapter, REG_FWHW_TXQ_CTRL + 2, (u1bTmp | BIT6));
705 }
706
707 /* Clear CR[8] or beacon packet will not be send to TxBuf anymore. */
708 u1bTmp = PlatformEFIORead1Byte(Adapter, REG_CR + 1);
709 PlatformEFIOWrite1Byte(Adapter, REG_CR + 1, (u1bTmp & (~BIT0)));
710
711 return ret;
712 }
713
ReservedPage_Compare(PADAPTER Adapter,PRT_MP_FIRMWARE pFirmware,u32 BTPatchSize)714 int ReservedPage_Compare(PADAPTER Adapter, PRT_MP_FIRMWARE pFirmware, u32 BTPatchSize)
715 {
716 u8 temp, ret, lastBTsz;
717 u32 u1bTmp = 0, address_start = 0, count = 0, i = 0;
718 u8 *myBTFwBuffer = NULL;
719
720 myBTFwBuffer = rtw_zmalloc(BTPatchSize);
721 if (myBTFwBuffer == NULL) {
722 RTW_INFO("%s can't be executed due to the failed malloc.\n", __FUNCTION__);
723 Adapter->mppriv.bTxBufCkFail = _TRUE;
724 return _FALSE;
725 }
726
727 temp = rtw_read8(Adapter, 0x209);
728
729 address_start = (temp * 128) / 8;
730
731 rtw_write32(Adapter, 0x140, 0x00000000);
732 rtw_write32(Adapter, 0x144, 0x00000000);
733 rtw_write32(Adapter, 0x148, 0x00000000);
734
735 rtw_write8(Adapter, 0x106, 0x69);
736
737 for (i = 0; i < (BTPatchSize / 8); i++) {
738 rtw_write32(Adapter, 0x140, address_start + 5 + i) ;
739
740 /* polling until reg 0x140[23]=1; */
741 do {
742 u1bTmp = rtw_read32(Adapter, 0x140);
743 if (u1bTmp & BIT(23)) {
744 ret = _SUCCESS;
745 break;
746 }
747 count++;
748 RTW_INFO("0x140=%x, wait for 10 ms (%d) times.\n", u1bTmp, count);
749 rtw_msleep_os(10); /* 10ms */
750 } while (!(u1bTmp & BIT(23)) && count < 50);
751
752 myBTFwBuffer[i * 8 + 0] = rtw_read8(Adapter, 0x144);
753 myBTFwBuffer[i * 8 + 1] = rtw_read8(Adapter, 0x145);
754 myBTFwBuffer[i * 8 + 2] = rtw_read8(Adapter, 0x146);
755 myBTFwBuffer[i * 8 + 3] = rtw_read8(Adapter, 0x147);
756 myBTFwBuffer[i * 8 + 4] = rtw_read8(Adapter, 0x148);
757 myBTFwBuffer[i * 8 + 5] = rtw_read8(Adapter, 0x149);
758 myBTFwBuffer[i * 8 + 6] = rtw_read8(Adapter, 0x14a);
759 myBTFwBuffer[i * 8 + 7] = rtw_read8(Adapter, 0x14b);
760 }
761
762 rtw_write32(Adapter, 0x140, address_start + 5 + BTPatchSize / 8) ;
763
764 lastBTsz = BTPatchSize % 8;
765
766 /* polling until reg 0x140[23]=1; */
767 u1bTmp = 0;
768 count = 0;
769 do {
770 u1bTmp = rtw_read32(Adapter, 0x140);
771 if (u1bTmp & BIT(23)) {
772 ret = _SUCCESS;
773 break;
774 }
775 count++;
776 RTW_INFO("0x140=%x, wait for 10 ms (%d) times.\n", u1bTmp, count);
777 rtw_msleep_os(10); /* 10ms */
778 } while (!(u1bTmp & BIT(23)) && count < 50);
779
780 for (i = 0; i < lastBTsz; i++)
781 myBTFwBuffer[(BTPatchSize / 8) * 8 + i] = rtw_read8(Adapter, (0x144 + i));
782
783
784 for (i = 0; i < BTPatchSize; i++) {
785 if (myBTFwBuffer[i] != pFirmware->szFwBuffer[i]) {
786 RTW_INFO(" In direct myBTFwBuffer[%d]=%x , pFirmware->szFwBuffer=%x\n", i, myBTFwBuffer[i], pFirmware->szFwBuffer[i]);
787 Adapter->mppriv.bTxBufCkFail = _TRUE;
788 break;
789 }
790 }
791
792 if (myBTFwBuffer != NULL)
793 rtw_mfree(myBTFwBuffer, BTPatchSize);
794
795 return _TRUE;
796 }
797
798 /* As the size of bt firmware is more than 16k which is too big for some platforms, we divide it
799 * into four parts to transfer. The last parameter of _WriteBTFWtoTxPktBuf8703B is used to indicate
800 * the location of every part. We call the first 4096 byte of bt firmware as part 1, the second 4096
801 * part as part 2, the third 4096 part as part 3, the remain as part 4. First we transform the part
802 * 4 and set the register 0x209 to 0x90, then the 32 bytes description are added to the head of part
803 * 4, and those bytes are putted at the location 0x90. Second we transform the part 3 and set the
804 * register 0x209 to 0x70. The 32 bytes description and part 3(4196 bytes) are putted at the location
805 * 0x70. It can contain 4196 bytes between 0x70 and 0x90. So the last 32 bytes os part 3 will cover the
806 * 32 bytes description of part4. Using this method, we can put the whole bt firmware to 0x30 and only
807 * has 32 bytes descrption at the head of part 1.
808 */
FirmwareDownloadBT(PADAPTER padapter,PRT_MP_FIRMWARE pFirmware)809 s32 FirmwareDownloadBT(PADAPTER padapter, PRT_MP_FIRMWARE pFirmware)
810 {
811 s32 rtStatus;
812 u8 *pBTFirmwareBuf;
813 u32 BTFirmwareLen;
814 u8 download_time;
815 s8 i;
816 BOOLEAN bRecover = _FALSE;
817
818 rtStatus = _SUCCESS;
819 pBTFirmwareBuf = NULL;
820 BTFirmwareLen = 0;
821
822 #if 0
823 /* */
824 /* Patch BT Fw. Download BT RAM code to Tx packet buffer. */
825 /* */
826 if (padapter->bBTFWReady) {
827 RTW_INFO("%s: BT Firmware is ready!!\n", __FUNCTION__);
828 return _FAIL;
829 }
830
831 #ifdef CONFIG_FILE_FWIMG
832 if (rtw_is_file_readable(rtw_fw_mp_bt_file_path) == _TRUE) {
833 RTW_INFO("%s: accquire MP BT FW from file:%s\n", __FUNCTION__, rtw_fw_mp_bt_file_path);
834
835 rtStatus = rtw_retrieve_from_file(rtw_fw_mp_bt_file_path, FwBuffer, FW_8703B_SIZE);
836 BTFirmwareLen = rtStatus >= 0 ? rtStatus : 0;
837 pBTFirmwareBuf = FwBuffer;
838 } else
839 #endif /* CONFIG_FILE_FWIMG */
840 {
841 #ifdef CONFIG_EMBEDDED_FWIMG
842 RTW_INFO("%s: Download MP BT FW from header\n", __FUNCTION__);
843
844 pBTFirmwareBuf = (u8 *)Rtl8703BFwBTImgArray;
845 BTFirmwareLen = Rtl8703BFwBTImgArrayLength;
846 pFirmware->szFwBuffer = pBTFirmwareBuf;
847 pFirmware->ulFwLength = BTFirmwareLen;
848 #endif /* CONFIG_EMBEDDED_FWIMG */
849 }
850
851 RTW_INFO("%s: MP BT Firmware size=%d\n", __FUNCTION__, BTFirmwareLen);
852
853 /* for h2c cam here should be set to true */
854 GET_HAL_DATA(padapter)->bFWReady = _TRUE;
855
856 download_time = (BTFirmwareLen + 4095) / 4096;
857 RTW_INFO("%s: download_time is %d\n", __FUNCTION__, download_time);
858
859 if (PlatformEFIORead1Byte(Adapter, REG_FWHW_TXQ_CTRL + 2) & BIT6)
860 bRecover = TRUE;
861
862 /* Download BT patch Fw. */
863 for (i = (download_time - 1); i >= 0; i--) {
864 if (i == (download_time - 1)) {
865 rtStatus = _WriteBTFWtoTxPktBuf8703B(padapter, pBTFirmwareBuf + (4096 * i), (BTFirmwareLen - (4096 * i)), 1);
866 RTW_INFO("%s: start %d, len %d, time 1\n", __FUNCTION__, 4096 * i, BTFirmwareLen - (4096 * i));
867 } else {
868 rtStatus = _WriteBTFWtoTxPktBuf8703B(padapter, pBTFirmwareBuf + (4096 * i), 4096, (download_time - i));
869 RTW_INFO("%s: start %d, len 4096, time %d\n", __FUNCTION__, 4096 * i, download_time - i);
870 }
871
872 if (rtStatus != _SUCCESS) {
873 RTW_INFO("%s: BT Firmware download to Tx packet buffer fail!\n", __FUNCTION__);
874 padapter->bBTFWReady = _FALSE;
875 return rtStatus;
876 }
877 }
878
879 ReservedPage_Compare(padapter, pFirmware, BTFirmwareLen);
880
881 padapter->bBTFWReady = _TRUE;
882 SetFwBTFwPatchCmd(padapter, (u16)BTFirmwareLen);
883 rtStatus = _CheckWLANFwPatchBTFwReady(padapter, bRecover);
884
885 RTW_INFO("<===%s: return %s!\n", __FUNCTION__, rtStatus == _SUCCESS ? "SUCCESS" : "FAIL");
886 #endif
887
888 return rtStatus;
889 }
890 #endif /* CONFIG_MP_INCLUDED */
891
892 #if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
rtl8703b_cal_txdesc_chksum(struct tx_desc * ptxdesc)893 void rtl8703b_cal_txdesc_chksum(struct tx_desc *ptxdesc)
894 {
895 u16 *usPtr = (u16 *)ptxdesc;
896 u32 count;
897 u32 index;
898 u16 checksum = 0;
899
900
901 /* Clear first */
902 ptxdesc->txdw7 &= cpu_to_le32(0xffff0000);
903
904 /* checksume is always calculated by first 32 bytes, */
905 /* and it doesn't depend on TX DESC length. */
906 /* Thomas,Lucas@SD4,20130515 */
907 count = 16;
908
909 for (index = 0; index < count; index++)
910 checksum ^= le16_to_cpu(*(usPtr + index));
911
912 ptxdesc->txdw7 |= cpu_to_le32(checksum & 0x0000ffff);
913 }
914 #endif
915
916 #ifdef CONFIG_SDIO_HCI
send_fw_packet(PADAPTER padapter,u8 * pRam_code,u32 length)917 u8 send_fw_packet(PADAPTER padapter, u8 *pRam_code, u32 length)
918 {
919 struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
920 struct xmit_buf xmit_buf_tmp;
921 struct submit_ctx sctx_tmp;
922 u8 *pTx_data_buffer = NULL;
923 u8 *pTmp_buffer = NULL;
924 u32 modify_ram_size;
925 u32 tmp_size, tmp_value;
926 u8 value8;
927 u32 i, counter;
928 u8 bRet;
929 u32 dwDataLength, writeLength;
930
931 /* Due to SDIO can not send 32K packet */
932 if (FW_DOWNLOAD_SIZE_8703B == length)
933 length--;
934
935 modify_ram_size = length << 2;
936 pTx_data_buffer = rtw_zmalloc(modify_ram_size);
937
938 if (NULL == pTx_data_buffer) {
939 RTW_INFO("Allocate buffer fail!!\n");
940 return _FALSE;
941 }
942
943 _rtw_memset(pTx_data_buffer, 0, modify_ram_size);
944
945 /* Transfer to new format */
946 tmp_size = length >> 1;
947 for (i = 0; i <= tmp_size; i++) {
948 *(pTx_data_buffer + i * 8) = *(pRam_code + i * 2);
949 *(pTx_data_buffer + i * 8 + 1) = *(pRam_code + i * 2 + 1);
950 }
951
952 /* Gen TX_DESC */
953 _rtw_memset(pTx_data_buffer, 0, TXDESC_SIZE);
954 pTmp_buffer = pTx_data_buffer;
955 #if 0
956 pTmp_buffer->qsel = BcnQsel;
957 pTmp_buffer->txpktsize = modify_ram_size - TXDESC_SIZE;
958 pTmp_buffer->offset = TXDESC_SIZE;
959 #else
960 SET_TX_DESC_QUEUE_SEL_8703B(pTmp_buffer, QSLT_BEACON);
961 SET_TX_DESC_PKT_SIZE_8703B(pTmp_buffer, modify_ram_size - TXDESC_SIZE);
962 SET_TX_DESC_OFFSET_8703B(pTmp_buffer, TXDESC_SIZE);
963 #endif
964 rtl8703b_cal_txdesc_chksum((struct tx_desc *)pTmp_buffer);
965
966
967 /* Send packet */
968 #if 0
969 dwDataLength = modify_ram_size;
970 overlap.Offset = 0;
971 overlap.OffsetHigh = 0;
972 overlap.hEvent = CreateEvent(NULL, FALSE, FALSE, NULL);
973 bRet = WriteFile(HalVari.hFile_Queue[TX_BCNQ]->handle, pTx_data_buffer, dwDataLength, &writeLength, &overlap);
974 if (WaitForSingleObject(overlap.hEvent, INFINITE) == WAIT_OBJECT_0) {
975
976 GetOverlappedResult(HalVari.hFile_Queue[TX_BCNQ]->handle, &overlap, &writeLength, FALSE);
977 if (writeLength != dwDataLength) {
978 TCHAR editbuf[100];
979 sprintf(editbuf, "DL FW Length Err: Write length error:bRet %d writeLength %ld dwDataLength %ld, Error Code:%ld", bRet, writeLength, dwDataLength, GetLastError());
980 AfxMessageBox(editbuf, MB_OK | MB_ICONERROR);
981 return FALSE;
982 }
983 }
984 CloseHandle(overlap.hEvent);
985 #else
986 xmit_buf_tmp.pdata = pTx_data_buffer;
987 xmit_buf_tmp.len = modify_ram_size;
988 rtw_sctx_init(&sctx_tmp, 10);
989 xmit_buf_tmp.sctx = &sctx_tmp;
990 if (rtw_write_port(padapter, pdvobjpriv->Queue2Pipe[BCN_QUEUE_INX], xmit_buf_tmp.len, (u8 *)&xmit_buf_tmp) == _FAIL) {
991 RTW_INFO("rtw_write_port fail\n");
992 return _FAIL;
993 }
994 #endif
995
996 /* check if DMA is OK */
997 counter = 100;
998 do {
999 if (0 == counter) {
1000 RTW_INFO("DMA time out!!\n");
1001 return _FALSE;
1002 }
1003 value8 = rtw_read8(padapter, REG_DWBCN0_CTRL_8703B + 2);
1004 counter--;
1005 } while (0 == (value8 & BIT(0)));
1006
1007 rtw_write8(padapter, REG_DWBCN0_CTRL_8703B + 2, value8);
1008
1009 /* Modify ram code by IO method */
1010 tmp_value = rtw_read8(padapter, REG_MCUFWDL + 1);
1011 /* Disable DMA */
1012 rtw_write8(padapter, REG_MCUFWDL + 1, (u8)tmp_value & ~(BIT(5)));
1013 tmp_value = (tmp_value >> 6) << 1;
1014 /* Set page start address */
1015 rtw_write8(padapter, REG_MCUFWDL + 2, (rtw_read8(padapter, REG_MCUFWDL + 2) & 0xF8) | tmp_value);
1016 tmp_size = TXDESC_SIZE >> 2; /* 10bytes */
1017 #if 0
1018 IO_Func.WriteRegister(0x1000, (u16)tmp_size, pRam_code);
1019 #else
1020 _BlockWrite(padapter, pRam_code, tmp_size);
1021 #endif
1022
1023 if (pTmp_buffer != NULL)
1024 rtw_mfree((u8 *)pTmp_buffer, modify_ram_size);
1025
1026 return _TRUE;
1027 }
1028 #endif /* CONFIG_SDIO_HCI */
1029
1030 /*
1031 * Description:
1032 * Download 8192C firmware code.
1033 *
1034 * */
rtl8703b_FirmwareDownload(PADAPTER padapter,BOOLEAN bUsedWoWLANFw)1035 s32 rtl8703b_FirmwareDownload(PADAPTER padapter, BOOLEAN bUsedWoWLANFw)
1036 {
1037 s32 rtStatus = _SUCCESS;
1038 u8 write_fw = 0;
1039 systime fwdl_start_time;
1040 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
1041 u8 *FwImage;
1042 u32 FwImageLen;
1043 u8 *pFwImageFileName;
1044 #ifdef CONFIG_WOWLAN
1045 u8 *FwImageWoWLAN;
1046 u32 FwImageWoWLANLen;
1047 #endif
1048 u8 *pucMappedFile = NULL;
1049 PRT_FIRMWARE_8703B pFirmware = NULL;
1050 PRT_8703B_FIRMWARE_HDR pFwHdr = NULL;
1051 u8 *pFirmwareBuf;
1052 u32 FirmwareLen;
1053 #ifdef CONFIG_FILE_FWIMG
1054 u8 *fwfilepath;
1055 #endif /* CONFIG_FILE_FWIMG */
1056 u8 value8;
1057 u16 value16;
1058 u32 value32;
1059 u8 dma_iram_sel;
1060 u16 new_chk_sum = 0;
1061 u32 send_pkt_size, pkt_size_tmp;
1062 u32 mem_offset;
1063 u32 counter;
1064 struct dvobj_priv *psdpriv = padapter->dvobj;
1065 struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
1066 struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
1067
1068
1069 pFirmware = (PRT_FIRMWARE_8703B)rtw_zmalloc(sizeof(RT_FIRMWARE_8703B));
1070
1071 if (!pFirmware) {
1072 rtStatus = _FAIL;
1073 goto exit;
1074 }
1075
1076 {
1077 u8 tmp_ps = 0, tmp_rf = 0;
1078 tmp_ps = rtw_read8(padapter, 0xa3);
1079 tmp_ps &= 0xf8;
1080 tmp_ps |= 0x02;
1081 /* 1. write 0xA3[:2:0] = 3b'010 */
1082 rtw_write8(padapter, 0xa3, tmp_ps);
1083 /* 2. read power_state = 0xA0[1:0] */
1084 tmp_ps = rtw_read8(padapter, 0xa0);
1085 tmp_ps &= 0x03;
1086 if (tmp_ps != 0x01) {
1087 RTW_INFO(FUNC_ADPT_FMT" tmp_ps=%x\n", FUNC_ADPT_ARG(padapter), tmp_ps);
1088 pdbgpriv->dbg_downloadfw_pwr_state_cnt++;
1089 }
1090 }
1091
1092 #ifdef CONFIG_BT_COEXIST
1093 rtw_btcoex_PreLoadFirmware(padapter);
1094 #endif /* CONFIG_BT_COEXIST */
1095
1096 #ifdef CONFIG_FILE_FWIMG
1097 #ifdef CONFIG_WOWLAN
1098 if (bUsedWoWLANFw)
1099 fwfilepath = rtw_fw_wow_file_path;
1100 else
1101 #endif /* CONFIG_WOWLAN */
1102 {
1103 fwfilepath = rtw_fw_file_path;
1104 }
1105 #endif /* CONFIG_FILE_FWIMG */
1106
1107 #ifdef CONFIG_FILE_FWIMG
1108 if (rtw_is_file_readable(fwfilepath) == _TRUE) {
1109 RTW_INFO("%s accquire FW from file:%s\n", __FUNCTION__, fwfilepath);
1110 pFirmware->eFWSource = FW_SOURCE_IMG_FILE;
1111 } else
1112 #endif /* CONFIG_FILE_FWIMG */
1113 {
1114 #ifdef CONFIG_EMBEDDED_FWIMG
1115 pFirmware->eFWSource = FW_SOURCE_HEADER_FILE;
1116 #else /* !CONFIG_EMBEDDED_FWIMG */
1117 pFirmware->eFWSource = FW_SOURCE_IMG_FILE; /* We should decided by Reg. */
1118 #endif /* !CONFIG_EMBEDDED_FWIMG */
1119 }
1120
1121 switch (pFirmware->eFWSource) {
1122 case FW_SOURCE_IMG_FILE:
1123 #ifdef CONFIG_FILE_FWIMG
1124 rtStatus = rtw_retrieve_from_file(fwfilepath, FwBuffer, FW_8703B_SIZE);
1125 pFirmware->ulFwLength = rtStatus >= 0 ? rtStatus : 0;
1126 pFirmware->szFwBuffer = FwBuffer;
1127 #endif /* CONFIG_FILE_FWIMG */
1128 break;
1129
1130 case FW_SOURCE_HEADER_FILE:
1131 if (bUsedWoWLANFw) {
1132 #ifdef CONFIG_WOWLAN
1133 if (pwrpriv->wowlan_mode) {
1134 pFirmware->szFwBuffer = array_mp_8703b_fw_wowlan;
1135 pFirmware->ulFwLength = array_length_mp_8703b_fw_wowlan;
1136
1137 RTW_INFO(" ===> %s fw: %s, size: %d\n",
1138 __FUNCTION__, "WoWLAN",
1139 pFirmware->ulFwLength);
1140 }
1141 #endif /*CONFIG_WOWLAN*/
1142
1143 #ifdef CONFIG_AP_WOWLAN
1144 if (pwrpriv->wowlan_ap_mode) {
1145 pFirmware->szFwBuffer = array_mp_8703b_fw_ap;
1146 pFirmware->ulFwLength = array_length_mp_8703b_fw_ap;
1147
1148 RTW_INFO(" ===> %s fw: %s, size: %d\n",
1149 __FUNCTION__, "AP_WoWLAN",
1150 pFirmware->ulFwLength);
1151 }
1152 #endif /* CONFIG_AP_WOWLAN */
1153 } else {
1154 pFirmware->szFwBuffer = array_mp_8703b_fw_nic;
1155 pFirmware->ulFwLength = array_length_mp_8703b_fw_nic;
1156 RTW_INFO("%s fw: %s, size: %d\n", __FUNCTION__, "FW_NIC", pFirmware->ulFwLength);
1157 }
1158 break;
1159 }
1160
1161 if ((pFirmware->ulFwLength - 32) > FW_8703B_SIZE) {
1162 rtStatus = _FAIL;
1163 RTW_ERR("Firmware size:%u exceed %u\n", pFirmware->ulFwLength, FW_8703B_SIZE);
1164 goto exit;
1165 }
1166
1167 pFirmwareBuf = pFirmware->szFwBuffer;
1168 FirmwareLen = pFirmware->ulFwLength;
1169
1170 /* To Check Fw header. Added by tynli. 2009.12.04. */
1171 pFwHdr = (PRT_8703B_FIRMWARE_HDR)pFirmwareBuf;
1172
1173 pHalData->firmware_version = le16_to_cpu(pFwHdr->Version);
1174 pHalData->firmware_sub_version = le16_to_cpu(pFwHdr->Subversion);
1175 pHalData->FirmwareSignature = le16_to_cpu(pFwHdr->Signature);
1176
1177 RTW_INFO("%s: fw_ver=%x fw_subver=%04x sig=0x%x, Month=%02x, Date=%02x, Hour=%02x, Minute=%02x\n",
1178 __FUNCTION__, pHalData->firmware_version, pHalData->firmware_sub_version, pHalData->FirmwareSignature
1179 , pFwHdr->Month, pFwHdr->Date, pFwHdr->Hour, pFwHdr->Minute);
1180
1181 if (IS_FW_HEADER_EXIST_8703B(pFwHdr)) {
1182 RTW_INFO("%s(): Shift for fw header!\n", __FUNCTION__);
1183 /* Shift 32 bytes for FW header */
1184 pFirmwareBuf = pFirmwareBuf + 32;
1185 FirmwareLen = FirmwareLen - 32;
1186 }
1187
1188 fwdl_start_time = rtw_get_current_time();
1189
1190 #if 1
1191 RTW_INFO("%s by IO write!\n", __FUNCTION__);
1192
1193
1194 /* To check if FW already exists before download FW */
1195 if (rtw_read8(padapter, REG_MCUFWDL) & RAM_DL_SEL) {
1196 rtw_write8(padapter, REG_MCUFWDL, 0x00);
1197 _8051Reset8703(padapter);
1198 }
1199
1200 _FWDownloadEnable(padapter, _TRUE);
1201
1202 while (!RTW_CANNOT_IO(padapter)
1203 && (write_fw++ < 3 || rtw_get_passing_time_ms(fwdl_start_time) < 500)) {
1204 /* reset FWDL chksum */
1205 rtw_write8(padapter, REG_MCUFWDL, rtw_read8(padapter, REG_MCUFWDL) | FWDL_ChkSum_rpt);
1206
1207 rtStatus = _WriteFW(padapter, pFirmwareBuf, FirmwareLen);
1208 if (rtStatus != _SUCCESS)
1209 continue;
1210
1211 rtStatus = polling_fwdl_chksum(padapter, 5, 50);
1212 if (rtStatus == _SUCCESS)
1213 break;
1214 }
1215 #else
1216 RTW_INFO("%s by Tx pkt write!\n", __FUNCTION__);
1217
1218 if ((rtw_read8(padapter, REG_MCUFWDL) & MCUFWDL_RDY) == 0) {
1219 /* DLFW use HIQ only */
1220 value32 = 0xFF | BIT(31);
1221 rtw_write32(padapter, REG_RQPN, value32);
1222
1223 /* Set beacon boundary to TXFIFO header */
1224 rtw_write8(padapter, REG_BCNQ_BDNY, 0);
1225 rtw_write16(padapter, REG_DWBCN0_CTRL_8703B + 1, BIT(8));
1226
1227 /* SDIO need read this register before send packet */
1228 rtw_read32(padapter, 0x10250020);
1229
1230 _FWDownloadEnable(padapter, _TRUE);
1231
1232 /* Get original check sum */
1233 new_chk_sum = *(pFirmwareBuf + FirmwareLen - 2) | ((u16)*(pFirmwareBuf + FirmwareLen - 1) << 8);
1234
1235 /* Send ram code flow */
1236 dma_iram_sel = 0;
1237 mem_offset = 0;
1238 pkt_size_tmp = FirmwareLen;
1239 while (0 != pkt_size_tmp) {
1240 if (pkt_size_tmp >= FW_DOWNLOAD_SIZE_8703B) {
1241 send_pkt_size = FW_DOWNLOAD_SIZE_8703B;
1242 /* Modify check sum value */
1243 new_chk_sum = (u16)(new_chk_sum ^ (((send_pkt_size - 1) << 2) - TXDESC_SIZE));
1244 } else {
1245 send_pkt_size = pkt_size_tmp;
1246 new_chk_sum = (u16)(new_chk_sum ^ ((send_pkt_size << 2) - TXDESC_SIZE));
1247
1248 }
1249
1250 if (send_pkt_size == pkt_size_tmp) {
1251 /* last partition packet, write new check sum to ram code file */
1252 *(pFirmwareBuf + FirmwareLen - 2) = new_chk_sum & 0xFF;
1253 *(pFirmwareBuf + FirmwareLen - 1) = (new_chk_sum & 0xFF00) >> 8;
1254 }
1255
1256 /* IRAM select */
1257 rtw_write8(padapter, REG_MCUFWDL + 1, (rtw_read8(padapter, REG_MCUFWDL + 1) & 0x3F) | (dma_iram_sel << 6));
1258 /* Enable DMA */
1259 rtw_write8(padapter, REG_MCUFWDL + 1, rtw_read8(padapter, REG_MCUFWDL + 1) | BIT(5));
1260
1261 if (_FALSE == send_fw_packet(padapter, pFirmwareBuf + mem_offset, send_pkt_size)) {
1262 RTW_INFO("%s: Send FW fail !\n", __FUNCTION__);
1263 rtStatus = _FAIL;
1264 goto DLFW_FAIL;
1265 }
1266
1267 dma_iram_sel++;
1268 mem_offset += send_pkt_size;
1269 pkt_size_tmp -= send_pkt_size;
1270 }
1271 } else {
1272 RTW_INFO("%s: Downlad FW fail since MCUFWDL_RDY is not set!\n", __FUNCTION__);
1273 rtStatus = _FAIL;
1274 goto DLFW_FAIL;
1275 }
1276 #endif
1277
1278 _FWDownloadEnable(padapter, _FALSE);
1279
1280 rtStatus = _FWFreeToGo(padapter, 10, 200);
1281 if (_SUCCESS != rtStatus)
1282 goto DLFW_FAIL;
1283
1284 RTW_INFO("%s: DLFW OK !\n", __FUNCTION__);
1285
1286 DLFW_FAIL:
1287 if (rtStatus == _FAIL) {
1288 /* Disable FWDL_EN */
1289 value8 = rtw_read8(padapter, REG_MCUFWDL);
1290 value8 = (value8 & ~(BIT(0)) & ~(BIT(1)));
1291 rtw_write8(padapter, REG_MCUFWDL, value8);
1292 }
1293
1294 RTW_INFO("%s %s. write_fw:%u, %dms\n"
1295 , __FUNCTION__, (rtStatus == _SUCCESS) ? "success" : "fail"
1296 , write_fw
1297 , rtw_get_passing_time_ms(fwdl_start_time)
1298 );
1299
1300 exit:
1301 if (pFirmware)
1302 rtw_mfree((u8 *)pFirmware, sizeof(RT_FIRMWARE_8703B));
1303
1304 rtl8703b_InitializeFirmwareVars(padapter);
1305
1306 RTW_INFO(" <=== %s()\n", __FUNCTION__);
1307
1308 return rtStatus;
1309 }
1310
rtl8703b_InitializeFirmwareVars(PADAPTER padapter)1311 void rtl8703b_InitializeFirmwareVars(PADAPTER padapter)
1312 {
1313 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
1314
1315 /* Init Fw LPS related. */
1316 adapter_to_pwrctl(padapter)->bFwCurrentInPSMode = _FALSE;
1317
1318 /* Init H2C cmd. */
1319 rtw_write8(padapter, REG_HMETFR, 0x0f);
1320
1321 /* Init H2C counter. by tynli. 2009.12.09. */
1322 pHalData->LastHMEBoxNum = 0;
1323 /* pHalData->H2CQueueHead = 0;
1324 * pHalData->H2CQueueTail = 0;
1325 * pHalData->H2CStopInsertQueue = _FALSE; */
1326 }
1327
1328 /* ***********************************************************
1329 * Efuse related code
1330 * *********************************************************** */
1331 static u8
hal_EfuseSwitchToBank(PADAPTER padapter,u8 bank,u8 bPseudoTest)1332 hal_EfuseSwitchToBank(
1333 PADAPTER padapter,
1334 u8 bank,
1335 u8 bPseudoTest)
1336 {
1337 u8 bRet = _FALSE;
1338 u32 value32 = 0;
1339 #ifdef HAL_EFUSE_MEMORY
1340 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
1341 PEFUSE_HAL pEfuseHal = &pHalData->EfuseHal;
1342 #endif
1343
1344
1345 RTW_INFO("%s: Efuse switch bank to %d\n", __FUNCTION__, bank);
1346 if (bPseudoTest) {
1347 #ifdef HAL_EFUSE_MEMORY
1348 pEfuseHal->fakeEfuseBank = bank;
1349 #else
1350 fakeEfuseBank = bank;
1351 #endif
1352 bRet = _TRUE;
1353 } else {
1354 value32 = rtw_read32(padapter, EFUSE_TEST);
1355 bRet = _TRUE;
1356 switch (bank) {
1357 case 0:
1358 value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0);
1359 break;
1360 case 1:
1361 value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_BT_SEL_0);
1362 break;
1363 case 2:
1364 value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_BT_SEL_1);
1365 break;
1366 case 3:
1367 value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_BT_SEL_2);
1368 break;
1369 default:
1370 value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0);
1371 bRet = _FALSE;
1372 break;
1373 }
1374 rtw_write32(padapter, EFUSE_TEST, value32);
1375 }
1376
1377 return bRet;
1378 }
1379
1380 static void
Hal_GetEfuseDefinition(PADAPTER padapter,u8 efuseType,u8 type,void * pOut,u8 bPseudoTest)1381 Hal_GetEfuseDefinition(
1382 PADAPTER padapter,
1383 u8 efuseType,
1384 u8 type,
1385 void *pOut,
1386 u8 bPseudoTest)
1387 {
1388 switch (type) {
1389 case TYPE_EFUSE_MAX_SECTION: {
1390 u8 *pMax_section;
1391 pMax_section = (u8 *)pOut;
1392
1393 if (efuseType == EFUSE_WIFI)
1394 *pMax_section = EFUSE_MAX_SECTION_8703B;
1395 else
1396 *pMax_section = EFUSE_BT_MAX_SECTION;
1397 }
1398 break;
1399
1400 case TYPE_EFUSE_REAL_CONTENT_LEN: {
1401 u16 *pu2Tmp;
1402 pu2Tmp = (u16 *)pOut;
1403
1404 if (efuseType == EFUSE_WIFI)
1405 *pu2Tmp = EFUSE_REAL_CONTENT_LEN_8703B;
1406 else
1407 *pu2Tmp = EFUSE_BT_REAL_CONTENT_LEN;
1408 }
1409 break;
1410
1411 case TYPE_AVAILABLE_EFUSE_BYTES_BANK: {
1412 u16 *pu2Tmp;
1413 pu2Tmp = (u16 *)pOut;
1414
1415 if (efuseType == EFUSE_WIFI)
1416 *pu2Tmp = (EFUSE_REAL_CONTENT_LEN_8703B - EFUSE_OOB_PROTECT_BYTES);
1417 else
1418 *pu2Tmp = (EFUSE_BT_REAL_BANK_CONTENT_LEN - EFUSE_PROTECT_BYTES_BANK);
1419 }
1420 break;
1421
1422 case TYPE_AVAILABLE_EFUSE_BYTES_TOTAL: {
1423 u16 *pu2Tmp;
1424 pu2Tmp = (u16 *)pOut;
1425
1426 if (efuseType == EFUSE_WIFI)
1427 *pu2Tmp = (EFUSE_REAL_CONTENT_LEN_8703B - EFUSE_OOB_PROTECT_BYTES);
1428 else
1429 *pu2Tmp = (EFUSE_BT_REAL_CONTENT_LEN - (EFUSE_PROTECT_BYTES_BANK * 3));
1430 }
1431 break;
1432
1433 case TYPE_EFUSE_MAP_LEN: {
1434 u16 *pu2Tmp;
1435 pu2Tmp = (u16 *)pOut;
1436
1437 if (efuseType == EFUSE_WIFI)
1438 *pu2Tmp = EFUSE_MAP_LEN_8703B;
1439 else
1440 *pu2Tmp = EFUSE_BT_MAP_LEN;
1441 }
1442 break;
1443
1444 case TYPE_EFUSE_PROTECT_BYTES_BANK: {
1445 u8 *pu1Tmp;
1446 pu1Tmp = (u8 *)pOut;
1447
1448 if (efuseType == EFUSE_WIFI)
1449 *pu1Tmp = EFUSE_OOB_PROTECT_BYTES;
1450 else
1451 *pu1Tmp = EFUSE_PROTECT_BYTES_BANK;
1452 }
1453 break;
1454
1455 case TYPE_EFUSE_CONTENT_LEN_BANK: {
1456 u16 *pu2Tmp;
1457 pu2Tmp = (u16 *)pOut;
1458
1459 if (efuseType == EFUSE_WIFI)
1460 *pu2Tmp = EFUSE_REAL_CONTENT_LEN_8703B;
1461 else
1462 *pu2Tmp = EFUSE_BT_REAL_BANK_CONTENT_LEN;
1463 }
1464 break;
1465
1466 default: {
1467 u8 *pu1Tmp;
1468 pu1Tmp = (u8 *)pOut;
1469 *pu1Tmp = 0;
1470 }
1471 break;
1472 }
1473 }
1474
1475 #define VOLTAGE_V25 0x03
1476 #define LDOE25_SHIFT 28
1477
1478 /* *****************************************************************
1479 * The following is for compile ok
1480 * That should be merged with the original in the future
1481 * ***************************************************************** */
1482 #define EFUSE_ACCESS_ON_8703 0x69 /* For RTL8703 only. */
1483 #define EFUSE_ACCESS_OFF_8703 0x00 /* For RTL8703 only. */
1484 #define REG_EFUSE_ACCESS_8703 0x00CF /* Efuse access protection for RTL8703 */
1485
1486 /* ***************************************************************** */
Hal_BT_EfusePowerSwitch(PADAPTER padapter,u8 bWrite,u8 PwrState)1487 static void Hal_BT_EfusePowerSwitch(
1488 PADAPTER padapter,
1489 u8 bWrite,
1490 u8 PwrState)
1491 {
1492 u8 tempval;
1493 if (PwrState == _TRUE) {
1494 /* enable BT power cut */
1495 /* 0x6A[14] = 1 */
1496 tempval = rtw_read8(padapter, 0x6B);
1497 tempval |= BIT(6);
1498 rtw_write8(padapter, 0x6B, tempval);
1499
1500 /* Attention!! Between 0x6A[14] and 0x6A[15] setting need 100us delay */
1501 /* So don't wirte 0x6A[14]=1 and 0x6A[15]=0 together! */
1502 rtw_usleep_os(100);
1503 /* disable BT output isolation */
1504 /* 0x6A[15] = 0 */
1505 tempval = rtw_read8(padapter, 0x6B);
1506 tempval &= ~BIT(7);
1507 rtw_write8(padapter, 0x6B, tempval);
1508 } else {
1509 /* enable BT output isolation */
1510 /* 0x6A[15] = 1 */
1511 tempval = rtw_read8(padapter, 0x6B);
1512 tempval |= BIT(7);
1513 rtw_write8(padapter, 0x6B, tempval);
1514
1515 /* Attention!! Between 0x6A[14] and 0x6A[15] setting need 100us delay */
1516 /* So don't wirte 0x6A[14]=1 and 0x6A[15]=0 together! */
1517
1518 /* disable BT power cut */
1519 /* 0x6A[14] = 1 */
1520 tempval = rtw_read8(padapter, 0x6B);
1521 tempval &= ~BIT(6);
1522 rtw_write8(padapter, 0x6B, tempval);
1523 }
1524
1525 }
1526 static void
Hal_EfusePowerSwitch(PADAPTER padapter,u8 bWrite,u8 PwrState)1527 Hal_EfusePowerSwitch(
1528 PADAPTER padapter,
1529 u8 bWrite,
1530 u8 PwrState)
1531 {
1532 u8 tempval;
1533 u16 tmpV16;
1534
1535
1536 if (PwrState == _TRUE) {
1537 /* enable BT power cut 0x6A[14] = 1*/
1538 tempval = rtw_read8(padapter, 0x6B);
1539 tempval |= BIT(6);
1540 rtw_write8(padapter, 0x6B, tempval);
1541 #ifdef CONFIG_SDIO_HCI
1542 /* To avoid cannot access efuse regsiters after disable/enable several times during DTM test. */
1543 /* Suggested by SD1 IsaacHsu. 2013.07.08, added by tynli. */
1544 tempval = rtw_read8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HSUS_CTRL);
1545 if (tempval & BIT(0)) { /* SDIO local register is suspend */
1546 u8 count = 0;
1547
1548
1549 tempval &= ~BIT(0);
1550 rtw_write8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HSUS_CTRL, tempval);
1551
1552 /* check 0x86[1:0]=10'2h, wait power state to leave suspend */
1553 do {
1554 tempval = rtw_read8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HSUS_CTRL);
1555 tempval &= 0x3;
1556 if (tempval == 0x02)
1557 break;
1558
1559 count++;
1560 if (count >= 100)
1561 break;
1562
1563 rtw_mdelay_os(10);
1564 } while (1);
1565
1566 if (count >= 100) {
1567 RTW_INFO(FUNC_ADPT_FMT ": Leave SDIO local register suspend fail! Local 0x86=%#X\n",
1568 FUNC_ADPT_ARG(padapter), tempval);
1569 } else {
1570 RTW_INFO(FUNC_ADPT_FMT ": Leave SDIO local register suspend OK! Local 0x86=%#X\n",
1571 FUNC_ADPT_ARG(padapter), tempval);
1572 }
1573 }
1574 #endif /* CONFIG_SDIO_HCI */
1575
1576 rtw_write8(padapter, REG_EFUSE_ACCESS_8703, EFUSE_ACCESS_ON_8703);
1577
1578 /* Reset: 0x0000h[28], default valid */
1579 tmpV16 = rtw_read16(padapter, REG_SYS_FUNC_EN);
1580 if (!(tmpV16 & FEN_ELDR)) {
1581 tmpV16 |= FEN_ELDR ;
1582 rtw_write16(padapter, REG_SYS_FUNC_EN, tmpV16);
1583 }
1584
1585 /* Clock: Gated(0x0008h[5]) 8M(0x0008h[1]) clock from ANA, default valid */
1586 tmpV16 = rtw_read16(padapter, REG_SYS_CLKR);
1587 if ((!(tmpV16 & LOADER_CLK_EN)) || (!(tmpV16 & ANA8M))) {
1588 tmpV16 |= (LOADER_CLK_EN | ANA8M) ;
1589 rtw_write16(padapter, REG_SYS_CLKR, tmpV16);
1590 }
1591
1592 if (bWrite == _TRUE) {
1593 /* Enable LDO 2.5V before read/write action */
1594 tempval = rtw_read8(padapter, EFUSE_TEST + 3);
1595 tempval &= 0x0F;
1596 /*tempval |= (VOLTAGE_V25 << 4);*/
1597 tempval |= 0x70; /* 0x34[30:28] = 0b'111, Use LDO 2.25V, Suggested by SD1 Morris & Victor*/
1598 rtw_write8(padapter, EFUSE_TEST + 3, (tempval | 0x80));
1599
1600 /* rtw_write8(padapter, REG_EFUSE_ACCESS, EFUSE_ACCESS_ON); */
1601 }
1602 } else {
1603
1604 /*enable BT output isolation 0x6A[15] = 1 */
1605 tempval = rtw_read8(padapter, 0x6B);
1606 tempval |= BIT(7);
1607 rtw_write8(padapter, 0x6B, tempval);
1608
1609 rtw_write8(padapter, REG_EFUSE_ACCESS, EFUSE_ACCESS_OFF);
1610
1611 if (bWrite == _TRUE) {
1612 /* Disable LDO 2.5V after read/write action */
1613 tempval = rtw_read8(padapter, EFUSE_TEST + 3);
1614 rtw_write8(padapter, EFUSE_TEST + 3, (tempval & 0x7F));
1615 }
1616
1617 }
1618 }
1619
1620 static void
hal_ReadEFuse_WiFi(PADAPTER padapter,u16 _offset,u16 _size_byte,u8 * pbuf,u8 bPseudoTest)1621 hal_ReadEFuse_WiFi(
1622 PADAPTER padapter,
1623 u16 _offset,
1624 u16 _size_byte,
1625 u8 *pbuf,
1626 u8 bPseudoTest)
1627 {
1628 #ifdef HAL_EFUSE_MEMORY
1629 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
1630 PEFUSE_HAL pEfuseHal = &pHalData->EfuseHal;
1631 #endif
1632 u8 *efuseTbl = NULL;
1633 u16 eFuse_Addr = 0;
1634 u8 offset, wden;
1635 u8 efuseHeader, efuseExtHdr, efuseData;
1636 u16 i, total, used;
1637 u8 efuse_usage = 0;
1638
1639 /* RTW_INFO("YJ: ====>%s():_offset=%d _size_byte=%d bPseudoTest=%d\n", __func__, _offset, _size_byte, bPseudoTest); */
1640 /* */
1641 /* Do NOT excess total size of EFuse table. Added by Roger, 2008.11.10. */
1642 /* */
1643 if ((_offset + _size_byte) > EFUSE_MAX_MAP_LEN) {
1644 RTW_INFO("%s: Invalid offset(%#x) with read bytes(%#x)!!\n", __FUNCTION__, _offset, _size_byte);
1645 return;
1646 }
1647
1648 efuseTbl = (u8 *)rtw_malloc(EFUSE_MAX_MAP_LEN);
1649 if (efuseTbl == NULL) {
1650 RTW_INFO("%s: alloc efuseTbl fail!\n", __FUNCTION__);
1651 return;
1652 }
1653 /* 0xff will be efuse default value instead of 0x00. */
1654 _rtw_memset(efuseTbl, 0xFF, EFUSE_MAX_MAP_LEN);
1655
1656
1657 #ifdef CONFIG_RTW_DEBUG
1658 if (0) {
1659 for (i = 0; i < 256; i++)
1660 /* ReadEFuseByte(padapter, i, &efuseTbl[i], _FALSE); */
1661 efuse_OneByteRead(padapter, i, &efuseTbl[i], _FALSE);
1662 RTW_INFO("Efuse Content:\n");
1663 for (i = 0; i < 256; i++) {
1664 if (i % 16 == 0)
1665 printk("\n");
1666 printk("%02X ", efuseTbl[i]);
1667 }
1668 printk("\n");
1669 }
1670 #endif
1671
1672
1673 /* switch bank back to bank 0 for later BT and wifi use. */
1674 hal_EfuseSwitchToBank(padapter, 0, bPseudoTest);
1675
1676 while (AVAILABLE_EFUSE_ADDR(eFuse_Addr)) {
1677 /* ReadEFuseByte(padapter, eFuse_Addr++, &efuseHeader, bPseudoTest); */
1678 efuse_OneByteRead(padapter, eFuse_Addr++, &efuseHeader, bPseudoTest);
1679 if (efuseHeader == 0xFF) {
1680 RTW_INFO("%s: data end at address=%#x\n", __FUNCTION__, eFuse_Addr - 1);
1681 break;
1682 }
1683 /* RTW_INFO("%s: efuse[0x%X]=0x%02X\n", __FUNCTION__, eFuse_Addr-1, efuseHeader); */
1684
1685 /* Check PG header for section num. */
1686 if (EXT_HEADER(efuseHeader)) { /* extended header */
1687 offset = GET_HDR_OFFSET_2_0(efuseHeader);
1688 /* RTW_INFO("%s: extended header offset=0x%X\n", __FUNCTION__, offset); */
1689
1690 /* ReadEFuseByte(padapter, eFuse_Addr++, &efuseExtHdr, bPseudoTest); */
1691 efuse_OneByteRead(padapter, eFuse_Addr++, &efuseExtHdr, bPseudoTest);
1692 /* RTW_INFO("%s: efuse[0x%X]=0x%02X\n", __FUNCTION__, eFuse_Addr-1, efuseExtHdr); */
1693 if (ALL_WORDS_DISABLED(efuseExtHdr))
1694 continue;
1695
1696 offset |= ((efuseExtHdr & 0xF0) >> 1);
1697 wden = (efuseExtHdr & 0x0F);
1698 } else {
1699 offset = ((efuseHeader >> 4) & 0x0f);
1700 wden = (efuseHeader & 0x0f);
1701 }
1702 /* RTW_INFO("%s: Offset=%d Worden=0x%X\n", __FUNCTION__, offset, wden); */
1703
1704 if (offset < EFUSE_MAX_SECTION_8703B) {
1705 u16 addr;
1706 /* Get word enable value from PG header
1707 * RTW_INFO("%s: Offset=%d Worden=0x%X\n", __FUNCTION__, offset, wden); */
1708
1709 addr = offset * PGPKT_DATA_SIZE;
1710 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
1711 /* Check word enable condition in the section */
1712 if (!(wden & (0x01 << i))) {
1713 efuseData = 0;
1714 /* ReadEFuseByte(padapter, eFuse_Addr++, &efuseData, bPseudoTest); */
1715 efuse_OneByteRead(padapter, eFuse_Addr++, &efuseData, bPseudoTest);
1716 /* RTW_INFO("%s: efuse[%#X]=0x%02X\n", __FUNCTION__, eFuse_Addr-1, efuseData); */
1717 efuseTbl[addr] = efuseData;
1718
1719 efuseData = 0;
1720 /* ReadEFuseByte(padapter, eFuse_Addr++, &efuseData, bPseudoTest); */
1721 efuse_OneByteRead(padapter, eFuse_Addr++, &efuseData, bPseudoTest);
1722 /* RTW_INFO("%s: efuse[%#X]=0x%02X\n", __FUNCTION__, eFuse_Addr-1, efuseData); */
1723 efuseTbl[addr + 1] = efuseData;
1724 }
1725 addr += 2;
1726 }
1727 } else {
1728 RTW_ERR("%s: offset(%d) is illegal!!\n", __FUNCTION__, offset);
1729 eFuse_Addr += Efuse_CalculateWordCnts(wden) * 2;
1730 }
1731 }
1732
1733 /* Copy from Efuse map to output pointer memory!!! */
1734 for (i = 0; i < _size_byte; i++)
1735 pbuf[i] = efuseTbl[_offset + i];
1736
1737 /* Calculate Efuse utilization */
1738 total = 0;
1739 EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, &total, bPseudoTest);
1740 used = eFuse_Addr - 1;
1741 if (total)
1742 efuse_usage = (u8)((used * 100) / total);
1743 else
1744 efuse_usage = 100;
1745 if (bPseudoTest) {
1746 #ifdef HAL_EFUSE_MEMORY
1747 pEfuseHal->fakeEfuseUsedBytes = used;
1748 #else
1749 fakeEfuseUsedBytes = used;
1750 #endif
1751 } else {
1752 rtw_hal_set_hwreg(padapter, HW_VAR_EFUSE_BYTES, (u8 *)&used);
1753 rtw_hal_set_hwreg(padapter, HW_VAR_EFUSE_USAGE, (u8 *)&efuse_usage);
1754 }
1755
1756 if (efuseTbl)
1757 rtw_mfree(efuseTbl, EFUSE_MAX_MAP_LEN);
1758 }
1759
1760 static void
hal_ReadEFuse_BT(PADAPTER padapter,u16 _offset,u16 _size_byte,u8 * pbuf,u8 bPseudoTest)1761 hal_ReadEFuse_BT(
1762 PADAPTER padapter,
1763 u16 _offset,
1764 u16 _size_byte,
1765 u8 *pbuf,
1766 u8 bPseudoTest
1767 )
1768 {
1769 #ifdef HAL_EFUSE_MEMORY
1770 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
1771 PEFUSE_HAL pEfuseHal = &pHalData->EfuseHal;
1772 #endif
1773 u8 *efuseTbl;
1774 u8 bank;
1775 u16 eFuse_Addr;
1776 u8 efuseHeader, efuseExtHdr, efuseData;
1777 u8 offset, wden;
1778 u16 i, total, used;
1779 u8 efuse_usage;
1780
1781
1782 /* */
1783 /* Do NOT excess total size of EFuse table. Added by Roger, 2008.11.10. */
1784 /* */
1785 if ((_offset + _size_byte) > EFUSE_BT_MAP_LEN) {
1786 RTW_INFO("%s: Invalid offset(%#x) with read bytes(%#x)!!\n", __FUNCTION__, _offset, _size_byte);
1787 return;
1788 }
1789
1790 efuseTbl = rtw_malloc(EFUSE_BT_MAP_LEN);
1791 if (efuseTbl == NULL) {
1792 RTW_INFO("%s: efuseTbl malloc fail!\n", __FUNCTION__);
1793 return;
1794 }
1795 /* 0xff will be efuse default value instead of 0x00. */
1796 _rtw_memset(efuseTbl, 0xFF, EFUSE_BT_MAP_LEN);
1797
1798 total = 0;
1799 EFUSE_GetEfuseDefinition(padapter, EFUSE_BT, TYPE_AVAILABLE_EFUSE_BYTES_BANK, &total, bPseudoTest);
1800
1801 for (bank = 1; bank < 3; bank++) { /* 8703b Max bake 0~2 */
1802 if (hal_EfuseSwitchToBank(padapter, bank, bPseudoTest) == _FALSE) {
1803 RTW_INFO("%s: hal_EfuseSwitchToBank Fail!!\n", __FUNCTION__);
1804 goto exit;
1805 }
1806
1807 eFuse_Addr = 0;
1808
1809 while (AVAILABLE_EFUSE_ADDR(eFuse_Addr)) {
1810 /* ReadEFuseByte(padapter, eFuse_Addr++, &efuseHeader, bPseudoTest); */
1811 efuse_OneByteRead(padapter, eFuse_Addr++, &efuseHeader, bPseudoTest);
1812 if (efuseHeader == 0xFF)
1813 break;
1814 RTW_INFO("%s: efuse[%#X]=0x%02x (header)\n", __FUNCTION__, (((bank - 1) * EFUSE_REAL_CONTENT_LEN_8703B) + eFuse_Addr - 1), efuseHeader);
1815
1816 /* Check PG header for section num. */
1817 if (EXT_HEADER(efuseHeader)) { /* extended header */
1818 offset = GET_HDR_OFFSET_2_0(efuseHeader);
1819 RTW_INFO("%s: extended header offset_2_0=0x%X\n", __FUNCTION__, offset);
1820
1821 /* ReadEFuseByte(padapter, eFuse_Addr++, &efuseExtHdr, bPseudoTest); */
1822 efuse_OneByteRead(padapter, eFuse_Addr++, &efuseExtHdr, bPseudoTest);
1823 RTW_INFO("%s: efuse[%#X]=0x%02x (ext header)\n", __FUNCTION__, (((bank - 1) * EFUSE_REAL_CONTENT_LEN_8703B) + eFuse_Addr - 1), efuseExtHdr);
1824 if (ALL_WORDS_DISABLED(efuseExtHdr))
1825 continue;
1826
1827 offset |= ((efuseExtHdr & 0xF0) >> 1);
1828 wden = (efuseExtHdr & 0x0F);
1829 } else {
1830 offset = ((efuseHeader >> 4) & 0x0f);
1831 wden = (efuseHeader & 0x0f);
1832 }
1833
1834 if (offset < EFUSE_BT_MAX_SECTION) {
1835 u16 addr;
1836
1837 /* Get word enable value from PG header */
1838 RTW_INFO("%s: Offset=%d Worden=%#X\n", __FUNCTION__, offset, wden);
1839
1840 addr = offset * PGPKT_DATA_SIZE;
1841 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
1842 /* Check word enable condition in the section */
1843 if (!(wden & (0x01 << i))) {
1844 efuseData = 0;
1845 /* ReadEFuseByte(padapter, eFuse_Addr++, &efuseData, bPseudoTest); */
1846 efuse_OneByteRead(padapter, eFuse_Addr++, &efuseData, bPseudoTest);
1847 RTW_INFO("%s: efuse[%#X]=0x%02X\n", __FUNCTION__, eFuse_Addr - 1, efuseData);
1848 efuseTbl[addr] = efuseData;
1849
1850 efuseData = 0;
1851 /* ReadEFuseByte(padapter, eFuse_Addr++, &efuseData, bPseudoTest); */
1852 efuse_OneByteRead(padapter, eFuse_Addr++, &efuseData, bPseudoTest);
1853 RTW_INFO("%s: efuse[%#X]=0x%02X\n", __FUNCTION__, eFuse_Addr - 1, efuseData);
1854 efuseTbl[addr + 1] = efuseData;
1855 }
1856 addr += 2;
1857 }
1858 } else {
1859 RTW_INFO("%s: offset(%d) is illegal!!\n", __FUNCTION__, offset);
1860 eFuse_Addr += Efuse_CalculateWordCnts(wden) * 2;
1861 }
1862 }
1863
1864 if ((eFuse_Addr - 1) < total) {
1865 RTW_INFO("%s: bank(%d) data end at %#x\n", __FUNCTION__, bank, eFuse_Addr - 1);
1866 break;
1867 }
1868 }
1869
1870 /* switch bank back to bank 0 for later BT and wifi use. */
1871 hal_EfuseSwitchToBank(padapter, 0, bPseudoTest);
1872
1873 /* Copy from Efuse map to output pointer memory!!! */
1874 for (i = 0; i < _size_byte; i++)
1875 pbuf[i] = efuseTbl[_offset + i];
1876
1877 /* */
1878 /* Calculate Efuse utilization. */
1879 /* */
1880 EFUSE_GetEfuseDefinition(padapter, EFUSE_BT, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, &total, bPseudoTest);
1881 used = (EFUSE_BT_REAL_BANK_CONTENT_LEN * (bank - 1)) + eFuse_Addr - 1;
1882 RTW_INFO("%s: bank(%d) data end at %#x ,used =%d\n", __FUNCTION__, bank, eFuse_Addr - 1, used);
1883 efuse_usage = (u8)((used * 100) / total);
1884 if (bPseudoTest) {
1885 #ifdef HAL_EFUSE_MEMORY
1886 pEfuseHal->fakeBTEfuseUsedBytes = used;
1887 #else
1888 fakeBTEfuseUsedBytes = used;
1889 #endif
1890 } else {
1891 rtw_hal_set_hwreg(padapter, HW_VAR_EFUSE_BT_BYTES, (u8 *)&used);
1892 rtw_hal_set_hwreg(padapter, HW_VAR_EFUSE_BT_USAGE, (u8 *)&efuse_usage);
1893 }
1894
1895 exit:
1896 if (efuseTbl)
1897 rtw_mfree(efuseTbl, EFUSE_BT_MAP_LEN);
1898 }
1899
1900 static void
Hal_ReadEFuse(PADAPTER padapter,u8 efuseType,u16 _offset,u16 _size_byte,u8 * pbuf,u8 bPseudoTest)1901 Hal_ReadEFuse(
1902 PADAPTER padapter,
1903 u8 efuseType,
1904 u16 _offset,
1905 u16 _size_byte,
1906 u8 *pbuf,
1907 u8 bPseudoTest)
1908 {
1909 if (efuseType == EFUSE_WIFI)
1910 hal_ReadEFuse_WiFi(padapter, _offset, _size_byte, pbuf, bPseudoTest);
1911 else
1912 hal_ReadEFuse_BT(padapter, _offset, _size_byte, pbuf, bPseudoTest);
1913 }
1914
1915 static u16
hal_EfuseGetCurrentSize_WiFi(PADAPTER padapter,u8 bPseudoTest)1916 hal_EfuseGetCurrentSize_WiFi(
1917 PADAPTER padapter,
1918 u8 bPseudoTest)
1919 {
1920 #ifdef HAL_EFUSE_MEMORY
1921 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
1922 PEFUSE_HAL pEfuseHal = &pHalData->EfuseHal;
1923 #endif
1924 u16 efuse_addr = 0;
1925 u16 start_addr = 0; /* for debug */
1926 u8 hoffset = 0, hworden = 0;
1927 u8 efuse_data, word_cnts = 0;
1928 u32 count = 0; /* for debug */
1929
1930
1931 if (bPseudoTest) {
1932 #ifdef HAL_EFUSE_MEMORY
1933 efuse_addr = (u16)pEfuseHal->fakeEfuseUsedBytes;
1934 #else
1935 efuse_addr = (u16)fakeEfuseUsedBytes;
1936 #endif
1937 } else
1938 rtw_hal_get_hwreg(padapter, HW_VAR_EFUSE_BYTES, (u8 *)&efuse_addr);
1939 start_addr = efuse_addr;
1940 RTW_INFO("%s: start_efuse_addr=0x%X\n", __FUNCTION__, efuse_addr);
1941
1942 /* switch bank back to bank 0 for later BT and wifi use. */
1943 hal_EfuseSwitchToBank(padapter, 0, bPseudoTest);
1944
1945 #if 0 /* for debug test */
1946 efuse_OneByteRead(padapter, 0x1FF, &efuse_data, bPseudoTest);
1947 RTW_INFO(FUNC_ADPT_FMT ": efuse raw 0x1FF=0x%02X\n",
1948 FUNC_ADPT_ARG(padapter), efuse_data);
1949 efuse_data = 0xFF;
1950 #endif /* for debug test */
1951
1952 count = 0;
1953 while (AVAILABLE_EFUSE_ADDR(efuse_addr)) {
1954 #if 1
1955 if (efuse_OneByteRead(padapter, efuse_addr, &efuse_data, bPseudoTest) == _FALSE) {
1956 RTW_ERR("%s: efuse_OneByteRead Fail! addr=0x%X !!\n", __FUNCTION__, efuse_addr);
1957 goto error;
1958 }
1959 #else
1960 ReadEFuseByte(padapter, efuse_addr, &efuse_data, bPseudoTest);
1961 #endif
1962
1963 if (efuse_data == 0xFF)
1964 break;
1965
1966 if ((start_addr != 0) && (efuse_addr == start_addr)) {
1967 count++;
1968 RTW_INFO(FUNC_ADPT_FMT ": [WARNING] efuse raw 0x%X=0x%02X not 0xFF!!(%d times)\n",
1969 FUNC_ADPT_ARG(padapter), efuse_addr, efuse_data, count);
1970
1971 efuse_data = 0xFF;
1972 if (count < 4) {
1973 /* try again! */
1974
1975 if (count > 2) {
1976 /* try again form address 0 */
1977 efuse_addr = 0;
1978 start_addr = 0;
1979 }
1980
1981 continue;
1982 }
1983
1984 goto error;
1985 }
1986
1987 if (EXT_HEADER(efuse_data)) {
1988 hoffset = GET_HDR_OFFSET_2_0(efuse_data);
1989 efuse_addr++;
1990 efuse_OneByteRead(padapter, efuse_addr, &efuse_data, bPseudoTest);
1991 if (ALL_WORDS_DISABLED(efuse_data))
1992 continue;
1993
1994 hoffset |= ((efuse_data & 0xF0) >> 1);
1995 hworden = efuse_data & 0x0F;
1996 } else {
1997 hoffset = (efuse_data >> 4) & 0x0F;
1998 hworden = efuse_data & 0x0F;
1999 }
2000
2001 word_cnts = Efuse_CalculateWordCnts(hworden);
2002 efuse_addr += (word_cnts * 2) + 1;
2003 }
2004
2005 if (bPseudoTest) {
2006 #ifdef HAL_EFUSE_MEMORY
2007 pEfuseHal->fakeEfuseUsedBytes = efuse_addr;
2008 #else
2009 fakeEfuseUsedBytes = efuse_addr;
2010 #endif
2011 } else
2012 rtw_hal_set_hwreg(padapter, HW_VAR_EFUSE_BYTES, (u8 *)&efuse_addr);
2013
2014 goto exit;
2015
2016 error:
2017 /* report max size to prevent wirte efuse */
2018 EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, &efuse_addr, bPseudoTest);
2019
2020 exit:
2021 RTW_INFO("%s: CurrentSize=%d\n", __FUNCTION__, efuse_addr);
2022
2023 return efuse_addr;
2024 }
2025
2026 static u16
hal_EfuseGetCurrentSize_BT(PADAPTER padapter,u8 bPseudoTest)2027 hal_EfuseGetCurrentSize_BT(
2028 PADAPTER padapter,
2029 u8 bPseudoTest)
2030 {
2031 #ifdef HAL_EFUSE_MEMORY
2032 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
2033 PEFUSE_HAL pEfuseHal = &pHalData->EfuseHal;
2034 #endif
2035 u16 btusedbytes;
2036 u16 efuse_addr;
2037 u8 bank, startBank;
2038 u8 hoffset = 0, hworden = 0;
2039 u8 efuse_data, word_cnts = 0;
2040 u16 retU2 = 0;
2041 u8 bContinual = _TRUE;
2042
2043
2044 if (bPseudoTest) {
2045 #ifdef HAL_EFUSE_MEMORY
2046 btusedbytes = pEfuseHal->fakeBTEfuseUsedBytes;
2047 #else
2048 btusedbytes = fakeBTEfuseUsedBytes;
2049 #endif
2050 } else {
2051 btusedbytes = 0;
2052 rtw_hal_get_hwreg(padapter, HW_VAR_EFUSE_BT_BYTES, (u8 *)&btusedbytes);
2053 }
2054 efuse_addr = (u16)((btusedbytes % EFUSE_BT_REAL_BANK_CONTENT_LEN));
2055 startBank = (u8)(1 + (btusedbytes / EFUSE_BT_REAL_BANK_CONTENT_LEN));
2056
2057 RTW_INFO("%s: start from bank=%d addr=0x%X\n", __FUNCTION__, startBank, efuse_addr);
2058
2059 EFUSE_GetEfuseDefinition(padapter, EFUSE_BT, TYPE_AVAILABLE_EFUSE_BYTES_BANK, &retU2, bPseudoTest);
2060
2061 for (bank = startBank; bank < 3; bank++) {
2062 if (hal_EfuseSwitchToBank(padapter, bank, bPseudoTest) == _FALSE) {
2063 RTW_ERR("%s: switch bank(%d) Fail!!\n", __FUNCTION__, bank);
2064 /* bank = EFUSE_MAX_BANK; */
2065 break;
2066 }
2067
2068 /* only when bank is switched we have to reset the efuse_addr. */
2069 if (bank != startBank)
2070 efuse_addr = 0;
2071 #if 1
2072
2073 while (AVAILABLE_EFUSE_ADDR(efuse_addr)) {
2074 if (efuse_OneByteRead(padapter, efuse_addr, &efuse_data, bPseudoTest) == _FALSE) {
2075 RTW_ERR("%s: efuse_OneByteRead Fail! addr=0x%X !!\n", __FUNCTION__, efuse_addr);
2076 /* bank = EFUSE_MAX_BANK; */
2077 break;
2078 }
2079 RTW_INFO("%s: efuse_OneByteRead ! addr=0x%X !efuse_data=0x%X! bank =%d\n", __FUNCTION__, efuse_addr, efuse_data, bank);
2080
2081 if (efuse_data == 0xFF)
2082 break;
2083
2084 if (EXT_HEADER(efuse_data)) {
2085 hoffset = GET_HDR_OFFSET_2_0(efuse_data);
2086 efuse_addr++;
2087 efuse_OneByteRead(padapter, efuse_addr, &efuse_data, bPseudoTest);
2088 RTW_INFO("%s: efuse_OneByteRead EXT_HEADER ! addr=0x%X !efuse_data=0x%X! bank =%d\n", __FUNCTION__, efuse_addr, efuse_data, bank);
2089
2090 if (ALL_WORDS_DISABLED(efuse_data)) {
2091 efuse_addr++;
2092 continue;
2093 }
2094
2095 /* hoffset = ((hoffset & 0xE0) >> 5) | ((efuse_data & 0xF0) >> 1); */
2096 hoffset |= ((efuse_data & 0xF0) >> 1);
2097 hworden = efuse_data & 0x0F;
2098 } else {
2099 hoffset = (efuse_data >> 4) & 0x0F;
2100 hworden = efuse_data & 0x0F;
2101 }
2102
2103 RTW_INFO(FUNC_ADPT_FMT": Offset=%d Worden=%#X\n",
2104 FUNC_ADPT_ARG(padapter), hoffset, hworden);
2105
2106 word_cnts = Efuse_CalculateWordCnts(hworden);
2107 /* read next header */
2108 efuse_addr += (word_cnts * 2) + 1;
2109 }
2110 #else
2111 while (bContinual &&
2112 efuse_OneByteRead(padapter, efuse_addr , &efuse_data, bPseudoTest) &&
2113 AVAILABLE_EFUSE_ADDR(efuse_addr)) {
2114 if (efuse_data != 0xFF) {
2115 if ((efuse_data & 0x1F) == 0x0F) { /* extended header */
2116 hoffset = efuse_data;
2117 efuse_addr++;
2118 efuse_OneByteRead(padapter, efuse_addr , &efuse_data, bPseudoTest);
2119 if ((efuse_data & 0x0F) == 0x0F) {
2120 efuse_addr++;
2121 continue;
2122 } else {
2123 hoffset = ((hoffset & 0xE0) >> 5) | ((efuse_data & 0xF0) >> 1);
2124 hworden = efuse_data & 0x0F;
2125 }
2126 } else {
2127 hoffset = (efuse_data >> 4) & 0x0F;
2128 hworden = efuse_data & 0x0F;
2129 }
2130 word_cnts = Efuse_CalculateWordCnts(hworden);
2131 /* read next header */
2132 efuse_addr = efuse_addr + (word_cnts * 2) + 1;
2133 } else
2134 bContinual = _FALSE ;
2135 }
2136 #endif
2137
2138
2139 /* Check if we need to check next bank efuse */
2140 if (efuse_addr < retU2) {
2141 break;/* don't need to check next bank. */
2142 }
2143 }
2144 #if 0
2145 retU2 = ((bank - 1) * EFUSE_BT_REAL_BANK_CONTENT_LEN) + efuse_addr;
2146 if (bPseudoTest) {
2147 #ifdef HAL_EFUSE_MEMORY
2148 pEfuseHal->fakeBTEfuseUsedBytes = retU2;
2149 #else
2150 fakeBTEfuseUsedBytes = retU2;
2151 #endif
2152 } else
2153 rtw_hal_set_hwreg(padapter, HW_VAR_EFUSE_BT_BYTES, (u8 *)&retU2);
2154 #else
2155 retU2 = ((bank - 1) * EFUSE_BT_REAL_BANK_CONTENT_LEN) + efuse_addr;
2156 if (bPseudoTest) {
2157 pEfuseHal->fakeBTEfuseUsedBytes = retU2;
2158 /* RT_DISP(FEEPROM, EFUSE_PG, ("Hal_EfuseGetCurrentSize_BT92C(), already use %u bytes\n", pEfuseHal->fakeBTEfuseUsedBytes)); */
2159 } else {
2160 pEfuseHal->BTEfuseUsedBytes = retU2;
2161 /* RT_DISP(FEEPROM, EFUSE_PG, ("Hal_EfuseGetCurrentSize_BT92C(), already use %u bytes\n", pEfuseHal->BTEfuseUsedBytes)); */
2162 }
2163 #endif
2164
2165 RTW_INFO("%s: CurrentSize=%d\n", __FUNCTION__, retU2);
2166 return retU2;
2167 }
2168
2169 static u16
Hal_EfuseGetCurrentSize(PADAPTER pAdapter,u8 efuseType,u8 bPseudoTest)2170 Hal_EfuseGetCurrentSize(
2171 PADAPTER pAdapter,
2172 u8 efuseType,
2173 u8 bPseudoTest)
2174 {
2175 u16 ret = 0;
2176
2177 if (efuseType == EFUSE_WIFI)
2178 ret = hal_EfuseGetCurrentSize_WiFi(pAdapter, bPseudoTest);
2179 else
2180 ret = hal_EfuseGetCurrentSize_BT(pAdapter, bPseudoTest);
2181
2182 return ret;
2183 }
2184
2185 static u8
Hal_EfuseWordEnableDataWrite(PADAPTER padapter,u16 efuse_addr,u8 word_en,u8 * data,u8 bPseudoTest)2186 Hal_EfuseWordEnableDataWrite(
2187 PADAPTER padapter,
2188 u16 efuse_addr,
2189 u8 word_en,
2190 u8 *data,
2191 u8 bPseudoTest)
2192 {
2193 u16 tmpaddr = 0;
2194 u16 start_addr = efuse_addr;
2195 u8 badworden = 0x0F;
2196 u8 tmpdata[PGPKT_DATA_SIZE];
2197
2198
2199 /* RTW_INFO("%s: efuse_addr=%#x word_en=%#x\n", __FUNCTION__, efuse_addr, word_en); */
2200 _rtw_memset(tmpdata, 0xFF, PGPKT_DATA_SIZE);
2201
2202 if (!(word_en & BIT(0))) {
2203 tmpaddr = start_addr;
2204 efuse_OneByteWrite(padapter, start_addr++, data[0], bPseudoTest);
2205 efuse_OneByteWrite(padapter, start_addr++, data[1], bPseudoTest);
2206 phy_set_mac_reg(padapter, EFUSE_TEST, BIT26, 0);
2207 efuse_OneByteRead(padapter, tmpaddr, &tmpdata[0], bPseudoTest);
2208 efuse_OneByteRead(padapter, tmpaddr + 1, &tmpdata[1], bPseudoTest);
2209 phy_set_mac_reg(padapter, EFUSE_TEST, BIT26, 1);
2210 if ((data[0] != tmpdata[0]) || (data[1] != tmpdata[1]))
2211 badworden &= (~BIT(0));
2212 }
2213 if (!(word_en & BIT(1))) {
2214 tmpaddr = start_addr;
2215 efuse_OneByteWrite(padapter, start_addr++, data[2], bPseudoTest);
2216 efuse_OneByteWrite(padapter, start_addr++, data[3], bPseudoTest);
2217 phy_set_mac_reg(padapter, EFUSE_TEST, BIT26, 0);
2218 efuse_OneByteRead(padapter, tmpaddr, &tmpdata[2], bPseudoTest);
2219 efuse_OneByteRead(padapter, tmpaddr + 1, &tmpdata[3], bPseudoTest);
2220 phy_set_mac_reg(padapter, EFUSE_TEST, BIT26, 1);
2221 if ((data[2] != tmpdata[2]) || (data[3] != tmpdata[3]))
2222 badworden &= (~BIT(1));
2223 }
2224 if (!(word_en & BIT(2))) {
2225 tmpaddr = start_addr;
2226 efuse_OneByteWrite(padapter, start_addr++, data[4], bPseudoTest);
2227 efuse_OneByteWrite(padapter, start_addr++, data[5], bPseudoTest);
2228 phy_set_mac_reg(padapter, EFUSE_TEST, BIT26, 0);
2229 efuse_OneByteRead(padapter, tmpaddr, &tmpdata[4], bPseudoTest);
2230 efuse_OneByteRead(padapter, tmpaddr + 1, &tmpdata[5], bPseudoTest);
2231 phy_set_mac_reg(padapter, EFUSE_TEST, BIT26, 1);
2232 if ((data[4] != tmpdata[4]) || (data[5] != tmpdata[5]))
2233 badworden &= (~BIT(2));
2234 }
2235 if (!(word_en & BIT(3))) {
2236 tmpaddr = start_addr;
2237 efuse_OneByteWrite(padapter, start_addr++, data[6], bPseudoTest);
2238 efuse_OneByteWrite(padapter, start_addr++, data[7], bPseudoTest);
2239 phy_set_mac_reg(padapter, EFUSE_TEST, BIT26, 0);
2240 efuse_OneByteRead(padapter, tmpaddr, &tmpdata[6], bPseudoTest);
2241 efuse_OneByteRead(padapter, tmpaddr + 1, &tmpdata[7], bPseudoTest);
2242 phy_set_mac_reg(padapter, EFUSE_TEST, BIT26, 1);
2243 if ((data[6] != tmpdata[6]) || (data[7] != tmpdata[7]))
2244 badworden &= (~BIT(3));
2245 }
2246
2247 return badworden;
2248 }
2249
2250 static s32
Hal_EfusePgPacketRead(PADAPTER padapter,u8 offset,u8 * data,u8 bPseudoTest)2251 Hal_EfusePgPacketRead(
2252 PADAPTER padapter,
2253 u8 offset,
2254 u8 *data,
2255 u8 bPseudoTest)
2256 {
2257 u8 bDataEmpty = _TRUE;
2258 u8 efuse_data, word_cnts = 0;
2259 u16 efuse_addr = 0;
2260 u8 hoffset = 0, hworden = 0;
2261 u8 i;
2262 u8 max_section = 0;
2263 s32 ret;
2264
2265
2266 if (data == NULL)
2267 return _FALSE;
2268
2269 EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAX_SECTION, &max_section, bPseudoTest);
2270 if (offset > max_section) {
2271 RTW_INFO("%s: Packet offset(%d) is illegal(>%d)!\n", __FUNCTION__, offset, max_section);
2272 return _FALSE;
2273 }
2274
2275 _rtw_memset(data, 0xFF, PGPKT_DATA_SIZE);
2276 ret = _TRUE;
2277
2278 /* */
2279 /* <Roger_TODO> Efuse has been pre-programmed dummy 5Bytes at the end of Efuse by CP. */
2280 /* Skip dummy parts to prevent unexpected data read from Efuse. */
2281 /* By pass right now. 2009.02.19. */
2282 /* */
2283 while (AVAILABLE_EFUSE_ADDR(efuse_addr)) {
2284 if (efuse_OneByteRead(padapter, efuse_addr++, &efuse_data, bPseudoTest) == _FALSE) {
2285 ret = _FALSE;
2286 break;
2287 }
2288
2289 if (efuse_data == 0xFF)
2290 break;
2291
2292 if (EXT_HEADER(efuse_data)) {
2293 hoffset = GET_HDR_OFFSET_2_0(efuse_data);
2294 efuse_OneByteRead(padapter, efuse_addr++, &efuse_data, bPseudoTest);
2295 if (ALL_WORDS_DISABLED(efuse_data)) {
2296 RTW_INFO("%s: Error!! All words disabled!\n", __FUNCTION__);
2297 continue;
2298 }
2299
2300 hoffset |= ((efuse_data & 0xF0) >> 1);
2301 hworden = efuse_data & 0x0F;
2302 } else {
2303 hoffset = (efuse_data >> 4) & 0x0F;
2304 hworden = efuse_data & 0x0F;
2305 }
2306
2307 if (hoffset == offset) {
2308 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
2309 /* Check word enable condition in the section */
2310 if (!(hworden & (0x01 << i))) {
2311 /* ReadEFuseByte(padapter, efuse_addr++, &efuse_data, bPseudoTest); */
2312 efuse_OneByteRead(padapter, efuse_addr++, &efuse_data, bPseudoTest);
2313 /* RTW_INFO("%s: efuse[%#X]=0x%02X\n", __FUNCTION__, efuse_addr+tmpidx, efuse_data); */
2314 data[i * 2] = efuse_data;
2315
2316 /* ReadEFuseByte(padapter, efuse_addr++, &efuse_data, bPseudoTest); */
2317 efuse_OneByteRead(padapter, efuse_addr++, &efuse_data, bPseudoTest);
2318 /* RTW_INFO("%s: efuse[%#X]=0x%02X\n", __FUNCTION__, efuse_addr+tmpidx, efuse_data); */
2319 data[(i * 2) + 1] = efuse_data;
2320 }
2321 }
2322 } else {
2323 word_cnts = Efuse_CalculateWordCnts(hworden);
2324 efuse_addr += word_cnts * 2;
2325 }
2326 }
2327
2328 return ret;
2329 }
2330
2331 static u8
hal_EfusePgCheckAvailableAddr(PADAPTER pAdapter,u8 efuseType,u8 bPseudoTest)2332 hal_EfusePgCheckAvailableAddr(
2333 PADAPTER pAdapter,
2334 u8 efuseType,
2335 u8 bPseudoTest)
2336 {
2337 u16 max_available = 0;
2338 u16 current_size;
2339
2340
2341 EFUSE_GetEfuseDefinition(pAdapter, efuseType, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, &max_available, bPseudoTest);
2342 /* RTW_INFO("%s: max_available=%d\n", __FUNCTION__, max_available); */
2343
2344 current_size = Efuse_GetCurrentSize(pAdapter, efuseType, bPseudoTest);
2345 if (current_size >= max_available) {
2346 RTW_INFO("%s: Error!! current_size(%d)>max_available(%d)\n", __FUNCTION__, current_size, max_available);
2347 return _FALSE;
2348 }
2349 return _TRUE;
2350 }
2351
2352 static void
hal_EfuseConstructPGPkt(u8 offset,u8 word_en,u8 * pData,PPGPKT_STRUCT pTargetPkt)2353 hal_EfuseConstructPGPkt(
2354 u8 offset,
2355 u8 word_en,
2356 u8 *pData,
2357 PPGPKT_STRUCT pTargetPkt)
2358 {
2359 _rtw_memset(pTargetPkt->data, 0xFF, PGPKT_DATA_SIZE);
2360 pTargetPkt->offset = offset;
2361 pTargetPkt->word_en = word_en;
2362 efuse_WordEnableDataRead(word_en, pData, pTargetPkt->data);
2363 pTargetPkt->word_cnts = Efuse_CalculateWordCnts(pTargetPkt->word_en);
2364 }
2365
2366 #if 0
2367 static u8
2368 wordEnMatched(
2369 PPGPKT_STRUCT pTargetPkt,
2370 PPGPKT_STRUCT pCurPkt,
2371 u8 *pWden)
2372 {
2373 u8 match_word_en = 0x0F; /* default all words are disabled */
2374 u8 i;
2375
2376 /* check if the same words are enabled both target and current PG packet */
2377 if (((pTargetPkt->word_en & BIT(0)) == 0) &&
2378 ((pCurPkt->word_en & BIT(0)) == 0)) {
2379 match_word_en &= ~BIT(0); /* enable word 0 */
2380 }
2381 if (((pTargetPkt->word_en & BIT(1)) == 0) &&
2382 ((pCurPkt->word_en & BIT(1)) == 0)) {
2383 match_word_en &= ~BIT(1); /* enable word 1 */
2384 }
2385 if (((pTargetPkt->word_en & BIT(2)) == 0) &&
2386 ((pCurPkt->word_en & BIT(2)) == 0)) {
2387 match_word_en &= ~BIT(2); /* enable word 2 */
2388 }
2389 if (((pTargetPkt->word_en & BIT(3)) == 0) &&
2390 ((pCurPkt->word_en & BIT(3)) == 0)) {
2391 match_word_en &= ~BIT(3); /* enable word 3 */
2392 }
2393
2394 *pWden = match_word_en;
2395
2396 if (match_word_en != 0xf)
2397 return _TRUE;
2398 else
2399 return _FALSE;
2400 }
2401
2402 static u8
2403 hal_EfuseCheckIfDatafollowed(
2404 PADAPTER pAdapter,
2405 u8 word_cnts,
2406 u16 startAddr,
2407 u8 bPseudoTest)
2408 {
2409 u8 bRet = _FALSE;
2410 u8 i, efuse_data;
2411
2412 for (i = 0; i < (word_cnts * 2); i++) {
2413 if (efuse_OneByteRead(pAdapter, (startAddr + i) , &efuse_data, bPseudoTest) == _FALSE) {
2414 RTW_INFO("%s: efuse_OneByteRead FAIL!!\n", __FUNCTION__);
2415 bRet = _TRUE;
2416 break;
2417 }
2418
2419 if (efuse_data != 0xFF) {
2420 bRet = _TRUE;
2421 break;
2422 }
2423 }
2424
2425 return bRet;
2426 }
2427 #endif
2428
2429 static u8
hal_EfusePartialWriteCheck(PADAPTER padapter,u8 efuseType,u16 * pAddr,PPGPKT_STRUCT pTargetPkt,u8 bPseudoTest)2430 hal_EfusePartialWriteCheck(
2431 PADAPTER padapter,
2432 u8 efuseType,
2433 u16 *pAddr,
2434 PPGPKT_STRUCT pTargetPkt,
2435 u8 bPseudoTest)
2436 {
2437 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
2438 PEFUSE_HAL pEfuseHal = &pHalData->EfuseHal;
2439 u8 bRet = _FALSE;
2440 u16 startAddr = 0, efuse_max_available_len = 0, efuse_max = 0;
2441 u8 efuse_data = 0;
2442 #if 0
2443 u8 i, cur_header = 0;
2444 u8 new_wden = 0, matched_wden = 0, badworden = 0;
2445 PGPKT_STRUCT curPkt;
2446 #endif
2447
2448
2449 EFUSE_GetEfuseDefinition(padapter, efuseType, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, &efuse_max_available_len, bPseudoTest);
2450 EFUSE_GetEfuseDefinition(padapter, efuseType, TYPE_EFUSE_CONTENT_LEN_BANK, &efuse_max, bPseudoTest);
2451
2452 if (efuseType == EFUSE_WIFI) {
2453 if (bPseudoTest) {
2454 #ifdef HAL_EFUSE_MEMORY
2455 startAddr = (u16)pEfuseHal->fakeEfuseUsedBytes;
2456 #else
2457 startAddr = (u16)fakeEfuseUsedBytes;
2458 #endif
2459 } else
2460 rtw_hal_get_hwreg(padapter, HW_VAR_EFUSE_BYTES, (u8 *)&startAddr);
2461 } else {
2462 if (bPseudoTest) {
2463 #ifdef HAL_EFUSE_MEMORY
2464 startAddr = (u16)pEfuseHal->fakeBTEfuseUsedBytes;
2465 #else
2466 startAddr = (u16)fakeBTEfuseUsedBytes;
2467 #endif
2468 } else
2469 rtw_hal_get_hwreg(padapter, HW_VAR_EFUSE_BT_BYTES, (u8 *)&startAddr);
2470 }
2471 startAddr %= efuse_max;
2472 RTW_INFO("%s: startAddr=%#X\n", __FUNCTION__, startAddr);
2473
2474 while (1) {
2475 if (startAddr >= efuse_max_available_len) {
2476 bRet = _FALSE;
2477 RTW_INFO("%s: startAddr(%d) >= efuse_max_available_len(%d)\n",
2478 __FUNCTION__, startAddr, efuse_max_available_len);
2479 break;
2480 }
2481
2482 if (efuse_OneByteRead(padapter, startAddr, &efuse_data, bPseudoTest) && (efuse_data != 0xFF)) {
2483 #if 1
2484 bRet = _FALSE;
2485 RTW_INFO("%s: Something Wrong! last bytes(%#X=0x%02X) is not 0xFF\n",
2486 __FUNCTION__, startAddr, efuse_data);
2487 break;
2488 #else
2489 if (EXT_HEADER(efuse_data)) {
2490 cur_header = efuse_data;
2491 startAddr++;
2492 efuse_OneByteRead(padapter, startAddr, &efuse_data, bPseudoTest);
2493 if (ALL_WORDS_DISABLED(efuse_data)) {
2494 RTW_INFO("%s: Error condition, all words disabled!", __FUNCTION__);
2495 bRet = _FALSE;
2496 break;
2497 } else {
2498 curPkt.offset = ((cur_header & 0xE0) >> 5) | ((efuse_data & 0xF0) >> 1);
2499 curPkt.word_en = efuse_data & 0x0F;
2500 }
2501 } else {
2502 cur_header = efuse_data;
2503 curPkt.offset = (cur_header >> 4) & 0x0F;
2504 curPkt.word_en = cur_header & 0x0F;
2505 }
2506
2507 curPkt.word_cnts = Efuse_CalculateWordCnts(curPkt.word_en);
2508 /* if same header is found but no data followed */
2509 /* write some part of data followed by the header. */
2510 if ((curPkt.offset == pTargetPkt->offset) &&
2511 (hal_EfuseCheckIfDatafollowed(padapter, curPkt.word_cnts, startAddr + 1, bPseudoTest) == _FALSE) &&
2512 wordEnMatched(pTargetPkt, &curPkt, &matched_wden) == _TRUE) {
2513 RTW_INFO("%s: Need to partial write data by the previous wrote header\n", __FUNCTION__);
2514 /* Here to write partial data */
2515 badworden = Efuse_WordEnableDataWrite(padapter, startAddr + 1, matched_wden, pTargetPkt->data, bPseudoTest);
2516 if (badworden != 0x0F) {
2517 u32 PgWriteSuccess = 0;
2518 /* if write fail on some words, write these bad words again */
2519 if (efuseType == EFUSE_WIFI)
2520 PgWriteSuccess = Efuse_PgPacketWrite(padapter, pTargetPkt->offset, badworden, pTargetPkt->data, bPseudoTest);
2521 else
2522 PgWriteSuccess = Efuse_PgPacketWrite_BT(padapter, pTargetPkt->offset, badworden, pTargetPkt->data, bPseudoTest);
2523
2524 if (!PgWriteSuccess) {
2525 bRet = _FALSE; /* write fail, return */
2526 break;
2527 }
2528 }
2529 /* partial write ok, update the target packet for later use */
2530 for (i = 0; i < 4; i++) {
2531 if ((matched_wden & (0x1 << i)) == 0) { /* this word has been written */
2532 pTargetPkt->word_en |= (0x1 << i); /* disable the word */
2533 }
2534 }
2535 pTargetPkt->word_cnts = Efuse_CalculateWordCnts(pTargetPkt->word_en);
2536 }
2537 /* read from next header */
2538 startAddr = startAddr + (curPkt.word_cnts * 2) + 1;
2539 #endif
2540 } else {
2541 /* not used header, 0xff */
2542 *pAddr = startAddr;
2543 /* RTW_INFO("%s: Started from unused header offset=%d\n", __FUNCTION__, startAddr)); */
2544 bRet = _TRUE;
2545 break;
2546 }
2547 }
2548
2549 return bRet;
2550 }
2551
2552 BOOLEAN
hal_EfuseFixHeaderProcess(PADAPTER pAdapter,u8 efuseType,PPGPKT_STRUCT pFixPkt,u16 * pAddr,BOOLEAN bPseudoTest)2553 hal_EfuseFixHeaderProcess(
2554 PADAPTER pAdapter,
2555 u8 efuseType,
2556 PPGPKT_STRUCT pFixPkt,
2557 u16 *pAddr,
2558 BOOLEAN bPseudoTest
2559 )
2560 {
2561 u8 originaldata[8], badworden=0;
2562 u16 efuse_addr=*pAddr;
2563 u32 PgWriteSuccess=0;
2564
2565 _rtw_memset((void *)originaldata, 0xff, 8);
2566
2567 if (Efuse_PgPacketRead(pAdapter, pFixPkt->offset, originaldata, bPseudoTest)) {
2568 badworden = Hal_EfuseWordEnableDataWrite(pAdapter, efuse_addr+1, pFixPkt->word_en, originaldata, bPseudoTest);
2569
2570 if (badworden != 0xf) {
2571
2572 PgWriteSuccess = Efuse_PgPacketWrite(pAdapter, pFixPkt->offset, badworden, originaldata, bPseudoTest);
2573 if (!PgWriteSuccess)
2574 return FALSE;
2575 else
2576 efuse_addr = Hal_EfuseGetCurrentSize(pAdapter, efuseType, bPseudoTest);
2577 } else {
2578 efuse_addr = efuse_addr + (pFixPkt->word_cnts*2) +1;
2579 }
2580 } else {
2581 efuse_addr = efuse_addr + (pFixPkt->word_cnts*2) +1;
2582 }
2583
2584 *pAddr = efuse_addr;
2585 return TRUE;
2586 }
2587
2588 static u8
hal_EfusePgPacketWrite1ByteHeader(PADAPTER pAdapter,u8 efuseType,u16 * pAddr,PPGPKT_STRUCT pTargetPkt,u8 bPseudoTest)2589 hal_EfusePgPacketWrite1ByteHeader(
2590 PADAPTER pAdapter,
2591 u8 efuseType,
2592 u16 *pAddr,
2593 PPGPKT_STRUCT pTargetPkt,
2594 u8 bPseudoTest)
2595 {
2596 u8 bRet = _FALSE;
2597 u8 pg_header = 0, tmp_header = 0;
2598 u16 efuse_addr = *pAddr;
2599 u8 repeatcnt = 0;
2600
2601
2602 /* RTW_INFO("%s\n", __FUNCTION__); */
2603 pg_header = ((pTargetPkt->offset << 4) & 0xf0) | pTargetPkt->word_en;
2604
2605 efuse_OneByteWrite(pAdapter, efuse_addr, pg_header, bPseudoTest);
2606
2607 phy_set_mac_reg(pAdapter, EFUSE_TEST, BIT26, 0);
2608
2609 efuse_OneByteRead(pAdapter, efuse_addr, &tmp_header, bPseudoTest);
2610
2611 phy_set_mac_reg(pAdapter, EFUSE_TEST, BIT26, 1);
2612
2613 while (tmp_header == 0xFF || pg_header != tmp_header) {
2614 if (repeatcnt++ > EFUSE_REPEAT_THRESHOLD_) {
2615 RTW_ERR("retry %d times fail!!\n", repeatcnt);
2616 return _FALSE;
2617 }
2618 efuse_OneByteWrite(pAdapter,efuse_addr, pg_header, bPseudoTest);
2619 efuse_OneByteRead(pAdapter,efuse_addr, &tmp_header, bPseudoTest);
2620 RTW_ERR("===>%s: Keep %d-th retrying,pg_header = 0x%X tmp_header = 0x%X\n", __FUNCTION__,repeatcnt, pg_header, tmp_header);
2621 }
2622
2623 if (pg_header == tmp_header)
2624 bRet = _TRUE;
2625 else {
2626 PGPKT_STRUCT fixPkt;
2627
2628 RTW_ERR(" pg_header(0x%X) != tmp_header(0x%X)\n", pg_header, tmp_header);
2629 RTW_ERR("Error condition for fixed PG packet, need to cover the existed data: (Addr, Data) = (0x%X, 0x%X)\n",
2630 efuse_addr, tmp_header);
2631 fixPkt.offset = (tmp_header>>4) & 0x0F;
2632 fixPkt.word_en = tmp_header & 0x0F;
2633 fixPkt.word_cnts = Efuse_CalculateWordCnts(fixPkt.word_en);
2634 if (!hal_EfuseFixHeaderProcess(pAdapter, efuseType, &fixPkt, &efuse_addr, bPseudoTest))
2635 return _FALSE;
2636 }
2637
2638 *pAddr = efuse_addr;
2639
2640 return _TRUE;
2641 }
2642
2643 static u8
hal_EfusePgPacketWrite2ByteHeader(PADAPTER padapter,u8 efuseType,u16 * pAddr,PPGPKT_STRUCT pTargetPkt,u8 bPseudoTest)2644 hal_EfusePgPacketWrite2ByteHeader(
2645 PADAPTER padapter,
2646 u8 efuseType,
2647 u16 *pAddr,
2648 PPGPKT_STRUCT pTargetPkt,
2649 u8 bPseudoTest)
2650 {
2651 u16 efuse_addr, efuse_max_available_len = 0;
2652 u8 pg_header = 0, tmp_header = 0, pg_header_temp = 0;
2653 u8 repeatcnt = 0;
2654
2655
2656 /* RTW_INFO("%s\n", __FUNCTION__); */
2657 EFUSE_GetEfuseDefinition(padapter, efuseType, TYPE_AVAILABLE_EFUSE_BYTES_BANK, &efuse_max_available_len, bPseudoTest);
2658
2659 efuse_addr = *pAddr;
2660
2661 if (efuse_addr >= efuse_max_available_len) {
2662 RTW_INFO("%s: addr(%d) over avaliable(%d)!!\n", __FUNCTION__, efuse_addr, efuse_max_available_len);
2663 return _FALSE;
2664 }
2665
2666 while (efuse_addr < efuse_max_available_len) {
2667 pg_header = ((pTargetPkt->offset & 0x07) << 5) | 0x0F;
2668 efuse_OneByteWrite(padapter, efuse_addr, pg_header, bPseudoTest);
2669 phy_set_mac_reg(padapter, EFUSE_TEST, BIT26, 0);
2670 efuse_OneByteRead(padapter, efuse_addr, &tmp_header, bPseudoTest);
2671 phy_set_mac_reg(padapter, EFUSE_TEST, BIT26, 1);
2672
2673 while (tmp_header == 0xFF || pg_header != tmp_header) {
2674 if (repeatcnt++ > EFUSE_REPEAT_THRESHOLD_) {
2675 RTW_INFO("%s, Repeat over limit for pg_header!!\n", __FUNCTION__);
2676 return _FALSE;
2677 }
2678
2679 efuse_OneByteWrite(padapter, efuse_addr, pg_header, bPseudoTest);
2680 efuse_OneByteRead(padapter, efuse_addr, &tmp_header, bPseudoTest);
2681 }
2682
2683 /*to write ext_header*/
2684 if (tmp_header == pg_header) {
2685 efuse_addr++;
2686 pg_header_temp = pg_header;
2687 pg_header = ((pTargetPkt->offset & 0x78) << 1) | pTargetPkt->word_en;
2688
2689 efuse_OneByteWrite(padapter, efuse_addr, pg_header, bPseudoTest);
2690 phy_set_mac_reg(padapter, EFUSE_TEST, BIT26, 0);
2691 efuse_OneByteRead(padapter, efuse_addr, &tmp_header, bPseudoTest);
2692 phy_set_mac_reg(padapter, EFUSE_TEST, BIT26, 1);
2693
2694 while (tmp_header == 0xFF || pg_header != tmp_header) {
2695 if (repeatcnt++ > EFUSE_REPEAT_THRESHOLD_) {
2696 RTW_INFO("%s, Repeat over limit for ext_header!!\n", __FUNCTION__);
2697 return _FALSE;
2698 }
2699
2700 efuse_OneByteWrite(padapter, efuse_addr, pg_header, bPseudoTest);
2701 efuse_OneByteRead(padapter, efuse_addr, &tmp_header, bPseudoTest);
2702 }
2703
2704 if ((tmp_header & 0x0F) == 0x0F) {
2705 if (repeatcnt++ > EFUSE_REPEAT_THRESHOLD_) {
2706 RTW_INFO("Repeat over limit for word_en!!\n");
2707 return _FALSE;
2708 } else {
2709 efuse_addr++;
2710 continue;
2711 }
2712 } else if (pg_header != tmp_header) {
2713 PGPKT_STRUCT fixPkt;
2714 RTW_ERR("Error, efuse_PgPacketWrite2ByteHeader(), offset PG fail, need to cover the existed data!!\n");
2715 RTW_ERR("Error condition for offset PG fail, need to cover the existed data\n");
2716 fixPkt.offset = ((pg_header_temp & 0xE0) >> 5) | ((tmp_header & 0xF0) >> 1);
2717 fixPkt.word_en = tmp_header & 0x0F;
2718 fixPkt.word_cnts = Efuse_CalculateWordCnts(fixPkt.word_en);
2719 if (!hal_EfuseFixHeaderProcess(padapter, efuseType, &fixPkt, &efuse_addr, bPseudoTest))
2720 return _FALSE;
2721 } else
2722 break;
2723 } else if ((tmp_header & 0x1F) == 0x0F) {/*wrong extended header*/
2724 efuse_addr += 2;
2725 continue;
2726 }
2727 }
2728
2729 *pAddr = efuse_addr;
2730
2731 return _TRUE;
2732 }
2733
2734 static u8
hal_EfusePgPacketWriteHeader(PADAPTER padapter,u8 efuseType,u16 * pAddr,PPGPKT_STRUCT pTargetPkt,u8 bPseudoTest)2735 hal_EfusePgPacketWriteHeader(
2736 PADAPTER padapter,
2737 u8 efuseType,
2738 u16 *pAddr,
2739 PPGPKT_STRUCT pTargetPkt,
2740 u8 bPseudoTest)
2741 {
2742 u8 bRet = _FALSE;
2743
2744 if (pTargetPkt->offset >= EFUSE_MAX_SECTION_BASE)
2745 bRet = hal_EfusePgPacketWrite2ByteHeader(padapter, efuseType, pAddr, pTargetPkt, bPseudoTest);
2746 else
2747 bRet = hal_EfusePgPacketWrite1ByteHeader(padapter, efuseType, pAddr, pTargetPkt, bPseudoTest);
2748
2749 return bRet;
2750 }
2751
2752 static u8
hal_EfusePgPacketWriteData(PADAPTER pAdapter,u8 efuseType,u16 * pAddr,PPGPKT_STRUCT pTargetPkt,u8 bPseudoTest)2753 hal_EfusePgPacketWriteData(
2754 PADAPTER pAdapter,
2755 u8 efuseType,
2756 u16 *pAddr,
2757 PPGPKT_STRUCT pTargetPkt,
2758 u8 bPseudoTest)
2759 {
2760 u16 efuse_addr;
2761 u8 badworden;
2762 u8 PgWriteSuccess = 0;
2763
2764
2765 efuse_addr = *pAddr;
2766 badworden = Efuse_WordEnableDataWrite(pAdapter, efuse_addr + 1, pTargetPkt->word_en, pTargetPkt->data, bPseudoTest);
2767 if (badworden == 0x0F) {
2768 RTW_INFO("%s: OK!!\n", __FUNCTION__);
2769 return _TRUE;
2770 } else { /* Reorganize other pg packet */
2771 RTW_ERR ("Error, efuse_PgPacketWriteData(), wirte data fail!!\n");
2772 RTW_ERR ("efuse_PgPacketWriteData Fail!!\n");
2773 PgWriteSuccess = Efuse_PgPacketWrite(pAdapter, pTargetPkt->offset, badworden, pTargetPkt->data, bPseudoTest);
2774 if (!PgWriteSuccess)
2775 return FALSE;
2776 else
2777 return TRUE;
2778 }
2779
2780 return _TRUE;
2781 }
2782
2783 static s32
Hal_EfusePgPacketWrite(PADAPTER padapter,u8 offset,u8 word_en,u8 * pData,u8 bPseudoTest)2784 Hal_EfusePgPacketWrite(
2785 PADAPTER padapter,
2786 u8 offset,
2787 u8 word_en,
2788 u8 *pData,
2789 u8 bPseudoTest)
2790 {
2791 PGPKT_STRUCT targetPkt;
2792 u16 startAddr = 0;
2793 u8 efuseType = EFUSE_WIFI;
2794
2795 if (!hal_EfusePgCheckAvailableAddr(padapter, efuseType, bPseudoTest))
2796 return _FALSE;
2797
2798 hal_EfuseConstructPGPkt(offset, word_en, pData, &targetPkt);
2799
2800 if (!hal_EfusePartialWriteCheck(padapter, efuseType, &startAddr, &targetPkt, bPseudoTest))
2801 return _FALSE;
2802
2803 if (!hal_EfusePgPacketWriteHeader(padapter, efuseType, &startAddr, &targetPkt, bPseudoTest))
2804 return _FALSE;
2805
2806 if (!hal_EfusePgPacketWriteData(padapter, efuseType, &startAddr, &targetPkt, bPseudoTest))
2807 return _FALSE;
2808
2809 return _TRUE;
2810 }
2811
2812 static u8
Hal_EfusePgPacketWrite_BT(PADAPTER pAdapter,u8 offset,u8 word_en,u8 * pData,u8 bPseudoTest)2813 Hal_EfusePgPacketWrite_BT(
2814 PADAPTER pAdapter,
2815 u8 offset,
2816 u8 word_en,
2817 u8 *pData,
2818 u8 bPseudoTest)
2819 {
2820 PGPKT_STRUCT targetPkt;
2821 u16 startAddr = 0;
2822 u8 efuseType = EFUSE_BT;
2823
2824 if (!hal_EfusePgCheckAvailableAddr(pAdapter, efuseType, bPseudoTest))
2825 return _FALSE;
2826
2827 hal_EfuseConstructPGPkt(offset, word_en, pData, &targetPkt);
2828
2829 if (!hal_EfusePartialWriteCheck(pAdapter, efuseType, &startAddr, &targetPkt, bPseudoTest))
2830 return _FALSE;
2831
2832 if (!hal_EfusePgPacketWriteHeader(pAdapter, efuseType, &startAddr, &targetPkt, bPseudoTest))
2833 return _FALSE;
2834
2835 if (!hal_EfusePgPacketWriteData(pAdapter, efuseType, &startAddr, &targetPkt, bPseudoTest))
2836 return _FALSE;
2837
2838 return _TRUE;
2839 }
2840
2841
read_chip_version_8703b(PADAPTER padapter)2842 static void read_chip_version_8703b(PADAPTER padapter)
2843 {
2844 u32 value32;
2845 HAL_DATA_TYPE *pHalData;
2846 pHalData = GET_HAL_DATA(padapter);
2847
2848 value32 = rtw_read32(padapter, REG_SYS_CFG);
2849 pHalData->version_id.ICType = CHIP_8703B;
2850 pHalData->version_id.ChipType = ((value32 & RTL_ID) ? TEST_CHIP : NORMAL_CHIP);
2851 pHalData->version_id.RFType = RF_TYPE_1T1R;
2852 pHalData->version_id.VendorType = ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : CHIP_VENDOR_TSMC);
2853 pHalData->version_id.CUTVersion = (value32 & CHIP_VER_RTL_MASK) >> CHIP_VER_RTL_SHIFT; /* IC version (CUT) */
2854
2855 /* For regulator mode. by tynli. 2011.01.14 */
2856 pHalData->RegulatorMode = ((value32 & SPS_SEL) ? RT_LDO_REGULATOR : RT_SWITCHING_REGULATOR);
2857
2858 value32 = rtw_read32(padapter, REG_GPIO_OUTSTS);
2859 pHalData->version_id.ROMVer = ((value32 & RF_RL_ID) >> 20); /* ROM code version. */
2860
2861 /* For multi-function consideration. Added by Roger, 2010.10.06. */
2862 pHalData->MultiFunc = RT_MULTI_FUNC_NONE;
2863 value32 = rtw_read32(padapter, REG_MULTI_FUNC_CTRL);
2864 pHalData->MultiFunc |= ((value32 & WL_FUNC_EN) ? RT_MULTI_FUNC_WIFI : 0);
2865 pHalData->MultiFunc |= ((value32 & BT_FUNC_EN) ? RT_MULTI_FUNC_BT : 0);
2866 pHalData->MultiFunc |= ((value32 & GPS_FUNC_EN) ? RT_MULTI_FUNC_GPS : 0);
2867 pHalData->PolarityCtl = ((value32 & WL_HWPDN_SL) ? RT_POLARITY_HIGH_ACT : RT_POLARITY_LOW_ACT);
2868
2869
2870 #if 0
2871 /* mark for chage to use efuse */
2872 if (IS_B_CUT(pHalData->version_id) || IS_C_CUT(pHalData->version_id)) {
2873 RTW_INFO(" IS_B/C_CUT SWR up 1 level !!!!!!!!!!!!!!!!!\n");
2874 phy_set_mac_reg(padapter, 0x14, BIT23 | BIT22 | BIT21 | BIT20, 0x5); /* MAC reg 0x14[23:20] = 4b'0101 (SWR 1.220V) */
2875 } else if (IS_D_CUT(pHalData->version_id))
2876 RTW_INFO(" IS_D_CUT SKIP SWR !!!!!!!!!!!!!!!!!\n");
2877 #endif
2878
2879 #if 1
2880 dump_chip_info(pHalData->version_id);
2881 #endif
2882
2883 }
2884
2885
rtl8703b_InitBeaconParameters(PADAPTER padapter)2886 void rtl8703b_InitBeaconParameters(PADAPTER padapter)
2887 {
2888 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
2889 u16 val16;
2890 u8 val8;
2891
2892
2893 val8 = DIS_TSF_UDT;
2894 val16 = val8 | (val8 << 8); /* port0 and port1 */
2895 #ifdef CONFIG_BT_COEXIST
2896 /* Enable prot0 beacon function for PSTDMA */
2897 val16 |= EN_BCN_FUNCTION;
2898 #endif
2899 rtw_write16(padapter, REG_BCN_CTRL, val16);
2900
2901 /* TBTT setup time */
2902 rtw_write8(padapter, REG_TBTT_PROHIBIT, TBTT_PROHIBIT_SETUP_TIME);
2903
2904 /* TBTT hold time: 0x540[19:8] */
2905 rtw_write8(padapter, REG_TBTT_PROHIBIT + 1, TBTT_PROHIBIT_HOLD_TIME_STOP_BCN & 0xFF);
2906 rtw_write8(padapter, REG_TBTT_PROHIBIT + 2,
2907 (rtw_read8(padapter, REG_TBTT_PROHIBIT + 2) & 0xF0) | (TBTT_PROHIBIT_HOLD_TIME_STOP_BCN >> 8));
2908
2909 /* Firmware will control REG_DRVERLYINT when power saving is enable, */
2910 /* so don't set this register on STA mode. */
2911 if (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE) == _FALSE)
2912 rtw_write8(padapter, REG_DRVERLYINT, DRIVER_EARLY_INT_TIME_8703B); /* 5ms */
2913 rtw_write8(padapter, REG_BCNDMATIM, BCN_DMA_ATIME_INT_TIME_8703B); /* 2ms */
2914
2915 /* Suggested by designer timchen. Change beacon AIFS to the largest number */
2916 /* beacause test chip does not contension before sending beacon. by tynli. 2009.11.03 */
2917 rtw_write16(padapter, REG_BCNTCFG, 0x4413);
2918
2919 }
2920
rtl8703b_InitBeaconMaxError(PADAPTER padapter,u8 InfraMode)2921 void rtl8703b_InitBeaconMaxError(PADAPTER padapter, u8 InfraMode)
2922 {
2923 #ifdef CONFIG_ADHOC_WORKAROUND_SETTING
2924 rtw_write8(padapter, REG_BCN_MAX_ERR, 0xFF);
2925 #else
2926 /* rtw_write8(Adapter, REG_BCN_MAX_ERR, (InfraMode ? 0xFF : 0x10)); */
2927 #endif
2928 }
2929
_InitBurstPktLen_8703BS(PADAPTER Adapter)2930 void _InitBurstPktLen_8703BS(PADAPTER Adapter)
2931 {
2932 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
2933
2934 rtw_write8(Adapter, 0x4c7, rtw_read8(Adapter, 0x4c7) | BIT(7)); /* enable single pkt ampdu */
2935 rtw_write8(Adapter, REG_RX_PKT_LIMIT_8703B, 0x18); /* for VHT packet length 11K */
2936 rtw_write8(Adapter, REG_MAX_AGGR_NUM_8703B, 0x1F);
2937 rtw_write8(Adapter, REG_PIFS_8703B, 0x00);
2938 rtw_write8(Adapter, REG_FWHW_TXQ_CTRL_8703B, rtw_read8(Adapter, REG_FWHW_TXQ_CTRL) & (~BIT(7)));
2939 if (pHalData->AMPDUBurstMode)
2940 rtw_write8(Adapter, REG_AMPDU_BURST_MODE_8703B, 0x5F);
2941 rtw_write8(Adapter, REG_AMPDU_MAX_TIME_8703B, 0x70);
2942
2943 /* ARFB table 9 for 11ac 5G 2SS */
2944 rtw_write32(Adapter, REG_ARFR0_8703B, 0x00000010);
2945 if (IS_NORMAL_CHIP(pHalData->version_id))
2946 rtw_write32(Adapter, REG_ARFR0_8703B + 4, 0xfffff000);
2947 else
2948 rtw_write32(Adapter, REG_ARFR0_8703B + 4, 0x3e0ff000);
2949
2950 /* ARFB table 10 for 11ac 5G 1SS */
2951 rtw_write32(Adapter, REG_ARFR1_8703B, 0x00000010);
2952 rtw_write32(Adapter, REG_ARFR1_8703B + 4, 0x003ff000);
2953 }
2954
_InitLTECoex_8703BS(PADAPTER Adapter)2955 void _InitLTECoex_8703BS(PADAPTER Adapter)
2956 {
2957 /* LTE COEX setting */
2958 rtw_write16(Adapter, REG_LTECOEX_WRITE_DATA, 0x7700);
2959 rtw_write32(Adapter, REG_LTECOEX_CTRL, 0xc0020038);
2960 rtw_write8(Adapter, 0x73, 0x04);
2961 }
2962
_InitMacAPLLSetting_8703B(PADAPTER Adapter)2963 void _InitMacAPLLSetting_8703B(PADAPTER Adapter)
2964 {
2965 u16 RegValue;
2966
2967 RegValue = rtw_read16(Adapter, REG_AFE_CTRL_4_8703B);
2968 RegValue |= BIT(4);
2969 RegValue |= BIT(15);
2970 rtw_write16(Adapter, REG_AFE_CTRL_4_8703B, RegValue);
2971 }
2972
2973
_BeaconFunctionEnable(PADAPTER padapter,u8 Enable,u8 Linked)2974 static void _BeaconFunctionEnable(PADAPTER padapter, u8 Enable, u8 Linked)
2975 {
2976 rtw_write8(padapter, REG_BCN_CTRL, DIS_TSF_UDT | EN_BCN_FUNCTION | DIS_BCNQ_SUB);
2977 rtw_write8(padapter, REG_RD_CTRL + 1, 0x6F);
2978 }
2979
rtl8703b_SetBeaconRelatedRegisters(PADAPTER padapter)2980 static void rtl8703b_SetBeaconRelatedRegisters(PADAPTER padapter)
2981 {
2982 u8 val8;
2983 u32 value32;
2984 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
2985 struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
2986 struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
2987 u32 bcn_ctrl_reg;
2988
2989 /* reset TSF, enable update TSF, correcting TSF On Beacon */
2990
2991 /* REG_MBSSID_BCN_SPACE */
2992 /* REG_BCNDMATIM */
2993 /* REG_ATIMWND */
2994 /* REG_TBTT_PROHIBIT */
2995 /* REG_DRVERLYINT */
2996 /* REG_BCN_MAX_ERR */
2997 /* REG_BCNTCFG */ /* (0x510) */
2998 /* REG_DUAL_TSF_RST */
2999 /* REG_BCN_CTRL */ /* (0x550) */
3000
3001
3002 bcn_ctrl_reg = REG_BCN_CTRL;
3003 #ifdef CONFIG_CONCURRENT_MODE
3004 if (padapter->hw_port == HW_PORT1)
3005 bcn_ctrl_reg = REG_BCN_CTRL_1;
3006 #endif
3007
3008 /* */
3009 /* ATIM window */
3010 /* */
3011 rtw_write16(padapter, REG_ATIMWND, 2);
3012
3013 /* */
3014 /* Beacon interval (in unit of TU). */
3015 /* */
3016 rtw_hal_set_hwreg(padapter, HW_VAR_BEACON_INTERVAL, (u8 *)&pmlmeinfo->bcn_interval);
3017
3018 rtl8703b_InitBeaconParameters(padapter);
3019
3020 rtw_write8(padapter, REG_SLOT, 0x09);
3021
3022 /* */
3023 /* Reset TSF Timer to zero, added by Roger. 2008.06.24 */
3024 /* */
3025 value32 = rtw_read32(padapter, REG_TCR);
3026 value32 &= ~TSFRST;
3027 rtw_write32(padapter, REG_TCR, value32);
3028
3029 value32 |= TSFRST;
3030 rtw_write32(padapter, REG_TCR, value32);
3031
3032 /* NOTE: Fix test chip's bug (about contention windows's randomness) */
3033 if (check_fwstate(&padapter->mlmepriv, WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE | WIFI_AP_STATE | WIFI_MESH_STATE) == _TRUE) {
3034 rtw_write8(padapter, REG_RXTSF_OFFSET_CCK, 0x50);
3035 rtw_write8(padapter, REG_RXTSF_OFFSET_OFDM, 0x50);
3036 }
3037
3038 _BeaconFunctionEnable(padapter, _TRUE, _TRUE);
3039
3040 ResumeTxBeacon(padapter);
3041 val8 = rtw_read8(padapter, bcn_ctrl_reg);
3042 val8 |= DIS_BCNQ_SUB;
3043 rtw_write8(padapter, bcn_ctrl_reg, val8);
3044 }
3045
hal_notch_filter_8703b(_adapter * adapter,bool enable)3046 void hal_notch_filter_8703b(_adapter *adapter, bool enable)
3047 {
3048 if (enable) {
3049 RTW_INFO("Enable notch filter\n");
3050 rtw_write8(adapter, rOFDM0_RxDSP + 1, rtw_read8(adapter, rOFDM0_RxDSP + 1) | BIT1);
3051 } else {
3052 RTW_INFO("Disable notch filter\n");
3053 rtw_write8(adapter, rOFDM0_RxDSP + 1, rtw_read8(adapter, rOFDM0_RxDSP + 1) & ~BIT1);
3054 }
3055 }
3056
3057 /*
3058 * Description: In normal chip, we should send some packet to Hw which will be used by Fw
3059 * in FW LPS mode. The function is to fill the Tx descriptor of this packets, then
3060 * Fw can tell Hw to send these packet derectly.
3061 * Added by tynli. 2009.10.15.
3062 *
3063 * type1:pspoll, type2:null */
rtl8703b_fill_fake_txdesc(PADAPTER padapter,u8 * pDesc,u32 BufferLen,u8 IsPsPoll,u8 IsBTQosNull,u8 bDataFrame)3064 void rtl8703b_fill_fake_txdesc(
3065 PADAPTER padapter,
3066 u8 *pDesc,
3067 u32 BufferLen,
3068 u8 IsPsPoll,
3069 u8 IsBTQosNull,
3070 u8 bDataFrame)
3071 {
3072 /* Clear all status */
3073 _rtw_memset(pDesc, 0, TXDESC_SIZE);
3074
3075 SET_TX_DESC_FIRST_SEG_8703B(pDesc, 1); /* bFirstSeg; */
3076 SET_TX_DESC_LAST_SEG_8703B(pDesc, 1); /* bLastSeg; */
3077
3078 SET_TX_DESC_OFFSET_8703B(pDesc, 0x28); /* Offset = 32 */
3079
3080 SET_TX_DESC_PKT_SIZE_8703B(pDesc, BufferLen); /* Buffer size + command header */
3081 SET_TX_DESC_QUEUE_SEL_8703B(pDesc, QSLT_MGNT); /* Fixed queue of Mgnt queue */
3082
3083 /* Set NAVUSEHDR to prevent Ps-poll AId filed to be changed to error vlaue by Hw. */
3084 if (_TRUE == IsPsPoll)
3085 SET_TX_DESC_NAV_USE_HDR_8703B(pDesc, 1);
3086 else {
3087 SET_TX_DESC_HWSEQ_EN_8703B(pDesc, 1); /* Hw set sequence number */
3088 SET_TX_DESC_HWSEQ_SEL_8703B(pDesc, 0);
3089 }
3090
3091 if (_TRUE == IsBTQosNull)
3092 SET_TX_DESC_BT_INT_8703B(pDesc, 1);
3093
3094 SET_TX_DESC_USE_RATE_8703B(pDesc, 1); /* use data rate which is set by Sw */
3095 SET_TX_DESC_OWN_8703B((u8 *)pDesc, 1);
3096
3097 SET_TX_DESC_TX_RATE_8703B(pDesc, DESC8703B_RATE1M);
3098
3099 /* */
3100 /* Encrypt the data frame if under security mode excepct null data. Suggested by CCW. */
3101 /* */
3102 if (_TRUE == bDataFrame) {
3103 u32 EncAlg;
3104
3105 EncAlg = padapter->securitypriv.dot11PrivacyAlgrthm;
3106 switch (EncAlg) {
3107 case _NO_PRIVACY_:
3108 SET_TX_DESC_SEC_TYPE_8703B(pDesc, 0x0);
3109 break;
3110 case _WEP40_:
3111 case _WEP104_:
3112 case _TKIP_:
3113 SET_TX_DESC_SEC_TYPE_8703B(pDesc, 0x1);
3114 break;
3115 case _SMS4_:
3116 SET_TX_DESC_SEC_TYPE_8703B(pDesc, 0x2);
3117 break;
3118 case _AES_:
3119 SET_TX_DESC_SEC_TYPE_8703B(pDesc, 0x3);
3120 break;
3121 default:
3122 SET_TX_DESC_SEC_TYPE_8703B(pDesc, 0x0);
3123 break;
3124 }
3125 }
3126
3127 #if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
3128 /* USB interface drop packet if the checksum of descriptor isn't correct. */
3129 /* Using this checksum can let hardware recovery from packet bulk out error (e.g. Cancel URC, Bulk out error.). */
3130 rtl8703b_cal_txdesc_chksum((struct tx_desc *)pDesc);
3131 #endif
3132 }
3133
rtl8703b_InitAntenna_Selection(PADAPTER padapter)3134 void rtl8703b_InitAntenna_Selection(PADAPTER padapter)
3135 {
3136 #if 0
3137 PHAL_DATA_TYPE pHalData;
3138 u8 val;
3139
3140
3141 pHalData = GET_HAL_DATA(padapter);
3142 #if 0
3143 val = rtw_read8(padapter, REG_LEDCFG2);
3144 /* Let 8051 take control antenna settting */
3145 val |= BIT(7); /* DPDT_SEL_EN, 0x4C[23] */
3146 rtw_write8(padapter, REG_LEDCFG2, val);
3147 #else
3148 /* TODO: <20130114, Kordan> The following setting is only for DPDT and Fixed board type. */
3149 /* TODO: A better solution is configure it according EFUSE during the run-time. */
3150 phy_set_mac_reg(padapter, 0x64, BIT20, 0x0); /* 0x66[4]=0 */
3151 phy_set_mac_reg(padapter, 0x64, BIT24, 0x0); /* 0x66[8]=0 */
3152 phy_set_mac_reg(padapter, 0x40, BIT4, 0x0); /* 0x40[4]=0 */
3153 phy_set_mac_reg(padapter, 0x40, BIT3, 0x1); /* 0x40[3]=1 */
3154 phy_set_mac_reg(padapter, 0x4C, BIT24, 0x1); /* 0x4C[24:23]=10 */
3155 phy_set_mac_reg(padapter, 0x4C, BIT23, 0x0); /* 0x4C[24:23]=10 */
3156 phy_set_bb_reg(padapter, 0x944, BIT1 | BIT0, 0x3); /* 0x944[1:0]=11 */
3157 phy_set_bb_reg(padapter, 0x930, bMaskByte0, 0x77); /* 0x930[7:0]=77 */
3158 phy_set_mac_reg(padapter, 0x38, BIT11, 0x1); /* 0x38[11]=1 */
3159 #endif
3160 #endif
3161 }
3162
rtl8703b_CheckAntenna_Selection(PADAPTER padapter)3163 void rtl8703b_CheckAntenna_Selection(PADAPTER padapter)
3164 {
3165 #if 0
3166 PHAL_DATA_TYPE pHalData;
3167 u8 val;
3168
3169
3170 pHalData = GET_HAL_DATA(padapter);
3171
3172 val = rtw_read8(padapter, REG_LEDCFG2);
3173 /* Let 8051 take control antenna settting */
3174 if (!(val & BIT(7))) {
3175 val |= BIT(7); /* DPDT_SEL_EN, 0x4C[23] */
3176 rtw_write8(padapter, REG_LEDCFG2, val);
3177 }
3178 #endif
3179 }
rtl8703b_DeinitAntenna_Selection(PADAPTER padapter)3180 void rtl8703b_DeinitAntenna_Selection(PADAPTER padapter)
3181 {
3182 #if 0
3183 PHAL_DATA_TYPE pHalData;
3184 u8 val;
3185
3186
3187 pHalData = GET_HAL_DATA(padapter);
3188 val = rtw_read8(padapter, REG_LEDCFG2);
3189 /* Let 8051 take control antenna settting */
3190 val &= ~BIT(7); /* DPDT_SEL_EN, clear 0x4C[23] */
3191 rtw_write8(padapter, REG_LEDCFG2, val);
3192 #endif
3193 }
3194
init_hal_spec_8703b(_adapter * adapter)3195 void init_hal_spec_8703b(_adapter *adapter)
3196 {
3197 struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
3198
3199 hal_spec->ic_name = "rtl8703b";
3200 hal_spec->macid_num = 16;
3201 hal_spec->sec_cam_ent_num = 16;
3202 hal_spec->sec_cap = 0;
3203 hal_spec->macid_cap = MACID_DROP_INDIRECT;
3204 hal_spec->macid_txrpt = 0x8100;
3205 hal_spec->macid_txrpt_pgsz = 16;
3206
3207 hal_spec->rfpath_num_2g = 1;
3208 hal_spec->rfpath_num_5g = 0;
3209 hal_spec->rf_reg_path_num = hal_spec->rf_reg_path_avail_num = 1;
3210 hal_spec->rf_reg_trx_path_bmp = 0x11;
3211 hal_spec->max_tx_cnt = 1;
3212
3213 hal_spec->tx_nss_num = 1;
3214 hal_spec->rx_nss_num = 1;
3215 hal_spec->band_cap = BAND_CAP_2G;
3216 hal_spec->bw_cap = BW_CAP_20M | BW_CAP_40M;
3217 hal_spec->port_num = 2;
3218 hal_spec->proto_cap = PROTO_CAP_11B | PROTO_CAP_11G | PROTO_CAP_11N;
3219
3220 hal_spec->txgi_max = 63;
3221 hal_spec->txgi_pdbm = 2;
3222
3223 hal_spec->wl_func = 0
3224 | WL_FUNC_P2P
3225 | WL_FUNC_MIRACAST
3226 | WL_FUNC_TDLS
3227 ;
3228
3229 hal_spec->tx_aclt_unit_factor = 1;
3230
3231 hal_spec->pg_txpwr_saddr = 0x10;
3232 hal_spec->pg_txgi_diff_factor = 1;
3233
3234 rtw_macid_ctl_init_sleep_reg(adapter_to_macidctl(adapter)
3235 , REG_MACID_SLEEP, 0, 0, 0);
3236 }
3237
rtl8703b_init_default_value(PADAPTER padapter)3238 void rtl8703b_init_default_value(PADAPTER padapter)
3239 {
3240 PHAL_DATA_TYPE pHalData;
3241 u8 i;
3242 pHalData = GET_HAL_DATA(padapter);
3243
3244 /* init default value */
3245 pHalData->fw_ractrl = _FALSE;
3246 if (!adapter_to_pwrctl(padapter)->bkeepfwalive)
3247 pHalData->LastHMEBoxNum = 0;
3248
3249 /* init phydm default value */
3250 pHalData->bIQKInitialized = _FALSE;
3251
3252 /* init Efuse variables */
3253 pHalData->EfuseUsedBytes = 0;
3254 pHalData->EfuseUsedPercentage = 0;
3255 #ifdef HAL_EFUSE_MEMORY
3256 pHalData->EfuseHal.fakeEfuseBank = 0;
3257 pHalData->EfuseHal.fakeEfuseUsedBytes = 0;
3258 _rtw_memset(pHalData->EfuseHal.fakeEfuseContent, 0xFF, EFUSE_MAX_HW_SIZE);
3259 _rtw_memset(pHalData->EfuseHal.fakeEfuseInitMap, 0xFF, EFUSE_MAX_MAP_LEN);
3260 _rtw_memset(pHalData->EfuseHal.fakeEfuseModifiedMap, 0xFF, EFUSE_MAX_MAP_LEN);
3261 pHalData->EfuseHal.BTEfuseUsedBytes = 0;
3262 pHalData->EfuseHal.BTEfuseUsedPercentage = 0;
3263 _rtw_memset(pHalData->EfuseHal.BTEfuseContent, 0xFF, EFUSE_MAX_BT_BANK * EFUSE_MAX_HW_SIZE);
3264 _rtw_memset(pHalData->EfuseHal.BTEfuseInitMap, 0xFF, EFUSE_BT_MAX_MAP_LEN);
3265 _rtw_memset(pHalData->EfuseHal.BTEfuseModifiedMap, 0xFF, EFUSE_BT_MAX_MAP_LEN);
3266 pHalData->EfuseHal.fakeBTEfuseUsedBytes = 0;
3267 _rtw_memset(pHalData->EfuseHal.fakeBTEfuseContent, 0xFF, EFUSE_MAX_BT_BANK * EFUSE_MAX_HW_SIZE);
3268 _rtw_memset(pHalData->EfuseHal.fakeBTEfuseInitMap, 0xFF, EFUSE_BT_MAX_MAP_LEN);
3269 _rtw_memset(pHalData->EfuseHal.fakeBTEfuseModifiedMap, 0xFF, EFUSE_BT_MAX_MAP_LEN);
3270 #endif
3271 }
3272
GetEEPROMSize8703B(PADAPTER padapter)3273 u8 GetEEPROMSize8703B(PADAPTER padapter)
3274 {
3275 u8 size = 0;
3276 u32 cr;
3277
3278 cr = rtw_read16(padapter, REG_9346CR);
3279 /* 6: EEPROM used is 93C46, 4: boot from E-Fuse. */
3280 size = (cr & BOOT_FROM_EEPROM) ? 6 : 4;
3281
3282 RTW_INFO("EEPROM type is %s\n", size == 4 ? "E-FUSE" : "93C46");
3283
3284 return size;
3285 }
3286
3287 /* -------------------------------------------------------------------------
3288 *
3289 * LLT R/W/Init function
3290 *
3291 * ------------------------------------------------------------------------- */
rtl8703b_InitLLTTable(PADAPTER padapter)3292 s32 rtl8703b_InitLLTTable(PADAPTER padapter)
3293 {
3294 systime start;
3295 u32 passing_time;
3296 u32 val32;
3297 s32 ret;
3298
3299
3300 ret = _FAIL;
3301
3302 val32 = rtw_read32(padapter, REG_AUTO_LLT);
3303 val32 |= BIT_AUTO_INIT_LLT;
3304 rtw_write32(padapter, REG_AUTO_LLT, val32);
3305
3306 start = rtw_get_current_time();
3307
3308 do {
3309 val32 = rtw_read32(padapter, REG_AUTO_LLT);
3310 if (!(val32 & BIT_AUTO_INIT_LLT)) {
3311 ret = _SUCCESS;
3312 break;
3313 }
3314
3315 passing_time = rtw_get_passing_time_ms(start);
3316 if (passing_time > 1000) {
3317 RTW_INFO("%s: FAIL!! REG_AUTO_LLT(0x%X)=%08x\n",
3318 __FUNCTION__, REG_AUTO_LLT, val32);
3319 break;
3320 }
3321
3322 rtw_usleep_os(2);
3323 } while (1);
3324
3325 return ret;
3326 }
3327
3328 #if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
_DisableGPIO(PADAPTER padapter)3329 void _DisableGPIO(PADAPTER padapter)
3330 {
3331 #if 0
3332 /* **************************************
3333 * j. GPIO_PIN_CTRL 0x44[31:0]=0x000
3334 * k.Value = GPIO_PIN_CTRL[7:0]
3335 * l. GPIO_PIN_CTRL 0x44[31:0] = 0x00FF0000 | (value <<8); write external PIN level
3336 * m. GPIO_MUXCFG 0x42 [15:0] = 0x0780
3337 * n. LEDCFG 0x4C[15:0] = 0x8080
3338 * ************************************** */
3339 #endif
3340 u8 value8;
3341 u16 value16;
3342 u32 value32;
3343 u32 u4bTmp;
3344
3345
3346 /* 1. Disable GPIO[7:0] */
3347 rtw_write16(padapter, REG_GPIO_PIN_CTRL + 2, 0x0000);
3348 value32 = rtw_read32(padapter, REG_GPIO_PIN_CTRL) & 0xFFFF00FF;
3349 u4bTmp = value32 & 0x000000FF;
3350 value32 |= ((u4bTmp << 8) | 0x00FF0000);
3351 rtw_write32(padapter, REG_GPIO_PIN_CTRL, value32);
3352
3353
3354 /* 2. Disable GPIO[10:8] */
3355 rtw_write8(padapter, REG_MAC_PINMUX_CFG, 0x00);
3356 value16 = rtw_read16(padapter, REG_GPIO_IO_SEL) & 0xFF0F;
3357 value8 = (u8)(value16 & 0x000F);
3358 value16 |= ((value8 << 4) | 0x0780);
3359 rtw_write16(padapter, REG_GPIO_IO_SEL, value16);
3360
3361
3362 /* 3. Disable LED0 & 1 */
3363 rtw_write16(padapter, REG_LEDCFG0, 0x8080);
3364
3365 } /* end of _DisableGPIO() */
3366
_DisableRFAFEAndResetBB8703B(PADAPTER padapter)3367 void _DisableRFAFEAndResetBB8703B(PADAPTER padapter)
3368 {
3369 #if 0
3370 /* *************************************
3371 * a. TXPAUSE 0x522[7:0] = 0xFF Pause MAC TX queue
3372 * b. RF path 0 offset 0x00 = 0x00 disable RF
3373 * c. APSD_CTRL 0x600[7:0] = 0x40
3374 * d. SYS_FUNC_EN 0x02[7:0] = 0x16 reset BB state machine
3375 * e. SYS_FUNC_EN 0x02[7:0] = 0x14 reset BB state machine
3376 * ************************************** */
3377 #endif
3378 enum rf_path eRFPath = RF_PATH_A, value8 = 0;
3379
3380 rtw_write8(padapter, REG_TXPAUSE, 0xFF);
3381
3382 phy_set_rf_reg(padapter, eRFPath, 0x0, bMaskByte0, 0x0);
3383
3384 value8 |= APSDOFF;
3385 rtw_write8(padapter, REG_APSD_CTRL, value8);/* 0x40 */
3386
3387 /* Set BB reset at first */
3388 value8 = 0 ;
3389 value8 |= (FEN_USBD | FEN_USBA | FEN_BB_GLB_RSTn);
3390 rtw_write8(padapter, REG_SYS_FUNC_EN, value8); /* 0x16 */
3391
3392 /* Set global reset. */
3393 value8 &= ~FEN_BB_GLB_RSTn;
3394 rtw_write8(padapter, REG_SYS_FUNC_EN, value8); /* 0x14 */
3395
3396 /* 2010/08/12 MH We need to set BB/GLBAL reset to save power for SS mode. */
3397
3398 }
3399
_DisableRFAFEAndResetBB(PADAPTER padapter)3400 void _DisableRFAFEAndResetBB(PADAPTER padapter)
3401 {
3402 _DisableRFAFEAndResetBB8703B(padapter);
3403 }
3404
_ResetDigitalProcedure1_8703B(PADAPTER padapter,BOOLEAN bWithoutHWSM)3405 void _ResetDigitalProcedure1_8703B(PADAPTER padapter, BOOLEAN bWithoutHWSM)
3406 {
3407 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
3408
3409 if (IS_FW_81xxC(padapter) && (pHalData->firmware_version <= 0x20)) {
3410 #if 0
3411 #if 0
3412 /* **************************** */
3413 /* f. SYS_FUNC_EN 0x03[7:0]=0x54 reset MAC register, DCORE */
3414 /* g. MCUFWDL 0x80[7:0]=0 reset MCU ready status
3415 * ***************************** */
3416 #endif
3417 u32 value32 = 0;
3418 rtw_write8(padapter, REG_SYS_FUNC_EN + 1, 0x54);
3419 rtw_write8(padapter, REG_MCUFWDL, 0);
3420 #else
3421 #if 0
3422 /* **************************** */
3423 /* f. MCUFWDL 0x80[7:0]=0 reset MCU ready status */
3424 /* g. SYS_FUNC_EN 0x02[10]= 0 reset MCU register, (8051 reset) */
3425 /* h. SYS_FUNC_EN 0x02[15-12]= 5 reset MAC register, DCORE */
3426 /* i. SYS_FUNC_EN 0x02[10]= 1 enable MCU register, (8051 enable) */
3427 /* ***************************** */
3428 #endif
3429 u16 valu16 = 0;
3430 rtw_write8(padapter, REG_MCUFWDL, 0);
3431
3432 valu16 = rtw_read16(padapter, REG_SYS_FUNC_EN);
3433 rtw_write16(padapter, REG_SYS_FUNC_EN, (valu16 & (~FEN_CPUEN)));/* reset MCU ,8051 */
3434
3435 valu16 = rtw_read16(padapter, REG_SYS_FUNC_EN) & 0x0FFF;
3436 rtw_write16(padapter, REG_SYS_FUNC_EN, (valu16 | (FEN_HWPDN | FEN_ELDR))); /* reset MAC */
3437
3438 valu16 = rtw_read16(padapter, REG_SYS_FUNC_EN);
3439 rtw_write16(padapter, REG_SYS_FUNC_EN, (valu16 | FEN_CPUEN));/* enable MCU ,8051 */
3440 #endif
3441 } else {
3442 u8 retry_cnts = 0;
3443
3444 /* 2010/08/12 MH For USB SS, we can not stop 8051 when we are trying to */
3445 /* enter IPS/HW&SW radio off. For S3/S4/S5/Disable, we can stop 8051 because */
3446 /* we will init FW when power on again. */
3447 /* if(!pDevice->RegUsbSS) */
3448 { /* If we want to SS mode, we can not reset 8051. */
3449 if (rtw_read8(padapter, REG_MCUFWDL) & BIT1) {
3450 /* IF fw in RAM code, do reset */
3451
3452
3453 if (pHalData->bFWReady) {
3454 /* 2010/08/25 MH Accordign to RD alfred's suggestion, we need to disable other */
3455 /* HRCV INT to influence 8051 reset. */
3456 rtw_write8(padapter, REG_FWIMR, 0x20);
3457 /* 2011/02/15 MH According to Alex's suggestion, close mask to prevent incorrect FW write operation. */
3458 rtw_write8(padapter, REG_FTIMR, 0x00);
3459 rtw_write8(padapter, REG_FSIMR, 0x00);
3460
3461 rtw_write8(padapter, REG_HMETFR + 3, 0x20); /* 8051 reset by self */
3462
3463 while ((retry_cnts++ < 100) && (FEN_CPUEN & rtw_read16(padapter, REG_SYS_FUNC_EN))) {
3464 rtw_udelay_os(50);/* us */
3465 /* 2010/08/25 For test only We keep on reset 5051 to prevent fail. */
3466 /* rtw_write8(padapter, REG_HMETFR+3, 0x20); */ /* 8051 reset by self */
3467 }
3468 /* RT_ASSERT((retry_cnts < 100), ("8051 reset failed!\n")); */
3469
3470 if (retry_cnts >= 100) {
3471 /* if 8051 reset fail we trigger GPIO 0 for LA */
3472 /* rtw_write32( padapter, */
3473 /* REG_GPIO_PIN_CTRL, */
3474 /* 0x00010100); */
3475 /* 2010/08/31 MH According to Filen's info, if 8051 reset fail, reset MAC directly. */
3476 rtw_write8(padapter, REG_SYS_FUNC_EN + 1, 0x50); /* Reset MAC and Enable 8051 */
3477 rtw_mdelay_os(10);
3478 }
3479
3480 }
3481 }
3482
3483 rtw_write8(padapter, REG_SYS_FUNC_EN + 1, 0x54); /* Reset MAC and Enable 8051 */
3484 rtw_write8(padapter, REG_MCUFWDL, 0);
3485 }
3486 }
3487
3488 /* if(pDevice->RegUsbSS) */
3489 /* bWithoutHWSM = TRUE; */ /* Sugest by Filen and Issau. */
3490
3491 if (bWithoutHWSM) {
3492 /* HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); */
3493 #if 0
3494 /* **************************** */
3495 /* Without HW auto state machine */
3496 /* g. SYS_CLKR 0x08[15:0] = 0x30A3 disable MAC clock */
3497 /* h. AFE_PLL_CTRL 0x28[7:0] = 0x80 disable AFE PLL */
3498 /* i. AFE_XTAL_CTRL 0x24[15:0] = 0x880F gated AFE DIG_CLOCK */
3499 /* j. SYS_ISO_CTRL 0x00[7:0] = 0xF9 isolated digital to PON */
3500 /* ***************************** */
3501 #endif
3502 /* rtw_write16(padapter, REG_SYS_CLKR, 0x30A3); */
3503 /* if(!pDevice->RegUsbSS) */
3504 /* 2011/01/26 MH SD4 Scott suggest to fix UNC-B cut bug. */
3505 rtw_write16(padapter, REG_SYS_CLKR, 0x70A3); /* modify to 0x70A3 by Scott. */
3506 rtw_write8(padapter, REG_AFE_PLL_CTRL, 0x80);
3507 rtw_write16(padapter, REG_AFE_XTAL_CTRL, 0x880F);
3508 /* if(!pDevice->RegUsbSS) */
3509 rtw_write8(padapter, REG_SYS_ISO_CTRL, 0xF9);
3510 } else {
3511 /* Disable all RF/BB power */
3512 rtw_write8(padapter, REG_RF_CTRL, 0x00);
3513 }
3514
3515 }
3516
_ResetDigitalProcedure1(PADAPTER padapter,BOOLEAN bWithoutHWSM)3517 void _ResetDigitalProcedure1(PADAPTER padapter, BOOLEAN bWithoutHWSM)
3518 {
3519 _ResetDigitalProcedure1_8703B(padapter, bWithoutHWSM);
3520 }
3521
_ResetDigitalProcedure2(PADAPTER padapter)3522 void _ResetDigitalProcedure2(PADAPTER padapter)
3523 {
3524 /* HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); */
3525 #if 0
3526 /* ****************************
3527 * k. SYS_FUNC_EN 0x03[7:0] = 0x44 disable ELDR runction
3528 * l. SYS_CLKR 0x08[15:0] = 0x3083 disable ELDR clock
3529 * m. SYS_ISO_CTRL 0x01[7:0] = 0x83 isolated ELDR to PON
3530 * ***************************** */
3531 #endif
3532 /* rtw_write8(padapter, REG_SYS_FUNC_EN+1, 0x44); */ /* marked by Scott. */
3533 /* 2011/01/26 MH SD4 Scott suggest to fix UNC-B cut bug. */
3534 rtw_write16(padapter, REG_SYS_CLKR, 0x70a3); /* modify to 0x70a3 by Scott. */
3535 rtw_write8(padapter, REG_SYS_ISO_CTRL + 1, 0x82); /* modify to 0x82 by Scott. */
3536 }
3537
_DisableAnalog(PADAPTER padapter,BOOLEAN bWithoutHWSM)3538 void _DisableAnalog(PADAPTER padapter, BOOLEAN bWithoutHWSM)
3539 {
3540 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
3541 u16 value16 = 0;
3542 u8 value8 = 0;
3543
3544
3545 if (bWithoutHWSM) {
3546 #if 0
3547 /* **************************** */
3548 /* n. LDOA15_CTRL 0x20[7:0] = 0x04 disable A15 power */
3549 /* o. LDOV12D_CTRL 0x21[7:0] = 0x54 disable digital core power */
3550 /* r. When driver call disable, the ASIC will turn off remaining clock automatically */
3551 /* ***************************** */
3552 #endif
3553
3554 rtw_write8(padapter, REG_LDOA15_CTRL, 0x04);
3555 /* rtw_write8(padapter, REG_LDOV12D_CTRL, 0x54); */
3556
3557 value8 = rtw_read8(padapter, REG_LDOV12D_CTRL);
3558 value8 &= (~LDV12_EN);
3559 rtw_write8(padapter, REG_LDOV12D_CTRL, value8);
3560 }
3561
3562 #if 0
3563 /* **************************** */
3564 /* h. SPS0_CTRL 0x11[7:0] = 0x23 enter PFM mode */
3565 /* i. APS_FSMCO 0x04[15:0] = 0x4802 set USB suspend */
3566 /* ***************************** */
3567 #endif
3568 value8 = 0x23;
3569
3570 rtw_write8(padapter, REG_SPS0_CTRL, value8);
3571
3572 if (bWithoutHWSM) {
3573 /* value16 |= (APDM_HOST | AFSM_HSUS |PFM_ALDN); */
3574 /* 2010/08/31 According to Filen description, we need to use HW to shut down 8051 automatically. */
3575 /* Becasue suspend operatione need the asistance of 8051 to wait for 3ms. */
3576 value16 |= (APDM_HOST | AFSM_HSUS | PFM_ALDN);
3577 } else
3578 value16 |= (APDM_HOST | AFSM_HSUS | PFM_ALDN);
3579
3580 rtw_write16(padapter, REG_APS_FSMCO, value16);/* 0x4802 */
3581
3582 rtw_write8(padapter, REG_RSV_CTRL, 0x0e);
3583
3584 #if 0
3585 /* tynli_test for suspend mode. */
3586 if (!bWithoutHWSM)
3587 rtw_write8(padapter, 0xfe10, 0x19);
3588 #endif
3589
3590 }
3591
3592 /* HW Auto state machine */
CardDisableHWSM(PADAPTER padapter,u8 resetMCU)3593 s32 CardDisableHWSM(PADAPTER padapter, u8 resetMCU)
3594 {
3595 int rtStatus = _SUCCESS;
3596
3597
3598 if (RTW_CANNOT_RUN(padapter))
3599 return rtStatus;
3600
3601 /* ==== RF Off Sequence ==== */
3602 _DisableRFAFEAndResetBB(padapter);
3603
3604 /* ==== Reset digital sequence ====== */
3605 _ResetDigitalProcedure1(padapter, _FALSE);
3606
3607 /* ==== Pull GPIO PIN to balance level and LED control ====== */
3608 _DisableGPIO(padapter);
3609
3610 /* ==== Disable analog sequence === */
3611 _DisableAnalog(padapter, _FALSE);
3612
3613
3614 return rtStatus;
3615 }
3616
3617 /* without HW Auto state machine */
CardDisableWithoutHWSM(PADAPTER padapter)3618 s32 CardDisableWithoutHWSM(PADAPTER padapter)
3619 {
3620 s32 rtStatus = _SUCCESS;
3621
3622
3623 if (RTW_CANNOT_RUN(padapter))
3624 return rtStatus;
3625
3626
3627 /* ==== RF Off Sequence ==== */
3628 _DisableRFAFEAndResetBB(padapter);
3629
3630 /* ==== Reset digital sequence ====== */
3631 _ResetDigitalProcedure1(padapter, _TRUE);
3632
3633 /* ==== Pull GPIO PIN to balance level and LED control ====== */
3634 _DisableGPIO(padapter);
3635
3636 /* ==== Reset digital sequence ====== */
3637 _ResetDigitalProcedure2(padapter);
3638
3639 /* ==== Disable analog sequence === */
3640 _DisableAnalog(padapter, _TRUE);
3641
3642 return rtStatus;
3643 }
3644 #endif /* CONFIG_USB_HCI || CONFIG_SDIO_HCI || CONFIG_GSPI_HCI */
3645
3646 void
Hal_InitPGData(PADAPTER padapter,u8 * PROMContent)3647 Hal_InitPGData(
3648 PADAPTER padapter,
3649 u8 *PROMContent)
3650 {
3651
3652 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
3653 u32 i;
3654 u16 value16;
3655
3656 if (_FALSE == pHalData->bautoload_fail_flag) {
3657 /* autoload OK.
3658 * if (IS_BOOT_FROM_EEPROM(padapter)) */
3659 if (_TRUE == pHalData->EepromOrEfuse) {
3660 /* Read all Content from EEPROM or EFUSE. */
3661 for (i = 0; i < HWSET_MAX_SIZE_8703B; i += 2) {
3662 /* value16 = EF2Byte(ReadEEprom(pAdapter, (u16) (i>>1)));
3663 * *((u16*)(&PROMContent[i])) = value16; */
3664 }
3665 } else {
3666 /* Read EFUSE real map to shadow. */
3667 EFUSE_ShadowMapUpdate(padapter, EFUSE_WIFI, _FALSE);
3668 }
3669 } else {
3670 /* autoload fail */
3671 /* pHalData->AutoloadFailFlag = _TRUE; */
3672 /* update to default value 0xFF */
3673 if (_FALSE == pHalData->EepromOrEfuse)
3674 EFUSE_ShadowMapUpdate(padapter, EFUSE_WIFI, _FALSE);
3675 }
3676
3677 #ifdef CONFIG_EFUSE_CONFIG_FILE
3678 if (check_phy_efuse_tx_power_info_valid(padapter) == _FALSE) {
3679 if (Hal_readPGDataFromConfigFile(padapter) != _SUCCESS)
3680 RTW_ERR("invalid phy efuse and read from file fail, will use driver default!!\n");
3681 }
3682 #endif
3683 }
3684
3685 void
Hal_EfuseParseIDCode(PADAPTER padapter,u8 * hwinfo)3686 Hal_EfuseParseIDCode(
3687 PADAPTER padapter,
3688 u8 *hwinfo
3689 )
3690 {
3691 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
3692 u16 EEPROMId;
3693
3694
3695 /* Checl 0x8129 again for making sure autoload status!! */
3696 EEPROMId = le16_to_cpu(*((u16 *)hwinfo));
3697 if (EEPROMId != RTL_EEPROM_ID) {
3698 RTW_INFO("EEPROM ID(%#x) is invalid!!\n", EEPROMId);
3699 pHalData->bautoload_fail_flag = _TRUE;
3700 } else
3701 pHalData->bautoload_fail_flag = _FALSE;
3702
3703 }
3704 void
Hal_EfuseParseTxPowerInfo_8703B(PADAPTER padapter,u8 * PROMContent,BOOLEAN AutoLoadFail)3705 Hal_EfuseParseTxPowerInfo_8703B(
3706 PADAPTER padapter,
3707 u8 *PROMContent,
3708 BOOLEAN AutoLoadFail
3709 )
3710 {
3711 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
3712
3713 pHalData->txpwr_pg_mode = TXPWR_PG_WITH_PWR_IDX;
3714
3715 /* 2010/10/19 MH Add Regulator recognize for CU. */
3716 if (!AutoLoadFail) {
3717 pHalData->EEPROMRegulatory = (PROMContent[EEPROM_RF_BOARD_OPTION_8703B] & 0x7); /* bit0~2 */
3718 if (PROMContent[EEPROM_RF_BOARD_OPTION_8703B] == 0xFF)
3719 pHalData->EEPROMRegulatory = (EEPROM_DEFAULT_BOARD_OPTION & 0x7); /* bit0~2 */
3720 } else
3721 pHalData->EEPROMRegulatory = 0;
3722 }
3723
3724 void
Hal_EfuseParseBoardType_8703B(PADAPTER Adapter,u8 * PROMContent,BOOLEAN AutoloadFail)3725 Hal_EfuseParseBoardType_8703B(
3726 PADAPTER Adapter,
3727 u8 *PROMContent,
3728 BOOLEAN AutoloadFail
3729 )
3730 {
3731
3732
3733 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
3734
3735 if (!AutoloadFail) {
3736 pHalData->InterfaceSel = (PROMContent[EEPROM_RF_BOARD_OPTION_8703B] & 0xE0) >> 5;
3737 if (PROMContent[EEPROM_RF_BOARD_OPTION_8703B] == 0xFF)
3738 pHalData->InterfaceSel = (EEPROM_DEFAULT_BOARD_OPTION & 0xE0) >> 5;
3739 } else
3740 pHalData->InterfaceSel = 0;
3741
3742 }
3743
3744 void
Hal_EfuseParseBTCoexistInfo_8703B(PADAPTER padapter,u8 * hwinfo,BOOLEAN AutoLoadFail)3745 Hal_EfuseParseBTCoexistInfo_8703B(
3746 PADAPTER padapter,
3747 u8 *hwinfo,
3748 BOOLEAN AutoLoadFail
3749 )
3750 {
3751 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
3752 u8 tempval;
3753 u32 tmpu4;
3754
3755 if (!AutoLoadFail) {
3756 tmpu4 = rtw_read32(padapter, REG_MULTI_FUNC_CTRL);
3757 if (tmpu4 & BT_FUNC_EN)
3758 pHalData->EEPROMBluetoothCoexist = _TRUE;
3759 else
3760 pHalData->EEPROMBluetoothCoexist = _FALSE;
3761
3762 pHalData->EEPROMBluetoothType = BT_RTL8703B;
3763
3764 tempval = hwinfo[EEPROM_RF_BT_SETTING_8703B];
3765 if (tempval != 0xFF) {
3766 pHalData->EEPROMBluetoothAntNum = tempval & BIT(0);
3767 #ifdef CONFIG_USB_HCI
3768 /*if(rtw_get_intf_type(padapter) == RTW_USB)*/
3769 pHalData->ant_path = RF_PATH_B; /* s0 */
3770 #else /* SDIO or PCIE */
3771 /* EFUSE_0xC3[6] == 0, S1(Main)-RF_PATH_A; */
3772 /* EFUSE_0xC3[6] == 1, S0(Aux)-RF_PATH_B */
3773 pHalData->ant_path = (tempval & BIT(6)) ? RF_PATH_B : RF_PATH_A;
3774 #endif
3775 } else {
3776 pHalData->EEPROMBluetoothAntNum = Ant_x1;
3777 #ifdef CONFIG_USB_HCI
3778 pHalData->ant_path = RF_PATH_B;/* s0 */
3779 #else
3780 pHalData->ant_path = RF_PATH_A;
3781 #endif
3782 }
3783 } else {
3784 if (padapter->registrypriv.mp_mode == 1)
3785 pHalData->EEPROMBluetoothCoexist = _TRUE;
3786 else
3787 pHalData->EEPROMBluetoothCoexist = _FALSE;
3788 pHalData->EEPROMBluetoothType = BT_RTL8703B;
3789 pHalData->EEPROMBluetoothAntNum = Ant_x1;
3790 #ifdef CONFIG_USB_HCI
3791 pHalData->ant_path = RF_PATH_B;/* s0 */
3792 #else
3793 pHalData->ant_path = RF_PATH_A;
3794 #endif
3795 }
3796
3797 #ifdef CONFIG_BT_COEXIST
3798 if (padapter->registrypriv.ant_num > 0) {
3799 RTW_INFO("%s: Apply driver defined antenna number(%d) to replace origin(%d)\n",
3800 __FUNCTION__,
3801 padapter->registrypriv.ant_num,
3802 pHalData->EEPROMBluetoothAntNum == Ant_x2 ? 2 : 1);
3803
3804 switch (padapter->registrypriv.ant_num) {
3805 case 1:
3806 pHalData->EEPROMBluetoothAntNum = Ant_x1;
3807 break;
3808 case 2:
3809 pHalData->EEPROMBluetoothAntNum = Ant_x2;
3810 break;
3811 default:
3812 RTW_INFO("%s: Discard invalid driver defined antenna number(%d)!\n",
3813 __FUNCTION__, padapter->registrypriv.ant_num);
3814 break;
3815 }
3816 }
3817 #endif /* CONFIG_BT_COEXIST */
3818
3819 RTW_INFO("%s: %s BT-coex, ant_num=%d\n",
3820 __FUNCTION__,
3821 pHalData->EEPROMBluetoothCoexist == _TRUE ? "Enable" : "Disable",
3822 pHalData->EEPROMBluetoothAntNum == Ant_x2 ? 2 : 1);
3823 }
3824
3825 void
Hal_EfuseParseEEPROMVer_8703B(PADAPTER padapter,u8 * hwinfo,BOOLEAN AutoLoadFail)3826 Hal_EfuseParseEEPROMVer_8703B(
3827 PADAPTER padapter,
3828 u8 *hwinfo,
3829 BOOLEAN AutoLoadFail
3830 )
3831 {
3832 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
3833
3834 if (!AutoLoadFail)
3835 pHalData->EEPROMVersion = hwinfo[EEPROM_VERSION_8703B];
3836 else
3837 pHalData->EEPROMVersion = 1;
3838 }
3839
3840 void
Hal_EfuseParseVoltage_8703B(PADAPTER pAdapter,u8 * hwinfo,BOOLEAN AutoLoadFail)3841 Hal_EfuseParseVoltage_8703B(
3842 PADAPTER pAdapter,
3843 u8 *hwinfo,
3844 BOOLEAN AutoLoadFail
3845 )
3846 {
3847 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
3848
3849 /* _rtw_memcpy(pHalData->adjuseVoltageVal, &hwinfo[EEPROM_Voltage_ADDR_8703B], 1); */
3850 RTW_INFO("%s hwinfo[EEPROM_Voltage_ADDR_8703B] =%02x\n", __func__, hwinfo[EEPROM_Voltage_ADDR_8703B]);
3851 pHalData->adjuseVoltageVal = (hwinfo[EEPROM_Voltage_ADDR_8703B] & 0xf0) >> 4 ;
3852 RTW_INFO("%s pHalData->adjuseVoltageVal =%x\n", __func__, pHalData->adjuseVoltageVal);
3853 }
3854
3855 void
Hal_EfuseParseChnlPlan_8703B(PADAPTER padapter,u8 * hwinfo,BOOLEAN AutoLoadFail)3856 Hal_EfuseParseChnlPlan_8703B(
3857 PADAPTER padapter,
3858 u8 *hwinfo,
3859 BOOLEAN AutoLoadFail
3860 )
3861 {
3862 hal_com_config_channel_plan(
3863 padapter
3864 , hwinfo ? &hwinfo[EEPROM_COUNTRY_CODE_8703B] : NULL
3865 , hwinfo ? hwinfo[EEPROM_ChannelPlan_8703B] : 0xFF
3866 , padapter->registrypriv.alpha2
3867 , padapter->registrypriv.channel_plan
3868 , AutoLoadFail
3869 );
3870 }
3871
3872 void
Hal_EfuseParseCustomerID_8703B(PADAPTER padapter,u8 * hwinfo,BOOLEAN AutoLoadFail)3873 Hal_EfuseParseCustomerID_8703B(
3874 PADAPTER padapter,
3875 u8 *hwinfo,
3876 BOOLEAN AutoLoadFail
3877 )
3878 {
3879 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
3880
3881 if (!AutoLoadFail)
3882 pHalData->EEPROMCustomerID = hwinfo[EEPROM_CustomID_8703B];
3883 else
3884 pHalData->EEPROMCustomerID = 0;
3885 }
3886
3887 void
Hal_EfuseParseAntennaDiversity_8703B(PADAPTER pAdapter,u8 * hwinfo,BOOLEAN AutoLoadFail)3888 Hal_EfuseParseAntennaDiversity_8703B(
3889 PADAPTER pAdapter,
3890 u8 *hwinfo,
3891 BOOLEAN AutoLoadFail
3892 )
3893 {
3894 #ifdef CONFIG_ANTENNA_DIVERSITY
3895 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter);
3896 struct registry_priv *registry_par = &pAdapter->registrypriv;
3897
3898 if (pHalData->EEPROMBluetoothAntNum == Ant_x1)
3899 pHalData->AntDivCfg = 0;
3900 else {
3901 if (registry_par->antdiv_cfg == 2) /* 0:OFF , 1:ON, 2:By EFUSE */
3902 pHalData->AntDivCfg = 1;
3903 else
3904 pHalData->AntDivCfg = registry_par->antdiv_cfg;
3905 }
3906
3907 /* If TRxAntDivType is AUTO in advanced setting, use EFUSE value instead. */
3908 if (registry_par->antdiv_type == 0) {
3909 pHalData->TRxAntDivType = hwinfo[EEPROM_RFE_OPTION_8703B];
3910 if (pHalData->TRxAntDivType == 0xFF)
3911 pHalData->TRxAntDivType = S0S1_SW_ANTDIV;/* GetRegAntDivType(pAdapter); */
3912 else if (pHalData->TRxAntDivType == 0x10)
3913 pHalData->TRxAntDivType = S0S1_SW_ANTDIV; /* intrnal switch S0S1 */
3914 else if (pHalData->TRxAntDivType == 0x11)
3915 pHalData->TRxAntDivType = S0S1_SW_ANTDIV; /* intrnal switch S0S1 */
3916 else
3917 RTW_INFO("%s: efuse[0x%x]=0x%02x is unknown type\n",
3918 __FUNCTION__, EEPROM_RFE_OPTION_8703B, pHalData->TRxAntDivType);
3919 } else {
3920 pHalData->TRxAntDivType = registry_par->antdiv_type ;/* GetRegAntDivType(pAdapter); */
3921 }
3922
3923 RTW_INFO("%s: AntDivCfg=%d, AntDivType=%d\n",
3924 __FUNCTION__, pHalData->AntDivCfg, pHalData->TRxAntDivType);
3925 #endif
3926 }
3927
3928 void
Hal_EfuseParseXtal_8703B(PADAPTER pAdapter,u8 * hwinfo,BOOLEAN AutoLoadFail)3929 Hal_EfuseParseXtal_8703B(
3930 PADAPTER pAdapter,
3931 u8 *hwinfo,
3932 BOOLEAN AutoLoadFail
3933 )
3934 {
3935 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
3936
3937 if (!AutoLoadFail) {
3938 pHalData->crystal_cap = hwinfo[EEPROM_XTAL_8703B];
3939 if (pHalData->crystal_cap == 0xFF)
3940 pHalData->crystal_cap = EEPROM_Default_CrystalCap_8703B; /* what value should 8812 set? */
3941 } else
3942 pHalData->crystal_cap = EEPROM_Default_CrystalCap_8703B;
3943 }
3944
3945
3946 void
Hal_EfuseParseThermalMeter_8703B(PADAPTER padapter,u8 * PROMContent,u8 AutoLoadFail)3947 Hal_EfuseParseThermalMeter_8703B(
3948 PADAPTER padapter,
3949 u8 *PROMContent,
3950 u8 AutoLoadFail
3951 )
3952 {
3953 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
3954
3955 /* */
3956 /* ThermalMeter from EEPROM */
3957 /* */
3958 if (_FALSE == AutoLoadFail)
3959 pHalData->eeprom_thermal_meter = PROMContent[EEPROM_THERMAL_METER_8703B];
3960 else
3961 pHalData->eeprom_thermal_meter = EEPROM_Default_ThermalMeter_8703B;
3962
3963 if ((pHalData->eeprom_thermal_meter == 0xff) || (_TRUE == AutoLoadFail)) {
3964 pHalData->odmpriv.rf_calibrate_info.is_apk_thermal_meter_ignore = _TRUE;
3965 pHalData->eeprom_thermal_meter = EEPROM_Default_ThermalMeter_8703B;
3966 }
3967
3968 }
3969
3970
Hal_ReadRFGainOffset(PADAPTER Adapter,u8 * PROMContent,BOOLEAN AutoloadFail)3971 void Hal_ReadRFGainOffset(
3972 PADAPTER Adapter,
3973 u8 *PROMContent,
3974 BOOLEAN AutoloadFail)
3975 {
3976 #ifdef CONFIG_RF_POWER_TRIM
3977
3978 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
3979 struct kfree_data_t *kfree_data = &pHalData->kfree_data;
3980 u8 pg_pwrtrim = 0xFF, pg_therm = 0xFF;
3981
3982 RTW_INFO("%s, Pwr Trim Enable config:%d\n", __func__, Adapter->registrypriv.RegPwrTrimEnable);
3983
3984 if ((Adapter->registrypriv.RegPwrTrimEnable == 1) || !AutoloadFail) {
3985 efuse_OneByteRead(Adapter, PPG_BB_GAIN_2G_TXA_OFFSET_8703B, &pg_pwrtrim, _FALSE);
3986 efuse_OneByteRead(Adapter, PPG_THERMAL_OFFSET_8703B, &pg_therm, _FALSE);
3987
3988 kfree_data->bb_gain[BB_GAIN_2G][RF_PATH_A]
3989 = KFREE_BB_GAIN_2G_TX_OFFSET(pg_pwrtrim & PPG_BB_GAIN_2G_TX_OFFSET_MASK);
3990 kfree_data->thermal
3991 = KFREE_THERMAL_OFFSET(pg_therm & PPG_THERMAL_OFFSET_MASK);
3992
3993 if (GET_PG_KFREE_ON_8703B(PROMContent) && PROMContent[0xc1] != 0xff)
3994 kfree_data->flag |= KFREE_FLAG_ON;
3995 if (GET_PG_KFREE_THERMAL_K_ON_8703B(PROMContent) && PROMContent[0xc8] != 0xff)
3996 kfree_data->flag |= KFREE_FLAG_THERMAL_K_ON;
3997 }
3998
3999 if (Adapter->registrypriv.RegPwrTrimEnable == 1) {
4000 kfree_data->flag |= KFREE_FLAG_ON;
4001 kfree_data->flag |= KFREE_FLAG_THERMAL_K_ON;
4002 }
4003
4004 if (kfree_data->flag & KFREE_FLAG_THERMAL_K_ON)
4005 pHalData->eeprom_thermal_meter += kfree_data->thermal;
4006
4007 RTW_INFO("kfree flag:%u\n", kfree_data->flag);
4008 if (Adapter->registrypriv.RegPwrTrimEnable == 1 || kfree_data->flag & KFREE_FLAG_ON)
4009 RTW_INFO("bb_gain:%d\n", kfree_data->bb_gain[BB_GAIN_2G][RF_PATH_A]);
4010 if (Adapter->registrypriv.RegPwrTrimEnable == 1 || kfree_data->flag & KFREE_FLAG_THERMAL_K_ON)
4011 RTW_INFO("thermal:%d\n", kfree_data->thermal);
4012
4013 #endif /*CONFIG_RF_POWER_TRIM */
4014
4015 }
4016
4017
4018 u8
BWMapping_8703B(PADAPTER Adapter,struct pkt_attrib * pattrib)4019 BWMapping_8703B(
4020 PADAPTER Adapter,
4021 struct pkt_attrib *pattrib
4022 )
4023 {
4024 u8 BWSettingOfDesc = 0;
4025 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
4026
4027 /* RTW_INFO("BWMapping pHalData->current_channel_bw %d, pattrib->bwmode %d\n",pHalData->current_channel_bw,pattrib->bwmode); */
4028
4029 if (pHalData->current_channel_bw == CHANNEL_WIDTH_80) {
4030 if (pattrib->bwmode == CHANNEL_WIDTH_80)
4031 BWSettingOfDesc = 2;
4032 else if (pattrib->bwmode == CHANNEL_WIDTH_40)
4033 BWSettingOfDesc = 1;
4034 else
4035 BWSettingOfDesc = 0;
4036 } else if (pHalData->current_channel_bw == CHANNEL_WIDTH_40) {
4037 if ((pattrib->bwmode == CHANNEL_WIDTH_40) || (pattrib->bwmode == CHANNEL_WIDTH_80))
4038 BWSettingOfDesc = 1;
4039 else
4040 BWSettingOfDesc = 0;
4041 } else
4042 BWSettingOfDesc = 0;
4043
4044 /* if(pTcb->bBTTxPacket) */
4045 /* BWSettingOfDesc = 0; */
4046
4047 return BWSettingOfDesc;
4048 }
4049
SCMapping_8703B(PADAPTER Adapter,struct pkt_attrib * pattrib)4050 u8 SCMapping_8703B(PADAPTER Adapter, struct pkt_attrib *pattrib)
4051 {
4052 u8 SCSettingOfDesc = 0;
4053 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
4054
4055 /* RTW_INFO("SCMapping: pHalData->current_channel_bw %d, pHalData->nCur80MhzPrimeSC %d, pHalData->nCur40MhzPrimeSC %d\n",pHalData->current_channel_bw,pHalData->nCur80MhzPrimeSC,pHalData->nCur40MhzPrimeSC); */
4056
4057 if (pHalData->current_channel_bw == CHANNEL_WIDTH_80) {
4058 if (pattrib->bwmode == CHANNEL_WIDTH_80)
4059 SCSettingOfDesc = VHT_DATA_SC_DONOT_CARE;
4060 else if (pattrib->bwmode == CHANNEL_WIDTH_40) {
4061 if (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)
4062 SCSettingOfDesc = VHT_DATA_SC_40_LOWER_OF_80MHZ;
4063 else if (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)
4064 SCSettingOfDesc = VHT_DATA_SC_40_UPPER_OF_80MHZ;
4065 else
4066 RTW_INFO("SCMapping: DONOT CARE Mode Setting\n");
4067 } else {
4068 if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER))
4069 SCSettingOfDesc = VHT_DATA_SC_20_LOWEST_OF_80MHZ;
4070 else if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER))
4071 SCSettingOfDesc = VHT_DATA_SC_20_LOWER_OF_80MHZ;
4072 else if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER))
4073 SCSettingOfDesc = VHT_DATA_SC_20_UPPER_OF_80MHZ;
4074 else if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER))
4075 SCSettingOfDesc = VHT_DATA_SC_20_UPPERST_OF_80MHZ;
4076 else
4077 RTW_INFO("SCMapping: DONOT CARE Mode Setting\n");
4078 }
4079 } else if (pHalData->current_channel_bw == CHANNEL_WIDTH_40) {
4080 /* RTW_INFO("SCMapping: HT Case: pHalData->current_channel_bw %d, pHalData->nCur40MhzPrimeSC %d\n",pHalData->current_channel_bw,pHalData->nCur40MhzPrimeSC); */
4081
4082 if (pattrib->bwmode == CHANNEL_WIDTH_40)
4083 SCSettingOfDesc = VHT_DATA_SC_DONOT_CARE;
4084 else if (pattrib->bwmode == CHANNEL_WIDTH_20) {
4085 if (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)
4086 SCSettingOfDesc = VHT_DATA_SC_20_UPPER_OF_80MHZ;
4087 else if (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)
4088 SCSettingOfDesc = VHT_DATA_SC_20_LOWER_OF_80MHZ;
4089 else
4090 SCSettingOfDesc = VHT_DATA_SC_DONOT_CARE;
4091 }
4092 } else
4093 SCSettingOfDesc = VHT_DATA_SC_DONOT_CARE;
4094
4095 return SCSettingOfDesc;
4096 }
4097
fill_txdesc_force_bmc_camid(struct pkt_attrib * pattrib,u8 * ptxdesc)4098 void fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc)
4099 {
4100 if ((pattrib->encrypt > 0) && (!pattrib->bswenc)
4101 && (pattrib->bmc_camid != INVALID_SEC_MAC_CAM_ID)) {
4102
4103 SET_TX_DESC_EN_DESC_ID_8703B(ptxdesc, 1);
4104 SET_TX_DESC_MACID_8703B(ptxdesc, pattrib->bmc_camid);
4105 }
4106 }
4107
fill_txdesc_bmc_tx_rate(struct pkt_attrib * pattrib,u8 * ptxdesc)4108 void fill_txdesc_bmc_tx_rate(struct pkt_attrib *pattrib, u8 *ptxdesc)
4109 {
4110 SET_TX_DESC_USE_RATE_8703B(ptxdesc, 1);
4111 SET_TX_DESC_TX_RATE_8703B(ptxdesc, MRateToHwRate(pattrib->rate));
4112 SET_TX_DESC_DISABLE_FB_8703B(ptxdesc, 1);
4113 }
4114
fill_txdesc_sectype(struct pkt_attrib * pattrib)4115 static u8 fill_txdesc_sectype(struct pkt_attrib *pattrib)
4116 {
4117 u8 sectype = 0;
4118 if ((pattrib->encrypt > 0) && !pattrib->bswenc) {
4119 switch (pattrib->encrypt) {
4120 /* SEC_TYPE */
4121 case _WEP40_:
4122 case _WEP104_:
4123 case _TKIP_:
4124 case _TKIP_WTMIC_:
4125 sectype = 1;
4126 break;
4127
4128 #ifdef CONFIG_WAPI_SUPPORT
4129 case _SMS4_:
4130 sectype = 2;
4131 break;
4132 #endif
4133 case _AES_:
4134 sectype = 3;
4135 break;
4136
4137 case _NO_PRIVACY_:
4138 default:
4139 break;
4140 }
4141 }
4142 return sectype;
4143 }
4144
fill_txdesc_vcs_8703b(PADAPTER padapter,struct pkt_attrib * pattrib,u8 * ptxdesc)4145 static void fill_txdesc_vcs_8703b(PADAPTER padapter, struct pkt_attrib *pattrib, u8 *ptxdesc)
4146 {
4147 /* RTW_INFO("cvs_mode=%d\n", pattrib->vcs_mode); */
4148
4149 if (pattrib->vcs_mode) {
4150 switch (pattrib->vcs_mode) {
4151 case RTS_CTS:
4152 SET_TX_DESC_RTS_ENABLE_8703B(ptxdesc, 1);
4153 SET_TX_DESC_HW_RTS_ENABLE_8703B(ptxdesc, 1);
4154 break;
4155
4156 case CTS_TO_SELF:
4157 SET_TX_DESC_CTS2SELF_8703B(ptxdesc, 1);
4158 break;
4159
4160 case NONE_VCS:
4161 default:
4162 break;
4163 }
4164
4165 SET_TX_DESC_RTS_RATE_8703B(ptxdesc, 8); /* RTS Rate=24M */
4166 SET_TX_DESC_RTS_RATE_FB_LIMIT_8703B(ptxdesc, 0xF);
4167
4168 if (padapter->mlmeextpriv.mlmext_info.preamble_mode == PREAMBLE_SHORT)
4169 SET_TX_DESC_RTS_SHORT_8703B(ptxdesc, 1);
4170
4171 /* Set RTS BW */
4172 if (pattrib->ht_en)
4173 SET_TX_DESC_RTS_SC_8703B(ptxdesc, SCMapping_8703B(padapter, pattrib));
4174 }
4175 }
4176
fill_txdesc_phy_8703b(PADAPTER padapter,struct pkt_attrib * pattrib,u8 * ptxdesc)4177 static void fill_txdesc_phy_8703b(PADAPTER padapter, struct pkt_attrib *pattrib, u8 *ptxdesc)
4178 {
4179 /* RTW_INFO("bwmode=%d, ch_off=%d\n", pattrib->bwmode, pattrib->ch_offset); */
4180
4181 if (pattrib->ht_en) {
4182 SET_TX_DESC_DATA_BW_8703B(ptxdesc, BWMapping_8703B(padapter, pattrib));
4183 SET_TX_DESC_DATA_SC_8703B(ptxdesc, SCMapping_8703B(padapter, pattrib));
4184 }
4185 }
4186
rtl8703b_fill_default_txdesc(struct xmit_frame * pxmitframe,u8 * pbuf)4187 static void rtl8703b_fill_default_txdesc(
4188 struct xmit_frame *pxmitframe,
4189 u8 *pbuf)
4190 {
4191 PADAPTER padapter;
4192 HAL_DATA_TYPE *pHalData;
4193 struct mlme_ext_priv *pmlmeext;
4194 struct mlme_ext_info *pmlmeinfo;
4195 struct pkt_attrib *pattrib;
4196 s32 bmcst;
4197
4198 _rtw_memset(pbuf, 0, TXDESC_SIZE);
4199
4200 padapter = pxmitframe->padapter;
4201 pHalData = GET_HAL_DATA(padapter);
4202 pmlmeext = &padapter->mlmeextpriv;
4203 pmlmeinfo = &(pmlmeext->mlmext_info);
4204
4205 pattrib = &pxmitframe->attrib;
4206 bmcst = IS_MCAST(pattrib->ra);
4207
4208 if (pxmitframe->frame_tag == DATA_FRAMETAG) {
4209 u8 drv_userate = 0;
4210
4211 SET_TX_DESC_MACID_8703B(pbuf, pattrib->mac_id);
4212 SET_TX_DESC_RATE_ID_8703B(pbuf, pattrib->raid);
4213 SET_TX_DESC_QUEUE_SEL_8703B(pbuf, pattrib->qsel);
4214 SET_TX_DESC_SEQ_8703B(pbuf, pattrib->seqnum);
4215
4216 SET_TX_DESC_SEC_TYPE_8703B(pbuf, fill_txdesc_sectype(pattrib));
4217
4218 if (bmcst)
4219 fill_txdesc_force_bmc_camid(pattrib, pbuf);
4220
4221 fill_txdesc_vcs_8703b(padapter, pattrib, pbuf);
4222
4223 #ifdef CONFIG_P2P
4224 if (!rtw_p2p_chk_state(&padapter->wdinfo, P2P_STATE_NONE)) {
4225 if (pattrib->icmp_pkt == 1 && padapter->registrypriv.wifi_spec == 1)
4226 drv_userate = 1;
4227 }
4228 #endif
4229
4230 if ((pattrib->ether_type != 0x888e) &&
4231 (pattrib->ether_type != 0x0806) &&
4232 (pattrib->ether_type != 0x88B4) &&
4233 (pattrib->dhcp_pkt != 1) &&
4234 (drv_userate != 1)
4235 #ifdef CONFIG_AUTO_AP_MODE
4236 && (pattrib->pctrl != _TRUE)
4237 #endif
4238 ) {
4239 /* Non EAP & ARP & DHCP type data packet */
4240
4241 if (pattrib->ampdu_en == _TRUE) {
4242 SET_TX_DESC_AGG_ENABLE_8703B(pbuf, 1);
4243 SET_TX_DESC_MAX_AGG_NUM_8703B(pbuf, 0x1F);
4244 SET_TX_DESC_AMPDU_DENSITY_8703B(pbuf, pattrib->ampdu_spacing);
4245 } else
4246 SET_TX_DESC_AGG_BREAK_8703B(pbuf, 1);
4247
4248 fill_txdesc_phy_8703b(padapter, pattrib, pbuf);
4249
4250 SET_TX_DESC_DATA_RATE_FB_LIMIT_8703B(pbuf, 0x1F);
4251
4252 if (pHalData->fw_ractrl == _FALSE) {
4253 SET_TX_DESC_USE_RATE_8703B(pbuf, 1);
4254
4255 if (pHalData->INIDATA_RATE[pattrib->mac_id] & BIT(7))
4256 SET_TX_DESC_DATA_SHORT_8703B(pbuf, 1);
4257
4258 SET_TX_DESC_TX_RATE_8703B(pbuf, pHalData->INIDATA_RATE[pattrib->mac_id] & 0x7F);
4259 }
4260
4261 if (bmcst)
4262 fill_txdesc_bmc_tx_rate(pattrib, pbuf);
4263
4264 /* modify data rate by iwpriv */
4265 if (padapter->fix_rate != 0xFF) {
4266 SET_TX_DESC_USE_RATE_8703B(pbuf, 1);
4267 if (padapter->fix_rate & BIT(7))
4268 SET_TX_DESC_DATA_SHORT_8703B(pbuf, 1);
4269 SET_TX_DESC_TX_RATE_8703B(pbuf, padapter->fix_rate & 0x7F);
4270 if (!padapter->data_fb)
4271 SET_TX_DESC_DISABLE_FB_8703B(pbuf, 1);
4272 }
4273
4274 if (pattrib->ldpc)
4275 SET_TX_DESC_DATA_LDPC_8703B(pbuf, 1);
4276
4277 if (pattrib->stbc)
4278 SET_TX_DESC_DATA_STBC_8703B(pbuf, 1);
4279
4280 #ifdef CONFIG_CMCC_TEST
4281 SET_TX_DESC_DATA_SHORT_8703B(pbuf, 1); /* use cck short premble */
4282 #endif
4283 } else {
4284 /* EAP data packet and ARP packet. */
4285 /* Use the 1M data rate to send the EAP/ARP packet. */
4286 /* This will maybe make the handshake smooth. */
4287
4288 SET_TX_DESC_AGG_BREAK_8703B(pbuf, 1);
4289 SET_TX_DESC_USE_RATE_8703B(pbuf, 1);
4290 if (pmlmeinfo->preamble_mode == PREAMBLE_SHORT)
4291 SET_TX_DESC_DATA_SHORT_8703B(pbuf, 1);
4292 #ifdef CONFIG_IP_R_MONITOR
4293 if((pattrib->ether_type == ETH_P_ARP) &&
4294 (IsSupportedTxOFDM(padapter->registrypriv.wireless_mode)))
4295 SET_TX_DESC_TX_RATE_8703B(pbuf, MRateToHwRate(IEEE80211_OFDM_RATE_6MB));
4296 else
4297 #endif/*CONFIG_IP_R_MONITOR*/
4298 SET_TX_DESC_TX_RATE_8703B(pbuf, MRateToHwRate(pmlmeext->tx_rate));
4299
4300 RTW_INFO(FUNC_ADPT_FMT ": SP Packet(0x%04X) rate=0x%x SeqNum = %d\n",
4301 FUNC_ADPT_ARG(padapter), pattrib->ether_type, MRateToHwRate(pmlmeext->tx_rate), pattrib->seqnum);
4302 }
4303
4304 #if defined(CONFIG_USB_TX_AGGREGATION) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
4305 SET_TX_DESC_USB_TXAGG_NUM_8703B(pbuf, pxmitframe->agg_num);
4306 #endif
4307
4308 #ifdef CONFIG_TDLS
4309 #ifdef CONFIG_XMIT_ACK
4310 /* CCX-TXRPT ack for xmit mgmt frames. */
4311 if (pxmitframe->ack_report) {
4312 #ifdef DBG_CCX
4313 RTW_INFO("%s set spe_rpt\n", __func__);
4314 #endif
4315 SET_TX_DESC_SPE_RPT_8703B(pbuf, 1);
4316 SET_TX_DESC_SW_DEFINE_8703B(pbuf, (u8)(GET_PRIMARY_ADAPTER(padapter)->xmitpriv.seq_no));
4317 }
4318 #endif /* CONFIG_XMIT_ACK */
4319 #endif
4320 } else if (pxmitframe->frame_tag == MGNT_FRAMETAG) {
4321
4322 SET_TX_DESC_MACID_8703B(pbuf, pattrib->mac_id);
4323 SET_TX_DESC_QUEUE_SEL_8703B(pbuf, pattrib->qsel);
4324 SET_TX_DESC_RATE_ID_8703B(pbuf, pattrib->raid);
4325 SET_TX_DESC_SEQ_8703B(pbuf, pattrib->seqnum);
4326 SET_TX_DESC_USE_RATE_8703B(pbuf, 1);
4327
4328 SET_TX_DESC_MBSSID_8703B(pbuf, pattrib->mbssid & 0xF);
4329
4330 SET_TX_DESC_RETRY_LIMIT_ENABLE_8703B(pbuf, 1);
4331 if (pattrib->retry_ctrl == _TRUE)
4332 SET_TX_DESC_DATA_RETRY_LIMIT_8703B(pbuf, 6);
4333 else
4334 SET_TX_DESC_DATA_RETRY_LIMIT_8703B(pbuf, 12);
4335
4336 SET_TX_DESC_TX_RATE_8703B(pbuf, MRateToHwRate(pattrib->rate));
4337
4338 #ifdef CONFIG_XMIT_ACK
4339 /* CCX-TXRPT ack for xmit mgmt frames. */
4340 if (pxmitframe->ack_report) {
4341 #ifdef DBG_CCX
4342 RTW_INFO("%s set spe_rpt\n", __FUNCTION__);
4343 #endif
4344 SET_TX_DESC_SPE_RPT_8703B(pbuf, 1);
4345 SET_TX_DESC_SW_DEFINE_8703B(pbuf, (u8)(GET_PRIMARY_ADAPTER(padapter)->xmitpriv.seq_no));
4346 }
4347 #endif /* CONFIG_XMIT_ACK */
4348 } else if (pxmitframe->frame_tag == TXAGG_FRAMETAG) {
4349 }
4350 #ifdef CONFIG_MP_INCLUDED
4351 else if (pxmitframe->frame_tag == MP_FRAMETAG) {
4352 fill_txdesc_for_mp(padapter, pbuf);
4353 }
4354 #endif
4355 else {
4356
4357 SET_TX_DESC_MACID_8703B(pbuf, pattrib->mac_id);
4358 SET_TX_DESC_RATE_ID_8703B(pbuf, pattrib->raid);
4359 SET_TX_DESC_QUEUE_SEL_8703B(pbuf, pattrib->qsel);
4360 SET_TX_DESC_SEQ_8703B(pbuf, pattrib->seqnum);
4361 SET_TX_DESC_USE_RATE_8703B(pbuf, 1);
4362 SET_TX_DESC_TX_RATE_8703B(pbuf, MRateToHwRate(pmlmeext->tx_rate));
4363 }
4364
4365 SET_TX_DESC_PKT_SIZE_8703B(pbuf, pattrib->last_txcmdsz);
4366
4367 {
4368 u8 pkt_offset, offset;
4369
4370 pkt_offset = 0;
4371 offset = TXDESC_SIZE;
4372 #ifdef CONFIG_USB_HCI
4373 pkt_offset = pxmitframe->pkt_offset;
4374 offset += (pxmitframe->pkt_offset >> 3);
4375 #endif /* CONFIG_USB_HCI */
4376
4377 #ifdef CONFIG_TX_EARLY_MODE
4378 if (pxmitframe->frame_tag == DATA_FRAMETAG) {
4379 pkt_offset = 1;
4380 offset += EARLY_MODE_INFO_SIZE;
4381 }
4382 #endif /* CONFIG_TX_EARLY_MODE */
4383
4384 SET_TX_DESC_PKT_OFFSET_8703B(pbuf, pkt_offset);
4385 SET_TX_DESC_OFFSET_8703B(pbuf, offset);
4386 }
4387
4388 if (bmcst)
4389 SET_TX_DESC_BMC_8703B(pbuf, 1);
4390
4391 /* 2009.11.05. tynli_test. Suggested by SD4 Filen for FW LPS. */
4392 /* (1) The sequence number of each non-Qos frame / broadcast / multicast / */
4393 /* mgnt frame should be controled by Hw because Fw will also send null data */
4394 /* which we cannot control when Fw LPS enable. */
4395 /* --> default enable non-Qos data sequense number. 2010.06.23. by tynli. */
4396 /* (2) Enable HW SEQ control for beacon packet, because we use Hw beacon. */
4397 /* (3) Use HW Qos SEQ to control the seq num of Ext port non-Qos packets. */
4398 /* 2010.06.23. Added by tynli. */
4399 if (!pattrib->qos_en)
4400 SET_TX_DESC_HWSEQ_EN_8703B(pbuf, 1);
4401
4402 #ifdef CONFIG_ANTENNA_DIVERSITY
4403 if (!bmcst && pattrib->psta)
4404 odm_set_tx_ant_by_tx_info(adapter_to_phydm(padapter), pbuf, pattrib->psta->cmn.mac_id);
4405 #endif
4406 }
4407
4408 /*
4409 * Description:
4410 *
4411 * Parameters:
4412 * pxmitframe xmitframe
4413 * pbuf where to fill tx desc
4414 */
rtl8703b_update_txdesc(struct xmit_frame * pxmitframe,u8 * pbuf)4415 void rtl8703b_update_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf)
4416 {
4417 rtl8703b_fill_default_txdesc(pxmitframe, pbuf);
4418
4419 #if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
4420 rtl8703b_cal_txdesc_chksum((struct tx_desc *)pbuf);
4421 #endif
4422 }
4423
hw_var_set_monitor(PADAPTER adapter,u8 variable,u8 * val)4424 static void hw_var_set_monitor(PADAPTER adapter, u8 variable, u8 *val)
4425 {
4426 #ifdef CONFIG_WIFI_MONITOR
4427 u32 tmp_32bit;
4428 struct net_device *ndev = adapter->pnetdev;
4429 struct mon_reg_backup *mon = &GET_HAL_DATA(adapter)->mon_backup;
4430
4431 mon->known_rcr = 1;
4432 rtw_hal_get_hwreg(adapter, HW_VAR_RCR, (u8 *)& mon->rcr);
4433
4434 /* Receive all type */
4435 tmp_32bit = RCR_AAP | RCR_APP_PHYST_RXFF;
4436
4437 if (ndev->type == ARPHRD_IEEE80211_RADIOTAP) {
4438 /* Append FCS */
4439 tmp_32bit |= RCR_APPFCS;
4440 }
4441
4442 rtw_hal_set_hwreg(adapter, HW_VAR_RCR, (u8 *)& tmp_32bit);
4443
4444 /* Receive all data frames */
4445 mon->known_rxfilter = 1;
4446 mon->rxfilter0 = rtw_read16(adapter, REG_RXFLTMAP0_8703B);
4447 mon->rxfilter1 = rtw_read16(adapter, REG_RXFLTMAP1_8703B);
4448 mon->rxfilter2 = rtw_read16(adapter, REG_RXFLTMAP2_8703B);
4449 rtw_write16(adapter, REG_RXFLTMAP0_8703B, 0xFFFF);
4450 rtw_write16(adapter, REG_RXFLTMAP1_8703B, 0xFFFF);
4451 rtw_write16(adapter, REG_RXFLTMAP2_8703B, 0xFFFF);
4452 #endif /* CONFIG_WIFI_MONITOR */
4453 }
4454
hw_var_set_opmode(PADAPTER padapter,u8 variable,u8 * val)4455 static void hw_var_set_opmode(PADAPTER padapter, u8 variable, u8 *val)
4456 {
4457 u8 val8;
4458 u8 mode = *((u8 *)val);
4459 static u8 isMonitor = _FALSE;
4460
4461 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
4462
4463 if (isMonitor == _TRUE) {
4464 #ifdef CONFIG_WIFI_MONITOR
4465 struct mon_reg_backup *backup = &GET_HAL_DATA(padapter)->mon_backup;
4466
4467 if (backup->known_rcr) {
4468 backup->known_rcr = 0;
4469 rtw_hal_set_hwreg(padapter, HW_VAR_RCR, (u8 *)&backup->rcr);
4470 rtw_hal_rcr_set_chk_bssid(padapter, MLME_ACTION_NONE);
4471 }
4472 if (backup->known_rxfilter) {
4473 backup->known_rxfilter = 0;
4474 rtw_write16(padapter, REG_RXFLTMAP0_8703B, backup->rxfilter0);
4475 rtw_write16(padapter, REG_RXFLTMAP1_8703B, backup->rxfilter1);
4476 rtw_write16(padapter, REG_RXFLTMAP2_8703B, backup->rxfilter2);
4477 }
4478 #endif /* CONFIG_WIFI_MONITOR */
4479 isMonitor = _FALSE;
4480 }
4481
4482 if (mode == _HW_STATE_MONITOR_) {
4483 isMonitor = _TRUE;
4484 /* set net_type */
4485 Set_MSR(padapter, _HW_STATE_NOLINK_);
4486
4487 hw_var_set_monitor(padapter, variable, val);
4488 return;
4489 }
4490 rtw_hal_set_hwreg(padapter, HW_VAR_MAC_ADDR, adapter_mac_addr(padapter)); /* set mac addr to mac register */
4491
4492 #ifdef CONFIG_CONCURRENT_MODE
4493 if (padapter->hw_port == HW_PORT1) {
4494 /* disable Port1 TSF update */
4495 rtw_iface_disable_tsf_update(padapter);
4496
4497 Set_MSR(padapter, mode);
4498
4499 RTW_INFO("#### %s()-%d hw_port(%d) mode=%d ####\n",
4500 __func__, __LINE__, padapter->hw_port, mode);
4501
4502 if ((mode == _HW_STATE_STATION_) || (mode == _HW_STATE_NOLINK_)) {
4503 if (!rtw_mi_get_ap_num(padapter) && !rtw_mi_get_mesh_num(padapter)) {
4504 StopTxBeacon(padapter);
4505 #ifdef CONFIG_PCI_HCI
4506 UpdateInterruptMask8703BE(padapter, 0, 0, RT_BCN_INT_MASKS, 0);
4507 #else /* !CONFIG_PCI_HCI */
4508 #ifdef CONFIG_INTERRUPT_BASED_TXBCN
4509
4510 #ifdef CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
4511 rtw_write8(padapter, REG_DRVERLYINT, 0x05);/* restore early int time to 5ms */
4512 UpdateInterruptMask8703BU(padapter, _TRUE, 0, IMR_BCNDMAINT0_8703B);
4513 #endif /* CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT */
4514
4515 #ifdef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR
4516 UpdateInterruptMask8703BU(padapter, _TRUE , 0, (IMR_TXBCN0ERR_8703B | IMR_TXBCN0OK_8703B));
4517 #endif /* CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR */
4518
4519 #endif /* CONFIG_INTERRUPT_BASED_TXBCN */
4520 #endif /* !CONFIG_PCI_HCI */
4521 }
4522
4523 /* disable atim wnd and disable beacon function */
4524 rtw_write8(padapter, REG_BCN_CTRL_1, DIS_TSF_UDT | DIS_ATIM);
4525 } else if (mode == _HW_STATE_ADHOC_) {
4526 ResumeTxBeacon(padapter);
4527 rtw_write8(padapter, REG_BCN_CTRL_1, DIS_TSF_UDT | EN_BCN_FUNCTION | DIS_BCNQ_SUB);
4528 } else if (mode == _HW_STATE_AP_) {
4529 #ifdef CONFIG_PCI_HCI
4530 UpdateInterruptMask8703BE(padapter, RT_BCN_INT_MASKS, 0, 0, 0);
4531 #else /* !CONFIG_PCI_HCI */
4532 #ifdef CONFIG_INTERRUPT_BASED_TXBCN
4533
4534 #ifdef CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
4535 UpdateInterruptMask8703BU(padapter, _TRUE, IMR_BCNDMAINT0_8703B, 0);
4536 #endif /* CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT */
4537
4538 #ifdef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR
4539 UpdateInterruptMask8703BU(padapter, _TRUE, (IMR_TXBCN0ERR_8703B | IMR_TXBCN0OK_8703B), 0);
4540 #endif /* CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR */
4541
4542 #endif /* CONFIG_INTERRUPT_BASED_TXBCN */
4543 #endif /* !CONFIG_PCI_HCI */
4544
4545 rtw_write8(padapter, REG_BCN_CTRL_1, DIS_TSF_UDT | DIS_BCNQ_SUB);
4546
4547 /* enable to rx data frame */
4548 rtw_write16(padapter, REG_RXFLTMAP2, 0xFFFF);
4549 /* enable to rx ps-poll */
4550 rtw_write16(padapter, REG_RXFLTMAP1, 0x0400);
4551
4552 /* Beacon Control related register for first time */
4553 rtw_write8(padapter, REG_BCNDMATIM, 0x02); /* 2ms */
4554
4555 /* rtw_write8(padapter, REG_BCN_MAX_ERR, 0xFF); */
4556 rtw_write8(padapter, REG_ATIMWND_1, 0x0a); /* 10ms for port1 */
4557
4558 rtw_write16(padapter, REG_TSFTR_SYN_OFFSET, 0x7fff);/* +32767 (~32ms) */
4559
4560 /* reset TSF2 */
4561 rtw_write8(padapter, REG_DUAL_TSF_RST, BIT(1));
4562
4563 /* enable BCN1 Function for if2 */
4564 /* don't enable update TSF1 for if2 (due to TSF update when beacon/probe rsp are received) */
4565 rtw_write8(padapter, REG_BCN_CTRL_1, (DIS_TSF_UDT | EN_BCN_FUNCTION | EN_TXBCN_RPT | DIS_BCNQ_SUB));
4566
4567 /* SW_BCN_SEL - Port1 */
4568 /* rtw_write8(Adapter, REG_DWBCN1_CTRL_8192E+2, rtw_read8(Adapter, REG_DWBCN1_CTRL_8192E+2)|BIT4); */
4569 rtw_hal_set_hwreg(padapter, HW_VAR_DL_BCN_SEL, NULL);
4570
4571 /* select BCN on port 1 */
4572 rtw_write8(padapter, REG_CCK_CHECK_8703B,
4573 (rtw_read8(padapter, REG_CCK_CHECK_8703B) | BIT_BCN_PORT_SEL));
4574
4575 if (!rtw_mi_buddy_check_mlmeinfo_state(padapter, WIFI_FW_ASSOC_SUCCESS)) {
4576 val8 = rtw_read8(padapter, REG_BCN_CTRL);
4577 val8 &= ~EN_BCN_FUNCTION;
4578 rtw_write8(padapter, REG_BCN_CTRL, val8);
4579 }
4580
4581 /* BCN1 TSF will sync to BCN0 TSF with offset(0x518) if if1_sta linked */
4582 /* rtw_write8(padapter, REG_BCN_CTRL_1, rtw_read8(padapter, REG_BCN_CTRL_1)|BIT(5)); */
4583 /* rtw_write8(padapter, REG_DUAL_TSF_RST, BIT(3)); */
4584
4585 /* dis BCN0 ATIM WND if if1 is station */
4586 rtw_write8(padapter, REG_BCN_CTRL, rtw_read8(padapter, REG_BCN_CTRL) | DIS_ATIM);
4587
4588 #ifdef CONFIG_TSF_RESET_OFFLOAD
4589 /* Reset TSF for STA+AP concurrent mode */
4590 if (DEV_STA_LD_NUM(adapter_to_dvobj(padapter))) {
4591 if (rtw_hal_reset_tsf(padapter, HW_PORT1) == _FAIL)
4592 RTW_INFO("ERROR! %s()-%d: Reset port1 TSF fail\n",
4593 __FUNCTION__, __LINE__);
4594 }
4595 #endif /* CONFIG_TSF_RESET_OFFLOAD */
4596 }
4597 } else /* else for port0 */
4598 #endif /* CONFIG_CONCURRENT_MODE */
4599 {
4600 #ifdef CONFIG_MI_WITH_MBSSID_CAM /*For Port0 - MBSS CAM*/
4601 hw_var_set_opmode_mbid(padapter, mode);
4602 #else
4603 /* disable Port0 TSF update */
4604 rtw_iface_disable_tsf_update(padapter);
4605
4606 /* set net_type */
4607 Set_MSR(padapter, mode);
4608 RTW_INFO("#### %s() -%d hw_port(0) mode = %d ####\n", __func__, __LINE__, mode);
4609
4610 if ((mode == _HW_STATE_STATION_) || (mode == _HW_STATE_NOLINK_)) {
4611 #ifdef CONFIG_CONCURRENT_MODE
4612 if (!rtw_mi_get_ap_num(padapter) && !rtw_mi_get_mesh_num(padapter))
4613 #endif /* CONFIG_CONCURRENT_MODE */
4614 {
4615 StopTxBeacon(padapter);
4616 #ifdef CONFIG_PCI_HCI
4617 UpdateInterruptMask8703BE(padapter, 0, 0, RT_BCN_INT_MASKS, 0);
4618 #else /* !CONFIG_PCI_HCI */
4619 #ifdef CONFIG_INTERRUPT_BASED_TXBCN
4620 #ifdef CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
4621 rtw_write8(padapter, REG_DRVERLYINT, 0x05); /* restore early int time to 5ms */
4622 UpdateInterruptMask8812AU(padapter, _TRUE, 0, IMR_BCNDMAINT0_8703B);
4623 #endif /* CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT */
4624
4625 #ifdef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR
4626 UpdateInterruptMask8812AU(padapter, _TRUE , 0, (IMR_TXBCN0ERR_8703B | IMR_TXBCN0OK_8703B));
4627 #endif /* CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR */
4628
4629 #endif /* CONFIG_INTERRUPT_BASED_TXBCN */
4630 #endif /* !CONFIG_PCI_HCI */
4631 }
4632
4633 /* disable atim wnd */
4634 rtw_write8(padapter, REG_BCN_CTRL, DIS_TSF_UDT | EN_BCN_FUNCTION | DIS_ATIM);
4635 /* rtw_write8(padapter,REG_BCN_CTRL, DIS_TSF_UDT | EN_BCN_FUNCTION); */
4636 } else if (mode == _HW_STATE_ADHOC_) {
4637 ResumeTxBeacon(padapter);
4638 rtw_write8(padapter, REG_BCN_CTRL, DIS_TSF_UDT | EN_BCN_FUNCTION | DIS_BCNQ_SUB);
4639 } else if (mode == _HW_STATE_AP_) {
4640 #ifdef CONFIG_PCI_HCI
4641 UpdateInterruptMask8703BE(padapter, RT_BCN_INT_MASKS, 0, 0, 0);
4642 #else /* !CONFIG_PCI_HCI */
4643 #ifdef CONFIG_INTERRUPT_BASED_TXBCN
4644 #ifdef CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
4645 UpdateInterruptMask8703BU(padapter, _TRUE , IMR_BCNDMAINT0_8703B, 0);
4646 #endif /* CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT */
4647
4648 #ifdef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR
4649 UpdateInterruptMask8703BU(padapter, _TRUE , (IMR_TXBCN0ERR_8703B | IMR_TXBCN0OK_8703B), 0);
4650 #endif /* CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR */
4651
4652 #endif /* CONFIG_INTERRUPT_BASED_TXBCN */
4653 #endif
4654
4655 rtw_write8(padapter, REG_BCN_CTRL, DIS_TSF_UDT | DIS_BCNQ_SUB);
4656
4657 /* enable to rx data frame */
4658 rtw_write16(padapter, REG_RXFLTMAP2, 0xFFFF);
4659 /* enable to rx ps-poll */
4660 rtw_write16(padapter, REG_RXFLTMAP1, 0x0400);
4661
4662 /* Beacon Control related register for first time */
4663 rtw_write8(padapter, REG_BCNDMATIM, 0x02); /* 2ms */
4664
4665 /* rtw_write8(padapter, REG_BCN_MAX_ERR, 0xFF); */
4666 rtw_write8(padapter, REG_ATIMWND, 0x0a); /* 10ms */
4667
4668 rtw_write16(padapter, REG_TSFTR_SYN_OFFSET, 0x7fff);/* +32767 (~32ms) */
4669
4670 /* reset TSF */
4671 rtw_write8(padapter, REG_DUAL_TSF_RST, BIT(0));
4672
4673 /* enable BCN0 Function for if1 */
4674 /* don't enable update TSF0 for if1 (due to TSF update when beacon/probe rsp are received) */
4675 rtw_write8(padapter, REG_BCN_CTRL, (DIS_TSF_UDT | EN_BCN_FUNCTION | EN_TXBCN_RPT | DIS_BCNQ_SUB));
4676
4677 /* SW_BCN_SEL - Port0 */
4678 /* rtw_write8(Adapter, REG_DWBCN1_CTRL_8192E+2, rtw_read8(Adapter, REG_DWBCN1_CTRL_8192E+2) & ~BIT4); */
4679 rtw_hal_set_hwreg(padapter, HW_VAR_DL_BCN_SEL, NULL);
4680
4681 /* select BCN on port 0 */
4682 rtw_write8(padapter, REG_CCK_CHECK_8703B,
4683 (rtw_read8(padapter, REG_CCK_CHECK_8703B) & ~BIT_BCN_PORT_SEL));
4684
4685 #ifdef CONFIG_CONCURRENT_MODE
4686 if (!rtw_mi_buddy_check_mlmeinfo_state(padapter, WIFI_FW_ASSOC_SUCCESS)) {
4687 val8 = rtw_read8(padapter, REG_BCN_CTRL_1);
4688 val8 &= ~EN_BCN_FUNCTION;
4689 rtw_write8(padapter, REG_BCN_CTRL_1, val8);
4690 }
4691 #endif /* CONFIG_CONCURRENT_MODE */
4692
4693 /* dis BCN1 ATIM WND if if2 is station */
4694 val8 = rtw_read8(padapter, REG_BCN_CTRL_1);
4695 val8 |= DIS_ATIM;
4696 rtw_write8(padapter, REG_BCN_CTRL_1, val8);
4697 #ifdef CONFIG_TSF_RESET_OFFLOAD
4698 /* Reset TSF for STA+AP concurrent mode */
4699 if (DEV_STA_LD_NUM(adapter_to_dvobj(padapter))) {
4700 if (rtw_hal_reset_tsf(padapter, HW_PORT0) == _FAIL)
4701 RTW_INFO("ERROR! %s()-%d: Reset port0 TSF fail\n",
4702 __FUNCTION__, __LINE__);
4703 }
4704 #endif /* CONFIG_TSF_RESET_OFFLOAD */
4705 }
4706 #endif
4707 }
4708 }
4709
CCX_FwC2HTxRpt_8703b(PADAPTER padapter,u8 * pdata,u8 len)4710 void CCX_FwC2HTxRpt_8703b(PADAPTER padapter, u8 *pdata, u8 len)
4711 {
4712 u8 seq_no;
4713
4714 #define GET_8703B_C2H_TX_RPT_LIFE_TIME_OVER(_Header) LE_BITS_TO_1BYTE((_Header + 0), 6, 1)
4715 #define GET_8703B_C2H_TX_RPT_RETRY_OVER(_Header) LE_BITS_TO_1BYTE((_Header + 0), 7, 1)
4716
4717 /* RTW_INFO("%s, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n", __func__, */
4718 /* *pdata, *(pdata+1), *(pdata+2), *(pdata+3), *(pdata+4), *(pdata+5), *(pdata+6), *(pdata+7)); */
4719
4720 seq_no = *(pdata + 6);
4721
4722 #ifdef CONFIG_XMIT_ACK
4723 if (GET_8703B_C2H_TX_RPT_RETRY_OVER(pdata) | GET_8703B_C2H_TX_RPT_LIFE_TIME_OVER(pdata))
4724 rtw_ack_tx_done(&padapter->xmitpriv, RTW_SCTX_DONE_CCX_PKT_FAIL);
4725 /*
4726 else if(seq_no != padapter->xmitpriv.seq_no) {
4727 RTW_INFO("tx_seq_no=%d, rpt_seq_no=%d\n", padapter->xmitpriv.seq_no, seq_no);
4728 rtw_ack_tx_done(&padapter->xmitpriv, RTW_SCTX_DONE_CCX_PKT_FAIL);
4729 }
4730 */
4731 else
4732 rtw_ack_tx_done(&padapter->xmitpriv, RTW_SCTX_DONE_SUCCESS);
4733 #endif
4734 }
4735
c2h_handler_8703b(_adapter * adapter,u8 id,u8 seq,u8 plen,u8 * payload)4736 static s32 c2h_handler_8703b(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload)
4737 {
4738 s32 ret = _SUCCESS;
4739
4740 switch (id) {
4741 case C2H_CCX_TX_RPT:
4742 CCX_FwC2HTxRpt_8703b(adapter, payload, plen);
4743 break;
4744 default:
4745 ret = _FAIL;
4746 break;
4747 }
4748
4749 return ret;
4750 }
4751
SetHwReg8703B(PADAPTER padapter,u8 variable,u8 * val)4752 u8 SetHwReg8703B(PADAPTER padapter, u8 variable, u8 *val)
4753 {
4754 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
4755 u8 ret = _SUCCESS;
4756 u8 val8;
4757 u16 val16;
4758 u32 val32;
4759
4760
4761 switch (variable) {
4762 case HW_VAR_SET_OPMODE:
4763 hw_var_set_opmode(padapter, variable, val);
4764 break;
4765
4766 case HW_VAR_BASIC_RATE:
4767 rtw_var_set_basic_rate(padapter, val);
4768 break;
4769
4770 case HW_VAR_TXPAUSE:
4771 rtw_write8(padapter, REG_TXPAUSE, *val);
4772 break;
4773
4774 case HW_VAR_SLOT_TIME:
4775 rtw_write8(padapter, REG_SLOT, *val);
4776 break;
4777
4778 case HW_VAR_RESP_SIFS:
4779 #if 0
4780 /* SIFS for OFDM Data ACK */
4781 rtw_write8(padapter, REG_SIFS_CTX + 1, val[0]);
4782 /* SIFS for OFDM consecutive tx like CTS data! */
4783 rtw_write8(padapter, REG_SIFS_TRX + 1, val[1]);
4784
4785 rtw_write8(padapter, REG_SPEC_SIFS + 1, val[0]);
4786 rtw_write8(padapter, REG_MAC_SPEC_SIFS + 1, val[0]);
4787
4788 /* 20100719 Joseph: Revise SIFS setting due to Hardware register definition change. */
4789 rtw_write8(padapter, REG_R2T_SIFS + 1, val[0]);
4790 rtw_write8(padapter, REG_T2T_SIFS + 1, val[0]);
4791
4792 #else
4793 /* SIFS_Timer = 0x0a0a0808; */
4794 /* RESP_SIFS for CCK */
4795 rtw_write8(padapter, REG_RESP_SIFS_CCK, val[0]); /* SIFS_T2T_CCK (0x08) */
4796 rtw_write8(padapter, REG_RESP_SIFS_CCK + 1, val[1]); /* SIFS_R2T_CCK(0x08) */
4797 /* RESP_SIFS for OFDM */
4798 rtw_write8(padapter, REG_RESP_SIFS_OFDM, val[2]); /* SIFS_T2T_OFDM (0x0a) */
4799 rtw_write8(padapter, REG_RESP_SIFS_OFDM + 1, val[3]); /* SIFS_R2T_OFDM(0x0a) */
4800 #endif
4801 break;
4802
4803 case HW_VAR_ACK_PREAMBLE: {
4804 u8 regTmp;
4805 u8 bShortPreamble = *val;
4806
4807 /* Joseph marked out for Netgear 3500 TKIP channel 7 issue.(Temporarily) */
4808 /* regTmp = (pHalData->nCur40MhzPrimeSC)<<5; */
4809 regTmp = 0;
4810 if (bShortPreamble)
4811 regTmp |= 0x80;
4812 rtw_write8(padapter, REG_RRSR + 2, regTmp);
4813 }
4814 break;
4815
4816 case HW_VAR_CAM_INVALID_ALL:
4817 rtw_write32(padapter, REG_CAMCMD, BIT(31) | BIT(30));
4818 break;
4819
4820 case HW_VAR_AC_PARAM_VO:
4821 rtw_write32(padapter, REG_EDCA_VO_PARAM, *((u32 *)val));
4822 break;
4823
4824 case HW_VAR_AC_PARAM_VI:
4825 rtw_write32(padapter, REG_EDCA_VI_PARAM, *((u32 *)val));
4826 break;
4827
4828 case HW_VAR_AC_PARAM_BE:
4829 pHalData->ac_param_be = ((u32 *)(val))[0];
4830 rtw_write32(padapter, REG_EDCA_BE_PARAM, *((u32 *)val));
4831 break;
4832
4833 case HW_VAR_AC_PARAM_BK:
4834 rtw_write32(padapter, REG_EDCA_BK_PARAM, *((u32 *)val));
4835 break;
4836
4837 case HW_VAR_ACM_CTRL: {
4838 u8 ctrl = *((u8 *)val);
4839 u8 hwctrl = 0;
4840
4841 if (ctrl != 0) {
4842 hwctrl |= AcmHw_HwEn;
4843
4844 if (ctrl & BIT(3)) /* BE */
4845 hwctrl |= AcmHw_BeqEn;
4846
4847 if (ctrl & BIT(2)) /* VI */
4848 hwctrl |= AcmHw_ViqEn;
4849
4850 if (ctrl & BIT(1)) /* VO */
4851 hwctrl |= AcmHw_VoqEn;
4852 }
4853
4854 RTW_INFO("[HW_VAR_ACM_CTRL] Write 0x%02X\n", hwctrl);
4855 rtw_write8(padapter, REG_ACMHWCTRL, hwctrl);
4856 }
4857 break;
4858 #ifdef CONFIG_80211N_HT
4859 case HW_VAR_AMPDU_FACTOR: {
4860 u32 AMPDULen = (*((u8 *)val));
4861
4862 if (AMPDULen < HT_AGG_SIZE_32K)
4863 AMPDULen = (0x2000 << (*((u8 *)val))) - 1;
4864 else
4865 AMPDULen = 0x7fff;
4866
4867 rtw_write32(padapter, REG_AMPDU_MAX_LENGTH_8703B, AMPDULen);
4868 }
4869 break;
4870 #endif /* CONFIG_80211N_HT */
4871 case HW_VAR_H2C_FW_PWRMODE: {
4872 u8 psmode = *val;
4873
4874 /* if (psmode != PS_MODE_ACTIVE) { */
4875 /* rtl8703b_set_lowpwr_lps_cmd(padapter, _TRUE); */
4876 /* } else { */
4877 /* rtl8703b_set_lowpwr_lps_cmd(padapter, _FALSE); */
4878 /* } */
4879 rtl8703b_set_FwPwrMode_cmd(padapter, psmode);
4880 }
4881 break;
4882 case HW_VAR_H2C_PS_TUNE_PARAM:
4883 rtl8703b_set_FwPsTuneParam_cmd(padapter);
4884 break;
4885
4886 case HW_VAR_H2C_FW_JOINBSSRPT:
4887 rtl8703b_set_FwJoinBssRpt_cmd(padapter, *val);
4888 break;
4889 case HW_VAR_DL_RSVD_PAGE:
4890 #ifdef CONFIG_BT_COEXIST
4891 if (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE)
4892 rtl8703b_download_BTCoex_AP_mode_rsvd_page(padapter);
4893 else
4894 #endif /* CONFIG_BT_COEXIST */
4895 {
4896 rtl8703b_download_rsvd_page(padapter, RT_MEDIA_CONNECT);
4897 }
4898 break;
4899
4900 #ifdef CONFIG_P2P
4901 case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
4902 rtl8703b_set_p2p_ps_offload_cmd(padapter, *val);
4903 break;
4904 #endif /* CONFIG_P2P */
4905
4906 case HW_VAR_EFUSE_USAGE:
4907 pHalData->EfuseUsedPercentage = *val;
4908 break;
4909
4910 case HW_VAR_EFUSE_BYTES:
4911 pHalData->EfuseUsedBytes = *((u16 *)val);
4912 break;
4913
4914 case HW_VAR_EFUSE_BT_USAGE:
4915 #ifdef HAL_EFUSE_MEMORY
4916 pHalData->EfuseHal.BTEfuseUsedPercentage = *val;
4917 #endif
4918 break;
4919
4920 case HW_VAR_EFUSE_BT_BYTES:
4921 #ifdef HAL_EFUSE_MEMORY
4922 pHalData->EfuseHal.BTEfuseUsedBytes = *((u16 *)val);
4923 #else
4924 BTEfuseUsedBytes = *((u16 *)val);
4925 #endif
4926 break;
4927
4928 case HW_VAR_FIFO_CLEARN_UP: {
4929 #define RW_RELEASE_EN BIT(18)
4930 #define RXDMA_IDLE BIT(17)
4931
4932 struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
4933 u8 trycnt = 100;
4934
4935 /* pause tx */
4936 rtw_write8(padapter, REG_TXPAUSE, 0xff);
4937
4938 /* keep sn */
4939 padapter->xmitpriv.nqos_ssn = rtw_read16(padapter, REG_NQOS_SEQ);
4940
4941 if (pwrpriv->bkeepfwalive != _TRUE) {
4942 /* RX DMA stop */
4943 val32 = rtw_read32(padapter, REG_RXPKT_NUM);
4944 val32 |= RW_RELEASE_EN;
4945 rtw_write32(padapter, REG_RXPKT_NUM, val32);
4946 do {
4947 val32 = rtw_read32(padapter, REG_RXPKT_NUM);
4948 val32 &= RXDMA_IDLE;
4949 if (val32)
4950 break;
4951
4952 RTW_INFO("%s: [HW_VAR_FIFO_CLEARN_UP] val=%x times:%d\n", __FUNCTION__, val32, trycnt);
4953 } while (--trycnt);
4954 if (trycnt == 0)
4955 RTW_INFO("[HW_VAR_FIFO_CLEARN_UP] Stop RX DMA failed......\n");
4956
4957 /* RQPN Load 0 */
4958 rtw_write16(padapter, REG_RQPN_NPQ, 0);
4959 rtw_write32(padapter, REG_RQPN, 0x80000000);
4960 rtw_mdelay_os(2);
4961 }
4962 }
4963 break;
4964
4965 case HW_VAR_RESTORE_HW_SEQ:
4966 /* restore Sequence No. */
4967 rtw_write8(padapter, 0x4dc, padapter->xmitpriv.nqos_ssn);
4968 break;
4969
4970 #ifdef CONFIG_CONCURRENT_MODE
4971 case HW_VAR_CHECK_TXBUF: {
4972 u32 i;
4973 u8 RetryLimit = 0x01;
4974 u32 reg_200, reg_204;
4975
4976 val16 = BIT_SRL(RetryLimit) | BIT_LRL(RetryLimit);
4977 rtw_write16(padapter, REG_RETRY_LIMIT, val16);
4978
4979 for (i = 0; i < 200; i++) { /* polling 200x10=2000 msec */
4980 reg_200 = rtw_read32(padapter, 0x200);
4981 reg_204 = rtw_read32(padapter, 0x204);
4982 if (reg_200 != reg_204) {
4983 /* RTW_INFO("packet in tx packet buffer - 0x204=%x, 0x200=%x (%d)\n", rtw_read32(padapter, 0x204), rtw_read32(padapter, 0x200), i); */
4984 rtw_msleep_os(10);
4985 } else {
4986 RTW_INFO("[HW_VAR_CHECK_TXBUF] no packet in tx packet buffer (%d)\n", i);
4987 break;
4988 }
4989 }
4990
4991 if (reg_200 != reg_204)
4992 RTW_INFO("packets in tx buffer - 0x204=%x, 0x200=%x\n", reg_204, reg_200);
4993
4994 RetryLimit = RL_VAL_STA;
4995 val16 = BIT_SRL(RetryLimit) | BIT_LRL(RetryLimit);
4996 rtw_write16(padapter, REG_RETRY_LIMIT, val16);
4997 }
4998 break;
4999 #endif /* CONFIG_CONCURRENT_MODE */
5000
5001 case HW_VAR_NAV_UPPER: {
5002 u32 usNavUpper = *((u32 *)val);
5003
5004 if (usNavUpper > HAL_NAV_UPPER_UNIT_8703B * 0xFF) {
5005 break;
5006 }
5007
5008 /* The value of ((usNavUpper + HAL_NAV_UPPER_UNIT_8703B - 1) / HAL_NAV_UPPER_UNIT_8703B) */
5009 /* is getting the upper integer. */
5010 usNavUpper = (usNavUpper + HAL_NAV_UPPER_UNIT_8703B - 1) / HAL_NAV_UPPER_UNIT_8703B;
5011 rtw_write8(padapter, REG_NAV_UPPER, (u8)usNavUpper);
5012 }
5013 break;
5014
5015 case HW_VAR_BCN_VALID:
5016 #ifdef CONFIG_CONCURRENT_MODE
5017 if (padapter->hw_port == HW_PORT1) {
5018 val8 = rtw_read8(padapter, REG_DWBCN1_CTRL_8703B + 2);
5019 val8 |= BIT(0);
5020 rtw_write8(padapter, REG_DWBCN1_CTRL_8703B + 2, val8);
5021 } else
5022 #endif /* CONFIG_CONCURRENT_MODE */
5023 {
5024 /* BCN_VALID, BIT16 of REG_TDECTRL = BIT0 of REG_TDECTRL+2, write 1 to clear, Clear by sw */
5025 val8 = rtw_read8(padapter, REG_TDECTRL + 2);
5026 val8 |= BIT(0);
5027 rtw_write8(padapter, REG_TDECTRL + 2, val8);
5028 }
5029 break;
5030
5031 case HW_VAR_DL_BCN_SEL:
5032 #ifdef CONFIG_CONCURRENT_MODE
5033 if (padapter->hw_port == HW_PORT1) {
5034 /* SW_BCN_SEL - Port1 */
5035 val8 = rtw_read8(padapter, REG_DWBCN1_CTRL_8703B + 2);
5036 val8 |= BIT(4);
5037 rtw_write8(padapter, REG_DWBCN1_CTRL_8703B + 2, val8);
5038 } else
5039 #endif /* CONFIG_CONCURRENT_MODE */
5040 {
5041 /* SW_BCN_SEL - Port0 */
5042 val8 = rtw_read8(padapter, REG_DWBCN1_CTRL_8703B + 2);
5043 val8 &= ~BIT(4);
5044 rtw_write8(padapter, REG_DWBCN1_CTRL_8703B + 2, val8);
5045 }
5046 break;
5047
5048 #ifdef CONFIG_GPIO_WAKEUP
5049 case HW_SET_GPIO_WL_CTRL: {
5050 u8 enable = *val;
5051 u8 value = rtw_read8(padapter, 0x4e);
5052 if (enable && (value & BIT(6))) {
5053 value &= ~BIT(6);
5054 rtw_write8(padapter, 0x4e, value);
5055 } else if (enable == _FALSE) {
5056 value |= BIT(6);
5057 rtw_write8(padapter, 0x4e, value);
5058 }
5059 RTW_INFO("%s: set WL control, 0x4E=0x%02X\n",
5060 __func__, rtw_read8(padapter, 0x4e));
5061 }
5062 break;
5063 #endif
5064
5065 default:
5066 ret = SetHwReg(padapter, variable, val);
5067 break;
5068 }
5069
5070 return ret;
5071 }
5072 #ifdef CONFIG_PROC_DEBUG
5073 struct qinfo_8703b {
5074 u32 head:8;
5075 u32 pkt_num:7;
5076 u32 tail:8;
5077 u32 ac:2;
5078 u32 macid:7;
5079 };
5080
5081 struct bcn_qinfo_8703b {
5082 u16 head:8;
5083 u16 pkt_num:8;
5084 };
5085
dump_qinfo_8703b(void * sel,struct qinfo_8703b * info,const char * tag)5086 void dump_qinfo_8703b(void *sel, struct qinfo_8703b *info, const char *tag)
5087 {
5088 /* if (info->pkt_num) */
5089 RTW_PRINT_SEL(sel, "%shead:0x%02x, tail:0x%02x, pkt_num:%u, macid:%u, ac:%u\n"
5090 , tag ? tag : "", info->head, info->tail, info->pkt_num, info->macid, info->ac
5091 );
5092 }
5093
dump_bcn_qinfo_8703b(void * sel,struct bcn_qinfo_8703b * info,const char * tag)5094 void dump_bcn_qinfo_8703b(void *sel, struct bcn_qinfo_8703b *info, const char *tag)
5095 {
5096 /* if (info->pkt_num) */
5097 RTW_PRINT_SEL(sel, "%shead:0x%02x, pkt_num:%u\n"
5098 , tag ? tag : "", info->head, info->pkt_num
5099 );
5100 }
5101
dump_mac_qinfo_8703b(void * sel,_adapter * adapter)5102 void dump_mac_qinfo_8703b(void *sel, _adapter *adapter)
5103 {
5104 u32 q0_info;
5105 u32 q1_info;
5106 u32 q2_info;
5107 u32 q3_info;
5108 u32 q4_info;
5109 u32 q5_info;
5110 u32 q6_info;
5111 u32 q7_info;
5112 u32 mg_q_info;
5113 u32 hi_q_info;
5114 u16 bcn_q_info;
5115
5116 q0_info = rtw_read32(adapter, REG_Q0_INFO);
5117 q1_info = rtw_read32(adapter, REG_Q1_INFO);
5118 q2_info = rtw_read32(adapter, REG_Q2_INFO);
5119 q3_info = rtw_read32(adapter, REG_Q3_INFO);
5120 q4_info = rtw_read32(adapter, REG_Q4_INFO);
5121 q5_info = rtw_read32(adapter, REG_Q5_INFO);
5122 q6_info = rtw_read32(adapter, REG_Q6_INFO);
5123 q7_info = rtw_read32(adapter, REG_Q7_INFO);
5124 mg_q_info = rtw_read32(adapter, REG_MGQ_INFO);
5125 hi_q_info = rtw_read32(adapter, REG_HGQ_INFO);
5126 bcn_q_info = rtw_read16(adapter, REG_BCNQ_INFO);
5127
5128 dump_qinfo_8703b(sel, (struct qinfo_8703b *)&q0_info, "Q0 ");
5129 dump_qinfo_8703b(sel, (struct qinfo_8703b *)&q1_info, "Q1 ");
5130 dump_qinfo_8703b(sel, (struct qinfo_8703b *)&q2_info, "Q2 ");
5131 dump_qinfo_8703b(sel, (struct qinfo_8703b *)&q3_info, "Q3 ");
5132 dump_qinfo_8703b(sel, (struct qinfo_8703b *)&q4_info, "Q4 ");
5133 dump_qinfo_8703b(sel, (struct qinfo_8703b *)&q5_info, "Q5 ");
5134 dump_qinfo_8703b(sel, (struct qinfo_8703b *)&q6_info, "Q6 ");
5135 dump_qinfo_8703b(sel, (struct qinfo_8703b *)&q7_info, "Q7 ");
5136 dump_qinfo_8703b(sel, (struct qinfo_8703b *)&mg_q_info, "MG ");
5137 dump_qinfo_8703b(sel, (struct qinfo_8703b *)&hi_q_info, "HI ");
5138 dump_bcn_qinfo_8703b(sel, (struct bcn_qinfo_8703b *)&bcn_q_info, "BCN ");
5139 }
5140
dump_mac_txfifo_8703b(void * sel,_adapter * adapter)5141 static void dump_mac_txfifo_8703b(void *sel, _adapter *adapter)
5142 {
5143 u32 rqpn, rqpn_npq;
5144 u32 hpq, lpq, npq, epq, pubq;
5145
5146 rqpn = rtw_read32(adapter, REG_FIFOPAGE);
5147 rqpn_npq = rtw_read32(adapter, REG_RQPN_NPQ);
5148
5149 hpq = (rqpn & 0xFF);
5150 lpq = ((rqpn & 0xFF00)>>8);
5151 pubq = ((rqpn & 0xFF0000)>>16);
5152 npq = ((rqpn_npq & 0xFF00)>>8);
5153 epq = ((rqpn_npq & 0xFF000000)>>24);
5154
5155 RTW_PRINT_SEL(sel, "Tx: available page num: ");
5156 if ((hpq == 0xEA) && (hpq == lpq) && (hpq == pubq))
5157 RTW_PRINT_SEL(sel, "N/A (reg val = 0xea)\n");
5158 else
5159 RTW_PRINT_SEL(sel, "HPQ: %d, LPQ: %d, NPQ: %d, EPQ: %d, PUBQ: %d\n"
5160 , hpq, lpq, npq, epq, pubq);
5161 }
5162 #endif
5163
GetHwReg8703B(PADAPTER padapter,u8 variable,u8 * val)5164 void GetHwReg8703B(PADAPTER padapter, u8 variable, u8 *val)
5165 {
5166 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
5167 u8 val8;
5168 u16 val16;
5169 u32 val32;
5170
5171
5172 switch (variable) {
5173 case HW_VAR_TXPAUSE:
5174 *val = rtw_read8(padapter, REG_TXPAUSE);
5175 break;
5176
5177 case HW_VAR_BCN_VALID:
5178 #ifdef CONFIG_CONCURRENT_MODE
5179 if (padapter->hw_port == HW_PORT1) {
5180 val8 = rtw_read8(padapter, REG_DWBCN1_CTRL_8703B + 2);
5181 *val = (BIT(0) & val8) ? _TRUE : _FALSE;
5182 } else
5183 #endif
5184 {
5185 /* BCN_VALID, BIT16 of REG_TDECTRL = BIT0 of REG_TDECTRL+2 */
5186 val8 = rtw_read8(padapter, REG_TDECTRL + 2);
5187 *val = (BIT(0) & val8) ? _TRUE : _FALSE;
5188 }
5189 break;
5190
5191 case HW_VAR_EFUSE_USAGE:
5192 *val = pHalData->EfuseUsedPercentage;
5193 break;
5194
5195 case HW_VAR_EFUSE_BYTES:
5196 *((u16 *)val) = pHalData->EfuseUsedBytes;
5197 break;
5198
5199 case HW_VAR_EFUSE_BT_USAGE:
5200 #ifdef HAL_EFUSE_MEMORY
5201 *val = pHalData->EfuseHal.BTEfuseUsedPercentage;
5202 #endif
5203 break;
5204
5205 case HW_VAR_EFUSE_BT_BYTES:
5206 #ifdef HAL_EFUSE_MEMORY
5207 *((u16 *)val) = pHalData->EfuseHal.BTEfuseUsedBytes;
5208 #else
5209 *((u16 *)val) = BTEfuseUsedBytes;
5210 #endif
5211 break;
5212
5213 case HW_VAR_CHK_HI_QUEUE_EMPTY:
5214 val16 = rtw_read16(padapter, REG_TXPKT_EMPTY);
5215 *val = (val16 & BIT(10)) ? _TRUE : _FALSE;
5216 break;
5217 case HW_VAR_CHK_MGQ_CPU_EMPTY:
5218 val16 = rtw_read16(padapter, REG_TXPKT_EMPTY);
5219 *val = (val16 & BIT(8)) ? _TRUE : _FALSE;
5220 break;
5221 #ifdef CONFIG_WOWLAN
5222 case HW_VAR_RPWM_TOG:
5223 *val = rtw_read8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1) & BIT7;
5224 break;
5225 case HW_VAR_WAKEUP_REASON:
5226 *val = rtw_read8(padapter, REG_WOWLAN_WAKE_REASON);
5227 if (*val == 0xEA)
5228 *val = 0;
5229 break;
5230 case HW_VAR_SYS_CLKR:
5231 *val = rtw_read8(padapter, REG_SYS_CLKR);
5232 break;
5233 #endif
5234 #ifdef CONFIG_PROC_DEBUG
5235 case HW_VAR_DUMP_MAC_QUEUE_INFO:
5236 dump_mac_qinfo_8703b(val, padapter);
5237 break;
5238 case HW_VAR_DUMP_MAC_TXFIFO:
5239 dump_mac_txfifo_8703b(val, padapter);
5240 break;
5241 #endif
5242 default:
5243 GetHwReg(padapter, variable, val);
5244 break;
5245 }
5246 }
5247
5248 /*
5249 * Description:
5250 * Change default setting of specified variable.
5251 */
SetHalDefVar8703B(PADAPTER padapter,HAL_DEF_VARIABLE variable,void * pval)5252 u8 SetHalDefVar8703B(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval)
5253 {
5254 PHAL_DATA_TYPE pHalData;
5255 u8 bResult;
5256
5257
5258 pHalData = GET_HAL_DATA(padapter);
5259 bResult = _SUCCESS;
5260
5261 switch (variable) {
5262 default:
5263 bResult = SetHalDefVar(padapter, variable, pval);
5264 break;
5265 }
5266
5267 return bResult;
5268 }
5269
hal_ra_info_dump(_adapter * padapter,void * sel)5270 void hal_ra_info_dump(_adapter *padapter , void *sel)
5271 {
5272 int i;
5273 u8 mac_id;
5274 u32 cmd;
5275 u32 ra_info1, ra_info2, bw_set;
5276 u32 rate_mask1, rate_mask2;
5277 u8 curr_tx_rate, curr_tx_sgi, hight_rate, lowest_rate;
5278 struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
5279 struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
5280 HAL_DATA_TYPE *HalData = GET_HAL_DATA(padapter);
5281
5282 for (i = 0; i < macid_ctl->num; i++) {
5283
5284 if (rtw_macid_is_used(macid_ctl, i) && !rtw_macid_is_bmc(macid_ctl, i)) {
5285
5286 mac_id = (u8) i;
5287 _RTW_PRINT_SEL(sel , "============ RA status check Mac_id:%d ===================\n", mac_id);
5288
5289 cmd = 0x40000100 | mac_id;
5290 rtw_write32(padapter, REG_HMEBOX_DBG_2_8703B, cmd);
5291 rtw_msleep_os(10);
5292 ra_info1 = rtw_read32(padapter, 0x2F0);
5293 curr_tx_sgi = rtw_get_current_tx_sgi(padapter, macid_ctl->sta[mac_id]);
5294 curr_tx_rate = rtw_get_current_tx_rate(padapter, macid_ctl->sta[mac_id]);
5295
5296 _RTW_PRINT_SEL(sel , "[ ra_info1:0x%08x ] =>cur_tx_rate= %s,cur_sgi:%d\n", ra_info1, HDATA_RATE(curr_tx_rate), curr_tx_sgi);
5297 _RTW_PRINT_SEL(sel , "[ ra_info1:0x%08x ] => PWRSTS = 0x%02x\n", ra_info1, (ra_info1 >> 8) & 0x07);
5298
5299 cmd = 0x40000400 | mac_id;
5300 rtw_write32(padapter, REG_HMEBOX_DBG_2_8703B, cmd);
5301 rtw_msleep_os(10);
5302 ra_info1 = rtw_read32(padapter, 0x2F0);
5303 ra_info2 = rtw_read32(padapter, 0x2F4);
5304 rate_mask1 = rtw_read32(padapter, 0x2F8);
5305 rate_mask2 = rtw_read32(padapter, 0x2FC);
5306 hight_rate = ra_info2 & 0xFF;
5307 lowest_rate = (ra_info2 >> 8) & 0xFF;
5308 bw_set = (ra_info1 >> 8) & 0xFF;
5309
5310 _RTW_PRINT_SEL(sel , "[ ra_info1:0x%08x ] => VHT_EN=0x%02x, ", ra_info1, (ra_info1 >> 24) & 0xFF);
5311
5312
5313 switch (bw_set) {
5314
5315 case CHANNEL_WIDTH_20:
5316 _RTW_PRINT_SEL(sel , "BW_setting=20M\n");
5317 break;
5318
5319 case CHANNEL_WIDTH_40:
5320 _RTW_PRINT_SEL(sel , "BW_setting=40M\n");
5321 break;
5322
5323 case CHANNEL_WIDTH_80:
5324 _RTW_PRINT_SEL(sel , "BW_setting=80M\n");
5325 break;
5326
5327 case CHANNEL_WIDTH_160:
5328 _RTW_PRINT_SEL(sel , "BW_setting=160M\n");
5329 break;
5330
5331 default:
5332 _RTW_PRINT_SEL(sel , "BW_setting=0x%02x\n", bw_set);
5333 break;
5334
5335 }
5336
5337 _RTW_PRINT_SEL(sel , "[ ra_info1:0x%08x ] =>RSSI=%d, DISRA=0x%02x\n",
5338 ra_info1,
5339 ra_info1 & 0xFF,
5340 (ra_info1 >> 16) & 0xFF);
5341
5342 _RTW_PRINT_SEL(sel , "[ ra_info2:0x%08x ] =>hight_rate=%s, lowest_rate=%s, SGI=0x%02x, RateID=%d\n",
5343 ra_info2,
5344 HDATA_RATE(hight_rate),
5345 HDATA_RATE(lowest_rate),
5346 (ra_info2 >> 16) & 0xFF,
5347 (ra_info2 >> 24) & 0xFF);
5348
5349 _RTW_PRINT_SEL(sel , "rate_mask2=0x%08x, rate_mask1=0x%08x\n", rate_mask2, rate_mask1);
5350
5351 }
5352 }
5353 }
5354
5355 /*
5356 * Description:
5357 * Query setting of specified variable.
5358 */
GetHalDefVar8703B(PADAPTER padapter,HAL_DEF_VARIABLE variable,void * pval)5359 u8 GetHalDefVar8703B(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval)
5360 {
5361 PHAL_DATA_TYPE pHalData;
5362 u8 bResult;
5363
5364
5365 pHalData = GET_HAL_DATA(padapter);
5366 bResult = _SUCCESS;
5367
5368 switch (variable) {
5369 case HAL_DEF_MAX_RECVBUF_SZ:
5370 *((u32 *)pval) = MAX_RECVBUF_SZ;
5371 break;
5372
5373 case HAL_DEF_RX_PACKET_OFFSET:
5374 *((u32 *)pval) = RXDESC_SIZE + DRVINFO_SZ * 8;
5375 break;
5376
5377 case HW_VAR_MAX_RX_AMPDU_FACTOR:
5378 /* Stanley@BB.SD3 suggests 16K can get stable performance */
5379 /* The experiment was done on SDIO interface */
5380 /* coding by Lucas@20130730 */
5381 *(HT_CAP_AMPDU_FACTOR *)pval = MAX_AMPDU_FACTOR_16K;
5382 break;
5383 case HW_VAR_BEST_AMPDU_DENSITY:
5384 *((u32 *)pval) = AMPDU_DENSITY_VALUE_7;
5385 break;
5386 case HAL_DEF_TX_LDPC:
5387 case HAL_DEF_RX_LDPC:
5388 *((u8 *)pval) = _FALSE;
5389 break;
5390 case HAL_DEF_RX_STBC:
5391 *((u8 *)pval) = 1;
5392 break;
5393 case HAL_DEF_EXPLICIT_BEAMFORMER:
5394 case HAL_DEF_EXPLICIT_BEAMFORMEE:
5395 *((u8 *)pval) = _FALSE;
5396 break;
5397
5398 case HW_DEF_RA_INFO_DUMP:
5399 hal_ra_info_dump(padapter, pval);
5400 break;
5401
5402 case HAL_DEF_TX_PAGE_BOUNDARY:
5403 if (!padapter->registrypriv.wifi_spec)
5404 *(u8 *)pval = TX_PAGE_BOUNDARY_8703B;
5405 else
5406 *(u8 *)pval = WMM_NORMAL_TX_PAGE_BOUNDARY_8703B;
5407 break;
5408 case HAL_DEF_TX_PAGE_SIZE:
5409 *((u32 *)pval) = PAGE_SIZE_128;
5410 break;
5411 case HAL_DEF_RX_DMA_SZ_WOW:
5412 *(u32 *)pval = RX_DMA_SIZE_8703B - RESV_FMWF;
5413 break;
5414 case HAL_DEF_RX_DMA_SZ:
5415 *(u32 *)pval = RX_DMA_BOUNDARY_8703B + 1;
5416 break;
5417 case HAL_DEF_RX_PAGE_SIZE:
5418 *((u32 *)pval) = 8;
5419 break;
5420 default:
5421 bResult = GetHalDefVar(padapter, variable, pval);
5422 break;
5423 }
5424
5425 return bResult;
5426 }
5427
5428 #ifdef CONFIG_WOWLAN
Hal_DetectWoWMode(PADAPTER pAdapter)5429 void Hal_DetectWoWMode(PADAPTER pAdapter)
5430 {
5431 adapter_to_pwrctl(pAdapter)->bSupportRemoteWakeup = _TRUE;
5432 RTW_INFO("%s\n", __func__);
5433 }
5434 #endif /* CONFIG_WOWLAN */
5435
rtl8703b_start_thread(_adapter * padapter)5436 void rtl8703b_start_thread(_adapter *padapter)
5437 {
5438 #if (defined CONFIG_SDIO_HCI) || (defined CONFIG_GSPI_HCI)
5439 #ifndef CONFIG_SDIO_TX_TASKLET
5440 struct xmit_priv *xmitpriv = &padapter->xmitpriv;
5441
5442 if (xmitpriv->SdioXmitThread == NULL) {
5443 RTW_INFO(FUNC_ADPT_FMT " start RTWHALXT\n", FUNC_ADPT_ARG(padapter));
5444 xmitpriv->SdioXmitThread = kthread_run(rtl8703bs_xmit_thread, padapter, "RTWHALXT");
5445 if (IS_ERR(xmitpriv->SdioXmitThread)) {
5446 RTW_ERR("%s: start rtl8703bs_xmit_thread FAIL!!\n", __func__);
5447 xmitpriv->SdioXmitThread = NULL;
5448 }
5449 }
5450 #endif
5451 #endif
5452 }
5453
rtl8703b_stop_thread(_adapter * padapter)5454 void rtl8703b_stop_thread(_adapter *padapter)
5455 {
5456 #if (defined CONFIG_SDIO_HCI) || (defined CONFIG_GSPI_HCI)
5457 #ifndef CONFIG_SDIO_TX_TASKLET
5458 struct xmit_priv *xmitpriv = &padapter->xmitpriv;
5459
5460 /* stop xmit_buf_thread */
5461 if (xmitpriv->SdioXmitThread) {
5462 _rtw_up_sema(&xmitpriv->SdioXmitSema);
5463 rtw_thread_stop(xmitpriv->SdioXmitThread);
5464 xmitpriv->SdioXmitThread = NULL;
5465 }
5466 #endif
5467 #endif
5468 }
5469
5470 #if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST)
5471 extern void check_bt_status_work(void *data);
rtl8703bs_init_checkbthang_workqueue(_adapter * adapter)5472 void rtl8703bs_init_checkbthang_workqueue(_adapter *adapter)
5473 {
5474 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37))
5475 adapter->priv_checkbt_wq = alloc_workqueue("sdio_wq", 0, 0);
5476 #else
5477 adapter->priv_checkbt_wq = create_workqueue("sdio_wq");
5478 #endif
5479 INIT_DELAYED_WORK(&adapter->checkbt_work, (void *)check_bt_status_work);
5480 }
5481
rtl8703bs_free_checkbthang_workqueue(_adapter * adapter)5482 void rtl8703bs_free_checkbthang_workqueue(_adapter *adapter)
5483 {
5484 if (adapter->priv_checkbt_wq) {
5485 cancel_delayed_work_sync(&adapter->checkbt_work);
5486 flush_workqueue(adapter->priv_checkbt_wq);
5487 destroy_workqueue(adapter->priv_checkbt_wq);
5488 adapter->priv_checkbt_wq = NULL;
5489 }
5490 }
5491
rtl8703bs_cancle_checkbthang_workqueue(_adapter * adapter)5492 void rtl8703bs_cancle_checkbthang_workqueue(_adapter *adapter)
5493 {
5494 if (adapter->priv_checkbt_wq)
5495 cancel_delayed_work_sync(&adapter->checkbt_work);
5496 }
5497
rtl8703bs_hal_check_bt_hang(_adapter * adapter)5498 void rtl8703bs_hal_check_bt_hang(_adapter *adapter)
5499 {
5500 if (adapter->priv_checkbt_wq)
5501 queue_delayed_work(adapter->priv_checkbt_wq, &(adapter->checkbt_work), 0);
5502 }
5503 #endif
5504
rtl8703b_set_hal_ops(struct hal_ops * pHalFunc)5505 void rtl8703b_set_hal_ops(struct hal_ops *pHalFunc)
5506 {
5507 pHalFunc->dm_init = &rtl8703b_init_dm_priv;
5508 pHalFunc->dm_deinit = &rtl8703b_deinit_dm_priv;
5509
5510 pHalFunc->read_chip_version = read_chip_version_8703b;
5511
5512 pHalFunc->set_chnl_bw_handler = &PHY_SetSwChnlBWMode8703B;
5513
5514 pHalFunc->set_tx_power_level_handler = &PHY_SetTxPowerLevel8703B;
5515 pHalFunc->set_tx_power_index_handler = PHY_SetTxPowerIndex_8703B;
5516 pHalFunc->get_tx_power_index_handler = hal_com_get_txpwr_idx;
5517
5518 pHalFunc->hal_dm_watchdog = &rtl8703b_HalDmWatchDog;
5519
5520 pHalFunc->SetBeaconRelatedRegistersHandler = &rtl8703b_SetBeaconRelatedRegisters;
5521
5522 pHalFunc->run_thread = &rtl8703b_start_thread;
5523 pHalFunc->cancel_thread = &rtl8703b_stop_thread;
5524
5525 pHalFunc->read_bbreg = &PHY_QueryBBReg_8703B;
5526 pHalFunc->write_bbreg = &PHY_SetBBReg_8703B;
5527 pHalFunc->read_rfreg = &PHY_QueryRFReg_8703B;
5528 pHalFunc->write_rfreg = &PHY_SetRFReg_8703B;
5529
5530 /* Efuse related function */
5531 pHalFunc->BTEfusePowerSwitch = &Hal_BT_EfusePowerSwitch;
5532 pHalFunc->EfusePowerSwitch = &Hal_EfusePowerSwitch;
5533 pHalFunc->ReadEFuse = &Hal_ReadEFuse;
5534 pHalFunc->EFUSEGetEfuseDefinition = &Hal_GetEfuseDefinition;
5535 pHalFunc->EfuseGetCurrentSize = &Hal_EfuseGetCurrentSize;
5536 pHalFunc->Efuse_PgPacketRead = &Hal_EfusePgPacketRead;
5537 pHalFunc->Efuse_PgPacketWrite = &Hal_EfusePgPacketWrite;
5538 pHalFunc->Efuse_WordEnableDataWrite = &Hal_EfuseWordEnableDataWrite;
5539 pHalFunc->Efuse_PgPacketWrite_BT = &Hal_EfusePgPacketWrite_BT;
5540
5541 #ifdef DBG_CONFIG_ERROR_DETECT
5542 pHalFunc->sreset_init_value = &sreset_init_value;
5543 pHalFunc->sreset_reset_value = &sreset_reset_value;
5544 pHalFunc->silentreset = &sreset_reset;
5545 pHalFunc->sreset_xmit_status_check = &rtl8703b_sreset_xmit_status_check;
5546 pHalFunc->sreset_linked_status_check = &rtl8703b_sreset_linked_status_check;
5547 pHalFunc->sreset_get_wifi_status = &sreset_get_wifi_status;
5548 pHalFunc->sreset_inprogress = &sreset_inprogress;
5549 #endif
5550 pHalFunc->GetHalODMVarHandler = GetHalODMVar;
5551 pHalFunc->SetHalODMVarHandler = SetHalODMVar;
5552
5553 #ifdef CONFIG_XMIT_THREAD_MODE
5554 pHalFunc->xmit_thread_handler = &hal_xmit_handler;
5555 #endif
5556 pHalFunc->hal_notch_filter = &hal_notch_filter_8703b;
5557
5558 pHalFunc->c2h_handler = c2h_handler_8703b;
5559
5560 pHalFunc->fill_h2c_cmd = &FillH2CCmd8703B;
5561 pHalFunc->fill_fake_txdesc = &rtl8703b_fill_fake_txdesc;
5562 pHalFunc->fw_dl = &rtl8703b_FirmwareDownload;
5563 pHalFunc->hal_get_tx_buff_rsvd_page_num = &GetTxBufferRsvdPageNum8703B;
5564 }
5565
5566