1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 *
19 ******************************************************************************/
20 #define _SDIO_HALINIT_C_
21
22 #include <drv_types.h>
23 #include <rtl8188e_hal.h>
24 #include "hal_com_h2c.h"
25 #ifndef CONFIG_SDIO_HCI
26 #error "CONFIG_SDIO_HCI shall be on!\n"
27 #endif
28
dump_sdio_f0(PADAPTER padapter)29 static void dump_sdio_f0(PADAPTER padapter)
30 {
31 char str_out[128];
32 char str_val[8];
33 char *p = NULL;
34 int index = 0, i = 0;
35 u8 val8 = 0, len = 0;
36
37 DBG_871X("Dump SDIO f0:\n");
38 for (index = 0 ; index < 0x100 ; index += 16) {
39 p = &str_out[0];
40 len = snprintf(str_val, sizeof(str_val),
41 "0x%02x: ", index);
42 strncpy(str_out, str_val, len);
43 p += len;
44
45 for (i = 0 ; i < 16 ; i++) {
46 len = snprintf(str_val, sizeof(str_val), "%02x ",
47 rtw_sd_f0_read8(padapter, (index + i)));
48 strncpy(p, str_val, len);
49 p += len;
50 }
51 DBG_871X("%s\n", str_out);
52 _rtw_memset(&str_out, '\0', sizeof(str_out));
53 }
54
55 }
56
dump_sdio_local(PADAPTER padapter)57 static void dump_sdio_local(PADAPTER padapter)
58 {
59 char str_out[128];
60 char str_val[8];
61 char *p = NULL;
62 int index = 0, i = 0;
63 u8 val8 = 0, len = 0;
64
65 DBG_871X("Dump SDIO local register:\n");
66 for (index = 0 ; index < 0x100 ; index += 16) {
67 p = &str_out[0];
68 len = snprintf(str_val, sizeof(str_val),
69 "0x%02x: ", index);
70 strncpy(str_out, str_val, len);
71 p += len;
72
73 for (i = 0 ; i < 16 ; i++) {
74 len = snprintf(str_val, sizeof(str_val), "%02x ",
75 rtw_read8(padapter, (0x1025 << 16) | (index + i)));
76 strncpy(p, str_val, len);
77 p += len;
78 }
79 DBG_871X("%s\n", str_out);
80 _rtw_memset(&str_out, '\0', sizeof(str_out));
81 }
82 }
83
84
dump_mac_page0(PADAPTER padapter)85 static void dump_mac_page0(PADAPTER padapter)
86 {
87 char str_out[128];
88 char str_val[8];
89 char *p = NULL;
90 int index = 0, i = 0;
91 u8 val8 = 0, len = 0;
92
93 DBG_871X("Dump MAC Page0 register:\n");
94 for (index = 0 ; index < 0x100 ; index += 16) {
95 p = &str_out[0];
96 len = snprintf(str_val, sizeof(str_val),
97 "0x%02x: ", index);
98 strncpy(str_out, str_val, len);
99 p += len;
100
101 for (i = 0 ; i < 16 ; i++) {
102 len = snprintf(str_val, sizeof(str_val), "%02x ",
103 rtw_read8(padapter, index + i));
104 strncpy(p, str_val, len);
105 p += len;
106 }
107 DBG_871X("%s\n", str_out);
108 _rtw_memset(&str_out, '\0', sizeof(str_out));
109 }
110 }
111
112 /*
113 * Description:
114 * Call this function to make sure power on successfully
115 *
116 * Return:
117 * _SUCCESS enable success
118 * _FAIL enable fail
119 */
120
PowerOnCheck(PADAPTER padapter)121 static int PowerOnCheck(PADAPTER padapter)
122 {
123 u32 val_offset0, val_offset1, val_offset2, val_offset3;
124 u32 val_mix = 0;
125 u32 res = 0;
126 u8 ret = _FAIL;
127 int index = 0;
128
129 val_offset0 = rtw_read8(padapter, REG_CR);
130 val_offset1 = rtw_read8(padapter, REG_CR+1);
131 val_offset2 = rtw_read8(padapter, REG_CR+2);
132 val_offset3 = rtw_read8(padapter, REG_CR+3);
133
134 if (val_offset0 == 0xEA || val_offset1 == 0xEA ||
135 val_offset2 == 0xEA || val_offset3 ==0xEA) {
136 DBG_871X("%s: power on fail, do Power on again\n", __func__);
137 return ret;
138 }
139
140 val_mix = val_offset3 << 24 | val_mix;
141 val_mix = val_offset2 << 16 | val_mix;
142 val_mix = val_offset1 << 8 | val_mix;
143 val_mix = val_offset0 | val_mix;
144
145 res = rtw_read32(padapter, REG_CR);
146
147 DBG_871X("%s: val_mix:0x%08x, res:0x%08x\n", __func__, val_mix, res);
148
149 while(index < 100) {
150 if (res == val_mix) {
151 DBG_871X("%s: 0x100 the result of cmd52 and cmd53 is the same.\n", __func__);
152 ret = _SUCCESS;
153 break;
154 } else {
155 DBG_871X("%s: 0x100 cmd52 and cmd53 is not the same(index:%d).\n", __func__, index);
156 res = rtw_read32(padapter, REG_CR);
157 index ++;
158 ret = _FAIL;
159 }
160 }
161
162 if (ret) {
163 index = 0;
164 while(index < 100) {
165 rtw_write32(padapter, 0x1B8, 0x12345678);
166 res = rtw_read32(padapter, 0x1B8);
167 if (res == 0x12345678) {
168 DBG_871X("%s: 0x1B8 test Pass.\n", __func__);
169 ret = _SUCCESS;
170 break;
171 } else {
172 index ++;
173 DBG_871X("%s: 0x1B8 test Fail(index: %d).\n", __func__, index);
174 ret = _FAIL;
175 }
176 }
177 } else {
178 DBG_871X("%s: fail at cmd52, cmd53.\n", __func__);
179 }
180
181 if (ret == _FAIL) {
182 dump_sdio_f0(padapter);
183 dump_sdio_local(padapter);
184 dump_mac_page0(padapter);
185 }
186
187 return ret;
188 }
189
190 #ifdef CONFIG_EXT_CLK
EnableGpio5ClockReq(PADAPTER Adapter,u8 in_interrupt,u32 Enable)191 void EnableGpio5ClockReq(PADAPTER Adapter, u8 in_interrupt, u32 Enable)
192 {
193 u32 value32;
194 HAL_DATA_TYPE *pHalData;
195
196 pHalData = GET_HAL_DATA(Adapter);
197 if(IS_D_CUT(pHalData->VersionID))
198 return;
199
200 //dbgdump("%s Enable:%x time:%d", __RTL_FUNC__, Enable, rtw_get_current_time());
201
202 if(in_interrupt)
203 value32 = _sdio_read32(Adapter, REG_GPIO_PIN_CTRL);
204 else
205 value32 = rtw_read32(Adapter, REG_GPIO_PIN_CTRL);
206
207 //open GPIO 5
208 if (Enable)
209 value32 |= BIT(13);//5+8
210 else
211 value32 &= ~BIT(13);
212
213 //GPIO 5 out put
214 value32 |= BIT(21);//5+16
215
216 //if (Enable)
217 // rtw_write8(Adapter, REG_GPIO_PIN_CTRL + 1, 0x20);
218 //else
219 // rtw_write8(Adapter, REG_GPIO_PIN_CTRL + 1, 0x00);
220
221 if(in_interrupt)
222 _sdio_write32(Adapter, REG_GPIO_PIN_CTRL, value32);
223 else
224 rtw_write32(Adapter, REG_GPIO_PIN_CTRL, value32);
225
226 } //end of EnableGpio5ClockReq()
227
_InitClockTo26MHz(IN PADAPTER Adapter)228 void _InitClockTo26MHz(
229 IN PADAPTER Adapter
230 )
231 {
232 u8 u1temp = 0;
233 HAL_DATA_TYPE *pHalData;
234
235 pHalData = GET_HAL_DATA(Adapter);
236
237 if(IS_D_CUT(pHalData->VersionID)) {
238 //FW special init
239 u1temp = rtw_read8(Adapter, REG_XCK_OUT_CTRL);
240 u1temp |= 0x18;
241 rtw_write8(Adapter, REG_XCK_OUT_CTRL, u1temp);
242 MSG_8192C("D cut version\n");
243 }
244
245 EnableGpio5ClockReq(Adapter, _FALSE, 1);
246
247 //0x2c[3:0] = 5 will set clock to 26MHz
248 u1temp = rtw_read8(Adapter, REG_APE_PLL_CTRL_EXT);
249 u1temp = (u1temp & 0xF0) | 0x05;
250 rtw_write8(Adapter, REG_APE_PLL_CTRL_EXT, u1temp);
251 }
252 #endif
253
254
rtl8188es_interface_configure(PADAPTER padapter)255 static void rtl8188es_interface_configure(PADAPTER padapter)
256 {
257 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
258 struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
259 struct registry_priv *pregistrypriv = &padapter->registrypriv;
260 BOOLEAN bWiFiConfig = pregistrypriv->wifi_spec;
261
262
263 pdvobjpriv->RtOutPipe[0] = WLAN_TX_HIQ_DEVICE_ID;
264 pdvobjpriv->RtOutPipe[1] = WLAN_TX_MIQ_DEVICE_ID;
265 pdvobjpriv->RtOutPipe[2] = WLAN_TX_LOQ_DEVICE_ID;
266
267 if (bWiFiConfig)
268 pHalData->OutEpNumber = 2;
269 else
270 pHalData->OutEpNumber = SDIO_MAX_TX_QUEUE;
271
272 switch(pHalData->OutEpNumber){
273 case 3:
274 pHalData->OutEpQueueSel=TX_SELE_HQ| TX_SELE_LQ|TX_SELE_NQ;
275 break;
276 case 2:
277 pHalData->OutEpQueueSel=TX_SELE_HQ| TX_SELE_NQ;
278 break;
279 case 1:
280 pHalData->OutEpQueueSel=TX_SELE_HQ;
281 break;
282 default:
283 break;
284 }
285
286 Hal_MappingOutPipe(padapter, pHalData->OutEpNumber);
287 }
288
289 /*
290 * Description:
291 * Call power on sequence to enable card
292 *
293 * Return:
294 * _SUCCESS enable success
295 * _FAIL enable fail
296 */
_CardEnable(PADAPTER padapter)297 static u8 _CardEnable(PADAPTER padapter)
298 {
299 u8 bMacPwrCtrlOn;
300 u8 ret;
301
302 DBG_871X("=>%s\n", __FUNCTION__);
303
304 rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
305 if (bMacPwrCtrlOn == _FALSE)
306 {
307 #ifdef CONFIG_PLATFORM_SPRD
308 u8 val8;
309 #endif // CONFIG_PLATFORM_SPRD
310
311 // RSV_CTRL 0x1C[7:0] = 0x00
312 // unlock ISO/CLK/Power control register
313 rtw_write8(padapter, REG_RSV_CTRL, 0x0);
314
315 #ifdef CONFIG_EXT_CLK
316 _InitClockTo26MHz(padapter);
317 #endif //CONFIG_EXT_CLK
318
319 #ifdef CONFIG_PLATFORM_SPRD
320 val8 = rtw_read8(padapter, 0x4);
321 val8 = val8 & ~BIT(5);
322 rtw_write8(padapter, 0x4, val8);
323 #endif // CONFIG_PLATFORM_SPRD
324
325 ret = HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, Rtl8188E_NIC_ENABLE_FLOW);
326 if (ret == _SUCCESS) {
327 u8 bMacPwrCtrlOn = _TRUE;
328 rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
329 }
330 else
331 {
332 DBG_871X(KERN_ERR "%s: run power on flow fail\n", __func__);
333 return _FAIL;
334 }
335
336 }
337 else
338 {
339
340 DBG_871X("=>%s bMacPwrCtrlOn == _TRUE do nothing !!\n", __FUNCTION__);
341 ret = _SUCCESS;
342 }
343
344 DBG_871X("<=%s\n", __FUNCTION__);
345
346 return ret;
347
348 }
349
_InitPowerOn_8188ES(PADAPTER padapter)350 static u32 _InitPowerOn_8188ES(PADAPTER padapter)
351 {
352 u8 value8;
353 u16 value16;
354 u32 value32;
355 u8 ret;
356
357 DBG_871X("=>%s\n", __FUNCTION__);
358
359 ret = _CardEnable(padapter);
360 if (ret == _FAIL) {
361 return ret;
362 }
363
364 /*
365 // Radio-Off Pin Trigger
366 value8 = rtw_read8(padapter, REG_GPIO_INTM+1);
367 value8 |= BIT(1); // Enable falling edge triggering interrupt
368 rtw_write8(padapter, REG_GPIO_INTM+1, value8);
369 value8 = rtw_read8(padapter, REG_GPIO_IO_SEL_2+1);
370 value8 |= BIT(1);
371 rtw_write8(padapter, REG_GPIO_IO_SEL_2+1, value8);
372 */
373
374 // Enable power down and GPIO interrupt
375 value16 = rtw_read16(padapter, REG_APS_FSMCO);
376 value16 |= EnPDN; // Enable HW power down and RF on
377 rtw_write16(padapter, REG_APS_FSMCO, value16);
378
379
380 // Enable MAC DMA/WMAC/SCHEDULE/SEC block
381 value16 = rtw_read16(padapter, REG_CR);
382 value16 |= (HCI_TXDMA_EN | HCI_RXDMA_EN | TXDMA_EN | RXDMA_EN
383 | PROTOCOL_EN | SCHEDULE_EN | ENSEC | CALTMR_EN);
384 // for SDIO - Set CR bit10 to enable 32k calibration. Suggested by SD1 Gimmy. Added by tynli. 2011.08.31.
385
386 rtw_write16(padapter, REG_CR, value16);
387
388 // Enable CMD53 R/W Operation
389 // bMacPwrCtrlOn = TRUE;
390 // rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, (pu8)(&bMacPwrCtrlOn));
391
392 DBG_871X("<=%s\n", __FUNCTION__);
393
394 return _SUCCESS;
395
396 }
397
hal_poweroff_8188es(PADAPTER padapter)398 static void hal_poweroff_8188es(PADAPTER padapter)
399 {
400 u8 u1bTmp;
401 u16 u2bTmp;
402 u32 u4bTmp;
403 u8 bMacPwrCtrlOn = _FALSE;
404 u8 ret;
405
406 #ifdef CONFIG_PLATFORM_SPRD
407 struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
408 #endif //CONFIG_PLATFORM_SPRD
409
410 rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
411 if(bMacPwrCtrlOn == _FALSE)
412 {
413 DBG_871X("=>%s bMacPwrCtrlOn == _FALSE return !!\n", __FUNCTION__);
414 return;
415 }
416 DBG_871X("=>%s\n", __FUNCTION__);
417
418
419 //Stop Tx Report Timer. 0x4EC[Bit1]=b'0
420 u1bTmp = rtw_read8(padapter, REG_TX_RPT_CTRL);
421 rtw_write8(padapter, REG_TX_RPT_CTRL, u1bTmp&(~BIT1));
422
423 // stop rx
424 rtw_write8(padapter,REG_CR, 0x0);
425
426
427 #ifdef CONFIG_EXT_CLK //for sprd For Power Consumption.
428 EnableGpio5ClockReq(padapter, _FALSE, 0);
429 #endif //CONFIG_EXT_CLK
430
431 #if 1
432 // For Power Consumption.
433 u1bTmp = rtw_read8(padapter, GPIO_IN);
434 rtw_write8(padapter, GPIO_OUT, u1bTmp);
435 rtw_write8(padapter, GPIO_IO_SEL, 0xFF);//Reg0x46
436
437 u1bTmp = rtw_read8(padapter, REG_GPIO_IO_SEL);
438 rtw_write8(padapter, REG_GPIO_IO_SEL, (u1bTmp<<4)|u1bTmp);
439 u1bTmp = rtw_read8(padapter, REG_GPIO_IO_SEL+1);
440 rtw_write8(padapter, REG_GPIO_IO_SEL+1, u1bTmp|0x0F);//Reg0x43
441 #endif
442
443
444 // Run LPS WL RFOFF flow
445 ret = HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, Rtl8188E_NIC_LPS_ENTER_FLOW);
446 if (ret == _FALSE) {
447 DBG_871X("%s: run RF OFF flow fail!\n", __func__);
448 }
449
450 // ==== Reset digital sequence ======
451
452 u1bTmp = rtw_read8(padapter, REG_MCUFWDL);
453 if ((u1bTmp & RAM_DL_SEL) && padapter->bFWReady) //8051 RAM code
454 {
455 //_8051Reset88E(padapter);
456
457 // Reset MCU 0x2[10]=0.
458 u1bTmp = rtw_read8(padapter, REG_SYS_FUNC_EN+1);
459 u1bTmp &= ~BIT(2); // 0x2[10], FEN_CPUEN
460 rtw_write8(padapter, REG_SYS_FUNC_EN+1, u1bTmp);
461 }
462
463 //u1bTmp = rtw_read8(padapter, REG_SYS_FUNC_EN+1);
464 //u1bTmp &= ~BIT(2); // 0x2[10], FEN_CPUEN
465 //rtw_write8(padapter, REG_SYS_FUNC_EN+1, u1bTmp);
466
467 // MCUFWDL 0x80[1:0]=0
468 // reset MCU ready status
469 rtw_write8(padapter, REG_MCUFWDL, 0);
470
471 //==== Reset digital sequence end ======
472
473
474 bMacPwrCtrlOn = _FALSE; // Disable CMD53 R/W
475 rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
476
477
478 /*
479 if((pMgntInfo->RfOffReason & RF_CHANGE_BY_HW) && pHalData->pwrdown)
480 {// Power Down
481
482 // Card disable power action flow
483 ret = HalPwrSeqCmdParsing(Adapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, Rtl8188E_NIC_PDN_FLOW);
484 }
485 else
486 */
487 { // Non-Power Down
488
489 // Card disable power action flow
490 ret = HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, Rtl8188E_NIC_DISABLE_FLOW);
491
492
493 if (ret == _FALSE) {
494 DBG_871X("%s: run CARD DISABLE flow fail!\n", __func__);
495 }
496 }
497
498
499 /*
500 // Reset MCU IO Wrapper, added by Roger, 2011.08.30
501 u1bTmp = rtw_read8(padapter, REG_RSV_CTRL+1);
502 u1bTmp &= ~BIT(0);
503 rtw_write8(padapter, REG_RSV_CTRL+1, u1bTmp);
504 u1bTmp = rtw_read8(padapter, REG_RSV_CTRL+1);
505 u1bTmp |= BIT(0);
506 rtw_write8(padapter, REG_RSV_CTRL+1, u1bTmp);
507 */
508
509
510 // RSV_CTRL 0x1C[7:0]=0x0E
511 // lock ISO/CLK/Power control register
512 rtw_write8(padapter, REG_RSV_CTRL, 0x0E);
513
514 padapter->bFWReady = _FALSE;
515 bMacPwrCtrlOn = _FALSE;
516 rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
517
518 DBG_871X("<=%s\n", __FUNCTION__);
519
520 }
521
522 //Tx Page FIFO threshold
_init_available_page_threshold(PADAPTER padapter,u8 numHQ,u8 numNQ,u8 numLQ,u8 numPubQ)523 static void _init_available_page_threshold(PADAPTER padapter, u8 numHQ, u8 numNQ, u8 numLQ, u8 numPubQ)
524 {
525 u16 HQ_threshold, NQ_threshold, LQ_threshold;
526
527 HQ_threshold = (numPubQ + numHQ + 1) >> 1;
528 HQ_threshold |= (HQ_threshold<<8);
529
530 NQ_threshold = (numPubQ + numNQ + 1) >> 1;
531 NQ_threshold |= (NQ_threshold<<8);
532
533 LQ_threshold = (numPubQ + numLQ + 1) >> 1;
534 LQ_threshold |= (LQ_threshold<<8);
535
536 rtw_write16(padapter, 0x218, HQ_threshold);
537 rtw_write16(padapter, 0x21A, NQ_threshold);
538 rtw_write16(padapter, 0x21C, LQ_threshold);
539 DBG_8192C("%s(): Enable Tx FIFO Page Threshold H:0x%x,N:0x%x,L:0x%x\n", __FUNCTION__, HQ_threshold, NQ_threshold, LQ_threshold);
540 }
541
_InitQueueReservedPage(PADAPTER padapter)542 static void _InitQueueReservedPage(PADAPTER padapter)
543 {
544 #ifdef RTL8188ES_MAC_LOOPBACK
545
546 //#define MAC_LOOPBACK_PAGE_NUM_PUBQ 0x26
547 //#define MAC_LOOPBACK_PAGE_NUM_HPQ 0x0b
548 //#define MAC_LOOPBACK_PAGE_NUM_LPQ 0x0b
549 //#define MAC_LOOPBACK_PAGE_NUM_NPQ 0x0b // 71 pages=>9088 bytes, 8.875k
550
551 rtw_write16(padapter, REG_RQPN_NPQ, 0x0b0b);
552 rtw_write32(padapter, REG_RQPN, 0x80260b0b);
553
554 #else //TX_PAGE_BOUNDARY_LOOPBACK_MODE
555 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
556 struct registry_priv *pregistrypriv = &padapter->registrypriv;
557 u32 outEPNum = (u32)pHalData->OutEpNumber;
558 u32 numHQ = 0;
559 u32 numLQ = 0;
560 u32 numNQ = 0;
561 u32 numPubQ = 0x00;
562 u32 value32;
563 u8 value8;
564 BOOLEAN bWiFiConfig = pregistrypriv->wifi_spec;
565
566 if(bWiFiConfig)
567 {
568 if (pHalData->OutEpQueueSel & TX_SELE_HQ)
569 numHQ = WMM_NORMAL_PAGE_NUM_HPQ_88E;
570
571 if (pHalData->OutEpQueueSel & TX_SELE_LQ)
572 numLQ = WMM_NORMAL_PAGE_NUM_LPQ_88E;
573
574 // NOTE: This step shall be proceed before writting REG_RQPN.
575 if (pHalData->OutEpQueueSel & TX_SELE_NQ)
576 numNQ = WMM_NORMAL_PAGE_NUM_NPQ_88E;
577 }
578 else
579 {
580 if(pHalData->OutEpQueueSel & TX_SELE_HQ)
581 numHQ = NORMAL_PAGE_NUM_HPQ_88E;
582
583 if(pHalData->OutEpQueueSel & TX_SELE_LQ)
584 numLQ = NORMAL_PAGE_NUM_LPQ_88E;
585
586 // NOTE: This step shall be proceed before writting REG_RQPN.
587 if(pHalData->OutEpQueueSel & TX_SELE_NQ)
588 numNQ = NORMAL_PAGE_NUM_NPQ_88E;
589 }
590
591 value8 = (u8)_NPQ(numNQ);
592 rtw_write8(padapter, REG_RQPN_NPQ, value8);
593
594 numPubQ = TX_TOTAL_PAGE_NUMBER_88E(padapter) - numHQ - numLQ - numNQ;
595
596 // TX DMA
597 value32 = _HPQ(numHQ) | _LPQ(numLQ) | _PUBQ(numPubQ) | LD_RQPN;
598 rtw_write32(padapter, REG_RQPN, value32);
599
600 rtw_hal_set_sdio_tx_max_length(padapter, numHQ, numNQ, numLQ, numPubQ);
601
602 #ifdef CONFIG_SDIO_TX_ENABLE_AVAL_INT
603 _init_available_page_threshold(padapter, numHQ, numNQ, numLQ, numPubQ);
604 #endif
605 #endif
606 return;
607 }
608
_InitTxBufferBoundary(PADAPTER padapter,u8 txpktbuf_bndy)609 static void _InitTxBufferBoundary(PADAPTER padapter, u8 txpktbuf_bndy)
610 {
611 struct registry_priv *pregistrypriv = &padapter->registrypriv;
612 //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
613
614 //u16 txdmactrl;
615
616 rtw_write8(padapter, REG_BCNQ_BDNY, txpktbuf_bndy);
617 rtw_write8(padapter, REG_MGQ_BDNY, txpktbuf_bndy);
618 rtw_write8(padapter, REG_WMAC_LBK_BF_HD, txpktbuf_bndy);
619 rtw_write8(padapter, REG_TRXFF_BNDY, txpktbuf_bndy);
620 rtw_write8(padapter, REG_TDECTRL+1, txpktbuf_bndy);
621
622 }
623
624 static VOID
_InitNormalChipRegPriority(IN PADAPTER Adapter,IN u16 beQ,IN u16 bkQ,IN u16 viQ,IN u16 voQ,IN u16 mgtQ,IN u16 hiQ)625 _InitNormalChipRegPriority(
626 IN PADAPTER Adapter,
627 IN u16 beQ,
628 IN u16 bkQ,
629 IN u16 viQ,
630 IN u16 voQ,
631 IN u16 mgtQ,
632 IN u16 hiQ
633 )
634 {
635 u16 value16 = (rtw_read16(Adapter, REG_TRXDMA_CTRL) & 0x7);
636
637 value16 |= _TXDMA_BEQ_MAP(beQ) | _TXDMA_BKQ_MAP(bkQ) |
638 _TXDMA_VIQ_MAP(viQ) | _TXDMA_VOQ_MAP(voQ) |
639 _TXDMA_MGQ_MAP(mgtQ)| _TXDMA_HIQ_MAP(hiQ);
640
641 rtw_write16(Adapter, REG_TRXDMA_CTRL, value16);
642 }
643
644 static VOID
_InitNormalChipOneOutEpPriority(IN PADAPTER Adapter)645 _InitNormalChipOneOutEpPriority(
646 IN PADAPTER Adapter
647 )
648 {
649 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
650
651 u16 value = 0;
652 switch(pHalData->OutEpQueueSel)
653 {
654 case TX_SELE_HQ:
655 value = QUEUE_HIGH;
656 break;
657 case TX_SELE_LQ:
658 value = QUEUE_LOW;
659 break;
660 case TX_SELE_NQ:
661 value = QUEUE_NORMAL;
662 break;
663 default:
664 //RT_ASSERT(FALSE,("Shall not reach here!\n"));
665 break;
666 }
667
668 _InitNormalChipRegPriority(Adapter,
669 value,
670 value,
671 value,
672 value,
673 value,
674 value
675 );
676
677 }
678
679 static VOID
_InitNormalChipTwoOutEpPriority(IN PADAPTER Adapter)680 _InitNormalChipTwoOutEpPriority(
681 IN PADAPTER Adapter
682 )
683 {
684 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
685 struct registry_priv *pregistrypriv = &Adapter->registrypriv;
686 u16 beQ,bkQ,viQ,voQ,mgtQ,hiQ;
687
688
689 u16 valueHi = 0;
690 u16 valueLow = 0;
691
692 switch(pHalData->OutEpQueueSel)
693 {
694 case (TX_SELE_HQ | TX_SELE_LQ):
695 valueHi = QUEUE_HIGH;
696 valueLow = QUEUE_LOW;
697 break;
698 case (TX_SELE_NQ | TX_SELE_LQ):
699 valueHi = QUEUE_NORMAL;
700 valueLow = QUEUE_LOW;
701 break;
702 case (TX_SELE_HQ | TX_SELE_NQ):
703 valueHi = QUEUE_HIGH;
704 valueLow = QUEUE_NORMAL;
705 break;
706 default:
707 //RT_ASSERT(FALSE,("Shall not reach here!\n"));
708 break;
709 }
710
711 if(!pregistrypriv->wifi_spec ){
712 beQ = valueLow;
713 bkQ = valueLow;
714 viQ = valueHi;
715 voQ = valueHi;
716 mgtQ = valueHi;
717 hiQ = valueHi;
718 }
719 else{//for WMM ,CONFIG_OUT_EP_WIFI_MODE
720 beQ = valueLow;
721 bkQ = valueHi;
722 viQ = valueHi;
723 voQ = valueLow;
724 mgtQ = valueHi;
725 hiQ = valueHi;
726 }
727
728 _InitNormalChipRegPriority(Adapter,beQ,bkQ,viQ,voQ,mgtQ,hiQ);
729
730 }
731
732 static VOID
_InitNormalChipThreeOutEpPriority(IN PADAPTER padapter)733 _InitNormalChipThreeOutEpPriority(
734 IN PADAPTER padapter
735 )
736 {
737 struct registry_priv *pregistrypriv = &padapter->registrypriv;
738 u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
739
740 if (!pregistrypriv->wifi_spec){// typical setting
741 beQ = QUEUE_LOW;
742 bkQ = QUEUE_LOW;
743 viQ = QUEUE_NORMAL;
744 voQ = QUEUE_HIGH;
745 mgtQ = QUEUE_HIGH;
746 hiQ = QUEUE_HIGH;
747 }
748 else {// for WMM
749 beQ = QUEUE_LOW;
750 bkQ = QUEUE_NORMAL;
751 viQ = QUEUE_NORMAL;
752 voQ = QUEUE_HIGH;
753 mgtQ = QUEUE_HIGH;
754 hiQ = QUEUE_HIGH;
755 }
756 _InitNormalChipRegPriority(padapter,beQ,bkQ,viQ,voQ,mgtQ,hiQ);
757 }
758
759 static VOID
_InitNormalChipQueuePriority(IN PADAPTER Adapter)760 _InitNormalChipQueuePriority(
761 IN PADAPTER Adapter
762 )
763 {
764 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
765
766 switch(pHalData->OutEpNumber)
767 {
768 case 1:
769 _InitNormalChipOneOutEpPriority(Adapter);
770 break;
771 case 2:
772 _InitNormalChipTwoOutEpPriority(Adapter);
773 break;
774 case 3:
775 _InitNormalChipThreeOutEpPriority(Adapter);
776 break;
777 default:
778 //RT_ASSERT(FALSE,("Shall not reach here!\n"));
779 break;
780 }
781
782
783 }
784
785
_InitQueuePriority(PADAPTER padapter)786 static void _InitQueuePriority(PADAPTER padapter)
787 {
788 _InitNormalChipQueuePriority(padapter);
789 }
790
_InitPageBoundary(PADAPTER padapter)791 static void _InitPageBoundary(PADAPTER padapter)
792 {
793 // RX Page Boundary
794 u16 rxff_bndy = 0;
795
796 rxff_bndy = MAX_RX_DMA_BUFFER_SIZE_88E(padapter) - 1;
797
798 rtw_write16(padapter, (REG_TRXFF_BNDY + 2), rxff_bndy);
799
800 }
801
_InitDriverInfoSize(PADAPTER padapter,u8 drvInfoSize)802 void _InitDriverInfoSize(PADAPTER padapter, u8 drvInfoSize)
803 {
804 rtw_write8(padapter, REG_RX_DRVINFO_SZ, drvInfoSize);
805 }
806
_InitNetworkType(PADAPTER padapter)807 void _InitNetworkType(PADAPTER padapter)
808 {
809 u32 value32;
810
811 value32 = rtw_read32(padapter, REG_CR);
812
813 // TODO: use the other function to set network type
814 // value32 = (value32 & ~MASK_NETTYPE) | _NETTYPE(NT_LINK_AD_HOC);
815 value32 = (value32 & ~MASK_NETTYPE) | _NETTYPE(NT_LINK_AP);
816
817 rtw_write32(padapter, REG_CR, value32);
818 }
819
_InitWMACSetting(PADAPTER padapter)820 void _InitWMACSetting(PADAPTER padapter)
821 {
822 u16 value16;
823 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
824
825
826 //pHalData->ReceiveConfig = RCR_AAP | RCR_APM | RCR_AM | RCR_AB | RCR_CBSSID_DATA | RCR_CBSSID_BCN | RCR_AMF | RCR_HTC_LOC_CTRL | RCR_APP_PHYST_RXFF | RCR_APP_ICV | RCR_APP_MIC;
827 // don't turn on AAP, it will allow all packets to driver
828 pHalData->ReceiveConfig = RCR_APM | RCR_AM | RCR_AB | RCR_CBSSID_DATA | RCR_CBSSID_BCN | RCR_AMF | RCR_HTC_LOC_CTRL | RCR_APP_PHYST_RXFF | RCR_APP_ICV | RCR_APP_MIC;
829
830 rtw_write32(padapter, REG_RCR, pHalData->ReceiveConfig);
831
832 // Accept all data frames
833 value16 = 0xFFFF;
834 rtw_write16(padapter, REG_RXFLTMAP2, value16);
835
836 // 2010.09.08 hpfan
837 // Since ADF is removed from RCR, ps-poll will not be indicate to driver,
838 // RxFilterMap should mask ps-poll to gurantee AP mode can rx ps-poll.
839 value16 = 0x400;
840 rtw_write16(padapter, REG_RXFLTMAP1, value16);
841
842 // Accept all management frames
843 value16 = 0xFFFF;
844 rtw_write16(padapter, REG_RXFLTMAP0, value16);
845
846 }
847
_InitAdaptiveCtrl(PADAPTER padapter)848 void _InitAdaptiveCtrl(PADAPTER padapter)
849 {
850 u16 value16;
851 u32 value32;
852
853 // Response Rate Set
854 value32 = rtw_read32(padapter, REG_RRSR);
855 value32 &= ~RATE_BITMAP_ALL;
856 value32 |= RATE_RRSR_CCK_ONLY_1M;
857 rtw_write32(padapter, REG_RRSR, value32);
858
859 // CF-END Threshold
860 //m_spIoBase->rtw_write8(REG_CFEND_TH, 0x1);
861
862 // SIFS (used in NAV)
863 value16 = _SPEC_SIFS_CCK(0x10) | _SPEC_SIFS_OFDM(0x10);
864 rtw_write16(padapter, REG_SPEC_SIFS, value16);
865
866 // Retry Limit
867 value16 = _LRL(0x30) | _SRL(0x30);
868 rtw_write16(padapter, REG_RL, value16);
869 }
870
_InitEDCA(PADAPTER padapter)871 void _InitEDCA(PADAPTER padapter)
872 {
873 // Set Spec SIFS (used in NAV)
874 rtw_write16(padapter, REG_SPEC_SIFS, 0x100a);
875 rtw_write16(padapter, REG_MAC_SPEC_SIFS, 0x100a);
876
877 // Set SIFS for CCK
878 rtw_write16(padapter, REG_SIFS_CTX, 0x100a);
879
880 // Set SIFS for OFDM
881 rtw_write16(padapter, REG_SIFS_TRX, 0x100a);
882
883 // TXOP
884 rtw_write32(padapter, REG_EDCA_BE_PARAM, 0x005EA42B);
885 rtw_write32(padapter, REG_EDCA_BK_PARAM, 0x0000A44F);
886 rtw_write32(padapter, REG_EDCA_VI_PARAM, 0x005EA324);
887 rtw_write32(padapter, REG_EDCA_VO_PARAM, 0x002FA226);
888 }
889
_InitRateFallback(PADAPTER padapter)890 void _InitRateFallback(PADAPTER padapter)
891 {
892 // Set Data Auto Rate Fallback Retry Count register.
893 rtw_write32(padapter, REG_DARFRC, 0x00000000);
894 rtw_write32(padapter, REG_DARFRC+4, 0x10080404);
895 rtw_write32(padapter, REG_RARFRC, 0x04030201);
896 rtw_write32(padapter, REG_RARFRC+4, 0x08070605);
897
898 }
899
_InitRetryFunction(PADAPTER padapter)900 void _InitRetryFunction(PADAPTER padapter)
901 {
902 u8 value8;
903
904 value8 = rtw_read8(padapter, REG_FWHW_TXQ_CTRL);
905 value8 |= EN_AMPDU_RTY_NEW;
906 rtw_write8(padapter, REG_FWHW_TXQ_CTRL, value8);
907
908 // Set ACK timeout
909 rtw_write8(padapter, REG_ACKTO, 0x40);
910 }
911
HalRxAggr8188ESdio(PADAPTER padapter)912 static void HalRxAggr8188ESdio(PADAPTER padapter)
913 {
914 #if 1
915 struct registry_priv *pregistrypriv;
916 u8 valueDMATimeout;
917 u8 valueDMAPageCount;
918
919
920 pregistrypriv = &padapter->registrypriv;
921
922 if (pregistrypriv->wifi_spec)
923 {
924 // 2010.04.27 hpfan
925 // Adjust RxAggrTimeout to close to zero disable RxAggr, suggested by designer
926 // Timeout value is calculated by 34 / (2^n)
927 valueDMATimeout = 0x0f;
928 valueDMAPageCount = 0x01;
929 }
930 else
931 {
932 valueDMATimeout = 0x06;
933 //valueDMAPageCount = 0x0F;
934 //valueDMATimeout = 0x0a;
935 valueDMAPageCount = 0x24;
936 }
937
938 rtw_write8(padapter, REG_RXDMA_AGG_PG_TH+1, valueDMATimeout);
939 rtw_write8(padapter, REG_RXDMA_AGG_PG_TH, valueDMAPageCount);
940 #endif
941 }
942
sdio_AggSettingRxUpdate(PADAPTER padapter)943 void sdio_AggSettingRxUpdate(PADAPTER padapter)
944 {
945 #if 1
946 //HAL_DATA_TYPE *pHalData;
947 u8 valueDMA;
948
949
950 //pHalData = GET_HAL_DATA(padapter);
951
952 valueDMA = rtw_read8(padapter, REG_TRXDMA_CTRL);
953 valueDMA |= RXDMA_AGG_EN;
954 rtw_write8(padapter, REG_TRXDMA_CTRL, valueDMA);
955
956 #if 0
957 switch (RX_PAGE_SIZE_REG_VALUE)
958 {
959 case PBP_64:
960 pHalData->HwRxPageSize = 64;
961 break;
962 case PBP_128:
963 pHalData->HwRxPageSize = 128;
964 break;
965 case PBP_256:
966 pHalData->HwRxPageSize = 256;
967 break;
968 case PBP_512:
969 pHalData->HwRxPageSize = 512;
970 break;
971 case PBP_1024:
972 pHalData->HwRxPageSize = 1024;
973 break;
974 default:
975 RT_TRACE(_module_hci_hal_init_c_, _drv_err_,
976 ("%s: RX_PAGE_SIZE_REG_VALUE definition is incorrect!\n", __FUNCTION__));
977 break;
978 }
979 #endif
980 #endif
981 }
982
_initSdioAggregationSetting(PADAPTER padapter)983 void _initSdioAggregationSetting(PADAPTER padapter)
984 {
985 #ifdef CONFIG_SDIO_AGG_ENABLE
986 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
987
988 // Tx aggregation setting
989 //sdio_AggSettingTxUpdate(padapter);
990
991 // Rx aggregation setting
992 HalRxAggr8188ESdio(padapter);
993 sdio_AggSettingRxUpdate(padapter);
994 #else
995 DBG_871X("%s SDIO Aggregation default off\n", __func__);
996 #endif
997
998 }
999
1000
_InitOperationMode(PADAPTER padapter)1001 void _InitOperationMode(PADAPTER padapter)
1002 {
1003 PHAL_DATA_TYPE pHalData;
1004 struct mlme_ext_priv *pmlmeext;
1005 u8 regBwOpMode = 0;
1006 u32 regRATR = 0, regRRSR = 0;
1007 u8 MinSpaceCfg = 0;
1008
1009
1010 pHalData = GET_HAL_DATA(padapter);
1011 pmlmeext = &padapter->mlmeextpriv;
1012
1013 //1 This part need to modified according to the rate set we filtered!!
1014 //
1015 // Set RRSR, RATR, and REG_BWOPMODE registers
1016 //
1017 switch(pmlmeext->cur_wireless_mode)
1018 {
1019 case WIRELESS_MODE_B:
1020 regBwOpMode = BW_OPMODE_20MHZ;
1021 regRATR = RATE_ALL_CCK;
1022 regRRSR = RATE_ALL_CCK;
1023 break;
1024 case WIRELESS_MODE_A:
1025 // RT_ASSERT(FALSE,("Error wireless a mode\n"));
1026 #if 0
1027 regBwOpMode = BW_OPMODE_5G |BW_OPMODE_20MHZ;
1028 regRATR = RATE_ALL_OFDM_AG;
1029 regRRSR = RATE_ALL_OFDM_AG;
1030 #endif
1031 break;
1032 case WIRELESS_MODE_G:
1033 regBwOpMode = BW_OPMODE_20MHZ;
1034 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
1035 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
1036 break;
1037 case WIRELESS_MODE_AUTO:
1038 #if 0
1039 if (padapter->bInHctTest)
1040 {
1041 regBwOpMode = BW_OPMODE_20MHZ;
1042 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
1043 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
1044 }
1045 else
1046 #endif
1047 {
1048 regBwOpMode = BW_OPMODE_20MHZ;
1049 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
1050 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
1051 }
1052 break;
1053 case WIRELESS_MODE_N_24G:
1054 // It support CCK rate by default.
1055 // CCK rate will be filtered out only when associated AP does not support it.
1056 regBwOpMode = BW_OPMODE_20MHZ;
1057 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
1058 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
1059 break;
1060 case WIRELESS_MODE_N_5G:
1061 // RT_ASSERT(FALSE,("Error wireless mode"));
1062 #if 0
1063 regBwOpMode = BW_OPMODE_5G;
1064 regRATR = RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
1065 regRRSR = RATE_ALL_OFDM_AG;
1066 #endif
1067 break;
1068
1069 default: //for MacOSX compiler warning.
1070 break;
1071 }
1072
1073 rtw_write8(padapter, REG_BWOPMODE, regBwOpMode);
1074
1075 }
1076
1077
_InitBeaconParameters(PADAPTER padapter)1078 void _InitBeaconParameters(PADAPTER padapter)
1079 {
1080 PHAL_DATA_TYPE pHalData;
1081
1082
1083 pHalData = GET_HAL_DATA(padapter);
1084
1085 rtw_write16(padapter, REG_BCN_CTRL, 0x1010);
1086
1087 /* setup time:128 us */
1088 rtw_write8(padapter, REG_TBTT_PROHIBIT, 0x04);
1089
1090 /*TBTT hold time :4ms */
1091 rtw_write16(padapter, REG_TBTT_PROHIBIT + 1,
1092 (rtw_read16(padapter, REG_TBTT_PROHIBIT + 1) & (~0xfff)) | (TBTT_PROBIHIT_HOLD_TIME));
1093
1094 rtw_write8(padapter, REG_DRVERLYINT, DRIVER_EARLY_INT_TIME_8188E);//ms
1095 rtw_write8(padapter, REG_BCNDMATIM, BCN_DMA_ATIME_INT_TIME_8188E);
1096
1097 // Suggested by designer timchen. Change beacon AIFS to the largest number
1098 // beacause test chip does not contension before sending beacon. by tynli. 2009.11.03
1099 rtw_write16(padapter, REG_BCNTCFG, 0x660F);
1100
1101
1102 pHalData->RegBcnCtrlVal = rtw_read8(padapter, REG_BCN_CTRL);
1103 pHalData->RegTxPause = rtw_read8(padapter, REG_TXPAUSE);
1104 pHalData->RegFwHwTxQCtrl = rtw_read8(padapter, REG_FWHW_TXQ_CTRL+2);
1105 pHalData->RegCR_1 = rtw_read8(padapter, REG_CR+1);
1106
1107 }
1108
_InitBeaconMaxError(PADAPTER padapter,BOOLEAN InfraMode)1109 void _InitBeaconMaxError(PADAPTER padapter, BOOLEAN InfraMode)
1110 {
1111 #ifdef CONFIG_ADHOC_WORKAROUND_SETTING
1112 rtw_write8(padapter, REG_BCN_MAX_ERR, 0xFF);
1113 #endif
1114 }
1115
_InitInterrupt(PADAPTER padapter)1116 void _InitInterrupt(PADAPTER padapter)
1117 {
1118
1119 //HISR write one to clear
1120 rtw_write32(padapter, REG_HISR_88E, 0xFFFFFFFF);
1121
1122 // HIMR - turn all off
1123 rtw_write32(padapter, REG_HIMR_88E, 0);
1124
1125 //
1126 // Initialize and enable SDIO Host Interrupt.
1127 //
1128 InitInterrupt8188ESdio(padapter);
1129
1130
1131 //
1132 // Initialize and enable system Host Interrupt.
1133 //
1134 //InitSysInterrupt8188ESdio(Adapter);//TODO:
1135
1136 //
1137 // Enable SDIO Host Interrupt.
1138 //
1139 //EnableInterrupt8188ESdio(padapter);//Move to sd_intf_start()/stop
1140
1141 }
1142
_InitRDGSetting(PADAPTER padapter)1143 void _InitRDGSetting(PADAPTER padapter)
1144 {
1145 rtw_write8(padapter, REG_RD_CTRL, 0xFF);
1146 rtw_write16(padapter, REG_RD_NAV_NXT, 0x200);
1147 rtw_write8(padapter, REG_RD_RESP_PKT_TH, 0x05);
1148 }
1149
1150
_InitRxSetting(PADAPTER padapter)1151 static void _InitRxSetting(PADAPTER padapter)
1152 {
1153 rtw_write32(padapter, REG_MACID, 0x87654321);
1154 rtw_write32(padapter, 0x0700, 0x87654321);
1155 }
1156
1157
_InitRFType(PADAPTER padapter)1158 static void _InitRFType(PADAPTER padapter)
1159 {
1160 struct registry_priv *pregpriv = &padapter->registrypriv;
1161 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
1162
1163 #if DISABLE_BB_RF
1164 pHalData->rf_chip = RF_PSEUDO_11N;
1165 return;
1166 #endif
1167 pHalData->rf_chip = RF_6052;
1168
1169 MSG_8192C("Set RF Chip ID to RF_6052 and RF type to %d.\n", pHalData->rf_type);
1170 }
1171
1172 // Set CCK and OFDM Block "ON"
_BBTurnOnBlock(PADAPTER padapter)1173 static void _BBTurnOnBlock(PADAPTER padapter)
1174 {
1175 #if (DISABLE_BB_RF)
1176 return;
1177 #endif
1178
1179 PHY_SetBBReg(padapter, rFPGA0_RFMOD, bCCKEn, 0x1);
1180 PHY_SetBBReg(padapter, rFPGA0_RFMOD, bOFDMEn, 0x1);
1181 }
1182
1183 #if 0
1184 static void _InitAntenna_Selection(PADAPTER padapter)
1185 {
1186 rtw_write8(padapter, REG_LEDCFG2, 0x82);
1187 }
1188 #endif
1189
_InitPABias(PADAPTER padapter)1190 static void _InitPABias(PADAPTER padapter)
1191 {
1192 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
1193 u8 pa_setting;
1194
1195 //FIXED PA current issue
1196 //efuse_one_byte_read(padapter, 0x1FA, &pa_setting);
1197 pa_setting = EFUSE_Read1Byte(padapter, 0x1FA);
1198
1199 //RT_TRACE(COMP_INIT, DBG_LOUD, ("_InitPABias 0x1FA 0x%x \n",pa_setting));
1200
1201 if(!(pa_setting & BIT0))
1202 {
1203 PHY_SetRFReg(padapter, RF_PATH_A, 0x15, 0x0FFFFF, 0x0F406);
1204 PHY_SetRFReg(padapter, RF_PATH_A, 0x15, 0x0FFFFF, 0x4F406);
1205 PHY_SetRFReg(padapter, RF_PATH_A, 0x15, 0x0FFFFF, 0x8F406);
1206 PHY_SetRFReg(padapter, RF_PATH_A, 0x15, 0x0FFFFF, 0xCF406);
1207 //RT_TRACE(COMP_INIT, DBG_LOUD, ("PA BIAS path A\n"));
1208 }
1209 if(!(pa_setting & BIT4))
1210 {
1211 pa_setting = rtw_read8(padapter, 0x16);
1212 pa_setting &= 0x0F;
1213 rtw_write8(padapter, 0x16, pa_setting | 0x80);
1214 rtw_write8(padapter, 0x16, pa_setting | 0x90);
1215 }
1216 }
1217
1218 #if 0
1219 VOID
1220 _InitRDGSetting_8188E(
1221 IN PADAPTER Adapter
1222 )
1223 {
1224 PlatformEFIOWrite1Byte(Adapter,REG_RD_CTRL,0xFF);
1225 PlatformEFIOWrite2Byte(Adapter, REG_RD_NAV_NXT, 0x200);
1226 PlatformEFIOWrite1Byte(Adapter,REG_RD_RESP_PKT_TH,0x05);
1227 }
1228 #endif
1229
rtl8188es_hal_init(PADAPTER padapter)1230 static u32 rtl8188es_hal_init(PADAPTER padapter)
1231 {
1232 s32 ret;
1233 u8 txpktbuf_bndy;
1234 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
1235 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
1236 struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);
1237 struct registry_priv *pregistrypriv = &padapter->registrypriv;
1238 rt_rf_power_state eRfPowerStateToSet;
1239 u8 value8;
1240 u8 cpwm_orig, cpwm_now, rpwm;
1241 u16 value16;
1242
1243 u32 init_start_time = rtw_get_current_time();
1244 u32 start_time;
1245
1246 #ifdef DBG_HAL_INIT_PROFILING
1247 enum HAL_INIT_STAGES {
1248 HAL_INIT_STAGES_BEGIN = 0,
1249 HAL_INIT_STAGES_INIT_PW_ON,
1250 HAL_INIT_STAGES_MISC01,
1251 HAL_INIT_STAGES_DOWNLOAD_FW,
1252 HAL_INIT_STAGES_MAC,
1253 HAL_INIT_STAGES_BB,
1254 HAL_INIT_STAGES_RF,
1255 HAL_INIT_STAGES_EFUSE_PATCH,
1256 HAL_INIT_STAGES_INIT_LLTT,
1257
1258 HAL_INIT_STAGES_MISC02,
1259 HAL_INIT_STAGES_TURN_ON_BLOCK,
1260 HAL_INIT_STAGES_INIT_SECURITY,
1261 HAL_INIT_STAGES_MISC11,
1262 HAL_INIT_STAGES_INIT_HAL_DM,
1263 //HAL_INIT_STAGES_RF_PS,
1264 HAL_INIT_STAGES_IQK,
1265 HAL_INIT_STAGES_PW_TRACK,
1266 HAL_INIT_STAGES_LCK,
1267 //HAL_INIT_STAGES_MISC21,
1268 HAL_INIT_STAGES_INIT_PABIAS,
1269 //HAL_INIT_STAGES_ANTENNA_SEL,
1270 HAL_INIT_STAGES_MISC31,
1271 HAL_INIT_STAGES_END,
1272 HAL_INIT_STAGES_NUM
1273 };
1274
1275 char * hal_init_stages_str[] = {
1276 "HAL_INIT_STAGES_BEGIN",
1277 "HAL_INIT_STAGES_INIT_PW_ON",
1278 "HAL_INIT_STAGES_MISC01",
1279 "HAL_INIT_STAGES_DOWNLOAD_FW",
1280 "HAL_INIT_STAGES_MAC",
1281 "HAL_INIT_STAGES_BB",
1282 "HAL_INIT_STAGES_RF",
1283 "HAL_INIT_STAGES_EFUSE_PATCH",
1284 "HAL_INIT_STAGES_INIT_LLTT",
1285 "HAL_INIT_STAGES_MISC02",
1286 "HAL_INIT_STAGES_TURN_ON_BLOCK",
1287 "HAL_INIT_STAGES_INIT_SECURITY",
1288 "HAL_INIT_STAGES_MISC11",
1289 "HAL_INIT_STAGES_INIT_HAL_DM",
1290 //"HAL_INIT_STAGES_RF_PS",
1291 "HAL_INIT_STAGES_IQK",
1292 "HAL_INIT_STAGES_PW_TRACK",
1293 "HAL_INIT_STAGES_LCK",
1294 //"HAL_INIT_STAGES_MISC21",
1295 "HAL_INIT_STAGES_INIT_PABIAS"
1296 //"HAL_INIT_STAGES_ANTENNA_SEL",
1297 "HAL_INIT_STAGES_MISC31",
1298 "HAL_INIT_STAGES_END",
1299 };
1300
1301
1302 int hal_init_profiling_i;
1303 u32 hal_init_stages_timestamp[HAL_INIT_STAGES_NUM]; //used to record the time of each stage's starting point
1304
1305 for(hal_init_profiling_i=0;hal_init_profiling_i<HAL_INIT_STAGES_NUM;hal_init_profiling_i++)
1306 hal_init_stages_timestamp[hal_init_profiling_i]=0;
1307
1308 #define HAL_INIT_PROFILE_TAG(stage) hal_init_stages_timestamp[(stage)]=rtw_get_current_time();
1309 #else
1310 #define HAL_INIT_PROFILE_TAG(stage) do {} while(0)
1311 #endif //DBG_HAL_INIT_PROFILING
1312
1313 DBG_8192C("+rtl8188es_hal_init\n");
1314
1315 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BEGIN);
1316 // Disable Interrupt first.
1317 // rtw_hal_disable_interrupt(padapter);
1318 // DisableInterrupt8188ESdio(padapter);
1319
1320
1321 if(rtw_read8(padapter, REG_MCUFWDL) == 0xc6) {
1322 #ifdef CONFIG_LPS_LCLK
1323 _enter_pwrlock(&pwrctrlpriv->lock);
1324 cpwm_orig = 0, rpwm = 0;
1325 rtw_hal_get_hwreg(padapter, HW_VAR_CPWM, &cpwm_orig);
1326
1327 value8 = rtw_read8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1);
1328 value8 &= 0x80;
1329 value8 ^= BIT7;
1330 rpwm = PS_STATE_S4 | PS_ACK | value8;
1331 rtw_hal_set_hwreg(padapter, HW_VAR_SET_RPWM, (u8 *)(&rpwm));
1332
1333 start_time = rtw_get_current_time();
1334 // polling cpwm
1335 do {
1336 rtw_mdelay_os(1);
1337
1338 rtw_hal_get_hwreg(padapter, HW_VAR_CPWM, &cpwm_now);
1339 if ((cpwm_orig ^ cpwm_now) & 0x80)
1340 {
1341 DBG_871X("%s:Leave LPS done before PowerOn!!\n",
1342 __func__);
1343 break;
1344 }
1345
1346 if (rtw_get_passing_time_ms(start_time) > LPS_RPWM_WAIT_MS)
1347 {
1348 if (rtw_read8(padapter, REG_CR) != 0xEA) {
1349 DBG_871X("%s: polling cpwm timeout! but 0x100 != 0xEA!!\n",
1350 __func__);
1351 } else {
1352 DBG_871X("%s, polling cpwm timeout and 0x100 = 0xEA!!\n",
1353 __func__);
1354 }
1355 break;
1356 }
1357 } while (1);
1358 _exit_pwrlock(&pwrctrlpriv->lock);
1359
1360 hal_poweroff_8188es(padapter);
1361 #endif
1362 } else {
1363 DBG_871X("FW does not exit before power on!!\n");
1364 }
1365
1366 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_PW_ON);
1367 ret = _InitPowerOn_8188ES(padapter);
1368 if (_FAIL == ret) {
1369 RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("Failed to init Power On!\n"));
1370 goto exit;
1371 }
1372
1373 ret = PowerOnCheck(padapter);
1374 if (_FAIL == ret ) {
1375 DBG_871X("Power on Fail! do it again\n");
1376 ret = _InitPowerOn_8188ES(padapter);
1377 if (_FAIL == ret) {
1378 DBG_871X("Failed to init Power On!\n");
1379 goto exit;
1380 }
1381 }
1382 DBG_871X("Power on ok!\n");
1383
1384
1385 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC01);
1386 if (!pregistrypriv->wifi_spec) {
1387 txpktbuf_bndy = TX_PAGE_BOUNDARY_88E(padapter);
1388 } else {
1389 // for WMM
1390 txpktbuf_bndy = WMM_NORMAL_TX_PAGE_BOUNDARY_88E(padapter);
1391 }
1392 _InitQueueReservedPage(padapter);
1393 _InitQueuePriority(padapter);
1394 _InitPageBoundary(padapter);
1395 _InitTransferPageSize(padapter);
1396
1397 #ifdef CONFIG_IOL_IOREG_CFG
1398 _InitTxBufferBoundary(padapter, 0);
1399 #endif
1400 //
1401 // Configure SDIO TxRx Control to enable Rx DMA timer masking.
1402 // 2010.02.24.
1403 //
1404 value8 = SdioLocalCmd52Read1Byte(padapter, SDIO_REG_TX_CTRL);
1405 SdioLocalCmd52Write1Byte(padapter, SDIO_REG_TX_CTRL, 0x02);
1406
1407 rtw_write8(padapter, SDIO_LOCAL_BASE|SDIO_REG_HRPWM1, 0);
1408
1409 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_DOWNLOAD_FW);
1410 #if (MP_DRIVER == 1)
1411 if (padapter->registrypriv.mp_mode == 1)
1412 {
1413 _InitRxSetting(padapter);
1414 }
1415 #endif //MP_DRIVER == 1
1416 {
1417 #if 0
1418 padapter->bFWReady = _FALSE; //because no fw for test chip
1419 pHalData->fw_ractrl = _FALSE;
1420 #else
1421
1422 ret = rtl8188e_FirmwareDownload(padapter, _FALSE);
1423
1424 if (ret != _SUCCESS) {
1425 DBG_871X("%s: Download Firmware failed!!\n", __FUNCTION__);
1426 padapter->bFWReady = _FALSE;
1427 pHalData->fw_ractrl = _FALSE;
1428 goto exit;
1429 } else {
1430 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("Initializepadapter8192CSdio(): Download Firmware Success!!\n"));
1431 padapter->bFWReady = _TRUE;
1432 #ifdef CONFIG_SFW_SUPPORTED
1433 pHalData->fw_ractrl = IS_VENDOR_8188E_I_CUT_SERIES(padapter)?_TRUE:_FALSE;
1434 #else
1435 pHalData->fw_ractrl = _FALSE;
1436 #endif
1437 }
1438 #endif
1439 }
1440
1441 rtl8188e_InitializeFirmwareVars(padapter);
1442
1443 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MAC);
1444 #if (HAL_MAC_ENABLE == 1)
1445 ret = PHY_MACConfig8188E(padapter);
1446 if(ret != _SUCCESS){
1447 // RT_TRACE(COMP_INIT, DBG_LOUD, ("Initializepadapter8192CSdio(): Fail to configure MAC!!\n"));
1448 goto exit;
1449 }
1450 #endif
1451
1452 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BB);
1453 //
1454 //d. Initialize BB related configurations.
1455 //
1456 #if (HAL_BB_ENABLE == 1)
1457 ret = PHY_BBConfig8188E(padapter);
1458 if(ret != _SUCCESS){
1459 // RT_TRACE(COMP_INIT, DBG_SERIOUS, ("Initializepadapter8192CSdio(): Fail to configure BB!!\n"));
1460 goto exit;
1461 }
1462 #endif
1463
1464
1465 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_RF);
1466
1467 #if (HAL_RF_ENABLE == 1)
1468 ret = PHY_RFConfig8188E(padapter);
1469
1470 if(ret != _SUCCESS){
1471 // RT_TRACE(COMP_INIT, DBG_LOUD, ("Initializepadapter8192CSdio(): Fail to configure RF!!\n"));
1472 goto exit;
1473 }
1474 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_EFUSE_PATCH);
1475 #if defined(CONFIG_IOL_EFUSE_PATCH)
1476 ret = rtl8188e_iol_efuse_patch(padapter);
1477 if(ret != _SUCCESS){
1478 DBG_871X("%s rtl8188e_iol_efuse_patch failed \n",__FUNCTION__);
1479 goto exit;
1480 }
1481 #endif
1482 _InitTxBufferBoundary(padapter, txpktbuf_bndy);
1483 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_LLTT);
1484 ret = InitLLTTable(padapter, txpktbuf_bndy);
1485 if (_SUCCESS != ret) {
1486 RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("Failed to init LLT Table!\n"));
1487 goto exit;
1488 }
1489
1490 //Enable TX Report & Tx Report Timer
1491 value8 = rtw_read8(padapter, REG_TX_RPT_CTRL);
1492 rtw_write8(padapter, REG_TX_RPT_CTRL, (value8|BIT1|BIT0));
1493
1494 #if (RATE_ADAPTIVE_SUPPORT==1)
1495 if(!pHalData->fw_ractrl ){
1496 //Set MAX RPT MACID
1497 rtw_write8(padapter, REG_TX_RPT_CTRL+1, 2);//FOR sta mode ,0: bc/mc ,1:AP
1498 //Tx RPT Timer. Unit: 32us
1499 rtw_write16(padapter, REG_TX_RPT_TIME, 0xCdf0);
1500 }
1501 else
1502 #endif
1503 {
1504 //disable tx rpt
1505 rtw_write8(padapter, REG_TX_RPT_CTRL+1, 0);//FOR sta mode ,0: bc/mc ,1:AP
1506 }
1507
1508 #if 0
1509 if(pHTInfo->bRDGEnable){
1510 _InitRDGSetting_8188E(Adapter);
1511 }
1512 #endif
1513
1514 #ifdef CONFIG_TX_EARLY_MODE
1515 if( pHalData->bEarlyModeEnable)
1516 {
1517 RT_TRACE(_module_hci_hal_init_c_, _drv_info_,("EarlyMode Enabled!!!\n"));
1518
1519 value8 = rtw_read8(padapter, REG_EARLY_MODE_CONTROL);
1520 #if RTL8188E_EARLY_MODE_PKT_NUM_10 == 1
1521 value8 = value8|0x1f;
1522 #else
1523 value8 = value8|0xf;
1524 #endif
1525 rtw_write8(padapter, REG_EARLY_MODE_CONTROL, value8);
1526
1527 rtw_write8(padapter, REG_EARLY_MODE_CONTROL+3, 0x80);
1528
1529 value8 = rtw_read8(padapter, REG_TCR+1);
1530 value8 = value8|0x40;
1531 rtw_write8(padapter,REG_TCR+1, value8);
1532 }
1533 else
1534 #endif
1535 {
1536 rtw_write8(padapter, REG_EARLY_MODE_CONTROL, 0);
1537 }
1538
1539
1540 #if(SIC_ENABLE == 1)
1541 SIC_Init(padapter);
1542 #endif
1543
1544
1545 if (pwrctrlpriv->reg_rfoff == _TRUE) {
1546 pwrctrlpriv->rf_pwrstate = rf_off;
1547 }
1548
1549 // 2010/08/09 MH We need to check if we need to turnon or off RF after detecting
1550 // HW GPIO pin. Before PHY_RFConfig8192C.
1551 HalDetectPwrDownMode88E(padapter);
1552
1553
1554 // Set RF type for BB/RF configuration
1555 _InitRFType(padapter);
1556
1557 // Save target channel
1558 // <Roger_Notes> Current Channel will be updated again later.
1559 pHalData->CurrentChannel = 1;
1560
1561
1562
1563 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC02);
1564 // Get Rx PHY status in order to report RSSI and others.
1565 _InitDriverInfoSize(padapter, 4);
1566 hal_init_macaddr(padapter);
1567 _InitNetworkType(padapter);
1568 _InitWMACSetting(padapter);
1569 _InitAdaptiveCtrl(padapter);
1570 _InitEDCA(padapter);
1571 _InitRateFallback(padapter);
1572 _InitRetryFunction(padapter);
1573 _initSdioAggregationSetting(padapter);
1574 _InitOperationMode(padapter);
1575 _InitBeaconParameters(padapter);
1576 _InitBeaconMaxError(padapter, _TRUE);
1577 _InitInterrupt(padapter);
1578
1579 // Enable MACTXEN/MACRXEN block
1580 value16 = rtw_read16(padapter, REG_CR);
1581 value16 |= (MACTXEN | MACRXEN);
1582 rtw_write8(padapter, REG_CR, value16);
1583
1584 rtw_write32(padapter,REG_MACID_NO_LINK_0,0xFFFFFFFF);
1585 rtw_write32(padapter,REG_MACID_NO_LINK_1,0xFFFFFFFF);
1586
1587 #if defined(CONFIG_CONCURRENT_MODE) || defined(CONFIG_TX_MCAST2UNI)
1588
1589 #ifdef CONFIG_CHECK_AC_LIFETIME
1590 // Enable lifetime check for the four ACs
1591 rtw_write8(padapter, REG_LIFETIME_CTRL, 0x0F);
1592 #endif // CONFIG_CHECK_AC_LIFETIME
1593
1594 #ifdef CONFIG_TX_MCAST2UNI
1595 rtw_write16(padapter, REG_PKT_VO_VI_LIFE_TIME, 0x0400); // unit: 256us. 256ms
1596 rtw_write16(padapter, REG_PKT_BE_BK_LIFE_TIME, 0x0400); // unit: 256us. 256ms
1597 #else // CONFIG_TX_MCAST2UNI
1598 rtw_write16(padapter, REG_PKT_VO_VI_LIFE_TIME, 0x3000); // unit: 256us. 3s
1599 rtw_write16(padapter, REG_PKT_BE_BK_LIFE_TIME, 0x3000); // unit: 256us. 3s
1600 #endif // CONFIG_TX_MCAST2UNI
1601 #endif // CONFIG_CONCURRENT_MODE || CONFIG_TX_MCAST2UNI
1602
1603
1604
1605
1606 #endif //HAL_RF_ENABLE == 1
1607
1608
1609 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_TURN_ON_BLOCK);
1610 _BBTurnOnBlock(padapter);
1611
1612 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_SECURITY);
1613 #if 1
1614 invalidate_cam_all(padapter);
1615 #else
1616 CamResetAllEntry(padapter);
1617 padapter->HalFunc.EnableHWSecCfgHandler(padapter);
1618 #endif
1619
1620 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC11);
1621 // 2010/12/17 MH We need to set TX power according to EFUSE content at first.
1622 PHY_SetTxPowerLevel8188E(padapter, pHalData->CurrentChannel);
1623 // Record original value for template. This is arough data, we can only use the data
1624 // for power adjust. The value can not be adjustde according to different power!!!
1625 // pHalData->OriginalCckTxPwrIdx = pHalData->CurrentCckTxPwrIdx;
1626 // pHalData->OriginalOfdm24GTxPwrIdx = pHalData->CurrentOfdm24GTxPwrIdx;
1627
1628 // Move by Neo for USB SS to below setp
1629 //_RfPowerSave(padapter);
1630
1631 //
1632 // Disable BAR, suggested by Scott
1633 // 2010.04.09 add by hpfan
1634 //
1635 rtw_write32(padapter, REG_BAR_MODE_CTRL, 0x0201ffff);
1636
1637 // HW SEQ CTRL
1638 // set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM.
1639 rtw_write8(padapter, REG_HWSEQ_CTRL, 0xFF);
1640
1641
1642 #ifdef RTL8188ES_MAC_LOOPBACK
1643 value8 = rtw_read8(padapter, REG_SYS_FUNC_EN);
1644 value8 &= ~(FEN_BBRSTB|FEN_BB_GLB_RSTn);
1645 rtw_write8(padapter, REG_SYS_FUNC_EN, value8);//disable BB, CCK/OFDM
1646
1647 rtw_write8(padapter, REG_RD_CTRL, 0x0F);
1648 rtw_write8(padapter, REG_RD_CTRL+1, 0xCF);
1649 //rtw_write8(padapter, REG_TXPKTBUF_WMAC_LBK_BF_HD, 0x80);//to check _InitPageBoundary()
1650 rtw_write32(padapter, REG_CR, 0x0b0202ff);//0x100[28:24]=0x01011, enable mac loopback, no HW Security Eng.
1651 #endif
1652
1653
1654 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_HAL_DM);
1655 // InitHalDm(padapter);
1656 rtl8188e_InitHalDm(padapter);
1657
1658
1659 #if (MP_DRIVER == 1)
1660 if (padapter->registrypriv.mp_mode == 1)
1661 {
1662 padapter->mppriv.channel = pHalData->CurrentChannel;
1663 MPT_InitializeAdapter(padapter, padapter->mppriv.channel);
1664 }
1665 else
1666 #endif //(MP_DRIVER == 1)
1667 {
1668 //
1669 // 2010/08/11 MH Merge from 8192SE for Minicard init. We need to confirm current radio status
1670 // and then decide to enable RF or not.!!!??? For Selective suspend mode. We may not
1671 // call init_adapter. May cause some problem??
1672 //
1673 // Fix the bug that Hw/Sw radio off before S3/S4, the RF off action will not be executed
1674 // in MgntActSet_RF_State() after wake up, because the value of pHalData->eRFPowerState
1675 // is the same as eRfOff, we should change it to eRfOn after we config RF parameters.
1676 // Added by tynli. 2010.03.30.
1677 pwrctrlpriv->rf_pwrstate = rf_on;
1678 RT_CLEAR_PS_LEVEL(pwrctrlpriv, RT_RF_OFF_LEVL_HALT_NIC);
1679
1680 // 20100326 Joseph: Copy from GPIOChangeRFWorkItemCallBack() function to check HW radio on/off.
1681 // 20100329 Joseph: Revise and integrate the HW/SW radio off code in initialization.
1682 // pHalData->bHwRadioOff = _FALSE;
1683 pwrctrlpriv->b_hw_radio_off = _FALSE;
1684 eRfPowerStateToSet = rf_on;
1685
1686 // 2010/-8/09 MH For power down module, we need to enable register block contrl reg at 0x1c.
1687 // Then enable power down control bit of register 0x04 BIT4 and BIT15 as 1.
1688 if(pHalData->pwrdown && eRfPowerStateToSet == rf_off)
1689 {
1690 // Enable register area 0x0-0xc.
1691 rtw_write8(padapter, REG_RSV_CTRL, 0x0);
1692
1693 //
1694 // <Roger_Notes> We should configure HW PDn source for WiFi ONLY, and then
1695 // our HW will be set in power-down mode if PDn source from all functions are configured.
1696 // 2010.10.06.
1697 //
1698
1699 rtw_write16(padapter, REG_APS_FSMCO, 0x8812);
1700
1701 }
1702 //DrvIFIndicateCurrentPhyStatus(padapter); // 2010/08/17 MH Disable to prevent BSOD.
1703
1704 // 2010/08/26 MH Merge from 8192CE.
1705 if(pwrctrlpriv->rf_pwrstate == rf_on)
1706 {
1707
1708 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_IQK);
1709 if(pHalData->bIQKInitialized){
1710 // PHY_IQCalibrate(padapter, _TRUE);
1711 PHY_IQCalibrate_8188E(padapter,_TRUE);
1712 }
1713 else
1714 {
1715 // PHY_IQCalibrate(padapter, _FALSE);
1716 PHY_IQCalibrate_8188E(padapter,_FALSE);
1717 pHalData->bIQKInitialized = _TRUE;
1718 }
1719
1720 // dm_CheckTXPowerTracking(padapter);
1721 // PHY_LCCalibrate(padapter);
1722
1723 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_PW_TRACK);
1724 ODM_TXPowerTrackingCheck(&pHalData->odmpriv );
1725
1726 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_LCK);
1727 PHY_LCCalibrate_8188E(&pHalData->odmpriv );
1728
1729
1730 }
1731 }
1732
1733 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_PABIAS);
1734 //if(pHalData->eRFPowerState == eRfOn)
1735 {
1736 _InitPABias(padapter);
1737 }
1738
1739 // Init BT hw config.
1740 // HALBT_InitHwConfig(padapter);
1741
1742
1743 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC31);
1744 // 2010/05/20 MH We need to init timer after update setting. Otherwise, we can not get correct inf setting.
1745 // 2010/05/18 MH For SE series only now. Init GPIO detect time
1746 #if 0
1747 if(pDevice->RegUsbSS)
1748 {
1749 RT_TRACE(COMP_INIT, DBG_LOUD, (" call GpioDetectTimerStart\n"));
1750 GpioDetectTimerStart(padapter); // Disable temporarily
1751 }
1752 #endif
1753
1754 // 2010/08/23 MH According to Alfred's suggestion, we need to to prevent HW enter
1755 // suspend mode automatically.
1756 //HwSuspendModeEnable92Cu(padapter, FALSE);
1757
1758 // 2010/12/17 MH For TX power level OID modification from UI.
1759 // padapter->HalFunc.GetTxPowerLevelHandler( padapter, &pHalData->DefaultTxPwrDbm );
1760 //DbgPrint("pHalData->DefaultTxPwrDbm = %d\n", pHalData->DefaultTxPwrDbm);
1761
1762 // if(pHalData->SwBeaconType < HAL92CSDIO_DEFAULT_BEACON_TYPE) // The lowest Beacon Type that HW can support
1763 // pHalData->SwBeaconType = HAL92CSDIO_DEFAULT_BEACON_TYPE;
1764
1765 //
1766 // Update current Tx FIFO page status.
1767 //
1768 HalQueryTxBufferStatus8189ESdio(padapter);
1769 HalQueryTxOQTBufferStatus8189ESdio(padapter);
1770 pHalData->SdioTxOQTMaxFreeSpace = pHalData->SdioTxOQTFreeSpace;
1771
1772
1773 if(pregistrypriv->wifi_spec) {
1774 rtw_write16(padapter,REG_FAST_EDCA_CTRL ,0);
1775 rtw_write8(padapter,REG_NAV_UPPER ,0x0);
1776 }
1777
1778 if(IS_HARDWARE_TYPE_8188ES(padapter))
1779 {
1780 value8= rtw_read8(padapter, 0x4d3);
1781 rtw_write8(padapter, 0x4d3, (value8|0x1));
1782 }
1783
1784 //pHalData->PreRpwmVal = PlatformEFSdioLocalCmd52Read1Byte(Adapter, SDIO_REG_HRPWM1)&0x80;
1785
1786 if(!pHalData->fw_ractrl ){
1787 // enable Tx report.
1788 rtw_write8(padapter, REG_FWHW_TXQ_CTRL+1, 0x0F);
1789 //tynli_test_tx_report.
1790 rtw_write16(padapter, REG_TX_RPT_TIME, 0x3DF0);
1791 }
1792 /*
1793 // Suggested by SD1 pisa. Added by tynli. 2011.10.21.
1794 PlatformEFIOWrite1Byte(Adapter, REG_EARLY_MODE_CONTROL+3, 0x01);
1795
1796 */
1797 //RT_TRACE(COMP_INIT, DBG_TRACE, ("InitializeAdapter8188EUsb() <====\n"));
1798
1799
1800 //enable tx DMA to drop the redundate data of packet
1801 rtw_write16(padapter,REG_TXDMA_OFFSET_CHK, (rtw_read16(padapter,REG_TXDMA_OFFSET_CHK) | DROP_DATA_EN));
1802
1803 //#debug print for checking compile flags
1804 //DBG_8192C("RTL8188E_FPGA_TRUE_PHY_VERIFICATION=%d\n", RTL8188E_FPGA_TRUE_PHY_VERIFICATION);
1805 DBG_8192C("DISABLE_BB_RF=%d\n", DISABLE_BB_RF);
1806 DBG_8192C("IS_HARDWARE_TYPE_8188ES=%d\n", IS_HARDWARE_TYPE_8188ES(padapter));
1807 //#
1808
1809 #ifdef CONFIG_PLATFORM_SPRD
1810 // For Power Consumption, set all GPIO pin to ouput mode
1811 //0x44~0x47 (GPIO 0~7), Note:GPIO5 is enabled for controlling external 26MHz request
1812 rtw_write8(padapter, GPIO_IO_SEL, 0xFF);//Reg0x46, set to o/p mode
1813
1814 //0x42~0x43 (GPIO 8~11)
1815 value8 = rtw_read8(padapter, REG_GPIO_IO_SEL);
1816 rtw_write8(padapter, REG_GPIO_IO_SEL, (value8<<4)|value8);
1817 value8 = rtw_read8(padapter, REG_GPIO_IO_SEL+1);
1818 rtw_write8(padapter, REG_GPIO_IO_SEL+1, value8|0x0F);//Reg0x43
1819 #endif //CONFIG_PLATFORM_SPRD
1820
1821
1822 #ifdef CONFIG_XMIT_ACK
1823 //ack for xmit mgmt frames.
1824 rtw_write32(padapter, REG_FWHW_TXQ_CTRL, rtw_read32(padapter, REG_FWHW_TXQ_CTRL)|BIT(12));
1825 #endif //CONFIG_XMIT_ACK
1826
1827 if (padapter->registrypriv.wifi_spec == 1)
1828 ODM_SetBBReg(pDM_Odm,
1829 rOFDM0_ECCAThreshold, bMaskDWord, 0x00fe0301);
1830
1831 //RT_TRACE(COMP_INIT, DBG_LOUD, ("<---Initializepadapter8192CSdio()\n"));
1832 DBG_8192C("-rtl8188es_hal_init\n");
1833
1834 exit:
1835 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_END);
1836
1837 DBG_871X("%s in %dms\n", __FUNCTION__, rtw_get_passing_time_ms(init_start_time));
1838
1839 #ifdef DBG_HAL_INIT_PROFILING
1840 hal_init_stages_timestamp[HAL_INIT_STAGES_END]=rtw_get_current_time();
1841
1842 for(hal_init_profiling_i=0;hal_init_profiling_i<HAL_INIT_STAGES_NUM-1;hal_init_profiling_i++) {
1843 DBG_871X("DBG_HAL_INIT_PROFILING: %35s, %u, %5u, %5u\n"
1844 , hal_init_stages_str[hal_init_profiling_i]
1845 , hal_init_stages_timestamp[hal_init_profiling_i]
1846 , (hal_init_stages_timestamp[hal_init_profiling_i+1]-hal_init_stages_timestamp[hal_init_profiling_i])
1847 , rtw_get_time_interval_ms(hal_init_stages_timestamp[hal_init_profiling_i], hal_init_stages_timestamp[hal_init_profiling_i+1])
1848 );
1849 }
1850 #endif
1851
1852 return ret;
1853
1854 }
1855
1856
1857
rtl8188es_hal_deinit(PADAPTER padapter)1858 static u32 rtl8188es_hal_deinit(PADAPTER padapter)
1859 {
1860 DBG_871X("=>%s\n", __FUNCTION__);
1861
1862 if (rtw_is_hw_init_completed(padapter))
1863 hal_poweroff_8188es(padapter);
1864
1865 DBG_871X("<=%s\n", __FUNCTION__);
1866
1867 return _SUCCESS;
1868 }
1869
rtl8188es_init_default_value(PADAPTER padapter)1870 static void rtl8188es_init_default_value(PADAPTER padapter)
1871 {
1872 PHAL_DATA_TYPE pHalData;
1873 struct pwrctrl_priv *pwrctrlpriv;
1874 u8 i;
1875
1876 pHalData = GET_HAL_DATA(padapter);
1877 pwrctrlpriv = adapter_to_pwrctl(padapter);
1878
1879 rtl8188e_init_default_value(padapter);
1880
1881 //init default value
1882 pHalData->fw_ractrl = _FALSE;
1883 if(!pwrctrlpriv->bkeepfwalive)
1884 pHalData->LastHMEBoxNum = 0;
1885
1886 //init dm default value
1887 pHalData->bIQKInitialized = _FALSE;
1888 pHalData->odmpriv.RFCalibrateInfo.TM_Trigger = 0;//for IQK
1889 //pdmpriv->binitialized = _FALSE;
1890 // pdmpriv->prv_traffic_idx = 3;
1891 // pdmpriv->initialize = 0;
1892 pHalData->pwrGroupCnt = 0;
1893 pHalData->PGMaxGroup= 13;
1894 pHalData->odmpriv.RFCalibrateInfo.ThermalValue_HP_index = 0;
1895 for(i = 0; i < HP_THERMAL_NUM; i++)
1896 pHalData->odmpriv.RFCalibrateInfo.ThermalValue_HP[i] = 0;
1897
1898 // interface related variable
1899 pHalData->SdioRxFIFOCnt = 0;
1900 pHalData->EfuseHal.fakeEfuseBank = 0;
1901 pHalData->EfuseHal.fakeEfuseUsedBytes = 0;
1902 _rtw_memset(pHalData->EfuseHal.fakeEfuseContent, 0xFF, EFUSE_MAX_HW_SIZE);
1903 _rtw_memset(pHalData->EfuseHal.fakeEfuseInitMap, 0xFF, EFUSE_MAX_MAP_LEN);
1904 _rtw_memset(pHalData->EfuseHal.fakeEfuseModifiedMap, 0xFF, EFUSE_MAX_MAP_LEN);
1905
1906 }
1907
1908 //
1909 // Description:
1910 // We should set Efuse cell selection to WiFi cell in default.
1911 //
1912 // Assumption:
1913 // PASSIVE_LEVEL
1914 //
1915 // Added by Roger, 2010.11.23.
1916 //
_EfuseCellSel(IN PADAPTER padapter)1917 static void _EfuseCellSel(
1918 IN PADAPTER padapter
1919 )
1920 {
1921 //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
1922
1923 u32 value32;
1924
1925 //if(INCLUDE_MULTI_FUNC_BT(padapter))
1926 {
1927 value32 = rtw_read32(padapter, EFUSE_TEST);
1928 value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0);
1929 rtw_write32(padapter, EFUSE_TEST, value32);
1930 }
1931 }
1932
1933 static VOID
_ReadRFType(IN PADAPTER Adapter)1934 _ReadRFType(
1935 IN PADAPTER Adapter
1936 )
1937 {
1938 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
1939
1940 #if DISABLE_BB_RF
1941 pHalData->rf_chip = RF_PSEUDO_11N;
1942 #else
1943 pHalData->rf_chip = RF_6052;
1944 #endif
1945 }
1946
1947 static void
Hal_EfuseParsePIDVID_8188ES(IN PADAPTER pAdapter,IN u8 * hwinfo,IN BOOLEAN AutoLoadFail)1948 Hal_EfuseParsePIDVID_8188ES(
1949 IN PADAPTER pAdapter,
1950 IN u8* hwinfo,
1951 IN BOOLEAN AutoLoadFail
1952 )
1953 {
1954 // HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1955
1956 //
1957 // <Roger_Notes> The PID/VID info was parsed from CISTPL_MANFID Tuple in CIS area before.
1958 // VID is parsed from Manufacture code field and PID is parsed from Manufacture information field.
1959 // 2011.04.01.
1960 //
1961
1962 // RT_TRACE(COMP_INIT, DBG_LOUD, ("EEPROM VID = 0x%4x\n", pHalData->EEPROMVID));
1963 // RT_TRACE(COMP_INIT, DBG_LOUD, ("EEPROM PID = 0x%4x\n", pHalData->EEPROMPID));
1964 }
1965
1966 static VOID
readAdapterInfo_8188ES(IN PADAPTER padapter)1967 readAdapterInfo_8188ES(
1968 IN PADAPTER padapter
1969 )
1970 {
1971 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
1972
1973 /* parse the eeprom/efuse content */
1974 Hal_EfuseParseIDCode88E(padapter, pHalData->efuse_eeprom_data);
1975 Hal_EfuseParsePIDVID_8188ES(padapter, pHalData->efuse_eeprom_data, pHalData->bautoload_fail_flag);
1976 hal_config_macaddr(padapter, pHalData->bautoload_fail_flag);
1977 Hal_ReadPowerSavingMode88E(padapter, pHalData->efuse_eeprom_data, pHalData->bautoload_fail_flag);
1978 Hal_ReadTxPowerInfo88E(padapter, pHalData->efuse_eeprom_data, pHalData->bautoload_fail_flag);
1979 Hal_EfuseParseEEPROMVer88E(padapter, pHalData->efuse_eeprom_data, pHalData->bautoload_fail_flag);
1980 rtl8188e_EfuseParseChnlPlan(padapter, pHalData->efuse_eeprom_data, pHalData->bautoload_fail_flag);
1981 Hal_EfuseParseXtal_8188E(padapter, pHalData->efuse_eeprom_data, pHalData->bautoload_fail_flag);
1982 Hal_EfuseParseCustomerID88E(padapter, pHalData->efuse_eeprom_data, pHalData->bautoload_fail_flag);
1983 //Hal_ReadAntennaDiversity88E(padapter, pHalData->efuse_eeprom_data, pHalData->bautoload_fail_flag);
1984 Hal_EfuseParseBoardType88E(padapter, pHalData->efuse_eeprom_data, pHalData->bautoload_fail_flag);
1985 Hal_ReadThermalMeter_88E(padapter, pHalData->efuse_eeprom_data, pHalData->bautoload_fail_flag);
1986 //
1987 // The following part initialize some vars by PG info.
1988 //
1989 #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
1990 Hal_DetectWoWMode(padapter);
1991 #endif
1992 #ifdef CONFIG_RF_GAIN_OFFSET
1993 Hal_ReadRFGainOffset(padapter, pHalData->efuse_eeprom_data, pHalData->bautoload_fail_flag);
1994 #endif //CONFIG_RF_GAIN_OFFSET
1995 }
1996
_ReadPROMContent(IN PADAPTER padapter)1997 static void _ReadPROMContent(
1998 IN PADAPTER padapter
1999 )
2000 {
2001 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
2002 u8 eeValue;
2003
2004 /* check system boot selection */
2005 eeValue = rtw_read8(padapter, REG_9346CR);
2006 pHalData->EepromOrEfuse = (eeValue & BOOT_FROM_EEPROM) ? _TRUE : _FALSE;
2007 pHalData->bautoload_fail_flag = (eeValue & EEPROM_EN) ? _FALSE : _TRUE;
2008
2009 DBG_871X("%s: 9346CR=0x%02X, Boot from %s, Autoload %s\n",
2010 __FUNCTION__, eeValue,
2011 (pHalData->EepromOrEfuse ? "EEPROM" : "EFUSE"),
2012 (pHalData->bautoload_fail_flag ? "Fail" : "OK"));
2013
2014 // pHalData->EEType = IS_BOOT_FROM_EEPROM(Adapter) ? EEPROM_93C46 : EEPROM_BOOT_EFUSE;
2015
2016
2017
2018 Hal_InitPGData88E(padapter);
2019 readAdapterInfo_8188ES(padapter);
2020 }
2021
2022 static VOID
_InitOtherVariable(IN PADAPTER Adapter)2023 _InitOtherVariable(
2024 IN PADAPTER Adapter
2025 )
2026 {
2027 //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
2028
2029
2030 //if(Adapter->bInHctTest){
2031 // pMgntInfo->PowerSaveControl.bInactivePs = FALSE;
2032 // pMgntInfo->PowerSaveControl.bIPSModeBackup = FALSE;
2033 // pMgntInfo->PowerSaveControl.bLeisurePs = FALSE;
2034 // pMgntInfo->keepAliveLevel = 0;
2035 //}
2036
2037
2038 }
2039
2040 //
2041 // Description:
2042 // Read HW adapter information by E-Fuse or EEPROM according CR9346 reported.
2043 //
2044 // Assumption:
2045 // PASSIVE_LEVEL (SDIO interface)
2046 //
2047 //
_ReadAdapterInfo8188ES(PADAPTER padapter)2048 static s32 _ReadAdapterInfo8188ES(PADAPTER padapter)
2049 {
2050 u32 start;
2051
2052
2053 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("+_ReadAdapterInfo8188ES\n"));
2054
2055 // before access eFuse, make sure card enable has been called
2056 if(_CardEnable(padapter) == _FAIL)
2057 {
2058 DBG_871X(KERN_ERR "%s: run power on flow fail\n", __func__);
2059 return _FAIL;
2060 }
2061
2062 start = rtw_get_current_time();
2063
2064 // Efuse_InitSomeVar(Adapter);
2065 // _EfuseCellSel(padapter);
2066
2067 _ReadRFType(padapter);//rf_chip -> _InitRFType()
2068 _ReadPROMContent(padapter);
2069
2070 // 2010/10/25 MH THe function must be called after borad_type & IC-Version recognize.
2071 //ReadSilmComboMode(Adapter);
2072 _InitOtherVariable(padapter);
2073
2074
2075 //MSG_8192C("%s()(done), rf_chip=0x%x, rf_type=0x%x\n", __FUNCTION__, pHalData->rf_chip, pHalData->rf_type);
2076 MSG_8192C("<==== ReadAdapterInfo8188ES in %d ms\n", rtw_get_passing_time_ms(start));
2077
2078 return _SUCCESS;
2079 }
2080
ReadAdapterInfo8188ES(PADAPTER padapter)2081 static void ReadAdapterInfo8188ES(PADAPTER padapter)
2082 {
2083 // Read EEPROM size before call any EEPROM function
2084 padapter->EepromAddressSize = GetEEPROMSize8188E(padapter);
2085
2086 _ReadAdapterInfo8188ES(padapter);
2087 }
2088
SetHwReg8188ES(PADAPTER Adapter,u8 variable,u8 * val)2089 static void SetHwReg8188ES(PADAPTER Adapter, u8 variable, u8* val)
2090 {
2091 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
2092
2093 _func_enter_;
2094
2095 switch(variable)
2096 {
2097 case HW_VAR_RXDMA_AGG_PG_TH:
2098 break;
2099
2100 case HW_VAR_SET_RPWM:
2101 #ifdef CONFIG_LPS_LCLK
2102 {
2103 u8 ps_state = *((u8 *)val);
2104 //rpwm value only use BIT0(clock bit) ,BIT6(Ack bit), and BIT7(Toggle bit) for 88e.
2105 //BIT0 value - 1: 32k, 0:40MHz.
2106 //BIT6 value - 1: report cpwm value after success set, 0:do not report.
2107 //BIT7 value - Toggle bit change.
2108 //modify by Thomas. 2012/4/2.
2109 ps_state = ps_state & 0xC1;
2110
2111 #ifdef CONFIG_EXT_CLK //for sprd
2112 if(ps_state&BIT(6)) // want to leave 32k
2113 {
2114 //enable ext clock req before leave LPS-32K
2115 //DBG_871X("enable ext clock req before leaving LPS-32K\n");
2116 EnableGpio5ClockReq(Adapter, _FALSE, 1);
2117 }
2118 #endif //CONFIG_EXT_CLK
2119
2120 //DBG_871X("##### Change RPWM value to = %x for switch clk #####\n",ps_state);
2121 rtw_write8(Adapter, SDIO_LOCAL_BASE|SDIO_REG_HRPWM1, ps_state);
2122 }
2123 #endif
2124 break;
2125 default:
2126 SetHwReg8188E(Adapter, variable, val);
2127 break;
2128 }
2129
2130 _func_exit_;
2131 }
2132
GetHwReg8188ES(PADAPTER padapter,u8 variable,u8 * val)2133 static void GetHwReg8188ES(PADAPTER padapter, u8 variable, u8 *val)
2134 {
2135 PHAL_DATA_TYPE pHalData= GET_HAL_DATA(padapter);
2136 _func_enter_;
2137
2138 switch (variable)
2139 {
2140 case HW_VAR_CPWM:
2141 *val = rtw_read8(padapter, SDIO_LOCAL_BASE|SDIO_REG_HCPWM1);
2142 break;
2143 default:
2144 GetHwReg8188E(padapter, variable, val);
2145 break;
2146 }
2147
2148 _func_exit_;
2149 }
2150
2151 //
2152 // Description:
2153 // Query setting of specified variable.
2154 //
2155 u8
GetHalDefVar8188ESDIO(IN PADAPTER Adapter,IN HAL_DEF_VARIABLE eVariable,IN PVOID pValue)2156 GetHalDefVar8188ESDIO(
2157 IN PADAPTER Adapter,
2158 IN HAL_DEF_VARIABLE eVariable,
2159 IN PVOID pValue
2160 )
2161 {
2162 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
2163 u8 bResult = _SUCCESS;
2164
2165 switch(eVariable)
2166 {
2167 case HW_VAR_MAX_RX_AMPDU_FACTOR:
2168 *(( u32*)pValue) = MAX_AMPDU_FACTOR_16K;
2169 break;
2170
2171 case HAL_DEF_TX_LDPC:
2172 case HAL_DEF_RX_LDPC:
2173 *((u8 *)pValue) = _FALSE;
2174 break;
2175 case HAL_DEF_TX_STBC:
2176 *((u8 *)pValue) = 0;
2177 break;
2178 case HAL_DEF_RX_STBC:
2179 *((u8 *)pValue) = 1;
2180 break;
2181 default:
2182 bResult = GetHalDefVar8188E(Adapter, eVariable, pValue);
2183 break;
2184 }
2185
2186 return bResult;
2187 }
2188
2189
2190
2191
2192 //
2193 // Description:
2194 // Change default setting of specified variable.
2195 //
2196 u8
SetHalDefVar8188ESDIO(IN PADAPTER Adapter,IN HAL_DEF_VARIABLE eVariable,IN PVOID pValue)2197 SetHalDefVar8188ESDIO(
2198 IN PADAPTER Adapter,
2199 IN HAL_DEF_VARIABLE eVariable,
2200 IN PVOID pValue
2201 )
2202 {
2203 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
2204 u8 bResult = _TRUE;
2205
2206 switch(eVariable)
2207 {
2208 default:
2209 bResult = SetHalDefVar(Adapter, eVariable, pValue);
2210 break;
2211 }
2212
2213 return bResult;
2214 }
2215
2216 static VOID
_BeaconFunctionEnable(IN PADAPTER padapter,IN BOOLEAN Enable,IN BOOLEAN Linked)2217 _BeaconFunctionEnable(
2218 IN PADAPTER padapter,
2219 IN BOOLEAN Enable,
2220 IN BOOLEAN Linked
2221 )
2222 {
2223 rtw_write8(padapter, REG_BCN_CTRL, (BIT4 | BIT3 | BIT1));
2224 // RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("_BeaconFunctionEnable 0x550 0x%x\n", rtw_read8(padapter, 0x550)));
2225
2226 rtw_write8(padapter, REG_RD_CTRL+1, 0x6F);
2227 }
2228
SetBeaconRelatedRegisters8188ESdio(PADAPTER padapter)2229 void SetBeaconRelatedRegisters8188ESdio(PADAPTER padapter)
2230 {
2231 u32 value32;
2232 //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
2233 struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
2234 struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
2235 u32 bcn_ctrl_reg = REG_BCN_CTRL;
2236 //reset TSF, enable update TSF, correcting TSF On Beacon
2237
2238 //REG_BCN_INTERVAL
2239 //REG_BCNDMATIM
2240 //REG_ATIMWND
2241 //REG_TBTT_PROHIBIT
2242 //REG_DRVERLYINT
2243 //REG_BCN_MAX_ERR
2244 //REG_BCNTCFG //(0x510)
2245 //REG_DUAL_TSF_RST
2246 //REG_BCN_CTRL //(0x550)
2247
2248
2249 #ifdef CONFIG_CONCURRENT_MODE
2250 if (padapter->iface_type == IFACE_PORT1){
2251 bcn_ctrl_reg = REG_BCN_CTRL_1;
2252 }
2253 #endif
2254 //
2255 // ATIM window
2256 //
2257 rtw_write16(padapter, REG_ATIMWND, 2);
2258
2259 //
2260 // Beacon interval (in unit of TU).
2261 //
2262 rtw_write16(padapter, REG_BCN_INTERVAL, pmlmeinfo->bcn_interval);
2263
2264 _InitBeaconParameters(padapter);
2265
2266 rtw_write8(padapter, REG_SLOT, 0x09);
2267
2268 //
2269 // Force beacon frame transmission even after receiving beacon frame from other ad hoc STA
2270 //
2271 //PlatformEFIOWrite1Byte(Adapter, BCN_ERR_THRESH, 0x0a); // We force beacon sent to prevent unexpect disconnect status in Ad hoc mode
2272
2273 //
2274 // Reset TSF Timer to zero, added by Roger. 2008.06.24
2275 //
2276 value32 = rtw_read32(padapter, REG_TCR);
2277 value32 &= ~TSFRST;
2278 rtw_write32(padapter, REG_TCR, value32);
2279
2280 value32 |= TSFRST;
2281 rtw_write32(padapter, REG_TCR, value32);
2282
2283 // TODO: Modify later (Find the right parameters)
2284 // NOTE: Fix test chip's bug (about contention windows's randomness)
2285 // if (OpMode == RT_OP_MODE_IBSS || OpMode == RT_OP_MODE_AP)
2286 if (check_fwstate(&padapter->mlmepriv, WIFI_ADHOC_STATE|WIFI_AP_STATE) == _TRUE)
2287 {
2288 rtw_write8(padapter, REG_RXTSF_OFFSET_CCK, 0x50);
2289 rtw_write8(padapter, REG_RXTSF_OFFSET_OFDM, 0x50);
2290 }
2291
2292 _BeaconFunctionEnable(padapter, _TRUE, _TRUE);
2293
2294 ResumeTxBeacon(padapter);
2295 rtw_write8(padapter, bcn_ctrl_reg, rtw_read8(padapter, bcn_ctrl_reg)|BIT(1));
2296 }
2297
rtl8188es_set_hal_ops(PADAPTER padapter)2298 void rtl8188es_set_hal_ops(PADAPTER padapter)
2299 {
2300 struct hal_ops *pHalFunc = &padapter->HalFunc;
2301
2302 _func_enter_;
2303
2304 pHalFunc->hal_power_on = _InitPowerOn_8188ES;
2305 pHalFunc->hal_power_off = hal_poweroff_8188es;
2306
2307 pHalFunc->hal_init = &rtl8188es_hal_init;
2308 pHalFunc->hal_deinit = &rtl8188es_hal_deinit;
2309
2310 pHalFunc->init_xmit_priv = &rtl8188es_init_xmit_priv;
2311 pHalFunc->free_xmit_priv = &rtl8188es_free_xmit_priv;
2312
2313 pHalFunc->init_recv_priv = &rtl8188es_init_recv_priv;
2314 pHalFunc->free_recv_priv = &rtl8188es_free_recv_priv;
2315
2316 pHalFunc->InitSwLeds = &rtl8188es_InitSwLeds;
2317 pHalFunc->DeInitSwLeds = &rtl8188es_DeInitSwLeds;
2318
2319 pHalFunc->init_default_value = &rtl8188es_init_default_value;
2320 pHalFunc->intf_chip_configure = &rtl8188es_interface_configure;
2321 pHalFunc->read_adapter_info = &ReadAdapterInfo8188ES;
2322
2323 pHalFunc->enable_interrupt = &EnableInterrupt8188ESdio;
2324 pHalFunc->disable_interrupt = &DisableInterrupt8188ESdio;
2325 pHalFunc->check_ips_status = &CheckIPSStatus;
2326
2327 #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
2328 pHalFunc->clear_interrupt = &ClearInterrupt8188ESdio;
2329 #endif
2330 pHalFunc->SetHwRegHandler = &SetHwReg8188ES;
2331 pHalFunc->GetHwRegHandler = &GetHwReg8188ES;
2332
2333 pHalFunc->GetHalDefVarHandler = &GetHalDefVar8188ESDIO;
2334 pHalFunc->SetHalDefVarHandler = &SetHalDefVar8188ESDIO;
2335
2336 pHalFunc->SetBeaconRelatedRegistersHandler = &SetBeaconRelatedRegisters8188ESdio;
2337
2338 pHalFunc->hal_xmit = &rtl8188es_hal_xmit;
2339 pHalFunc->mgnt_xmit = &rtl8188es_mgnt_xmit;
2340 pHalFunc->hal_xmitframe_enqueue = &rtl8188es_hal_xmitframe_enqueue;
2341
2342 #ifdef CONFIG_HOSTAPD_MLME
2343 pHalFunc->hostap_mgnt_xmit_entry = NULL;
2344 #endif
2345 #ifdef CONFIG_XMIT_THREAD_MODE
2346 pHalFunc->xmit_thread_handler = &rtl8188es_xmit_buf_handler;
2347 #endif
2348 rtl8188e_set_hal_ops(pHalFunc);
2349 _func_exit_;
2350
2351 }
2352
2353