1 /*
2 * Copyright (c) 2015-2025, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8
9 #if MEASURED_BOOT
10 #include "./include/rpi3_measured_boot.h"
11 #endif
12
13 #include <arch_helpers.h>
14 #include <common/bl_common.h>
15 #include <common/debug.h>
16 #include <common/desc_image_load.h>
17 #include <lib/optee_utils.h>
18 #include <lib/xlat_tables/xlat_mmu_helpers.h>
19 #include <lib/xlat_tables/xlat_tables_defs.h>
20 #include <drivers/generic_delay_timer.h>
21 #include <drivers/rpi3/gpio/rpi3_gpio.h>
22 #if TRANSFER_LIST
23 #include <tpm_event_log.h>
24 #include <transfer_list.h>
25 #endif /* TRANSFER_LIST */
26
27 #include <drivers/rpi3/sdhost/rpi3_sdhost.h>
28 #include <platform_def.h>
29 #include <rpi_shared.h>
30
31 /* Data structure which holds the extents of the trusted SRAM for BL2 */
32 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
33 struct transfer_list_header __maybe_unused *bl2_tl;
34
35 /* Data structure which holds the MMC info */
36 static struct mmc_device_info mmc_info;
37
38 /* Variables that hold the eventlog addr and size for use in BL2 Measured Boot */
39 static uint8_t *event_log_start;
40 static size_t event_log_size;
41
rpi3_sdhost_setup(void)42 static void rpi3_sdhost_setup(void)
43 {
44 struct rpi3_sdhost_params params;
45
46 memset(¶ms, 0, sizeof(struct rpi3_sdhost_params));
47 params.reg_base = RPI3_SDHOST_BASE;
48 params.bus_width = MMC_BUS_WIDTH_1;
49 params.clk_rate = 50000000;
50 params.clk_rate_initial = (RPI3_SDHOST_MAX_CLOCK / HC_CLOCKDIVISOR_MAXVAL);
51 mmc_info.mmc_dev_type = MMC_IS_SD_HC;
52 mmc_info.ocr_voltage = OCR_3_2_3_3 | OCR_3_3_3_4;
53 rpi3_sdhost_init(¶ms, &mmc_info);
54 }
55
rpi3_mboot_fetch_eventlog_info(uint8_t ** eventlog_addr,size_t * eventlog_size)56 void rpi3_mboot_fetch_eventlog_info(uint8_t **eventlog_addr, size_t *eventlog_size)
57 {
58 *eventlog_addr = event_log_start;
59 *eventlog_size = event_log_size;
60 }
61
62 /*******************************************************************************
63 * BL1 has passed the extents of the trusted SRAM that should be visible to BL2
64 * in x0. This memory layout is sitting at the base of the free trusted SRAM.
65 * Copy it to a safe location before its reclaimed by later BL2 functionality.
66 ******************************************************************************/
67
bl2_early_platform_setup2(u_register_t arg0,u_register_t arg1,u_register_t arg2,u_register_t arg3)68 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1,
69 u_register_t arg2, u_register_t arg3)
70 {
71 meminfo_t *mem_layout = (meminfo_t *) arg1;
72
73 /* Initialize the console to provide early debug support */
74 rpi3_console_init();
75
76 /* Enable arch timer */
77 generic_delay_timer_init();
78
79 /* Setup GPIO driver */
80 rpi3_gpio_init();
81
82 /* Setup the BL2 memory layout */
83 bl2_tzram_layout = *mem_layout;
84
85 /* Setup SDHost driver */
86 rpi3_sdhost_setup();
87 /* When TRANSFER_LIST is used, BL1 already set handoff args:
88 * arg3 = transfer list header; event log is inside TL.
89 * When legacy path, arg2/arg3 carry event log base/size.
90 */
91 #if TRANSFER_LIST
92 bl2_tl = (struct transfer_list_header *)(uintptr_t)arg3;
93 if (bl2_tl != NULL &&
94 transfer_list_check_header(bl2_tl) != TL_OPS_NON) {
95 INFO("BL2: Transfer List found\n");
96 } else {
97 WARN("BL2: TransferList not found; reinit TL\n");
98 bl2_tl = transfer_list_init((void *)(uintptr_t)FW_HANDOFF_BASE,
99 FW_HANDOFF_SIZE);
100 if (!bl2_tl) {
101 ERROR("BL2: Failed to re-initialize transfer list\n");
102 panic();
103 }
104 }
105 #else
106 event_log_start = (uint8_t *)(uintptr_t)arg2;
107 event_log_size = arg3;
108 #endif
109
110 plat_rpi3_io_setup();
111 }
112
bl2_platform_setup(void)113 void bl2_platform_setup(void)
114 {
115 /*
116 * This is where a TrustZone address space controller and other
117 * security related peripherals would be configured.
118 */
119 }
120
rpi3_bl2_sync_transfer_list(void)121 void rpi3_bl2_sync_transfer_list(void)
122 {
123 #if TRANSFER_LIST
124 transfer_list_update_checksum(bl2_tl);
125 #endif
126 }
127 /*******************************************************************************
128 * Perform the very early platform specific architectural setup here.
129 ******************************************************************************/
bl2_plat_arch_setup(void)130 void bl2_plat_arch_setup(void)
131 {
132 rpi3_setup_page_tables(bl2_tzram_layout.total_base,
133 bl2_tzram_layout.total_size,
134 BL_CODE_BASE, BL_CODE_END,
135 BL_RO_DATA_BASE, BL_RO_DATA_END
136 #if USE_COHERENT_MEM
137 , BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END
138 #endif
139 );
140
141 enable_mmu_el1(0);
142 }
143
144 /*******************************************************************************
145 * This function can be used by the platforms to update/use image
146 * information for given `image_id`.
147 ******************************************************************************/
bl2_plat_handle_post_image_load(unsigned int image_id)148 int bl2_plat_handle_post_image_load(unsigned int image_id)
149 {
150 int err = 0;
151 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
152 #ifdef SPD_opteed
153 bl_mem_params_node_t *pager_mem_params = NULL;
154 bl_mem_params_node_t *paged_mem_params = NULL;
155 #endif
156 #if TRANSFER_LIST
157 struct transfer_list_header *ns_tl = NULL;
158 #endif
159 assert(bl_mem_params != NULL);
160
161 switch (image_id) {
162 #if TRANSFER_LIST
163 case BL31_IMAGE_ID:
164 /*
165 * arg0 is a bl_params_t reserved for bl31_early_platform_setup2
166 * we just need arg1 and arg3 for BL31 to update the TL from S
167 * to NS memory before it exits
168 */
169 if (GET_RW(bl_mem_params->ep_info.spsr) == MODE_RW_64) {
170 bl_mem_params->ep_info.args.arg1 =
171 TRANSFER_LIST_HANDOFF_X1_VALUE(REGISTER_CONVENTION_VERSION);
172 }
173 bl_mem_params->ep_info.args.arg3 = (uintptr_t)bl2_tl;
174 break;
175 #endif
176 case BL32_IMAGE_ID:
177 #ifdef SPD_opteed
178 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
179 assert(pager_mem_params);
180
181 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
182 assert(paged_mem_params);
183
184 err = parse_optee_header(&bl_mem_params->ep_info,
185 &pager_mem_params->image_info,
186 &paged_mem_params->image_info);
187 if (err != 0)
188 WARN("OPTEE header parse error.\n");
189 #endif
190 bl_mem_params->ep_info.spsr = rpi3_get_spsr_for_bl32_entry();
191 break;
192
193 case BL33_IMAGE_ID:
194 /* BL33 expects to receive the primary CPU MPID (through r0) */
195
196 bl_mem_params->ep_info.spsr = rpi3_get_spsr_for_bl33_entry();
197
198 #if TRANSFER_LIST
199 if (bl2_tl) {
200 #ifdef FW_NS_HANDOFF_BASE
201 /* relocate the tl to pre-allocate NS memory if macro provided */
202 ns_tl = transfer_list_relocate(
203 bl2_tl, (void *)(uintptr_t)FW_NS_HANDOFF_BASE,
204 bl2_tl->max_size);
205 if (!ns_tl) {
206 ERROR("Relocate TL to 0x%lx failed\n",
207 (unsigned long)FW_NS_HANDOFF_BASE);
208 return -1;
209 }
210 INFO("TL relocated to ns region\n");
211 #endif
212 }
213
214 if (!transfer_list_set_handoff_args(ns_tl,
215 &bl_mem_params->ep_info)) {
216 WARN("Invalid TL, fallback to default arguments\n");
217 bl_mem_params->ep_info.args.arg0 = 0xffff &
218 read_mpidr();
219 }
220 #else
221 /* BL33 expects to receive the primary CPU MPID (through r0) */
222 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
223 #endif
224
225 /* Shutting down the SDHost driver to let BL33 drives SDHost.*/
226 rpi3_sdhost_stop();
227 break;
228
229 default:
230 /* Do nothing in default case */
231 break;
232 }
233
234 return err;
235 }
236