1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2019 Rockchip Electronics Co., Ltd
4 */
5
6 #include <common.h>
7 #include <dm.h>
8 #include <dm/pinctrl.h>
9 #include <regmap.h>
10 #include <syscon.h>
11 #include <fdtdec.h>
12
13 #include "pinctrl-rockchip.h"
14
15 #define MAX_ROCKCHIP_PINS_ENTRIES 30
16 #define MAX_ROCKCHIP_GPIO_PER_BANK 32
17 #define RK_FUNC_GPIO 0
18
rockchip_verify_config(struct udevice * dev,u32 bank,u32 pin)19 static int rockchip_verify_config(struct udevice *dev, u32 bank, u32 pin)
20 {
21 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev);
22 struct rockchip_pin_ctrl *ctrl = priv->ctrl;
23
24 if (bank >= ctrl->nr_banks) {
25 debug("pin conf bank %d >= nbanks %d\n", bank, ctrl->nr_banks);
26 return -EINVAL;
27 }
28
29 if (pin >= MAX_ROCKCHIP_GPIO_PER_BANK) {
30 debug("pin conf pin %d >= %d\n", pin,
31 MAX_ROCKCHIP_GPIO_PER_BANK);
32 return -EINVAL;
33 }
34
35 return 0;
36 }
37
rockchip_get_recalced_mux(struct rockchip_pin_bank * bank,int pin,int * reg,u8 * bit,int * mask)38 void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
39 int *reg, u8 *bit, int *mask)
40 {
41 struct rockchip_pinctrl_priv *priv = bank->priv;
42 struct rockchip_pin_ctrl *ctrl = priv->ctrl;
43 struct rockchip_mux_recalced_data *data;
44 int i;
45
46 for (i = 0; i < ctrl->niomux_recalced; i++) {
47 data = &ctrl->iomux_recalced[i];
48 if (data->num == bank->bank_num &&
49 data->pin == pin)
50 break;
51 }
52
53 if (i >= ctrl->niomux_recalced)
54 return;
55
56 *reg = data->reg;
57 *mask = data->mask;
58 *bit = data->bit;
59 }
60
61 static enum rockchip_pin_route_type
rockchip_get_mux_route(struct rockchip_pin_bank * bank,int pin,int mux,u32 * reg,u32 * value)62 rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
63 int mux, u32 *reg, u32 *value)
64 {
65 struct rockchip_pinctrl_priv *priv = bank->priv;
66 struct rockchip_pin_ctrl *ctrl = priv->ctrl;
67 struct rockchip_mux_route_data *data;
68 int i;
69
70 for (i = 0; i < ctrl->niomux_routes; i++) {
71 data = &ctrl->iomux_routes[i];
72 if (data->bank_num == bank->bank_num &&
73 data->pin == pin && data->func == mux)
74 break;
75 }
76
77 if (i >= ctrl->niomux_routes)
78 return ROUTE_TYPE_INVALID;
79
80 *reg = data->route_offset;
81 *value = data->route_val;
82
83 return data->route_type;
84 }
85
rockchip_get_mux_data(int mux_type,int pin,u8 * bit,int * mask)86 int rockchip_get_mux_data(int mux_type, int pin, u8 *bit, int *mask)
87 {
88 int offset = 0;
89
90 if (mux_type & IOMUX_WIDTH_4BIT) {
91 if ((pin % 8) >= 4)
92 offset = 0x4;
93 *bit = (pin % 4) * 4;
94 *mask = 0xf;
95 } else if (mux_type & IOMUX_WIDTH_3BIT) {
96 /*
97 * pin0 ~ pin4 are at first register, and
98 * pin5 ~ pin7 are at second register.
99 */
100 if ((pin % 8) >= 5)
101 offset = 0x4;
102 *bit = (pin % 8 % 5) * 3;
103 *mask = 0x7;
104 } else {
105 *bit = (pin % 8) * 2;
106 *mask = 0x3;
107 }
108
109 return offset;
110 }
111
rockchip_get_mux(struct rockchip_pin_bank * bank,int pin)112 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
113 {
114 struct rockchip_pinctrl_priv *priv = bank->priv;
115 int iomux_num = (pin / 8);
116 struct regmap *regmap;
117 unsigned int val;
118 int reg, ret, mask, mux_type;
119 u8 bit;
120
121 if (iomux_num > 3)
122 return -EINVAL;
123
124 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
125 debug("pin %d is unrouted\n", pin);
126 return -ENOTSUPP;
127 }
128
129 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
130 return RK_FUNC_GPIO;
131
132 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
133 ? priv->regmap_pmu : priv->regmap_base;
134
135 /* get basic quadrupel of mux registers and the correct reg inside */
136 mux_type = bank->iomux[iomux_num].type;
137 reg = bank->iomux[iomux_num].offset;
138 reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
139
140 if (bank->recalced_mask & BIT(pin))
141 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
142
143 ret = regmap_read(regmap, reg, &val);
144 if (ret)
145 return ret;
146
147 return ((val >> bit) & mask);
148 }
149
rockchip_pinctrl_get_gpio_mux(struct udevice * dev,int banknum,int index)150 static int rockchip_pinctrl_get_gpio_mux(struct udevice *dev, int banknum,
151 int index)
152 { struct rockchip_pinctrl_priv *priv = dev_get_priv(dev);
153 struct rockchip_pin_ctrl *ctrl = priv->ctrl;
154
155 return rockchip_get_mux(&ctrl->pin_banks[banknum], index);
156 }
157
rockchip_verify_mux(struct rockchip_pin_bank * bank,int pin,int mux)158 static int rockchip_verify_mux(struct rockchip_pin_bank *bank,
159 int pin, int mux)
160 {
161 int iomux_num = (pin / 8);
162
163 if (iomux_num > 3)
164 return -EINVAL;
165
166 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
167 debug("pin %d is unrouted\n", pin);
168 return -ENOTSUPP;
169 }
170
171 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
172 if (mux != IOMUX_GPIO_ONLY) {
173 debug("pin %d only supports a gpio mux\n", pin);
174 return -ENOTSUPP;
175 }
176 }
177
178 return 0;
179 }
180
181 /*
182 * Set a new mux function for a pin.
183 *
184 * The register is divided into the upper and lower 16 bit. When changing
185 * a value, the previous register value is not read and changed. Instead
186 * it seems the changed bits are marked in the upper 16 bit, while the
187 * changed value gets set in the same offset in the lower 16 bit.
188 * All pin settings seem to be 2 bit wide in both the upper and lower
189 * parts.
190 * @bank: pin bank to change
191 * @pin: pin to change
192 * @mux: new mux function to set
193 */
rockchip_set_mux(struct rockchip_pin_bank * bank,int pin,int mux)194 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
195 {
196 struct rockchip_pinctrl_priv *priv = bank->priv;
197 struct rockchip_pin_ctrl *ctrl = priv->ctrl;
198 int iomux_num = (pin / 8);
199 int ret;
200
201 ret = rockchip_verify_mux(bank, pin, mux);
202 if (ret < 0)
203 return ret == -ENOTSUPP ? 0 : ret;
204
205 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
206 return 0;
207
208 debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);
209
210 if (!ctrl->set_mux)
211 return -ENOTSUPP;
212
213 ret = ctrl->set_mux(bank, pin, mux);
214 if (ret)
215 return ret;
216
217 if (bank->route_mask & BIT(pin)) {
218 struct regmap *regmap;
219 u32 route_reg = 0, route_val = 0;
220
221 ret = rockchip_get_mux_route(bank, pin, mux,
222 &route_reg, &route_val);
223 switch (ret) {
224 case ROUTE_TYPE_DEFAULT:
225 if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
226 regmap = priv->regmap_pmu;
227 else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU)
228 regmap = (pin % 8 < 4) ? priv->regmap_pmu : priv->regmap_base;
229 else
230 regmap = priv->regmap_base;
231
232 regmap_write(regmap, route_reg, route_val);
233 break;
234 case ROUTE_TYPE_TOPGRF:
235 regmap_write(priv->regmap_base, route_reg, route_val);
236 break;
237 case ROUTE_TYPE_PMUGRF:
238 regmap_write(priv->regmap_pmu, route_reg, route_val);
239 break;
240 case ROUTE_TYPE_INVALID: /* Fall through */
241 default:
242 break;
243 }
244 }
245
246 return 0;
247 }
248
249 static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = {
250 { 2, 4, 8, 12, -1, -1, -1, -1 },
251 { 3, 6, 9, 12, -1, -1, -1, -1 },
252 { 5, 10, 15, 20, -1, -1, -1, -1 },
253 { 4, 6, 8, 10, 12, 14, 16, 18 },
254 { 4, 7, 10, 13, 16, 19, 22, 26 }
255 };
256
rockchip_translate_drive_value(int type,int strength)257 int rockchip_translate_drive_value(int type, int strength)
258 {
259 int i, ret;
260
261 ret = -EINVAL;
262 for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[type]); i++) {
263 if (rockchip_perpin_drv_list[type][i] == strength) {
264 ret = i;
265 break;
266 } else if (rockchip_perpin_drv_list[type][i] < 0) {
267 ret = rockchip_perpin_drv_list[type][i];
268 break;
269 }
270 }
271
272 return ret;
273 }
274
rockchip_set_drive_perpin(struct rockchip_pin_bank * bank,int pin_num,int strength)275 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
276 int pin_num, int strength)
277 {
278 struct rockchip_pinctrl_priv *priv = bank->priv;
279 struct rockchip_pin_ctrl *ctrl = priv->ctrl;
280
281 debug("setting drive of GPIO%d-%d to %d\n", bank->bank_num,
282 pin_num, strength);
283
284 if (!ctrl->set_drive)
285 return -ENOTSUPP;
286
287 return ctrl->set_drive(bank, pin_num, strength);
288 }
289
290 static int rockchip_pull_list[PULL_TYPE_MAX][4] = {
291 {
292 PIN_CONFIG_BIAS_DISABLE,
293 PIN_CONFIG_BIAS_PULL_UP,
294 PIN_CONFIG_BIAS_PULL_DOWN,
295 PIN_CONFIG_BIAS_BUS_HOLD
296 },
297 {
298 PIN_CONFIG_BIAS_DISABLE,
299 PIN_CONFIG_BIAS_PULL_DOWN,
300 PIN_CONFIG_BIAS_DISABLE,
301 PIN_CONFIG_BIAS_PULL_UP
302 },
303 };
304
rockchip_translate_pull_value(int type,int pull)305 int rockchip_translate_pull_value(int type, int pull)
306 {
307 int i, ret;
308
309 ret = -EINVAL;
310 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[type]);
311 i++) {
312 if (rockchip_pull_list[type][i] == pull) {
313 ret = i;
314 break;
315 }
316 }
317
318 return ret;
319 }
320
rockchip_set_pull(struct rockchip_pin_bank * bank,int pin_num,int pull)321 static int rockchip_set_pull(struct rockchip_pin_bank *bank,
322 int pin_num, int pull)
323 {
324 struct rockchip_pinctrl_priv *priv = bank->priv;
325 struct rockchip_pin_ctrl *ctrl = priv->ctrl;
326
327 debug("setting pull of GPIO%d-%d to %d\n", bank->bank_num,
328 pin_num, pull);
329
330 if (!ctrl->set_pull)
331 return -ENOTSUPP;
332
333 return ctrl->set_pull(bank, pin_num, pull);
334 }
335
rockchip_set_schmitt(struct rockchip_pin_bank * bank,int pin_num,int enable)336 static int rockchip_set_schmitt(struct rockchip_pin_bank *bank,
337 int pin_num, int enable)
338 {
339 struct rockchip_pinctrl_priv *priv = bank->priv;
340 struct rockchip_pin_ctrl *ctrl = priv->ctrl;
341
342 debug("setting input schmitt of GPIO%d-%d to %d\n", bank->bank_num,
343 pin_num, enable);
344
345 if (!ctrl->set_schmitt)
346 return -ENOTSUPP;
347
348 return ctrl->set_schmitt(bank, pin_num, enable);
349 }
350
351 /* set the pin config settings for a specified pin */
rockchip_pinconf_set(struct rockchip_pin_bank * bank,u32 pin,u32 param,u32 arg)352 static int rockchip_pinconf_set(struct rockchip_pin_bank *bank,
353 u32 pin, u32 param, u32 arg)
354 {
355 int rc;
356
357 switch (param) {
358 case PIN_CONFIG_BIAS_DISABLE:
359 case PIN_CONFIG_BIAS_PULL_UP:
360 case PIN_CONFIG_BIAS_PULL_DOWN:
361 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
362 case PIN_CONFIG_BIAS_BUS_HOLD:
363 rc = rockchip_set_pull(bank, pin, param);
364 if (rc)
365 return rc;
366 break;
367
368 case PIN_CONFIG_DRIVE_STRENGTH:
369 rc = rockchip_set_drive_perpin(bank, pin, arg);
370 if (rc < 0)
371 return rc;
372 break;
373
374 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
375 rc = rockchip_set_schmitt(bank, pin, arg);
376 if (rc < 0)
377 return rc;
378 break;
379
380 default:
381 break;
382 }
383
384 return 0;
385 }
386
387 static const struct pinconf_param rockchip_conf_params[] = {
388 { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
389 { "bias-bus-hold", PIN_CONFIG_BIAS_BUS_HOLD, 0 },
390 { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 },
391 { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 },
392 { "bias-pull-pin-default", PIN_CONFIG_BIAS_PULL_PIN_DEFAULT, 1 },
393 { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 },
394 { "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 },
395 { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 },
396 };
397
rockchip_pinconf_prop_name_to_param(const char * property,u32 * default_value)398 static int rockchip_pinconf_prop_name_to_param(const char *property,
399 u32 *default_value)
400 {
401 const struct pinconf_param *p, *end;
402
403 p = rockchip_conf_params;
404 end = p + sizeof(rockchip_conf_params) / sizeof(struct pinconf_param);
405
406 /* See if this pctldev supports this parameter */
407 for (; p < end; p++) {
408 if (!strcmp(property, p->property)) {
409 *default_value = p->default_value;
410 return p->param;
411 }
412 }
413
414 *default_value = 0;
415 return -EPERM;
416 }
417
rockchip_pinctrl_set_state(struct udevice * dev,struct udevice * config)418 static int rockchip_pinctrl_set_state(struct udevice *dev,
419 struct udevice *config)
420 {
421 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev);
422 struct rockchip_pin_ctrl *ctrl = priv->ctrl;
423 u32 cells[MAX_ROCKCHIP_PINS_ENTRIES * 4];
424 u32 bank, pin, mux, conf, arg, default_val;
425 int ret, count, i;
426 const char *prop_name;
427 const void *value;
428 int prop_len, param;
429 const u32 *data;
430 ofnode node;
431 #if CONFIG_IS_ENABLED(OF_LIVE)
432 const struct device_node *np;
433 struct property *pp;
434 #else
435 int property_offset, pcfg_node;
436 const void *blob = gd->fdt_blob;
437 #endif
438 data = dev_read_prop(config, "rockchip,pins", &count);
439 if (count < 0) {
440 debug("%s: bad array size %d\n", __func__, count);
441 return -EINVAL;
442 }
443
444 count /= sizeof(u32);
445 if (count > MAX_ROCKCHIP_PINS_ENTRIES * 4) {
446 debug("%s: unsupported pins array count %d\n",
447 __func__, count);
448 return -EINVAL;
449 }
450
451 for (i = 0; i < count; i++)
452 cells[i] = fdt32_to_cpu(data[i]);
453
454 for (i = 0; i < (count >> 2); i++) {
455 bank = cells[4 * i + 0];
456 pin = cells[4 * i + 1];
457 mux = cells[4 * i + 2];
458 conf = cells[4 * i + 3];
459
460 ret = rockchip_verify_config(dev, bank, pin);
461 if (ret)
462 return ret;
463
464 ret = rockchip_set_mux(&ctrl->pin_banks[bank], pin, mux);
465 if (ret)
466 return ret;
467
468 node = ofnode_get_by_phandle(conf);
469 if (!ofnode_valid(node))
470 return -ENODEV;
471 #if CONFIG_IS_ENABLED(OF_LIVE)
472 np = ofnode_to_np(node);
473 for (pp = np->properties; pp; pp = pp->next) {
474 prop_name = pp->name;
475 prop_len = pp->length;
476 value = pp->value;
477 #else
478 pcfg_node = ofnode_to_offset(node);
479 fdt_for_each_property_offset(property_offset, blob, pcfg_node) {
480 value = fdt_getprop_by_offset(blob, property_offset,
481 &prop_name, &prop_len);
482 if (!value)
483 return -ENOENT;
484 #endif
485 param = rockchip_pinconf_prop_name_to_param(prop_name,
486 &default_val);
487 if (param < 0)
488 break;
489
490 if (prop_len >= sizeof(fdt32_t))
491 arg = fdt32_to_cpu(*(fdt32_t *)value);
492 else
493 arg = default_val;
494
495 ret = rockchip_pinconf_set(&ctrl->pin_banks[bank], pin,
496 param, arg);
497 if (ret) {
498 debug("%s: rockchip_pinconf_set fail: %d\n",
499 __func__, ret);
500 return ret;
501 }
502 }
503 }
504
505 return 0;
506 }
507
508 static int rockchip_pinctrl_get_pins_count(struct udevice *dev)
509 {
510 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev);
511 struct rockchip_pin_ctrl *ctrl = priv->ctrl;
512
513 return ctrl->nr_pins;
514 }
515
516 const struct pinctrl_ops rockchip_pinctrl_ops = {
517 .get_pins_count = rockchip_pinctrl_get_pins_count,
518 .set_state = rockchip_pinctrl_set_state,
519 .get_gpio_mux = rockchip_pinctrl_get_gpio_mux,
520 };
521
522 /* retrieve the soc specific data */
523 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(struct udevice *dev)
524 {
525 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev);
526 struct rockchip_pin_ctrl *ctrl =
527 (struct rockchip_pin_ctrl *)dev_get_driver_data(dev);
528 struct rockchip_pin_bank *bank;
529 int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
530 u32 nr_pins;
531
532 grf_offs = ctrl->grf_mux_offset;
533 pmu_offs = ctrl->pmu_mux_offset;
534 drv_pmu_offs = ctrl->pmu_drv_offset;
535 drv_grf_offs = ctrl->grf_drv_offset;
536 bank = ctrl->pin_banks;
537
538 nr_pins = 0;
539 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
540 int bank_pins = 0;
541
542 bank->priv = priv;
543 bank->pin_base = nr_pins;
544 nr_pins += bank->nr_pins;
545
546 /* calculate iomux and drv offsets */
547 for (j = 0; j < 4; j++) {
548 struct rockchip_iomux *iom = &bank->iomux[j];
549 struct rockchip_drv *drv = &bank->drv[j];
550 int inc;
551
552 if (bank_pins >= nr_pins)
553 break;
554
555 /* preset iomux offset value, set new start value */
556 if (iom->offset >= 0) {
557 if ((iom->type & IOMUX_SOURCE_PMU) || (iom->type & IOMUX_L_SOURCE_PMU))
558 pmu_offs = iom->offset;
559 else
560 grf_offs = iom->offset;
561 } else { /* set current iomux offset */
562 iom->offset = ((iom->type & IOMUX_SOURCE_PMU) ||
563 (iom->type & IOMUX_L_SOURCE_PMU)) ?
564 pmu_offs : grf_offs;
565 }
566
567 /* preset drv offset value, set new start value */
568 if (drv->offset >= 0) {
569 if (iom->type & IOMUX_SOURCE_PMU)
570 drv_pmu_offs = drv->offset;
571 else
572 drv_grf_offs = drv->offset;
573 } else { /* set current drv offset */
574 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ?
575 drv_pmu_offs : drv_grf_offs;
576 }
577
578 debug("bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n",
579 i, j, iom->offset, drv->offset);
580
581 /*
582 * Increase offset according to iomux width.
583 * 4bit iomux'es are spread over two registers.
584 */
585 inc = (iom->type & (IOMUX_WIDTH_4BIT |
586 IOMUX_WIDTH_3BIT |
587 IOMUX_8WIDTH_2BIT)) ? 8 : 4;
588 if ((iom->type & IOMUX_SOURCE_PMU) || (iom->type & IOMUX_L_SOURCE_PMU))
589 pmu_offs += inc;
590 else
591 grf_offs += inc;
592
593 /*
594 * Increase offset according to drv width.
595 * 3bit drive-strenth'es are spread over two registers.
596 */
597 if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
598 (drv->drv_type == DRV_TYPE_IO_3V3_ONLY))
599 inc = 8;
600 else
601 inc = 4;
602
603 if (iom->type & IOMUX_SOURCE_PMU)
604 drv_pmu_offs += inc;
605 else
606 drv_grf_offs += inc;
607
608 bank_pins += 8;
609 }
610
611 /* calculate the per-bank recalced_mask */
612 for (j = 0; j < ctrl->niomux_recalced; j++) {
613 int pin = 0;
614
615 if (ctrl->iomux_recalced[j].num == bank->bank_num) {
616 pin = ctrl->iomux_recalced[j].pin;
617 bank->recalced_mask |= BIT(pin);
618 }
619 }
620
621 /* calculate the per-bank route_mask */
622 for (j = 0; j < ctrl->niomux_routes; j++) {
623 int pin = 0;
624
625 if (ctrl->iomux_routes[j].bank_num == bank->bank_num) {
626 pin = ctrl->iomux_routes[j].pin;
627 bank->route_mask |= BIT(pin);
628 }
629 }
630 }
631
632 WARN_ON(nr_pins != ctrl->nr_pins);
633
634 return ctrl;
635 }
636
637 int rockchip_pinctrl_probe(struct udevice *dev)
638 {
639 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev);
640 struct rockchip_pin_ctrl *ctrl;
641 struct udevice *syscon;
642 struct regmap *regmap;
643 int ret = 0;
644
645 /* get rockchip grf syscon phandle */
646 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,grf",
647 &syscon);
648 if (ret) {
649 debug("unable to find rockchip,grf syscon device (%d)\n", ret);
650 return ret;
651 }
652
653 /* get grf-reg base address */
654 regmap = syscon_get_regmap(syscon);
655 if (!regmap) {
656 debug("unable to find rockchip grf regmap\n");
657 return -ENODEV;
658 }
659 priv->regmap_base = regmap;
660
661 /* option: get pmu-reg base address */
662 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pmu",
663 &syscon);
664 if (!ret) {
665 /* get pmugrf-reg base address */
666 regmap = syscon_get_regmap(syscon);
667 if (!regmap) {
668 debug("unable to find rockchip pmu regmap\n");
669 return -ENODEV;
670 }
671 priv->regmap_pmu = regmap;
672 }
673
674 ctrl = rockchip_pinctrl_get_soc_data(dev);
675 if (!ctrl) {
676 debug("driver data not available\n");
677 return -EINVAL;
678 }
679
680 priv->ctrl = ctrl;
681 return 0;
682 }
683