1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
4 */
5
6 #include <linux/io.h>
7
8 #include "rkpm_helpers.h"
9 #include "rkpm_uart.h"
10
11 #define UART_DEFAULT_BAUDRATE 115200
12
rkpm_uart_debug_init(void __iomem * base,unsigned int uart_clk,unsigned int baud_rate)13 void rkpm_uart_debug_init(void __iomem *base,
14 unsigned int uart_clk,
15 unsigned int baud_rate)
16 {
17 u32 uart_dll, uart_dlh;
18 u32 div;
19
20 if (!base || !uart_clk || !baud_rate)
21 return;
22
23 div = uart_clk / baud_rate / 16;
24 uart_dll = div & 0xff;
25 uart_dlh = (div >> 8) & 0xff;
26
27 /* Reset uart */
28 writel_relaxed(XMIT_FIFO_RESET | RCVR_FIFO_RESET | UART_RESET,
29 base + UARTSRR);
30 rkpm_raw_udelay(10);
31
32 writel_relaxed(DIAGNOSTIC_MODE, base + UARTMCR);
33 writel_relaxed(0x83, base + UARTLCR);
34 writel_relaxed(uart_dll, base + UARTDLL);
35 writel_relaxed(uart_dlh, base + UARTDLLM);
36 writel_relaxed(0x03, base + UARTLCR);
37 writel_relaxed(0x01, base + UARTIER);
38 writel_relaxed(UARTFCR_FIFOEN, base + UARTFCR);
39 writel_relaxed(0, base + UARTMCR);
40 }
41
rkpm_uart_debug_save(void __iomem * base,struct uart_debug_ctx * ctx)42 void rkpm_uart_debug_save(void __iomem *base,
43 struct uart_debug_ctx *ctx)
44 {
45 u32 wait_cnt = 50000;
46
47 while ((readl_relaxed(base + UARTUSR) & UARTUSR_BUSY) &&
48 --wait_cnt)
49 rkpm_raw_udelay(10);
50
51 /* Uart error! Unlikely to reach here */
52 if (wait_cnt == 0)
53 rkpm_uart_debug_init(base, 24000000, UART_DEFAULT_BAUDRATE);
54
55 ctx->uart_lcr = readl_relaxed(base + UARTLCR);
56 ctx->uart_ier = readl_relaxed(base + UARTIER);
57 ctx->uart_mcr = readl_relaxed(base + UARTMCR);
58 writel_relaxed(ctx->uart_lcr | UARTLCR_DLAB, base + UARTLCR);
59 ctx->uart_dll = readl_relaxed(base + UARTDLL);
60 ctx->uart_dlh = readl_relaxed(base + UARTDLLM);
61 writel_relaxed(ctx->uart_lcr, base + UARTLCR);
62 }
63
rkpm_uart_debug_restore(void __iomem * base,struct uart_debug_ctx * ctx)64 void rkpm_uart_debug_restore(void __iomem *base,
65 struct uart_debug_ctx *ctx)
66 {
67 u32 uart_lcr;
68 u32 wait_cnt = 50000;
69
70 while ((readl_relaxed(base + UARTUSR) & UARTUSR_BUSY) &&
71 --wait_cnt)
72 rkpm_raw_udelay(10);
73
74 writel_relaxed(XMIT_FIFO_RESET | RCVR_FIFO_RESET | UART_RESET,
75 base + UARTSRR);
76 rkpm_raw_udelay(10);
77 uart_lcr = readl_relaxed(base + UARTLCR);
78 writel_relaxed(DIAGNOSTIC_MODE, base + UARTMCR);
79 writel_relaxed(uart_lcr | UARTLCR_DLAB, base + UARTLCR);
80 writel_relaxed(ctx->uart_dll, base + UARTDLL);
81 writel_relaxed(ctx->uart_dlh, base + UARTDLLM);
82 writel_relaxed(ctx->uart_lcr, base + UARTLCR);
83 writel_relaxed(ctx->uart_ier, base + UARTIER);
84 writel_relaxed(UARTFCR_FIFOEN, base + UARTFCR);
85 writel_relaxed(ctx->uart_mcr, base + UARTMCR);
86 }
87
88