1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2020 Rockchip Electronics Co., Ltd. */
3
4 #include <linux/delay.h>
5 #include <linux/pm_runtime.h>
6 #include <media/v4l2-common.h>
7 #include <media/v4l2-event.h>
8 #include <media/v4l2-fh.h>
9 #include <media/v4l2-ioctl.h>
10 #include <media/v4l2-subdev.h>
11 #include <media/videobuf2-dma-contig.h>
12 #include <media/videobuf2-dma-sg.h>
13 #include "dev.h"
14 #include "regs.h"
15
16 #define CIF_ISP_REQ_BUFS_MIN 0
17
18 static int mi_frame_end(struct rkisp_stream *stream, u32 state);
19 static void rkisp_buf_queue(struct vb2_buffer *vb);
20
21 static const struct capture_fmt mp_fmts[] = {
22 /* yuv422 */
23 {
24 .fourcc = V4L2_PIX_FMT_UYVY,
25 .fmt_type = FMT_YUV,
26 .bpp = { 16 },
27 .cplanes = 1,
28 .mplanes = 1,
29 .uv_swap = 0,
30 .write_format = MI_CTRL_MP_WRITE_YUVINT,
31 .output_format = ISP32_MI_OUTPUT_YUV422,
32 }, {
33 .fourcc = V4L2_PIX_FMT_YUV422P,
34 .fmt_type = FMT_YUV,
35 .bpp = { 8, 4, 4 },
36 .cplanes = 3,
37 .mplanes = 1,
38 .uv_swap = 0,
39 .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
40 .output_format = ISP32_MI_OUTPUT_YUV422,
41 }, {
42 .fourcc = V4L2_PIX_FMT_NV16,
43 .fmt_type = FMT_YUV,
44 .bpp = { 8, 16 },
45 .cplanes = 2,
46 .mplanes = 1,
47 .uv_swap = 0,
48 .write_format = MI_CTRL_MP_WRITE_YUV_SPLA,
49 .output_format = ISP32_MI_OUTPUT_YUV422,
50 }, {
51 .fourcc = V4L2_PIX_FMT_NV61,
52 .fmt_type = FMT_YUV,
53 .bpp = { 8, 16 },
54 .cplanes = 2,
55 .mplanes = 1,
56 .uv_swap = 1,
57 .write_format = MI_CTRL_MP_WRITE_YUV_SPLA,
58 .output_format = ISP32_MI_OUTPUT_YUV422,
59 }, {
60 .fourcc = V4L2_PIX_FMT_YUV422M,
61 .fmt_type = FMT_YUV,
62 .bpp = { 8, 8, 8 },
63 .cplanes = 3,
64 .mplanes = 3,
65 .uv_swap = 0,
66 .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
67 .output_format = ISP32_MI_OUTPUT_YUV422,
68 },
69 /* yuv420 */
70 {
71 .fourcc = V4L2_PIX_FMT_NV21,
72 .fmt_type = FMT_YUV,
73 .bpp = { 8, 16 },
74 .cplanes = 2,
75 .mplanes = 1,
76 .uv_swap = 1,
77 .write_format = MI_CTRL_MP_WRITE_YUV_SPLA,
78 .output_format = ISP32_MI_OUTPUT_YUV420,
79 }, {
80 .fourcc = V4L2_PIX_FMT_NV12,
81 .fmt_type = FMT_YUV,
82 .bpp = { 8, 16 },
83 .cplanes = 2,
84 .mplanes = 1,
85 .uv_swap = 0,
86 .write_format = MI_CTRL_MP_WRITE_YUV_SPLA,
87 .output_format = ISP32_MI_OUTPUT_YUV420,
88 }, {
89 .fourcc = V4L2_PIX_FMT_NV21M,
90 .fmt_type = FMT_YUV,
91 .bpp = { 8, 16 },
92 .cplanes = 2,
93 .mplanes = 2,
94 .uv_swap = 1,
95 .write_format = MI_CTRL_MP_WRITE_YUV_SPLA,
96 .output_format = ISP32_MI_OUTPUT_YUV420,
97 }, {
98 .fourcc = V4L2_PIX_FMT_NV12M,
99 .fmt_type = FMT_YUV,
100 .bpp = { 8, 16 },
101 .cplanes = 2,
102 .mplanes = 2,
103 .uv_swap = 0,
104 .write_format = MI_CTRL_MP_WRITE_YUV_SPLA,
105 .output_format = ISP32_MI_OUTPUT_YUV420,
106 }, {
107 .fourcc = V4L2_PIX_FMT_YUV420,
108 .fmt_type = FMT_YUV,
109 .bpp = { 8, 8, 8 },
110 .cplanes = 3,
111 .mplanes = 1,
112 .uv_swap = 0,
113 .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
114 .output_format = ISP32_MI_OUTPUT_YUV420,
115 },
116 /* yuv444 */
117 {
118 .fourcc = V4L2_PIX_FMT_YUV444M,
119 .fmt_type = FMT_YUV,
120 .bpp = { 8, 8, 8 },
121 .cplanes = 3,
122 .mplanes = 3,
123 .uv_swap = 0,
124 .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
125 .output_format = 0,
126 },
127 /* raw */
128 {
129 .fourcc = V4L2_PIX_FMT_SRGGB8,
130 .fmt_type = FMT_BAYER,
131 .bpp = { 8 },
132 .mplanes = 1,
133 .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
134 .output_format = 0,
135 }, {
136 .fourcc = V4L2_PIX_FMT_SGRBG8,
137 .fmt_type = FMT_BAYER,
138 .bpp = { 8 },
139 .mplanes = 1,
140 .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
141 .output_format = 0,
142 }, {
143 .fourcc = V4L2_PIX_FMT_SGBRG8,
144 .fmt_type = FMT_BAYER,
145 .bpp = { 8 },
146 .mplanes = 1,
147 .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
148 .output_format = 0,
149 }, {
150 .fourcc = V4L2_PIX_FMT_SBGGR8,
151 .fmt_type = FMT_BAYER,
152 .bpp = { 8 },
153 .mplanes = 1,
154 .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
155 .output_format = 0,
156 }, {
157 .fourcc = V4L2_PIX_FMT_SRGGB10,
158 .fmt_type = FMT_BAYER,
159 .bpp = { 10 },
160 .mplanes = 1,
161 .write_format = MI_CTRL_MP_WRITE_RAW12,
162 .output_format = 0,
163 }, {
164 .fourcc = V4L2_PIX_FMT_SGRBG10,
165 .fmt_type = FMT_BAYER,
166 .bpp = { 10 },
167 .mplanes = 1,
168 .write_format = MI_CTRL_MP_WRITE_RAW12,
169 .output_format = 0,
170 }, {
171 .fourcc = V4L2_PIX_FMT_SGBRG10,
172 .fmt_type = FMT_BAYER,
173 .bpp = { 10 },
174 .mplanes = 1,
175 .write_format = MI_CTRL_MP_WRITE_RAW12,
176 .output_format = 0,
177 }, {
178 .fourcc = V4L2_PIX_FMT_SBGGR10,
179 .fmt_type = FMT_BAYER,
180 .bpp = { 10 },
181 .mplanes = 1,
182 .write_format = MI_CTRL_MP_WRITE_RAW12,
183 .output_format = 0,
184 }, {
185 .fourcc = V4L2_PIX_FMT_SRGGB12,
186 .fmt_type = FMT_BAYER,
187 .bpp = { 12 },
188 .mplanes = 1,
189 .write_format = MI_CTRL_MP_WRITE_RAW12,
190 .output_format = 0,
191 }, {
192 .fourcc = V4L2_PIX_FMT_SGRBG12,
193 .fmt_type = FMT_BAYER,
194 .bpp = { 12 },
195 .mplanes = 1,
196 .write_format = MI_CTRL_MP_WRITE_RAW12,
197 .output_format = 0,
198 }, {
199 .fourcc = V4L2_PIX_FMT_SGBRG12,
200 .fmt_type = FMT_BAYER,
201 .bpp = { 12 },
202 .mplanes = 1,
203 .write_format = MI_CTRL_MP_WRITE_RAW12,
204 .output_format = 0,
205 }, {
206 .fourcc = V4L2_PIX_FMT_SBGGR12,
207 .fmt_type = FMT_BAYER,
208 .bpp = { 12 },
209 .mplanes = 1,
210 .write_format = MI_CTRL_MP_WRITE_RAW12,
211 .output_format = 0,
212 },
213 };
214
215 static const struct capture_fmt sp_fmts[] = {
216 /* yuv422 */
217 {
218 .fourcc = V4L2_PIX_FMT_UYVY,
219 .fmt_type = FMT_YUV,
220 .bpp = { 16 },
221 .cplanes = 1,
222 .mplanes = 1,
223 .uv_swap = 0,
224 .write_format = MI_CTRL_SP_WRITE_INT,
225 .output_format = MI_CTRL_SP_OUTPUT_YUV422,
226 }, {
227 .fourcc = V4L2_PIX_FMT_YUV422P,
228 .fmt_type = FMT_YUV,
229 .bpp = { 8, 8, 8 },
230 .cplanes = 3,
231 .mplanes = 1,
232 .uv_swap = 0,
233 .write_format = MI_CTRL_SP_WRITE_PLA,
234 .output_format = MI_CTRL_SP_OUTPUT_YUV422,
235 }, {
236 .fourcc = V4L2_PIX_FMT_NV16,
237 .fmt_type = FMT_YUV,
238 .bpp = { 8, 16 },
239 .cplanes = 2,
240 .mplanes = 1,
241 .uv_swap = 0,
242 .write_format = MI_CTRL_SP_WRITE_SPLA,
243 .output_format = MI_CTRL_SP_OUTPUT_YUV422,
244 }, {
245 .fourcc = V4L2_PIX_FMT_NV61,
246 .fmt_type = FMT_YUV,
247 .bpp = { 8, 16 },
248 .cplanes = 2,
249 .mplanes = 1,
250 .uv_swap = 1,
251 .write_format = MI_CTRL_SP_WRITE_SPLA,
252 .output_format = MI_CTRL_SP_OUTPUT_YUV422,
253 }, {
254 .fourcc = V4L2_PIX_FMT_YUV422M,
255 .fmt_type = FMT_YUV,
256 .bpp = { 8, 8, 8 },
257 .cplanes = 3,
258 .mplanes = 3,
259 .uv_swap = 0,
260 .write_format = MI_CTRL_SP_WRITE_PLA,
261 .output_format = MI_CTRL_SP_OUTPUT_YUV422,
262 },
263 /* yuv420 */
264 {
265 .fourcc = V4L2_PIX_FMT_NV21,
266 .fmt_type = FMT_YUV,
267 .bpp = { 8, 16 },
268 .cplanes = 2,
269 .mplanes = 1,
270 .uv_swap = 1,
271 .write_format = MI_CTRL_SP_WRITE_SPLA,
272 .output_format = MI_CTRL_SP_OUTPUT_YUV420,
273 }, {
274 .fourcc = V4L2_PIX_FMT_NV12,
275 .fmt_type = FMT_YUV,
276 .bpp = { 8, 16 },
277 .cplanes = 2,
278 .mplanes = 1,
279 .uv_swap = 0,
280 .write_format = MI_CTRL_SP_WRITE_SPLA,
281 .output_format = MI_CTRL_SP_OUTPUT_YUV420,
282 }, {
283 .fourcc = V4L2_PIX_FMT_NV21M,
284 .fmt_type = FMT_YUV,
285 .bpp = { 8, 16 },
286 .cplanes = 2,
287 .mplanes = 2,
288 .uv_swap = 1,
289 .write_format = MI_CTRL_SP_WRITE_SPLA,
290 .output_format = MI_CTRL_SP_OUTPUT_YUV420,
291 }, {
292 .fourcc = V4L2_PIX_FMT_NV12M,
293 .fmt_type = FMT_YUV,
294 .bpp = { 8, 16 },
295 .cplanes = 2,
296 .mplanes = 2,
297 .uv_swap = 0,
298 .write_format = MI_CTRL_SP_WRITE_SPLA,
299 .output_format = MI_CTRL_SP_OUTPUT_YUV420,
300 }, {
301 .fourcc = V4L2_PIX_FMT_YUV420,
302 .fmt_type = FMT_YUV,
303 .bpp = { 8, 8, 8 },
304 .cplanes = 3,
305 .mplanes = 1,
306 .uv_swap = 0,
307 .write_format = MI_CTRL_SP_WRITE_PLA,
308 .output_format = MI_CTRL_SP_OUTPUT_YUV420,
309 },
310 /* yuv444 */
311 {
312 .fourcc = V4L2_PIX_FMT_YUV444M,
313 .fmt_type = FMT_YUV,
314 .bpp = { 8, 8, 8 },
315 .cplanes = 3,
316 .mplanes = 3,
317 .uv_swap = 0,
318 .write_format = MI_CTRL_SP_WRITE_PLA,
319 .output_format = MI_CTRL_SP_OUTPUT_YUV444,
320 },
321 /* yuv400 */
322 {
323 .fourcc = V4L2_PIX_FMT_GREY,
324 .fmt_type = FMT_YUV,
325 .bpp = { 8 },
326 .cplanes = 1,
327 .mplanes = 1,
328 .uv_swap = 0,
329 .write_format = MI_CTRL_SP_WRITE_PLA,
330 .output_format = MI_CTRL_SP_OUTPUT_YUV400,
331 },
332 /* rgb */
333 {
334 .fourcc = V4L2_PIX_FMT_XBGR32,
335 .fmt_type = FMT_RGB,
336 .bpp = { 32 },
337 .mplanes = 1,
338 .write_format = MI_CTRL_SP_WRITE_PLA,
339 .output_format = MI_CTRL_SP_OUTPUT_RGB888,
340 }, {
341 .fourcc = V4L2_PIX_FMT_RGB565,
342 .fmt_type = FMT_RGB,
343 .bpp = { 16 },
344 .mplanes = 1,
345 .write_format = MI_CTRL_SP_WRITE_PLA,
346 .output_format = MI_CTRL_SP_OUTPUT_RGB565,
347 },
348 /* fbcg */
349 {
350 .fourcc = V4L2_PIX_FMT_FBCG,
351 .fmt_type = FMT_FBCGAIN,
352 .bpp = { 8, 16 },
353 .cplanes = 2,
354 .mplanes = 2,
355 .uv_swap = 0,
356 .write_format = MI_CTRL_SP_WRITE_SPLA,
357 .output_format = MI_CTRL_SP_OUTPUT_YUV420,
358 }
359 };
360 static const struct capture_fmt dmatx_fmts[] = {
361 /* raw */
362 {
363 .fourcc = V4L2_PIX_FMT_SRGGB8,
364 .fmt_type = FMT_BAYER,
365 .bpp = { 8 },
366 .mplanes = 1,
367 }, {
368 .fourcc = V4L2_PIX_FMT_SGRBG8,
369 .fmt_type = FMT_BAYER,
370 .bpp = { 8 },
371 .mplanes = 1,
372 }, {
373 .fourcc = V4L2_PIX_FMT_SGBRG8,
374 .fmt_type = FMT_BAYER,
375 .bpp = { 8 },
376 .mplanes = 1,
377 }, {
378 .fourcc = V4L2_PIX_FMT_SBGGR8,
379 .fmt_type = FMT_BAYER,
380 .bpp = { 8 },
381 .mplanes = 1,
382 }, {
383 .fourcc = V4L2_PIX_FMT_GREY,
384 .fmt_type = FMT_BAYER,
385 .bpp = { 8 },
386 .mplanes = 1,
387 }, {
388 .fourcc = V4L2_PIX_FMT_SRGGB10,
389 .fmt_type = FMT_BAYER,
390 .bpp = { 10 },
391 .mplanes = 1,
392 }, {
393 .fourcc = V4L2_PIX_FMT_SGRBG10,
394 .fmt_type = FMT_BAYER,
395 .bpp = { 10 },
396 .mplanes = 1,
397 }, {
398 .fourcc = V4L2_PIX_FMT_SGBRG10,
399 .fmt_type = FMT_BAYER,
400 .bpp = { 10 },
401 .mplanes = 1,
402 }, {
403 .fourcc = V4L2_PIX_FMT_SBGGR10,
404 .fmt_type = FMT_BAYER,
405 .bpp = { 10 },
406 .mplanes = 1,
407 }, {
408 .fourcc = V4L2_PIX_FMT_Y10,
409 .fmt_type = FMT_BAYER,
410 .bpp = { 10 },
411 .mplanes = 1,
412 }, {
413 .fourcc = V4L2_PIX_FMT_SRGGB12,
414 .fmt_type = FMT_BAYER,
415 .bpp = { 12 },
416 .mplanes = 1,
417 }, {
418 .fourcc = V4L2_PIX_FMT_SGRBG12,
419 .fmt_type = FMT_BAYER,
420 .bpp = { 12 },
421 .mplanes = 1,
422 }, {
423 .fourcc = V4L2_PIX_FMT_SGBRG12,
424 .fmt_type = FMT_BAYER,
425 .bpp = { 12 },
426 .mplanes = 1,
427 }, {
428 .fourcc = V4L2_PIX_FMT_SBGGR12,
429 .fmt_type = FMT_BAYER,
430 .bpp = { 12 },
431 .mplanes = 1,
432 }, {
433 .fourcc = V4L2_PIX_FMT_Y12,
434 .fmt_type = FMT_BAYER,
435 .bpp = { 12 },
436 .mplanes = 1,
437 }, {
438 .fourcc = V4L2_PIX_FMT_YUYV,
439 .fmt_type = FMT_YUV,
440 .bpp = { 16 },
441 .mplanes = 1,
442 }, {
443 .fourcc = V4L2_PIX_FMT_YVYU,
444 .fmt_type = FMT_YUV,
445 .bpp = { 16 },
446 .mplanes = 1,
447 }, {
448 .fourcc = V4L2_PIX_FMT_UYVY,
449 .fmt_type = FMT_YUV,
450 .bpp = { 16 },
451 .mplanes = 1,
452 }, {
453 .fourcc = V4L2_PIX_FMT_VYUY,
454 .fmt_type = FMT_YUV,
455 .bpp = { 16 },
456 .mplanes = 1,
457 }, {
458 .fourcc = V4l2_PIX_FMT_EBD8,
459 .fmt_type = FMT_EBD,
460 .bpp = { 8 },
461 .mplanes = 1,
462 }, {
463 .fourcc = V4l2_PIX_FMT_SPD16,
464 .fmt_type = FMT_SPD,
465 .bpp = { 16 },
466 .mplanes = 1,
467 }
468 };
469
470 static struct stream_config rkisp2_dmatx0_stream_config = {
471 .fmts = dmatx_fmts,
472 .fmt_size = ARRAY_SIZE(dmatx_fmts),
473 .frame_end_id = MI_RAW0_WR_FRAME,
474 .mi = {
475 .y_size_init = MI_RAW0_WR_SIZE,
476 .y_base_ad_init = MI_RAW0_WR_BASE,
477 .y_base_ad_shd = MI_RAW0_WR_BASE_SHD,
478 .length = MI_RAW0_WR_LENGTH,
479 },
480 .dma = {
481 .ctrl = CSI2RX_RAW0_WR_CTRL,
482 .pic_size = CSI2RX_RAW0_WR_PIC_SIZE,
483 .pic_offs = CSI2RX_RAW0_WR_PIC_OFF,
484 },
485 };
486
487 static struct stream_config rkisp2_dmatx1_stream_config = {
488 .fmts = dmatx_fmts,
489 .fmt_size = ARRAY_SIZE(dmatx_fmts),
490 .frame_end_id = MI_RAW1_WR_FRAME,
491 .mi = {
492 .y_size_init = MI_RAW1_WR_SIZE,
493 .y_base_ad_init = MI_RAW1_WR_BASE,
494 .y_base_ad_shd = MI_RAW1_WR_BASE_SHD,
495 .length = MI_RAW1_WR_LENGTH,
496 },
497 .dma = {
498 .ctrl = CSI2RX_RAW1_WR_CTRL,
499 .pic_size = CSI2RX_RAW1_WR_PIC_SIZE,
500 .pic_offs = CSI2RX_RAW1_WR_PIC_OFF,
501 },
502 };
503
504 static struct stream_config rkisp2_dmatx2_stream_config = {
505 .fmts = dmatx_fmts,
506 .fmt_size = ARRAY_SIZE(dmatx_fmts),
507 .frame_end_id = MI_RAW2_WR_FRAME,
508 .mi = {
509 .y_size_init = MI_RAW2_WR_SIZE,
510 .y_base_ad_init = MI_RAW2_WR_BASE,
511 .y_base_ad_shd = MI_RAW2_WR_BASE_SHD,
512 .length = MI_RAW2_WR_LENGTH,
513 },
514 .dma = {
515 .ctrl = CSI2RX_RAW2_WR_CTRL,
516 .pic_size = CSI2RX_RAW2_WR_PIC_SIZE,
517 .pic_offs = CSI2RX_RAW2_WR_PIC_OFF,
518 },
519 };
520
521 static struct stream_config rkisp2_dmatx3_stream_config = {
522 .fmts = dmatx_fmts,
523 .fmt_size = ARRAY_SIZE(dmatx_fmts),
524 .frame_end_id = MI_RAW3_WR_FRAME,
525 .mi = {
526 .y_size_init = MI_RAW3_WR_SIZE,
527 .y_base_ad_init = MI_RAW3_WR_BASE,
528 .y_base_ad_shd = MI_RAW3_WR_BASE_SHD,
529 .length = MI_RAW3_WR_LENGTH,
530 },
531 .dma = {
532 .ctrl = CSI2RX_RAW3_WR_CTRL,
533 .pic_size = CSI2RX_RAW3_WR_PIC_SIZE,
534 .pic_offs = CSI2RX_RAW3_WR_PIC_OFF,
535 },
536 };
537
is_rdbk_stream(struct rkisp_stream * stream)538 static bool is_rdbk_stream(struct rkisp_stream *stream)
539 {
540 struct rkisp_device *dev = stream->ispdev;
541 bool en = false;
542
543 if ((dev->hdr.op_mode == HDR_RDBK_FRAME1 &&
544 stream->id == RKISP_STREAM_DMATX2) ||
545 (dev->hdr.op_mode == HDR_RDBK_FRAME2 &&
546 (stream->id == RKISP_STREAM_DMATX2 ||
547 stream->id == RKISP_STREAM_DMATX0)) ||
548 (dev->hdr.op_mode == HDR_RDBK_FRAME3 &&
549 (stream->id == RKISP_STREAM_DMATX2 ||
550 stream->id == RKISP_STREAM_DMATX1 ||
551 stream->id == RKISP_STREAM_DMATX0)))
552 en = true;
553 return en;
554 }
555
556 /* configure dual-crop unit */
rkisp_stream_config_dcrop(struct rkisp_stream * stream,bool async)557 static int rkisp_stream_config_dcrop(struct rkisp_stream *stream, bool async)
558 {
559 struct rkisp_device *dev = stream->ispdev;
560 struct v4l2_rect *dcrop = &stream->dcrop;
561 struct v4l2_rect *input_win;
562 u32 src_w, src_h;
563
564 /* dual-crop unit get data from isp */
565 input_win = rkisp_get_isp_sd_win(&dev->isp_sdev);
566 src_w = input_win->width;
567 src_h = input_win->height;
568
569 if (dev->isp_ver == ISP_V20 &&
570 dev->rd_mode == HDR_RDBK_FRAME1 &&
571 dev->isp_sdev.in_fmt.fmt_type == FMT_BAYER &&
572 dev->isp_sdev.out_fmt.fmt_type == FMT_YUV)
573 src_h += RKMODULE_EXTEND_LINE;
574
575 if (dcrop->width == src_w &&
576 dcrop->height == src_h &&
577 dcrop->left == 0 && dcrop->top == 0) {
578 rkisp_disable_dcrop(stream, async);
579 v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
580 "stream %d crop disabled\n", stream->id);
581 if (RKMODULE_EXTEND_LINE != 0) {
582 rkisp_write(dev, stream->config->dual_crop.h_size, src_w, false);
583 rkisp_write(dev, stream->config->dual_crop.v_size, src_h, false);
584 }
585 return 0;
586 }
587
588 rkisp_config_dcrop(stream, dcrop, async);
589
590 v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
591 "stream %d crop: %dx%d -> %dx%d\n", stream->id,
592 src_w, src_h, dcrop->width, dcrop->height);
593
594 return 0;
595 }
596
597 /* configure scale unit */
rkisp_stream_config_rsz(struct rkisp_stream * stream,bool async)598 static int rkisp_stream_config_rsz(struct rkisp_stream *stream, bool async)
599 {
600 struct rkisp_device *dev = stream->ispdev;
601 struct v4l2_pix_format_mplane output_fmt = stream->out_fmt;
602 struct capture_fmt *output_isp_fmt = &stream->out_isp_fmt;
603 struct ispsd_out_fmt *input_isp_fmt =
604 rkisp_get_ispsd_out_fmt(&dev->isp_sdev);
605 struct v4l2_rect in_y, in_c, out_y, out_c;
606 u32 xsubs_in = 1, ysubs_in = 1;
607 u32 xsubs_out = 1, ysubs_out = 1;
608
609 if (input_isp_fmt->fmt_type == FMT_BAYER ||
610 (dev->br_dev.en && stream->id != RKISP_STREAM_SP))
611 goto disable;
612
613 /* set input and output sizes for scale calculation */
614 in_y.width = stream->dcrop.width;
615 in_y.height = stream->dcrop.height;
616 out_y.width = output_fmt.width;
617 out_y.height = output_fmt.height;
618
619 /* The size of Cb,Cr are related to the format */
620 if (rkisp_mbus_code_xysubs(input_isp_fmt->mbus_code, &xsubs_in, &ysubs_in)) {
621 v4l2_err(&dev->v4l2_dev, "Not xsubs/ysubs found\n");
622 return -EINVAL;
623 }
624 in_c.width = in_y.width / xsubs_in;
625 in_c.height = in_y.height / ysubs_in;
626
627 if (output_isp_fmt->fmt_type == FMT_YUV || output_isp_fmt->fmt_type == FMT_FBCGAIN) {
628 rkisp_fcc_xysubs(output_isp_fmt->fourcc, &xsubs_out, &ysubs_out);
629 if (stream->id == RKISP_STREAM_SP &&
630 stream->out_isp_fmt.fmt_type == FMT_FBCGAIN &&
631 !(dev->br_dev.work_mode & ISP_ISPP_422)) {
632 xsubs_out = 2;
633 ysubs_out = 1;
634 }
635
636 out_c.width = out_y.width / xsubs_out;
637 out_c.height = out_y.height / ysubs_out;
638 } else {
639 out_c.width = out_y.width / xsubs_in;
640 out_c.height = out_y.height / ysubs_in;
641 }
642
643 if (in_c.width == out_c.width && in_c.height == out_c.height)
644 goto disable;
645
646 /* set RSZ input and output */
647 v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
648 "stream %d rsz/scale: %dx%d -> %dx%d\n",
649 stream->id, stream->dcrop.width, stream->dcrop.height,
650 output_fmt.width, output_fmt.height);
651 v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
652 "chroma scaling %dx%d -> %dx%d\n",
653 in_c.width, in_c.height, out_c.width, out_c.height);
654
655 /* calculate and set scale */
656 rkisp_config_rsz(stream, &in_y, &in_c, &out_y, &out_c, async);
657
658 if (rkisp_debug)
659 rkisp_dump_rsz_regs(stream);
660
661 return 0;
662
663 disable:
664 rkisp_disable_rsz(stream, async);
665
666 return 0;
667 }
668
669 /***************************** stream operations*******************************/
670
671 /*
672 * memory base addresses should be with respect
673 * to the burst alignment restriction for AXI.
674 */
calc_burst_len(struct rkisp_stream * stream)675 static u32 calc_burst_len(struct rkisp_stream *stream)
676 {
677 struct rkisp_device *dev = stream->ispdev;
678 u32 y_size = stream->out_fmt.plane_fmt[0].bytesperline *
679 stream->out_fmt.height;
680 u32 cb_size = stream->out_fmt.plane_fmt[1].sizeimage;
681 u32 cr_size = stream->out_fmt.plane_fmt[2].sizeimage;
682 u32 cb_offs, cr_offs;
683 u32 bus = 16, burst;
684 int i;
685
686 if (stream->out_isp_fmt.fmt_type == FMT_FBCGAIN)
687 y_size = ALIGN(y_size, 64);
688 /* y/c base addr: burstN * bus alignment */
689 cb_offs = y_size;
690 cr_offs = cr_size ? (cb_size + cb_offs) : 0;
691
692 if (!(cb_offs % (bus * 16)) &&
693 !(cr_offs % (bus * 16)))
694 burst = CIF_MI_CTRL_BURST_LEN_LUM_16 |
695 CIF_MI_CTRL_BURST_LEN_CHROM_16;
696 else if (!(cb_offs % (bus * 8)) &&
697 !(cr_offs % (bus * 8)))
698 burst = CIF_MI_CTRL_BURST_LEN_LUM_8 |
699 CIF_MI_CTRL_BURST_LEN_CHROM_8;
700 else
701 burst = CIF_MI_CTRL_BURST_LEN_LUM_4 |
702 CIF_MI_CTRL_BURST_LEN_CHROM_4;
703
704 if (cb_offs % (bus * 4) ||
705 cr_offs % (bus * 4))
706 v4l2_warn(&dev->v4l2_dev,
707 "%dx%d fmt:0x%x not support, should be %d aligned\n",
708 stream->out_fmt.width,
709 stream->out_fmt.height,
710 stream->out_fmt.pixelformat,
711 (cr_offs == 0) ? bus * 4 : bus * 16);
712
713 stream->burst = burst;
714 for (i = 0; i < RKISP_MAX_STREAM; i++)
715 if (burst > dev->cap_dev.stream[i].burst)
716 burst = dev->cap_dev.stream[i].burst;
717
718 if (stream->interlaced) {
719 if (!stream->out_fmt.width % (bus * 16))
720 stream->burst = CIF_MI_CTRL_BURST_LEN_LUM_16 |
721 CIF_MI_CTRL_BURST_LEN_CHROM_16;
722 else if (!stream->out_fmt.width % (bus * 8))
723 stream->burst = CIF_MI_CTRL_BURST_LEN_LUM_8 |
724 CIF_MI_CTRL_BURST_LEN_CHROM_8;
725 else
726 stream->burst = CIF_MI_CTRL_BURST_LEN_LUM_4 |
727 CIF_MI_CTRL_BURST_LEN_CHROM_4;
728 if (stream->out_fmt.width % (bus * 4))
729 v4l2_warn(&dev->v4l2_dev,
730 "interlaced: width should be %d aligned\n",
731 bus * 4);
732 burst = min(stream->burst, burst);
733 stream->burst = burst;
734 }
735
736 return burst;
737 }
738
739 /*
740 * configure memory interface for mainpath
741 * This should only be called when stream-on
742 */
mp_config_mi(struct rkisp_stream * stream)743 static int mp_config_mi(struct rkisp_stream *stream)
744 {
745 void __iomem *base = stream->ispdev->base_addr;
746
747 /*
748 * NOTE: plane_fmt[0].sizeimage is total size of all planes for single
749 * memory plane formats, so calculate the size explicitly.
750 */
751 mi_set_y_size(stream, stream->out_fmt.plane_fmt[0].bytesperline *
752 stream->out_fmt.height);
753 mi_set_cb_size(stream, stream->out_fmt.plane_fmt[1].sizeimage);
754 mi_set_cr_size(stream, stream->out_fmt.plane_fmt[2].sizeimage);
755 mi_frame_end_int_enable(stream);
756 if (stream->out_isp_fmt.uv_swap)
757 mp_set_uv_swap(base);
758
759 config_mi_ctrl(stream, calc_burst_len(stream));
760 mp_mi_ctrl_set_format(base, stream->out_isp_fmt.write_format);
761 mp_mi_ctrl_autoupdate_en(base);
762
763 /* set up first buffer */
764 mi_frame_end(stream, FRAME_INIT);
765 return 0;
766 }
767
mbus_code_sp_in_fmt(u32 in_mbus_code,u32 out_fourcc,u32 * format)768 static int mbus_code_sp_in_fmt(u32 in_mbus_code, u32 out_fourcc, u32 *format)
769 {
770 switch (in_mbus_code) {
771 case MEDIA_BUS_FMT_YUYV8_2X8:
772 *format = MI_CTRL_SP_INPUT_YUV422;
773 break;
774 default:
775 return -EINVAL;
776 }
777
778 /*
779 * Only SP can support output format of YCbCr4:0:0,
780 * and the input format of SP must be YCbCr4:0:0
781 * when outputting YCbCr4:0:0.
782 * The output format of isp is YCbCr4:2:2,
783 * so the CbCr data is discarded here.
784 */
785 if (out_fourcc == V4L2_PIX_FMT_GREY)
786 *format = MI_CTRL_SP_INPUT_YUV400;
787
788 return 0;
789 }
790
791 /*
792 * configure memory interface for selfpath
793 * This should only be called when stream-on
794 */
sp_config_mi(struct rkisp_stream * stream)795 static int sp_config_mi(struct rkisp_stream *stream)
796 {
797 void __iomem *base = stream->ispdev->base_addr;
798 struct rkisp_device *dev = stream->ispdev;
799 struct capture_fmt *output_isp_fmt = &stream->out_isp_fmt;
800 struct ispsd_out_fmt *input_isp_fmt =
801 rkisp_get_ispsd_out_fmt(&dev->isp_sdev);
802 u32 sp_in_fmt, output_format;
803
804 if (mbus_code_sp_in_fmt(input_isp_fmt->mbus_code,
805 output_isp_fmt->fourcc, &sp_in_fmt)) {
806 v4l2_err(&dev->v4l2_dev, "Can't find the input format\n");
807 return -EINVAL;
808 }
809
810 /*
811 * NOTE: plane_fmt[0].sizeimage is total size of all planes for single
812 * memory plane formats, so calculate the size explicitly.
813 */
814 mi_set_y_size(stream, stream->out_fmt.plane_fmt[0].bytesperline *
815 stream->out_fmt.height);
816 mi_set_cb_size(stream, stream->out_fmt.plane_fmt[1].sizeimage);
817 mi_set_cr_size(stream, stream->out_fmt.plane_fmt[2].sizeimage);
818
819 sp_set_y_width(base, stream->out_fmt.width);
820 if (stream->interlaced) {
821 stream->u.sp.vir_offs =
822 stream->out_fmt.plane_fmt[0].bytesperline;
823 sp_set_y_height(base, stream->out_fmt.height / 2);
824 sp_set_y_line_length(base, stream->u.sp.y_stride * 2);
825 } else {
826 sp_set_y_height(base, stream->out_fmt.height);
827 sp_set_y_line_length(base, stream->u.sp.y_stride);
828 }
829
830 mi_frame_end_int_enable(stream);
831 if (output_isp_fmt->uv_swap)
832 sp_set_uv_swap(base);
833
834 config_mi_ctrl(stream, calc_burst_len(stream));
835 output_format = output_isp_fmt->output_format;
836 if (stream->id == RKISP_STREAM_SP &&
837 stream->out_isp_fmt.fmt_type == FMT_FBCGAIN &&
838 !(dev->br_dev.work_mode & ISP_ISPP_422)) {
839 sp_in_fmt = MI_CTRL_SP_INPUT_YUV422;
840 output_format = MI_CTRL_SP_OUTPUT_YUV422;
841 sp_set_y_width(base, 0);
842 sp_set_y_line_length(base, ALIGN(stream->out_fmt.width, 16));
843 }
844
845 sp_mi_ctrl_set_format(base, stream->out_isp_fmt.write_format |
846 sp_in_fmt | output_format);
847
848 sp_mi_ctrl_autoupdate_en(base);
849
850 /* set up first buffer */
851 mi_frame_end(stream, FRAME_INIT);
852 return 0;
853 }
854
dmatx3_config_mi(struct rkisp_stream * stream)855 static int dmatx3_config_mi(struct rkisp_stream *stream)
856 {
857 void __iomem *base = stream->ispdev->base_addr;
858 struct rkisp_device *dev = stream->ispdev;
859 struct rkisp_csi_device *csi = &dev->csi_dev;
860 u32 in_size;
861 u8 vc;
862
863 if (!csi->sink[CSI_SRC_CH4 - 1].linked ||
864 stream->streaming)
865 return -EBUSY;
866
867 if (!dev->active_sensor ||
868 (dev->active_sensor &&
869 dev->active_sensor->mbus.type != V4L2_MBUS_CSI2_DPHY)) {
870 v4l2_err(&dev->v4l2_dev,
871 "only mipi sensor support rawwr3\n");
872 return -EINVAL;
873 }
874 atomic_set(&stream->sequence, 0);
875 in_size = stream->out_fmt.plane_fmt[0].sizeimage;
876 raw_wr_set_pic_size(stream,
877 stream->out_fmt.width,
878 stream->out_fmt.height);
879 raw_wr_set_pic_offs(stream, 0);
880
881 vc = csi->sink[CSI_SRC_CH4 - 1].index;
882 raw_wr_ctrl(stream,
883 SW_CSI_RAW_WR_CH_EN(vc) |
884 stream->memory |
885 SW_CSI_RAW_WR_EN_ORG);
886 mi_set_y_size(stream, in_size);
887 mi_frame_end(stream, FRAME_INIT);
888 mi_frame_end_int_enable(stream);
889 mi_wr_ctrl2(base, SW_RAW3_WR_AUTOUPD);
890 mi_raw_length(stream);
891 v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
892 "rawwr3 %dx%d ctrl:0x%x\n",
893 stream->out_fmt.width,
894 stream->out_fmt.height,
895 readl(base + CSI2RX_RAW3_WR_CTRL));
896 return 0;
897 }
898
dmatx2_config_mi(struct rkisp_stream * stream)899 static int dmatx2_config_mi(struct rkisp_stream *stream)
900 {
901 void __iomem *base = stream->ispdev->base_addr;
902 struct rkisp_device *dev = stream->ispdev;
903 struct rkisp_csi_device *csi = &dev->csi_dev;
904 u32 val, in_size;
905 u8 vc;
906
907 if (!csi->sink[CSI_SRC_CH3 - 1].linked ||
908 stream->streaming)
909 return -EBUSY;
910
911 if (!dev->active_sensor ||
912 (dev->active_sensor &&
913 dev->active_sensor->mbus.type != V4L2_MBUS_CSI2_DPHY)) {
914 v4l2_err(&dev->v4l2_dev,
915 "only mipi sensor support rawwr2 path\n");
916 return -EINVAL;
917 }
918
919 if (!stream->u.dmatx.is_config) {
920 atomic_set(&stream->sequence, 0);
921 in_size = stream->out_fmt.plane_fmt[0].sizeimage;
922 raw_wr_set_pic_size(stream,
923 stream->out_fmt.width,
924 stream->out_fmt.height);
925 raw_wr_set_pic_offs(stream, 0);
926 vc = csi->sink[CSI_SRC_CH3 - 1].index;
927 val = SW_CSI_RAW_WR_CH_EN(vc);
928 val |= stream->memory;
929 if (dev->hdr.op_mode != HDR_NORMAL)
930 val |= SW_CSI_RAW_WR_EN_ORG;
931 raw_wr_ctrl(stream, val);
932 mi_set_y_size(stream, in_size);
933 mi_frame_end(stream, FRAME_INIT);
934 mi_frame_end_int_enable(stream);
935 mi_wr_ctrl2(base, SW_RAW2_WR_AUTOUPD);
936 mi_raw_length(stream);
937 stream->u.dmatx.is_config = true;
938 }
939 return 0;
940 }
941
dmatx1_config_mi(struct rkisp_stream * stream)942 static int dmatx1_config_mi(struct rkisp_stream *stream)
943 {
944 void __iomem *base = stream->ispdev->base_addr;
945 struct rkisp_device *dev = stream->ispdev;
946 struct rkisp_csi_device *csi = &dev->csi_dev;
947 u32 val, in_size;
948 u8 vc;
949
950 if (!csi->sink[CSI_SRC_CH2 - 1].linked ||
951 stream->streaming)
952 return -EBUSY;
953
954 if (!dev->active_sensor ||
955 (dev->active_sensor &&
956 dev->active_sensor->mbus.type != V4L2_MBUS_CSI2_DPHY)) {
957 if (stream->id == RKISP_STREAM_DMATX1)
958 v4l2_err(&dev->v4l2_dev,
959 "only mipi sensor support dmatx1 path\n");
960 return -EINVAL;
961 }
962
963 if (!stream->u.dmatx.is_config) {
964 atomic_set(&stream->sequence, 0);
965 in_size = stream->out_fmt.plane_fmt[0].sizeimage;
966 raw_wr_set_pic_size(stream,
967 stream->out_fmt.width,
968 stream->out_fmt.height);
969 raw_wr_set_pic_offs(stream, 0);
970 vc = csi->sink[CSI_SRC_CH2 - 1].index;
971 val = SW_CSI_RAW_WR_CH_EN(vc);
972 val |= stream->memory;
973 if (dev->hdr.op_mode != HDR_NORMAL)
974 val |= SW_CSI_RAW_WR_EN_ORG;
975 raw_wr_ctrl(stream, val);
976 mi_set_y_size(stream, in_size);
977 mi_frame_end(stream, FRAME_INIT);
978 mi_frame_end_int_enable(stream);
979 mi_wr_ctrl2(base, SW_RAW1_WR_AUTOUPD);
980 mi_raw_length(stream);
981 stream->u.dmatx.is_config = true;
982 }
983 return 0;
984 }
985
dmatx0_config_mi(struct rkisp_stream * stream)986 static int dmatx0_config_mi(struct rkisp_stream *stream)
987 {
988 void __iomem *base = stream->ispdev->base_addr;
989 struct rkisp_device *dev = stream->ispdev;
990 struct rkisp_csi_device *csi = &dev->csi_dev;
991 struct rkisp_stream *dmatx =
992 &dev->cap_dev.stream[RKISP_STREAM_DMATX0];
993 u32 val, in_size;
994 u8 vc;
995
996 if (!csi->sink[CSI_SRC_CH1 - 1].linked ||
997 dmatx->streaming)
998 return -EBUSY;
999
1000 if (!dev->active_sensor ||
1001 (dev->active_sensor &&
1002 dev->active_sensor->mbus.type != V4L2_MBUS_CSI2_DPHY)) {
1003 if (stream->id == RKISP_STREAM_DMATX0)
1004 v4l2_err(&dev->v4l2_dev,
1005 "only mipi sensor support rawwr0 path\n");
1006 return -EINVAL;
1007 }
1008
1009 in_size = dmatx->out_fmt.plane_fmt[0].sizeimage;
1010 if (!stream->u.dmatx.is_config) {
1011 if (dmatx->u.dmatx.is_config)
1012 return 0;
1013 atomic_set(&dmatx->sequence, 0);
1014 raw_wr_set_pic_size(dmatx,
1015 dmatx->out_fmt.width,
1016 dmatx->out_fmt.height);
1017 raw_wr_set_pic_offs(dmatx, 0);
1018 vc = csi->sink[CSI_SRC_CH1 - 1].index;
1019 val = SW_CSI_RAW_WR_CH_EN(vc);
1020 val |= stream->memory;
1021 if (dev->hdr.op_mode != HDR_NORMAL)
1022 val |= SW_CSI_RAW_WR_EN_ORG;
1023 raw_wr_ctrl(dmatx, val);
1024 mi_set_y_size(dmatx, in_size);
1025 mi_frame_end(dmatx, FRAME_INIT);
1026 mi_frame_end_int_enable(dmatx);
1027 mi_wr_ctrl2(base, SW_RAW0_WR_AUTOUPD);
1028 mi_raw_length(stream);
1029 dmatx->u.dmatx.is_config = true;
1030 }
1031
1032 return 0;
1033 }
1034
mp_enable_mi(struct rkisp_stream * stream)1035 static void mp_enable_mi(struct rkisp_stream *stream)
1036 {
1037 void __iomem *base = stream->ispdev->base_addr;
1038 struct capture_fmt *isp_fmt = &stream->out_isp_fmt;
1039
1040 mi_ctrl_mp_disable(base);
1041 if (isp_fmt->fmt_type == FMT_BAYER)
1042 mi_ctrl_mpraw_enable(base);
1043 else if (isp_fmt->fmt_type == FMT_YUV)
1044 mi_ctrl_mpyuv_enable(base);
1045 }
1046
sp_enable_mi(struct rkisp_stream * stream)1047 static void sp_enable_mi(struct rkisp_stream *stream)
1048 {
1049 void __iomem *base = stream->ispdev->base_addr;
1050
1051 mi_ctrl_spyuv_enable(base);
1052 }
1053
dmatx_enable_mi(struct rkisp_stream * stream)1054 static void dmatx_enable_mi(struct rkisp_stream *stream)
1055 {
1056 raw_wr_enable(stream);
1057 }
1058
mp_disable_mi(struct rkisp_stream * stream)1059 static void mp_disable_mi(struct rkisp_stream *stream)
1060 {
1061 struct rkisp_device *dev = stream->ispdev;
1062 void __iomem *base = dev->base_addr;
1063
1064 mi_ctrl_mp_disable(base);
1065 hdr_stop_dmatx(dev);
1066 }
1067
sp_disable_mi(struct rkisp_stream * stream)1068 static void sp_disable_mi(struct rkisp_stream *stream)
1069 {
1070 void __iomem *base = stream->ispdev->base_addr;
1071
1072 mi_ctrl_spyuv_disable(base);
1073 }
1074
update_dmatx_v2(struct rkisp_stream * stream)1075 static void update_dmatx_v2(struct rkisp_stream *stream)
1076 {
1077 struct rkisp_device *dev = stream->ispdev;
1078 void __iomem *base = dev->base_addr;
1079 struct rkisp_dummy_buffer *buf = NULL;
1080 u8 index;
1081
1082 if (stream->next_buf) {
1083 mi_set_y_addr(stream,
1084 stream->next_buf->buff_addr[RKISP_PLANE_Y]);
1085 } else {
1086 if (stream->id == RKISP_STREAM_DMATX0)
1087 index = dev->hdr.index[HDR_DMA0];
1088 else if (stream->id == RKISP_STREAM_DMATX1)
1089 index = dev->hdr.index[HDR_DMA1];
1090 else if (stream->id == RKISP_STREAM_DMATX2)
1091 index = dev->hdr.index[HDR_DMA2];
1092
1093 if ((stream->id == RKISP_STREAM_DMATX0 ||
1094 stream->id == RKISP_STREAM_DMATX1 ||
1095 stream->id == RKISP_STREAM_DMATX2)) {
1096 buf = hdr_dqbuf(&dev->hdr.q_tx[index]);
1097 if (IS_HDR_RDBK(dev->hdr.op_mode) &&
1098 !dev->dmarx_dev.trigger)
1099 hdr_qbuf(&dev->hdr.q_rx[index], buf);
1100 else
1101 hdr_qbuf(&dev->hdr.q_tx[index], buf);
1102 }
1103 if (!buf && dev->hw_dev->dummy_buf.mem_priv) {
1104 buf = &dev->hw_dev->dummy_buf;
1105 stream->dbg.frameloss++;
1106 }
1107 if (buf)
1108 mi_set_y_addr(stream, buf->dma_addr);
1109 }
1110 v4l2_dbg(2, rkisp_debug, &dev->v4l2_dev,
1111 "%s stream:%d Y:0x%x SHD:0x%x\n",
1112 __func__, stream->id,
1113 readl(base + stream->config->mi.y_base_ad_init),
1114 readl(base + stream->config->mi.y_base_ad_shd));
1115 }
1116
1117 /* Update buffer info to memory interface, it's called in interrupt */
update_mi(struct rkisp_stream * stream)1118 static void update_mi(struct rkisp_stream *stream)
1119 {
1120 struct rkisp_dummy_buffer *dummy_buf = &stream->ispdev->hw_dev->dummy_buf;
1121 void __iomem *base = stream->ispdev->base_addr;
1122
1123 /* The dummy space allocated by dma_alloc_coherent is used, we can
1124 * throw data to it if there is no available buffer.
1125 */
1126 if (stream->next_buf) {
1127 mi_set_y_addr(stream,
1128 stream->next_buf->buff_addr[RKISP_PLANE_Y]);
1129 mi_set_cb_addr(stream,
1130 stream->next_buf->buff_addr[RKISP_PLANE_CB]);
1131 mi_set_cr_addr(stream,
1132 stream->next_buf->buff_addr[RKISP_PLANE_CR]);
1133 } else if (dummy_buf->mem_priv) {
1134 mi_set_y_addr(stream, dummy_buf->dma_addr);
1135 mi_set_cb_addr(stream, dummy_buf->dma_addr);
1136 mi_set_cr_addr(stream, dummy_buf->dma_addr);
1137 stream->dbg.frameloss++;
1138 }
1139
1140 mi_set_y_offset(stream, 0);
1141 mi_set_cb_offset(stream, 0);
1142 mi_set_cr_offset(stream, 0);
1143 v4l2_dbg(2, rkisp_debug, &stream->ispdev->v4l2_dev,
1144 "%s stream:%d Y:0x%x CB:0x%x CR:0x%x\n",
1145 __func__, stream->id,
1146 readl(base + stream->config->mi.y_base_ad_init),
1147 readl(base + stream->config->mi.cb_base_ad_init),
1148 readl(base + stream->config->mi.cr_base_ad_init));
1149 }
1150
mp_stop_mi(struct rkisp_stream * stream)1151 static void mp_stop_mi(struct rkisp_stream *stream)
1152 {
1153 if (!stream->streaming)
1154 return;
1155 mi_frame_end_int_clear(stream);
1156 stream->ops->disable_mi(stream);
1157 }
1158
sp_stop_mi(struct rkisp_stream * stream)1159 static void sp_stop_mi(struct rkisp_stream *stream)
1160 {
1161 if (!stream->streaming)
1162 return;
1163 mi_frame_end_int_clear(stream);
1164 stream->ops->disable_mi(stream);
1165 }
1166
dmatx_stop_mi(struct rkisp_stream * stream)1167 static void dmatx_stop_mi(struct rkisp_stream *stream)
1168 {
1169 struct rkisp_hw_dev *hw = stream->ispdev->hw_dev;
1170
1171 raw_wr_disable(stream);
1172 if (hw->dummy_buf.mem_priv)
1173 mi_set_y_addr(stream, hw->dummy_buf.dma_addr);
1174 stream->u.dmatx.is_config = false;
1175 }
1176
1177 static struct streams_ops rkisp_mp_streams_ops = {
1178 .config_mi = mp_config_mi,
1179 .enable_mi = mp_enable_mi,
1180 .disable_mi = mp_disable_mi,
1181 .stop_mi = mp_stop_mi,
1182 .set_data_path = stream_data_path,
1183 .is_stream_stopped = mp_is_stream_stopped,
1184 .update_mi = update_mi,
1185 .frame_end = mi_frame_end,
1186 };
1187
1188 static struct streams_ops rkisp_sp_streams_ops = {
1189 .config_mi = sp_config_mi,
1190 .enable_mi = sp_enable_mi,
1191 .disable_mi = sp_disable_mi,
1192 .stop_mi = sp_stop_mi,
1193 .set_data_path = stream_data_path,
1194 .is_stream_stopped = sp_is_stream_stopped,
1195 .update_mi = update_mi,
1196 .frame_end = mi_frame_end,
1197 };
1198
1199 static struct streams_ops rkisp2_dmatx0_streams_ops = {
1200 .config_mi = dmatx0_config_mi,
1201 .enable_mi = dmatx_enable_mi,
1202 .stop_mi = dmatx_stop_mi,
1203 .is_stream_stopped = dmatx0_is_stream_stopped,
1204 .update_mi = update_dmatx_v2,
1205 .frame_end = mi_frame_end,
1206 };
1207
1208 static struct streams_ops rkisp2_dmatx1_streams_ops = {
1209 .config_mi = dmatx1_config_mi,
1210 .enable_mi = dmatx_enable_mi,
1211 .stop_mi = dmatx_stop_mi,
1212 .is_stream_stopped = dmatx1_is_stream_stopped,
1213 .update_mi = update_dmatx_v2,
1214 .frame_end = mi_frame_end,
1215 };
1216
1217 static struct streams_ops rkisp2_dmatx2_streams_ops = {
1218 .config_mi = dmatx2_config_mi,
1219 .enable_mi = dmatx_enable_mi,
1220 .stop_mi = dmatx_stop_mi,
1221 .is_stream_stopped = dmatx2_is_stream_stopped,
1222 .update_mi = update_dmatx_v2,
1223 .frame_end = mi_frame_end,
1224 };
1225
1226 static struct streams_ops rkisp2_dmatx3_streams_ops = {
1227 .config_mi = dmatx3_config_mi,
1228 .enable_mi = dmatx_enable_mi,
1229 .stop_mi = dmatx_stop_mi,
1230 .is_stream_stopped = dmatx3_is_stream_stopped,
1231 .update_mi = update_dmatx_v2,
1232 .frame_end = mi_frame_end,
1233 };
1234
rdbk_frame_end(struct rkisp_stream * stream)1235 static void rdbk_frame_end(struct rkisp_stream *stream)
1236 {
1237 struct rkisp_device *isp_dev = stream->ispdev;
1238 struct rkisp_capture_device *cap = &isp_dev->cap_dev;
1239 struct rkisp_sensor_info *sensor = isp_dev->active_sensor;
1240 u32 denominator = sensor->fi.interval.denominator;
1241 u32 numerator = sensor->fi.interval.numerator;
1242 u64 l_ts, m_ts, s_ts;
1243 int ret, fps = -1, time = 30000000;
1244
1245 if (stream->id != RKISP_STREAM_DMATX2)
1246 return;
1247
1248 if (denominator && numerator)
1249 time = numerator * 1000 / denominator * 1000 * 1000;
1250
1251 if (isp_dev->hdr.op_mode == HDR_RDBK_FRAME3) {
1252 if (cap->rdbk_buf[RDBK_L] && cap->rdbk_buf[RDBK_M] &&
1253 cap->rdbk_buf[RDBK_S]) {
1254 l_ts = cap->rdbk_buf[RDBK_L]->vb.vb2_buf.timestamp;
1255 m_ts = cap->rdbk_buf[RDBK_M]->vb.vb2_buf.timestamp;
1256 s_ts = cap->rdbk_buf[RDBK_S]->vb.vb2_buf.timestamp;
1257
1258 if ((m_ts - l_ts) > time || (s_ts - m_ts) > time) {
1259 ret = v4l2_subdev_call(sensor->sd,
1260 video, g_frame_interval, &sensor->fi);
1261 if (!ret) {
1262 denominator = sensor->fi.interval.denominator;
1263 numerator = sensor->fi.interval.numerator;
1264 time = numerator * 1000 / denominator * 1000 * 1000;
1265 if (numerator)
1266 fps = denominator / numerator;
1267 }
1268 if ((m_ts - l_ts) > time || (s_ts - m_ts) > time) {
1269 v4l2_err(&isp_dev->v4l2_dev,
1270 "timestamp no match, s:%lld m:%lld l:%lld, fps:%d\n",
1271 s_ts, m_ts, l_ts, fps);
1272 goto RDBK_FRM_UNMATCH;
1273 }
1274 }
1275
1276 if (m_ts < l_ts || s_ts < m_ts) {
1277 v4l2_err(&isp_dev->v4l2_dev,
1278 "s/m/l frame err, timestamp s:%lld m:%lld l:%lld\n",
1279 s_ts, m_ts, l_ts);
1280 goto RDBK_FRM_UNMATCH;
1281 }
1282
1283 cap->rdbk_buf[RDBK_S]->vb.sequence = cap->rdbk_buf[RDBK_L]->vb.sequence;
1284 cap->rdbk_buf[RDBK_M]->vb.sequence = cap->rdbk_buf[RDBK_L]->vb.sequence;
1285 rkisp_stream_buf_done(&cap->stream[RKISP_STREAM_DMATX0], cap->rdbk_buf[RDBK_L]);
1286 rkisp_stream_buf_done(&cap->stream[RKISP_STREAM_DMATX1], cap->rdbk_buf[RDBK_M]);
1287 rkisp_stream_buf_done(stream, cap->rdbk_buf[RDBK_S]);
1288 } else {
1289 v4l2_err(&isp_dev->v4l2_dev, "lost long or middle frames\n");
1290 goto RDBK_FRM_UNMATCH;
1291 }
1292 } else if (isp_dev->hdr.op_mode == HDR_RDBK_FRAME2) {
1293 if (cap->rdbk_buf[RDBK_L] && cap->rdbk_buf[RDBK_S]) {
1294 l_ts = cap->rdbk_buf[RDBK_L]->vb.vb2_buf.timestamp;
1295 s_ts = cap->rdbk_buf[RDBK_S]->vb.vb2_buf.timestamp;
1296
1297 if ((s_ts - l_ts) > time) {
1298 ret = v4l2_subdev_call(sensor->sd,
1299 video, g_frame_interval, &sensor->fi);
1300 if (!ret) {
1301 denominator = sensor->fi.interval.denominator;
1302 numerator = sensor->fi.interval.numerator;
1303 time = numerator * 1000 / denominator * 1000 * 1000;
1304 if (numerator)
1305 fps = denominator / numerator;
1306 }
1307 if ((s_ts - l_ts) > time) {
1308 v4l2_err(&isp_dev->v4l2_dev,
1309 "timestamp no match, s:%lld l:%lld, fps:%d\n",
1310 s_ts, l_ts, fps);
1311 goto RDBK_FRM_UNMATCH;
1312 }
1313 }
1314
1315 if (s_ts < l_ts) {
1316 v4l2_err(&isp_dev->v4l2_dev,
1317 "s/l frame err, timestamp s:%lld l:%lld\n",
1318 s_ts, l_ts);
1319 goto RDBK_FRM_UNMATCH;
1320 }
1321
1322 cap->rdbk_buf[RDBK_S]->vb.sequence = cap->rdbk_buf[RDBK_L]->vb.sequence;
1323 rkisp_stream_buf_done(&cap->stream[RKISP_STREAM_DMATX0], cap->rdbk_buf[RDBK_L]);
1324 rkisp_stream_buf_done(stream, cap->rdbk_buf[RDBK_S]);
1325 } else {
1326 v4l2_err(&isp_dev->v4l2_dev, "lost long frames\n");
1327 goto RDBK_FRM_UNMATCH;
1328 }
1329 } else {
1330 rkisp_stream_buf_done(stream, cap->rdbk_buf[RDBK_S]);
1331 }
1332
1333 cap->rdbk_buf[RDBK_L] = NULL;
1334 cap->rdbk_buf[RDBK_M] = NULL;
1335 cap->rdbk_buf[RDBK_S] = NULL;
1336 return;
1337
1338 RDBK_FRM_UNMATCH:
1339 if (cap->rdbk_buf[RDBK_L])
1340 rkisp_buf_queue(&cap->rdbk_buf[RDBK_L]->vb.vb2_buf);
1341 if (cap->rdbk_buf[RDBK_M])
1342 rkisp_buf_queue(&cap->rdbk_buf[RDBK_M]->vb.vb2_buf);
1343 if (cap->rdbk_buf[RDBK_S])
1344 rkisp_buf_queue(&cap->rdbk_buf[RDBK_S]->vb.vb2_buf);
1345
1346 cap->rdbk_buf[RDBK_L] = NULL;
1347 cap->rdbk_buf[RDBK_M] = NULL;
1348 cap->rdbk_buf[RDBK_S] = NULL;
1349 }
1350
1351 /*
1352 * This function is called when a frame end come. The next frame
1353 * is processing and we should set up buffer for next-next frame,
1354 * otherwise it will overflow.
1355 */
mi_frame_end(struct rkisp_stream * stream,u32 state)1356 static int mi_frame_end(struct rkisp_stream *stream, u32 state)
1357 {
1358 struct rkisp_device *dev = stream->ispdev;
1359 struct rkisp_capture_device *cap = &dev->cap_dev;
1360 struct capture_fmt *isp_fmt = &stream->out_isp_fmt;
1361 bool interlaced = stream->interlaced;
1362 unsigned long lock_flags = 0;
1363 u64 ns = 0;
1364 int i = 0;
1365
1366 if (!stream->next_buf && stream->streaming &&
1367 dev->dmarx_dev.trigger == T_MANUAL &&
1368 is_rdbk_stream(stream))
1369 v4l2_info(&dev->v4l2_dev,
1370 "tx stream:%d lose frame:%d, isp state:0x%x frame:%d\n",
1371 stream->id, atomic_read(&stream->sequence) - 1,
1372 dev->isp_state, dev->dmarx_dev.cur_frame.id);
1373
1374 if (stream->curr_buf &&
1375 (!interlaced ||
1376 (stream->u.sp.field_rec == RKISP_FIELD_ODD &&
1377 stream->u.sp.field == RKISP_FIELD_EVEN))) {
1378 struct vb2_buffer *vb2_buf = &stream->curr_buf->vb.vb2_buf;
1379
1380 /* Dequeue a filled buffer */
1381 for (i = 0; i < isp_fmt->mplanes; i++) {
1382 u32 payload_size =
1383 stream->out_fmt.plane_fmt[i].sizeimage;
1384 vb2_set_plane_payload(vb2_buf, i, payload_size);
1385 }
1386 if (stream->id == RKISP_STREAM_MP ||
1387 stream->id == RKISP_STREAM_SP)
1388 rkisp_dmarx_get_frame(dev,
1389 &stream->curr_buf->vb.sequence,
1390 NULL, &ns, true);
1391 else
1392 stream->curr_buf->vb.sequence =
1393 atomic_read(&stream->sequence) - 1;
1394 if (!ns)
1395 ns = ktime_get_ns();
1396 vb2_buf->timestamp = ns;
1397
1398 ns = ktime_get_ns();
1399 stream->dbg.interval = ns - stream->dbg.timestamp;
1400 stream->dbg.timestamp = ns;
1401 stream->dbg.id = stream->curr_buf->vb.sequence;
1402 if (stream->id == RKISP_STREAM_MP || stream->id == RKISP_STREAM_SP)
1403 stream->dbg.delay = ns - dev->isp_sdev.frm_timestamp;
1404
1405 if (!stream->streaming) {
1406 vb2_buffer_done(vb2_buf, VB2_BUF_STATE_ERROR);
1407 } else if (is_rdbk_stream(stream) &&
1408 dev->dmarx_dev.trigger == T_MANUAL) {
1409 if (stream->id == RKISP_STREAM_DMATX0) {
1410 if (cap->rdbk_buf[RDBK_L]) {
1411 v4l2_err(&dev->v4l2_dev,
1412 "multiple long data in hdr frame\n");
1413 rkisp_buf_queue(&cap->rdbk_buf[RDBK_L]->vb.vb2_buf);
1414 stream->dbg.frameloss++;
1415 }
1416 cap->rdbk_buf[RDBK_L] = stream->curr_buf;
1417 } else if (stream->id == RKISP_STREAM_DMATX1) {
1418 if (cap->rdbk_buf[RDBK_M]) {
1419 v4l2_err(&dev->v4l2_dev,
1420 "multiple middle data in hdr frame\n");
1421 rkisp_buf_queue(&cap->rdbk_buf[RDBK_M]->vb.vb2_buf);
1422 stream->dbg.frameloss++;
1423 }
1424 cap->rdbk_buf[RDBK_M] = stream->curr_buf;
1425 } else if (stream->id == RKISP_STREAM_DMATX2) {
1426 if (cap->rdbk_buf[RDBK_S]) {
1427 v4l2_err(&dev->v4l2_dev,
1428 "multiple short data in hdr frame\n");
1429 rkisp_buf_queue(&cap->rdbk_buf[RDBK_S]->vb.vb2_buf);
1430 stream->dbg.frameloss++;
1431 }
1432 cap->rdbk_buf[RDBK_S] = stream->curr_buf;
1433 rdbk_frame_end(stream);
1434 } else {
1435 rkisp_stream_buf_done(stream, stream->curr_buf);
1436 }
1437 } else {
1438 if (stream->id == RKISP_STREAM_SP && isp_fmt->fmt_type == FMT_FBCGAIN) {
1439 u32 sizeimage = vb2_plane_size(&stream->curr_buf->vb.vb2_buf, 0);
1440 u32 *buf = (u32 *)vb2_plane_vaddr(&stream->curr_buf->vb.vb2_buf, 0);
1441
1442 *(u64 *)(buf + sizeimage / 4 - 2) = ktime_get_ns();
1443 stream->curr_buf->dev_id = dev->dev_id;
1444 rkisp_bridge_save_spbuf(dev, stream->curr_buf);
1445 } else {
1446 rkisp_stream_buf_done(stream, stream->curr_buf);
1447 }
1448 }
1449
1450 stream->curr_buf = NULL;
1451 } else if (stream->id == RKISP_STREAM_SP && isp_fmt->fmt_type == FMT_FBCGAIN) {
1452 u32 frm_id;
1453
1454 rkisp_dmarx_get_frame(dev, &frm_id, NULL, &ns, true);
1455 v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
1456 "use dummy buffer, lost sp data, frm_id %d\n", frm_id);
1457 }
1458
1459 if (!interlaced ||
1460 (stream->curr_buf == stream->next_buf &&
1461 stream->u.sp.field == RKISP_FIELD_ODD)) {
1462 /* Next frame is writing to it
1463 * Interlaced: odd field next buffer address
1464 */
1465 stream->curr_buf = stream->next_buf;
1466 stream->next_buf = NULL;
1467
1468 /* Set up an empty buffer for the next-next frame */
1469 spin_lock_irqsave(&stream->vbq_lock, lock_flags);
1470 if (!list_empty(&stream->buf_queue)) {
1471 stream->next_buf =
1472 list_first_entry(&stream->buf_queue,
1473 struct rkisp_buffer,
1474 queue);
1475 list_del(&stream->next_buf->queue);
1476 }
1477 spin_unlock_irqrestore(&stream->vbq_lock, lock_flags);
1478 } else if (stream->u.sp.field_rec == RKISP_FIELD_ODD &&
1479 stream->u.sp.field == RKISP_FIELD_EVEN) {
1480 /* Interlaced: event field next buffer address */
1481 if (stream->next_buf) {
1482 stream->next_buf->buff_addr[RKISP_PLANE_Y] +=
1483 stream->u.sp.vir_offs;
1484 stream->next_buf->buff_addr[RKISP_PLANE_CB] +=
1485 stream->u.sp.vir_offs;
1486 stream->next_buf->buff_addr[RKISP_PLANE_CR] +=
1487 stream->u.sp.vir_offs;
1488 }
1489 stream->curr_buf = stream->next_buf;
1490 }
1491
1492 stream->ops->update_mi(stream);
1493
1494 if (interlaced)
1495 stream->u.sp.field_rec = stream->u.sp.field;
1496
1497 return 0;
1498 }
1499
1500 /***************************** vb2 operations*******************************/
1501
1502 /*
1503 * Set flags and wait, it should stop in interrupt.
1504 * If it didn't, stop it by force.
1505 */
rkisp_stream_stop(struct rkisp_stream * stream)1506 static void rkisp_stream_stop(struct rkisp_stream *stream)
1507 {
1508 struct rkisp_device *dev = stream->ispdev;
1509 struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
1510 int ret = 0;
1511
1512 if (!dev->dmarx_dev.trigger &&
1513 is_rdbk_stream(stream)) {
1514 stream->streaming = false;
1515 return;
1516 }
1517
1518 stream->stopping = true;
1519 stream->ops->stop_mi(stream);
1520 if ((dev->isp_state & ISP_START) &&
1521 dev->isp_inp != INP_DMARX_ISP &&
1522 !dev->hw_dev->is_shutdown) {
1523 ret = wait_event_timeout(stream->done,
1524 !stream->streaming,
1525 msecs_to_jiffies(1000));
1526 if (!ret)
1527 v4l2_warn(v4l2_dev, "%s id:%d timeout\n",
1528 __func__, stream->id);
1529 }
1530
1531 stream->stopping = false;
1532 stream->streaming = false;
1533
1534 if (stream->id == RKISP_STREAM_MP ||
1535 stream->id == RKISP_STREAM_SP) {
1536 rkisp_disable_dcrop(stream, true);
1537 rkisp_disable_rsz(stream, true);
1538 }
1539
1540 stream->burst =
1541 CIF_MI_CTRL_BURST_LEN_LUM_16 |
1542 CIF_MI_CTRL_BURST_LEN_CHROM_16;
1543 stream->interlaced = false;
1544 }
1545
1546 /*
1547 * Most of registers inside rockchip isp1 have shadow register since
1548 * they must be not changed during processing a frame.
1549 * Usually, each sub-module updates its shadow register after
1550 * processing the last pixel of a frame.
1551 */
rkisp_start(struct rkisp_stream * stream)1552 static int rkisp_start(struct rkisp_stream *stream)
1553 {
1554 struct rkisp_device *dev = stream->ispdev;
1555 int ret;
1556
1557 /* only MP support HDR mode, SP want to with HDR need
1558 * to start after MP.
1559 */
1560 if (stream->id == RKISP_STREAM_MP)
1561 hdr_config_dmatx(dev);
1562
1563 if (stream->ops->set_data_path)
1564 stream->ops->set_data_path(stream);
1565 ret = stream->ops->config_mi(stream);
1566 if (ret)
1567 return ret;
1568
1569 stream->ops->enable_mi(stream);
1570 stream->streaming = true;
1571
1572 return 0;
1573 }
1574
rkisp_queue_setup(struct vb2_queue * queue,unsigned int * num_buffers,unsigned int * num_planes,unsigned int sizes[],struct device * alloc_ctxs[])1575 static int rkisp_queue_setup(struct vb2_queue *queue,
1576 unsigned int *num_buffers,
1577 unsigned int *num_planes,
1578 unsigned int sizes[],
1579 struct device *alloc_ctxs[])
1580 {
1581 struct rkisp_stream *stream = queue->drv_priv;
1582 struct rkisp_device *dev = stream->ispdev;
1583 const struct v4l2_pix_format_mplane *pixm = NULL;
1584 const struct capture_fmt *isp_fmt = NULL;
1585 u32 i;
1586
1587 pixm = &stream->out_fmt;
1588 isp_fmt = &stream->out_isp_fmt;
1589 *num_planes = isp_fmt->mplanes;
1590
1591 for (i = 0; i < isp_fmt->mplanes; i++) {
1592 const struct v4l2_plane_pix_format *plane_fmt;
1593
1594 plane_fmt = &pixm->plane_fmt[i];
1595 /* height to align with 16 when allocating memory
1596 * so that Rockchip encoder can use DMA buffer directly
1597 */
1598 switch (isp_fmt->fmt_type) {
1599 case FMT_YUV:
1600 sizes[i] = plane_fmt->sizeimage / pixm->height * ALIGN(pixm->height, 16);
1601 break;
1602 case FMT_FBCGAIN:
1603 if (i == isp_fmt->mplanes - 1)
1604 sizes[i] = sizeof(struct isp2x_ispgain_buf);
1605 else
1606 sizes[i] = plane_fmt->sizeimage / pixm->height *
1607 ALIGN(pixm->height, 16) + RKISP_MOTION_DECT_TS_SIZE;
1608 break;
1609 default:
1610 sizes[i] = plane_fmt->sizeimage;
1611 }
1612
1613 }
1614
1615 rkisp_chk_tb_over(dev);
1616 v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev, "%s count %d, size %d\n",
1617 v4l2_type_names[queue->type], *num_buffers, sizes[0]);
1618
1619 return 0;
1620 }
1621
1622 /*
1623 * The vb2_buffer are stored in rkisp_buffer, in order to unify
1624 * mplane buffer and none-mplane buffer.
1625 */
rkisp_buf_queue(struct vb2_buffer * vb)1626 static void rkisp_buf_queue(struct vb2_buffer *vb)
1627 {
1628 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
1629 struct rkisp_buffer *ispbuf = to_rkisp_buffer(vbuf);
1630 struct vb2_queue *queue = vb->vb2_queue;
1631 struct rkisp_stream *stream = queue->drv_priv;
1632 unsigned long lock_flags = 0;
1633 struct v4l2_pix_format_mplane *pixm = &stream->out_fmt;
1634 struct capture_fmt *isp_fmt = &stream->out_isp_fmt;
1635 struct sg_table *sgt;
1636 u32 val;
1637 int i;
1638
1639 memset(ispbuf->buff_addr, 0, sizeof(ispbuf->buff_addr));
1640 for (i = 0; i < isp_fmt->mplanes; i++) {
1641 vb2_plane_vaddr(vb, i);
1642 if (stream->ispdev->hw_dev->is_dma_sg_ops) {
1643 sgt = vb2_dma_sg_plane_desc(vb, i);
1644 ispbuf->buff_addr[i] = sg_dma_address(sgt->sgl);
1645 } else {
1646 ispbuf->buff_addr[i] = vb2_dma_contig_plane_dma_addr(vb, i);
1647 }
1648 }
1649 /*
1650 * NOTE: plane_fmt[0].sizeimage is total size of all planes for single
1651 * memory plane formats, so calculate the size explicitly.
1652 */
1653 if (isp_fmt->mplanes == 1 || isp_fmt->fmt_type == FMT_FBCGAIN) {
1654 for (i = 0; i < isp_fmt->cplanes - 1; i++) {
1655 val = pixm->plane_fmt[i].bytesperline * pixm->height;
1656 if (isp_fmt->fmt_type == FMT_FBCGAIN)
1657 val = ALIGN(val, 64);
1658 ispbuf->buff_addr[i + 1] = (i == 0) ?
1659 ispbuf->buff_addr[i] + val :
1660 ispbuf->buff_addr[i] +
1661 pixm->plane_fmt[i].sizeimage;
1662 }
1663 }
1664
1665 v4l2_dbg(2, rkisp_debug, &stream->ispdev->v4l2_dev,
1666 "stream:%d queue buf:0x%x\n",
1667 stream->id, ispbuf->buff_addr[0]);
1668
1669 if (stream->ispdev->send_fbcgain && stream->id == RKISP_STREAM_SP)
1670 rkisp_bridge_sendtopp_buffer(stream->ispdev, stream->ispdev->dev_id, vb->index);
1671
1672 spin_lock_irqsave(&stream->vbq_lock, lock_flags);
1673 list_add_tail(&ispbuf->queue, &stream->buf_queue);
1674 spin_unlock_irqrestore(&stream->vbq_lock, lock_flags);
1675 }
1676
rkisp_create_dummy_buf(struct rkisp_stream * stream)1677 static int rkisp_create_dummy_buf(struct rkisp_stream *stream)
1678 {
1679 return rkisp_alloc_common_dummy_buf(stream->ispdev);
1680 }
1681
rkisp_destroy_dummy_buf(struct rkisp_stream * stream)1682 static void rkisp_destroy_dummy_buf(struct rkisp_stream *stream)
1683 {
1684 struct rkisp_device *dev = stream->ispdev;
1685
1686 hdr_destroy_buf(dev);
1687 rkisp_free_common_dummy_buf(dev);
1688 }
1689
destroy_buf_queue(struct rkisp_stream * stream,enum vb2_buffer_state state)1690 static void destroy_buf_queue(struct rkisp_stream *stream,
1691 enum vb2_buffer_state state)
1692 {
1693 struct rkisp_device *isp_dev = stream->ispdev;
1694 struct rkisp_capture_device *cap = &isp_dev->cap_dev;
1695 unsigned long lock_flags = 0;
1696 struct rkisp_buffer *buf;
1697
1698 spin_lock_irqsave(&stream->vbq_lock, lock_flags);
1699 if (cap->rdbk_buf[RDBK_L] && stream->id == RKISP_STREAM_DMATX0) {
1700 list_add_tail(&cap->rdbk_buf[RDBK_L]->queue,
1701 &stream->buf_queue);
1702 if (cap->rdbk_buf[RDBK_L] == stream->curr_buf)
1703 stream->curr_buf = NULL;
1704 if (cap->rdbk_buf[RDBK_L] == stream->next_buf)
1705 stream->next_buf = NULL;
1706 cap->rdbk_buf[RDBK_L] = NULL;
1707 }
1708 if (cap->rdbk_buf[RDBK_M] && stream->id == RKISP_STREAM_DMATX1) {
1709 list_add_tail(&cap->rdbk_buf[RDBK_M]->queue,
1710 &stream->buf_queue);
1711 if (cap->rdbk_buf[RDBK_M] == stream->curr_buf)
1712 stream->curr_buf = NULL;
1713 if (cap->rdbk_buf[RDBK_M] == stream->next_buf)
1714 stream->next_buf = NULL;
1715 cap->rdbk_buf[RDBK_M] = NULL;
1716 }
1717 if (cap->rdbk_buf[RDBK_S] && stream->id == RKISP_STREAM_DMATX2) {
1718 list_add_tail(&cap->rdbk_buf[RDBK_S]->queue,
1719 &stream->buf_queue);
1720 if (cap->rdbk_buf[RDBK_S] == stream->curr_buf)
1721 stream->curr_buf = NULL;
1722 if (cap->rdbk_buf[RDBK_S] == stream->next_buf)
1723 stream->next_buf = NULL;
1724 cap->rdbk_buf[RDBK_S] = NULL;
1725 }
1726 if (stream->curr_buf) {
1727 list_add_tail(&stream->curr_buf->queue, &stream->buf_queue);
1728 if (stream->curr_buf == stream->next_buf)
1729 stream->next_buf = NULL;
1730 stream->curr_buf = NULL;
1731 }
1732 if (stream->next_buf) {
1733 list_add_tail(&stream->next_buf->queue, &stream->buf_queue);
1734 stream->next_buf = NULL;
1735 }
1736 while (!list_empty(&stream->buf_queue)) {
1737 buf = list_first_entry(&stream->buf_queue,
1738 struct rkisp_buffer, queue);
1739 list_del(&buf->queue);
1740 vb2_buffer_done(&buf->vb.vb2_buf, state);
1741 }
1742 while (!list_empty(&stream->buf_done_list)) {
1743 buf = list_first_entry(&stream->buf_done_list,
1744 struct rkisp_buffer, queue);
1745 list_del(&buf->queue);
1746 vb2_buffer_done(&buf->vb.vb2_buf, state);
1747 }
1748 spin_unlock_irqrestore(&stream->vbq_lock, lock_flags);
1749 }
1750
rkisp_stop_streaming(struct vb2_queue * queue)1751 static void rkisp_stop_streaming(struct vb2_queue *queue)
1752 {
1753 struct rkisp_stream *stream = queue->drv_priv;
1754 struct rkisp_vdev_node *node = &stream->vnode;
1755 struct rkisp_device *dev = stream->ispdev;
1756 struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
1757 int ret;
1758
1759 mutex_lock(&dev->hw_dev->dev_lock);
1760
1761 v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
1762 "%s %d\n", __func__, stream->id);
1763
1764 if (stream->id != RKISP_STREAM_SP || stream->out_isp_fmt.fmt_type != FMT_FBCGAIN) {
1765 if (!stream->streaming)
1766 goto end;
1767 rkisp_stream_stop(stream);
1768 }
1769
1770 if (stream->id == RKISP_STREAM_MP ||
1771 (stream->id == RKISP_STREAM_SP && stream->out_isp_fmt.fmt_type != FMT_FBCGAIN)) {
1772 /* call to the other devices */
1773 media_pipeline_stop(&node->vdev.entity);
1774 ret = dev->pipe.set_stream(&dev->pipe, false);
1775 if (ret < 0)
1776 v4l2_err(v4l2_dev,
1777 "pipeline stream-off failed:%d\n", ret);
1778 }
1779
1780 rkisp_stop_spstream(stream);
1781
1782 /* release buffers */
1783 destroy_buf_queue(stream, VB2_BUF_STATE_ERROR);
1784
1785 ret = dev->pipe.close(&dev->pipe);
1786 if (ret < 0)
1787 v4l2_err(v4l2_dev, "pipeline close failed error:%d\n", ret);
1788 rkisp_destroy_dummy_buf(stream);
1789 atomic_dec(&dev->cap_dev.refcnt);
1790 stream->start_stream = false;
1791 tasklet_disable(&stream->buf_done_tasklet);
1792 end:
1793 mutex_unlock(&dev->hw_dev->dev_lock);
1794 }
1795
rkisp_stream_start(struct rkisp_stream * stream)1796 static int rkisp_stream_start(struct rkisp_stream *stream)
1797 {
1798 struct v4l2_device *v4l2_dev = &stream->ispdev->v4l2_dev;
1799 struct rkisp_device *dev = stream->ispdev;
1800 struct rkisp_stream *other = &dev->cap_dev.stream[stream->id ^ 1];
1801 bool async = false;
1802 int ret;
1803
1804 /* STREAM DMATX don't have rsz and dcrop */
1805 if (stream->id == RKISP_STREAM_DMATX0 ||
1806 stream->id == RKISP_STREAM_DMATX1 ||
1807 stream->id == RKISP_STREAM_DMATX2 ||
1808 stream->id == RKISP_STREAM_DMATX3)
1809 goto end;
1810
1811 if (other->streaming)
1812 async = true;
1813
1814 ret = rkisp_stream_config_rsz(stream, async);
1815 if (ret < 0) {
1816 v4l2_err(v4l2_dev, "config rsz failed with error %d\n", ret);
1817 return ret;
1818 }
1819
1820 /*
1821 * can't be async now, otherwise the latter started stream fails to
1822 * produce mi interrupt.
1823 */
1824 ret = rkisp_stream_config_dcrop(stream, false);
1825 if (ret < 0) {
1826 v4l2_err(v4l2_dev, "config dcrop failed with error %d\n", ret);
1827 return ret;
1828 }
1829
1830 end:
1831 return rkisp_start(stream);
1832 }
1833
1834 static int
rkisp_start_streaming(struct vb2_queue * queue,unsigned int count)1835 rkisp_start_streaming(struct vb2_queue *queue, unsigned int count)
1836 {
1837 struct rkisp_stream *stream = queue->drv_priv;
1838 struct rkisp_vdev_node *node = &stream->vnode;
1839 struct rkisp_device *dev = stream->ispdev;
1840 struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
1841 int ret = -1;
1842
1843 mutex_lock(&dev->hw_dev->dev_lock);
1844
1845 v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
1846 "%s %d\n", __func__, stream->id);
1847
1848 if (stream->id != RKISP_STREAM_SP || stream->out_isp_fmt.fmt_type != FMT_FBCGAIN) {
1849 if (WARN_ON(stream->streaming)) {
1850 mutex_unlock(&dev->hw_dev->dev_lock);
1851 return -EBUSY;
1852 }
1853 }
1854
1855 memset(&stream->dbg, 0, sizeof(stream->dbg));
1856 atomic_inc(&dev->cap_dev.refcnt);
1857 if (!dev->isp_inp || !stream->linked) {
1858 v4l2_err(v4l2_dev, "check video link or isp input\n");
1859 goto buffer_done;
1860 }
1861
1862 if (atomic_read(&dev->cap_dev.refcnt) == 1 &&
1863 (dev->isp_inp & INP_CSI || dev->isp_inp & INP_DVP)) {
1864 /* update sensor info when first streaming */
1865 ret = rkisp_update_sensor_info(dev);
1866 if (ret < 0) {
1867 v4l2_err(v4l2_dev,
1868 "update sensor info failed %d\n",
1869 ret);
1870 goto buffer_done;
1871 }
1872 }
1873
1874 if (dev->active_sensor &&
1875 dev->active_sensor->fmt[0].format.field ==
1876 V4L2_FIELD_INTERLACED) {
1877 if (stream->id != RKISP_STREAM_SP) {
1878 v4l2_err(v4l2_dev,
1879 "only selfpath support interlaced\n");
1880 ret = -EINVAL;
1881 goto buffer_done;
1882 }
1883 stream->interlaced = true;
1884 stream->u.sp.field = RKISP_FIELD_INVAL;
1885 stream->u.sp.field_rec = RKISP_FIELD_INVAL;
1886 }
1887
1888 ret = rkisp_create_dummy_buf(stream);
1889 if (ret < 0)
1890 goto buffer_done;
1891
1892 /* enable clocks/power-domains */
1893 ret = dev->pipe.open(&dev->pipe, &node->vdev.entity, true);
1894 if (ret < 0) {
1895 v4l2_err(v4l2_dev, "open cif pipeline failed %d\n", ret);
1896 goto destroy_dummy_buf;
1897 }
1898
1899 if (stream->id != RKISP_STREAM_SP ||
1900 (stream->id == RKISP_STREAM_SP && stream->out_isp_fmt.fmt_type != FMT_FBCGAIN)) {
1901 /* configure stream hardware to start */
1902 ret = rkisp_stream_start(stream);
1903 if (ret < 0) {
1904 v4l2_err(v4l2_dev, "start streaming failed\n");
1905 goto close_pipe;
1906 }
1907 }
1908
1909 if (stream->id == RKISP_STREAM_MP ||
1910 (stream->id == RKISP_STREAM_SP && stream->out_isp_fmt.fmt_type != FMT_FBCGAIN)) {
1911 /* start sub-devices */
1912 ret = dev->pipe.set_stream(&dev->pipe, true);
1913 if (ret < 0)
1914 goto stop_stream;
1915
1916 ret = media_pipeline_start(&node->vdev.entity, &dev->pipe.pipe);
1917 if (ret < 0) {
1918 v4l2_err(&dev->v4l2_dev,
1919 "start pipeline failed %d\n", ret);
1920 goto pipe_stream_off;
1921 }
1922 }
1923
1924 stream->start_stream = true;
1925 tasklet_enable(&stream->buf_done_tasklet);
1926 mutex_unlock(&dev->hw_dev->dev_lock);
1927 return 0;
1928
1929 pipe_stream_off:
1930 dev->pipe.set_stream(&dev->pipe, false);
1931 stop_stream:
1932 rkisp_stream_stop(stream);
1933 close_pipe:
1934 dev->pipe.close(&dev->pipe);
1935 destroy_dummy_buf:
1936 rkisp_destroy_dummy_buf(stream);
1937 buffer_done:
1938 destroy_buf_queue(stream, VB2_BUF_STATE_QUEUED);
1939 atomic_dec(&dev->cap_dev.refcnt);
1940 stream->streaming = false;
1941 mutex_unlock(&dev->hw_dev->dev_lock);
1942 return ret;
1943 }
1944
1945 static struct vb2_ops rkisp_vb2_ops = {
1946 .queue_setup = rkisp_queue_setup,
1947 .buf_queue = rkisp_buf_queue,
1948 .wait_prepare = vb2_ops_wait_prepare,
1949 .wait_finish = vb2_ops_wait_finish,
1950 .stop_streaming = rkisp_stop_streaming,
1951 .start_streaming = rkisp_start_streaming,
1952 };
1953
rkisp_init_vb2_queue(struct vb2_queue * q,struct rkisp_stream * stream,enum v4l2_buf_type buf_type)1954 static int rkisp_init_vb2_queue(struct vb2_queue *q,
1955 struct rkisp_stream *stream,
1956 enum v4l2_buf_type buf_type)
1957 {
1958 q->type = buf_type;
1959 q->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF;
1960 q->drv_priv = stream;
1961 q->ops = &rkisp_vb2_ops;
1962 q->mem_ops = stream->ispdev->hw_dev->mem_ops;
1963 q->buf_struct_size = sizeof(struct rkisp_buffer);
1964 q->min_buffers_needed = CIF_ISP_REQ_BUFS_MIN;
1965 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
1966 q->lock = &stream->apilock;
1967 q->dev = stream->ispdev->hw_dev->dev;
1968 q->allow_cache_hints = 1;
1969 q->bidirectional = 1;
1970 if (stream->ispdev->hw_dev->is_dma_contig)
1971 q->dma_attrs = DMA_ATTR_FORCE_CONTIGUOUS;
1972 q->gfp_flags = GFP_DMA32;
1973 return vb2_queue_init(q);
1974 }
1975
rkisp_stream_init(struct rkisp_device * dev,u32 id)1976 static int rkisp_stream_init(struct rkisp_device *dev, u32 id)
1977 {
1978 struct rkisp_capture_device *cap_dev = &dev->cap_dev;
1979 struct rkisp_stream *stream;
1980 struct video_device *vdev;
1981 struct rkisp_vdev_node *node;
1982 int ret = 0;
1983
1984 stream = &cap_dev->stream[id];
1985 stream->id = id;
1986 stream->ispdev = dev;
1987 vdev = &stream->vnode.vdev;
1988
1989 INIT_LIST_HEAD(&stream->buf_queue);
1990 init_waitqueue_head(&stream->done);
1991 spin_lock_init(&stream->vbq_lock);
1992
1993 stream->linked = true;
1994 /* isp2 disable MP/SP, enable BRIDGE default */
1995 if (id == RKISP_STREAM_MP)
1996 stream->linked = false;
1997
1998 switch (id) {
1999 case RKISP_STREAM_SP:
2000 strlcpy(vdev->name, SP_VDEV_NAME,
2001 sizeof(vdev->name));
2002 stream->ops = &rkisp_sp_streams_ops;
2003 stream->config = &rkisp_sp_stream_config;
2004 stream->config->fmts = sp_fmts;
2005 stream->config->fmt_size = ARRAY_SIZE(sp_fmts);
2006 break;
2007 case RKISP_STREAM_DMATX0:
2008 strlcpy(vdev->name, DMATX0_VDEV_NAME,
2009 sizeof(vdev->name));
2010 stream->ops = &rkisp2_dmatx0_streams_ops;
2011 stream->config = &rkisp2_dmatx0_stream_config;
2012 break;
2013 case RKISP_STREAM_DMATX1:
2014 strlcpy(vdev->name, DMATX1_VDEV_NAME,
2015 sizeof(vdev->name));
2016 stream->ops = &rkisp2_dmatx1_streams_ops;
2017 stream->config = &rkisp2_dmatx1_stream_config;
2018 break;
2019 case RKISP_STREAM_DMATX2:
2020 strlcpy(vdev->name, DMATX2_VDEV_NAME,
2021 sizeof(vdev->name));
2022 stream->ops = &rkisp2_dmatx2_streams_ops;
2023 stream->config = &rkisp2_dmatx2_stream_config;
2024 break;
2025 case RKISP_STREAM_DMATX3:
2026 strlcpy(vdev->name, DMATX3_VDEV_NAME,
2027 sizeof(vdev->name));
2028 stream->ops = &rkisp2_dmatx3_streams_ops;
2029 stream->config = &rkisp2_dmatx3_stream_config;
2030 break;
2031 default:
2032 strlcpy(vdev->name, MP_VDEV_NAME,
2033 sizeof(vdev->name));
2034 stream->ops = &rkisp_mp_streams_ops;
2035 stream->config = &rkisp_mp_stream_config;
2036 stream->config->fmts = mp_fmts;
2037 stream->config->fmt_size = ARRAY_SIZE(mp_fmts);
2038 }
2039
2040 node = vdev_to_node(vdev);
2041 rkisp_init_vb2_queue(&node->buf_queue, stream,
2042 V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
2043 ret = rkisp_register_stream_vdev(stream);
2044 if (ret < 0)
2045 return ret;
2046
2047 stream->streaming = false;
2048 stream->interlaced = false;
2049 stream->burst =
2050 CIF_MI_CTRL_BURST_LEN_LUM_16 |
2051 CIF_MI_CTRL_BURST_LEN_CHROM_16;
2052 atomic_set(&stream->sequence, 0);
2053 return 0;
2054 }
2055
rkisp_register_stream_v20(struct rkisp_device * dev)2056 int rkisp_register_stream_v20(struct rkisp_device *dev)
2057 {
2058 struct rkisp_capture_device *cap_dev = &dev->cap_dev;
2059 int ret;
2060
2061 ret = rkisp_stream_init(dev, RKISP_STREAM_MP);
2062 if (ret < 0)
2063 goto err;
2064 ret = rkisp_stream_init(dev, RKISP_STREAM_SP);
2065 if (ret < 0)
2066 goto err_free_mp;
2067 ret = rkisp_stream_init(dev, RKISP_STREAM_DMATX0);
2068 if (ret < 0)
2069 goto err_free_sp;
2070 ret = rkisp_stream_init(dev, RKISP_STREAM_DMATX1);
2071 if (ret < 0)
2072 goto err_free_tx0;
2073 ret = rkisp_stream_init(dev, RKISP_STREAM_DMATX2);
2074 if (ret < 0)
2075 goto err_free_tx1;
2076 ret = rkisp_stream_init(dev, RKISP_STREAM_DMATX3);
2077 if (ret < 0)
2078 goto err_free_tx2;
2079
2080 return 0;
2081 err_free_tx2:
2082 rkisp_unregister_stream_vdev(&cap_dev->stream[RKISP_STREAM_DMATX2]);
2083 err_free_tx1:
2084 rkisp_unregister_stream_vdev(&cap_dev->stream[RKISP_STREAM_DMATX1]);
2085 err_free_tx0:
2086 rkisp_unregister_stream_vdev(&cap_dev->stream[RKISP_STREAM_DMATX0]);
2087 err_free_sp:
2088 rkisp_unregister_stream_vdev(&cap_dev->stream[RKISP_STREAM_SP]);
2089 err_free_mp:
2090 rkisp_unregister_stream_vdev(&cap_dev->stream[RKISP_STREAM_MP]);
2091 err:
2092 return ret;
2093 }
2094
rkisp_unregister_stream_v20(struct rkisp_device * dev)2095 void rkisp_unregister_stream_v20(struct rkisp_device *dev)
2096 {
2097 struct rkisp_capture_device *cap_dev = &dev->cap_dev;
2098 struct rkisp_stream *stream;
2099
2100 stream = &cap_dev->stream[RKISP_STREAM_MP];
2101 rkisp_unregister_stream_vdev(stream);
2102 stream = &cap_dev->stream[RKISP_STREAM_SP];
2103 rkisp_unregister_stream_vdev(stream);
2104 stream = &cap_dev->stream[RKISP_STREAM_DMATX0];
2105 rkisp_unregister_stream_vdev(stream);
2106 stream = &cap_dev->stream[RKISP_STREAM_DMATX1];
2107 rkisp_unregister_stream_vdev(stream);
2108 stream = &cap_dev->stream[RKISP_STREAM_DMATX2];
2109 rkisp_unregister_stream_vdev(stream);
2110 stream = &cap_dev->stream[RKISP_STREAM_DMATX3];
2111 rkisp_unregister_stream_vdev(stream);
2112 }
2113
rkisp_spbuf_queue(struct rkisp_stream * stream,struct rkisp_buffer * sp_buf)2114 void rkisp_spbuf_queue(struct rkisp_stream *stream, struct rkisp_buffer *sp_buf)
2115 {
2116 unsigned long lock_flags = 0;
2117
2118 spin_lock_irqsave(&stream->vbq_lock, lock_flags);
2119 list_add_tail(&sp_buf->queue, &stream->buf_queue);
2120 spin_unlock_irqrestore(&stream->vbq_lock, lock_flags);
2121 }
2122
rkisp_start_spstream(struct rkisp_stream * stream)2123 int rkisp_start_spstream(struct rkisp_stream *stream)
2124 {
2125 struct rkisp_device *dev = stream->ispdev;
2126 struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
2127 int ret = -1;
2128
2129 dev->send_fbcgain = false;
2130 if (stream->id == RKISP_STREAM_SP && stream->out_isp_fmt.fmt_type == FMT_FBCGAIN) {
2131 /* configure stream hardware to start */
2132 ret = rkisp_stream_start(stream);
2133 if (ret < 0) {
2134 v4l2_err(v4l2_dev, "start streaming failed\n");
2135 return ret;
2136 }
2137 dev->send_fbcgain = true;
2138 }
2139
2140 return 0;
2141 }
2142
rkisp_stop_spstream(struct rkisp_stream * stream)2143 void rkisp_stop_spstream(struct rkisp_stream *stream)
2144 {
2145 struct rkisp_device *dev = stream->ispdev;
2146 unsigned long lock_flags = 0;
2147
2148 if (stream->id == RKISP_STREAM_SP && stream->out_isp_fmt.fmt_type == FMT_FBCGAIN) {
2149 rkisp_stream_stop(stream);
2150 rkisp_bridge_stop_spstream(dev);
2151 dev->send_fbcgain = false;
2152
2153 spin_lock_irqsave(&stream->vbq_lock, lock_flags);
2154 if (stream->curr_buf) {
2155 list_add_tail(&stream->curr_buf->queue, &stream->buf_queue);
2156 if (stream->curr_buf == stream->next_buf)
2157 stream->next_buf = NULL;
2158 stream->curr_buf = NULL;
2159 }
2160 if (stream->next_buf) {
2161 list_add_tail(&stream->next_buf->queue, &stream->buf_queue);
2162 stream->next_buf = NULL;
2163 }
2164 spin_unlock_irqrestore(&stream->vbq_lock, lock_flags);
2165 }
2166 }
2167
rkisp_update_spstream_buf(struct rkisp_stream * stream)2168 void rkisp_update_spstream_buf(struct rkisp_stream *stream)
2169 {
2170 if (stream->id == RKISP_STREAM_SP && stream->out_isp_fmt.fmt_type == FMT_FBCGAIN)
2171 mi_frame_end(stream, FRAME_INIT);
2172 }
2173
2174 /**************** Interrupter Handler ****************/
2175
rkisp_mi_v20_isr(u32 mis_val,struct rkisp_device * dev)2176 void rkisp_mi_v20_isr(u32 mis_val, struct rkisp_device *dev)
2177 {
2178 unsigned int i;
2179 static u8 end_tx0, end_tx1, end_tx2;
2180
2181 v4l2_dbg(3, rkisp_debug, &dev->v4l2_dev,
2182 "mi isr:0x%x\n", mis_val);
2183
2184 if (mis_val & CIF_MI_DMA_READY)
2185 rkisp_dmarx_isr(mis_val, dev);
2186
2187 for (i = 0; i < RKISP_MAX_STREAM; ++i) {
2188 struct rkisp_stream *stream = &dev->cap_dev.stream[i];
2189
2190 if (!(mis_val & CIF_MI_FRAME(stream)))
2191 continue;
2192
2193 if (i == RKISP_STREAM_DMATX0)
2194 end_tx0 = true;
2195 if (i == RKISP_STREAM_DMATX1)
2196 end_tx1 = true;
2197 if (i == RKISP_STREAM_DMATX2)
2198 end_tx2 = true;
2199 /* DMATX3 no csi frame end isr, mi isr instead */
2200 if (i == RKISP_STREAM_DMATX3)
2201 atomic_inc(&stream->sequence);
2202
2203 mi_frame_end_int_clear(stream);
2204
2205 if (stream->stopping) {
2206 /*
2207 * Make sure stream is actually stopped, whose state
2208 * can be read from the shadow register, before
2209 * wake_up() thread which would immediately free all
2210 * frame buffers. stop_mi() takes effect at the next
2211 * frame end that sync the configurations to shadow
2212 * regs.
2213 */
2214 if (stream->ops->is_stream_stopped(stream)) {
2215 stream->stopping = false;
2216 stream->streaming = false;
2217 wake_up(&stream->done);
2218 }
2219 if (i == RKISP_STREAM_MP) {
2220 end_tx0 = false;
2221 end_tx1 = false;
2222 end_tx2 = false;
2223 }
2224 } else {
2225 mi_frame_end(stream, FRAME_IRQ);
2226 if (dev->dmarx_dev.trigger == T_AUTO &&
2227 ((dev->hdr.op_mode == HDR_RDBK_FRAME1 && end_tx2) ||
2228 (dev->hdr.op_mode == HDR_RDBK_FRAME2 && end_tx2 && end_tx0) ||
2229 (dev->hdr.op_mode == HDR_RDBK_FRAME3 && end_tx2 && end_tx1 && end_tx0))) {
2230 end_tx0 = false;
2231 end_tx1 = false;
2232 end_tx2 = false;
2233 rkisp_trigger_read_back(dev, false, false, false);
2234 }
2235 }
2236 }
2237
2238 rkisp_bridge_isr(&mis_val, dev);
2239 }
2240
rkisp_mipi_v20_isr(unsigned int phy,unsigned int packet,unsigned int overflow,unsigned int state,struct rkisp_device * dev)2241 void rkisp_mipi_v20_isr(unsigned int phy, unsigned int packet,
2242 unsigned int overflow, unsigned int state,
2243 struct rkisp_device *dev)
2244 {
2245 struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
2246 struct rkisp_stream *stream;
2247 u32 packet_err = PACKET_ERR_F_BNDRY_MATCG | PACKET_ERR_F_SEQ |
2248 PACKET_ERR_FRAME_DATA | PACKET_ERR_ECC_1BIT |
2249 PACKET_ERR_ECC_2BIT | PACKET_ERR_CHECKSUM;
2250 u32 state_err = RAW_WR_SIZE_ERR | RAW_RD_SIZE_ERR;
2251 int i;
2252
2253 v4l2_dbg(3, rkisp_debug, &dev->v4l2_dev,
2254 "csi state:0x%x\n", state);
2255 dev->csi_dev.irq_cnt++;
2256 if (phy && (dev->isp_inp & INP_CSI) &&
2257 dev->csi_dev.err_cnt++ < RKISP_CONTI_ERR_MAX)
2258 v4l2_warn(v4l2_dev, "MIPI error: phy: 0x%08x\n", phy);
2259 if ((packet & packet_err) && (dev->isp_inp & INP_CSI) &&
2260 dev->csi_dev.err_cnt < RKISP_CONTI_ERR_MAX) {
2261 if (packet & 0xfff)
2262 dev->csi_dev.err_cnt++;
2263 v4l2_warn(v4l2_dev, "MIPI error: packet: 0x%08x\n", packet);
2264 }
2265 if (overflow &&
2266 dev->csi_dev.err_cnt++ < RKISP_CONTI_ERR_MAX)
2267 v4l2_warn(v4l2_dev, "MIPI error: overflow: 0x%08x\n", overflow);
2268 if (state & state_err)
2269 v4l2_warn(v4l2_dev, "MIPI error: size: 0x%08x\n", state);
2270 if (state & MIPI_DROP_FRM)
2271 v4l2_warn(v4l2_dev, "MIPI drop frame\n");
2272
2273 /* first Y_STATE irq as csi sof event */
2274 if (state & (RAW0_Y_STATE | RAW1_Y_STATE | RAW2_Y_STATE)) {
2275 for (i = 0; i < HDR_DMA_MAX; i++) {
2276 if (!((RAW0_Y_STATE << i) & state) ||
2277 dev->csi_dev.tx_first[i])
2278 continue;
2279 dev->csi_dev.tx_first[i] = true;
2280 rkisp_csi_sof(dev, i);
2281 stream = &dev->cap_dev.stream[i + RKISP_STREAM_DMATX0];
2282 atomic_inc(&stream->sequence);
2283 }
2284 }
2285 if (state & (RAW0_WR_FRAME | RAW1_WR_FRAME | RAW2_WR_FRAME)) {
2286 dev->csi_dev.err_cnt = 0;
2287 for (i = 0; i < HDR_DMA_MAX; i++) {
2288 if (!((RAW0_WR_FRAME << i) & state))
2289 continue;
2290 dev->csi_dev.tx_first[i] = false;
2291
2292 if (!IS_HDR_RDBK(dev->hdr.op_mode)) {
2293 stream = &dev->cap_dev.stream[i + RKISP_STREAM_DMATX0];
2294 atomic_inc(&stream->sequence);
2295 }
2296 }
2297 }
2298
2299 if (state & (RAW0_Y_STATE | RAW1_Y_STATE | RAW2_Y_STATE |
2300 RAW0_WR_FRAME | RAW1_WR_FRAME | RAW2_WR_FRAME))
2301 rkisp_luma_isr(&dev->luma_vdev, state);
2302
2303 if (dev->csi_dev.err_cnt > RKISP_CONTI_ERR_MAX) {
2304 if (!(dev->isp_state & ISP_MIPI_ERROR)) {
2305 dev->isp_state |= ISP_MIPI_ERROR;
2306 rkisp_write(dev, CSI2RX_MASK_PHY, 0, true);
2307 rkisp_write(dev, CSI2RX_MASK_PACKET, 0, true);
2308 rkisp_write(dev, CSI2RX_MASK_OVERFLOW, 0, true);
2309 if (dev->hw_dev->monitor.is_en) {
2310 if (!completion_done(&dev->hw_dev->monitor.cmpl))
2311 complete(&dev->hw_dev->monitor.cmpl);
2312 dev->hw_dev->monitor.state |= ISP_MIPI_ERROR;
2313 }
2314 }
2315 }
2316 }
2317