1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd. */
3
4 #include <linux/delay.h>
5 #include <linux/pm_runtime.h>
6 #include <media/v4l2-common.h>
7 #include <media/v4l2-event.h>
8 #include <media/v4l2-fh.h>
9 #include <media/v4l2-ioctl.h>
10 #include <media/v4l2-subdev.h>
11 #include <media/videobuf2-dma-contig.h>
12 #include <media/videobuf2-dma-sg.h>
13 #include <linux/dma-iommu.h>
14 #include "dev.h"
15 #include "regs.h"
16
17 #define CIF_ISP_REQ_BUFS_MIN 0
18
19 static const struct capture_fmt dmarx_fmts[] = {
20 /* bayer raw */
21 {
22 .fourcc = V4L2_PIX_FMT_SRGGB8,
23 .mbus_code = MEDIA_BUS_FMT_SRGGB8_1X8,
24 .fmt_type = FMT_BAYER,
25 .bpp = { 8 },
26 .mplanes = 1,
27 .write_format = CIF_MI_DMA_CTRL_READ_FMT_PACKED,
28 .output_format = CIF_MI_DMA_CTRL_RGB_BAYER_8BIT,
29 }, {
30 .fourcc = V4L2_PIX_FMT_SGRBG8,
31 .mbus_code = MEDIA_BUS_FMT_SGRBG8_1X8,
32 .fmt_type = FMT_BAYER,
33 .bpp = { 8 },
34 .mplanes = 1,
35 .write_format = CIF_MI_DMA_CTRL_READ_FMT_PACKED,
36 .output_format = CIF_MI_DMA_CTRL_RGB_BAYER_8BIT,
37 }, {
38 .fourcc = V4L2_PIX_FMT_SGBRG8,
39 .mbus_code = MEDIA_BUS_FMT_SGBRG8_1X8,
40 .fmt_type = FMT_BAYER,
41 .bpp = { 8 },
42 .mplanes = 1,
43 .write_format = CIF_MI_DMA_CTRL_READ_FMT_PACKED,
44 .output_format = CIF_MI_DMA_CTRL_RGB_BAYER_8BIT,
45 }, {
46 .fourcc = V4L2_PIX_FMT_SBGGR8,
47 .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8,
48 .fmt_type = FMT_BAYER,
49 .bpp = { 8 },
50 .mplanes = 1,
51 .write_format = CIF_MI_DMA_CTRL_READ_FMT_PACKED,
52 .output_format = CIF_MI_DMA_CTRL_RGB_BAYER_8BIT,
53 }, { /* 12bit used, 4 lower bits of LSB unused */
54 .fourcc = V4L2_PIX_FMT_SBGGR16,
55 .mbus_code = MEDIA_BUS_FMT_SBGGR12_1X12,
56 .fmt_type = FMT_BAYER,
57 .bpp = { 16 },
58 .mplanes = 1,
59 .write_format = CIF_MI_DMA_CTRL_READ_FMT_PACKED,
60 .output_format = CIF_MI_DMA_CTRL_RGB_BAYER_16BIT,
61 }, {
62 .fourcc = V4L2_PIX_FMT_YUYV,
63 .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8,
64 .fmt_type = FMT_YUV,
65 .bpp = { 16 },
66 .cplanes = 1,
67 .mplanes = 1,
68 .uv_swap = 0,
69 .write_format = CIF_MI_DMA_CTRL_READ_FMT_PACKED,
70 .output_format = CIF_MI_DMA_CTRL_FMT_YUV422,
71 }, {
72 .fourcc = V4L2_PIX_FMT_YVYU,
73 .mbus_code = MEDIA_BUS_FMT_YVYU8_2X8,
74 .fmt_type = FMT_YUV,
75 .bpp = { 16 },
76 .cplanes = 1,
77 .mplanes = 1,
78 .uv_swap = 0,
79 .write_format = CIF_MI_DMA_CTRL_READ_FMT_PACKED,
80 .output_format = CIF_MI_DMA_CTRL_FMT_YUV422,
81 }, {
82 .fourcc = V4L2_PIX_FMT_UYVY,
83 .mbus_code = MEDIA_BUS_FMT_UYVY8_2X8,
84 .fmt_type = FMT_YUV,
85 .bpp = { 16 },
86 .cplanes = 1,
87 .mplanes = 1,
88 .uv_swap = 0,
89 .write_format = CIF_MI_DMA_CTRL_READ_FMT_PACKED,
90 .output_format = CIF_MI_DMA_CTRL_FMT_YUV422,
91 }, {
92 .fourcc = V4L2_PIX_FMT_VYUY,
93 .mbus_code = MEDIA_BUS_FMT_VYUY8_2X8,
94 .fmt_type = FMT_YUV,
95 .bpp = { 16 },
96 .cplanes = 1,
97 .mplanes = 1,
98 .uv_swap = 0,
99 .write_format = CIF_MI_DMA_CTRL_READ_FMT_PACKED,
100 .output_format = CIF_MI_DMA_CTRL_FMT_YUV422,
101 }
102 };
103
104 static const struct capture_fmt rawrd_fmts[] = {
105 {
106 .fourcc = V4L2_PIX_FMT_SRGGB8,
107 .fmt_type = FMT_BAYER,
108 .bpp = { 8 },
109 .mplanes = 1,
110 }, {
111 .fourcc = V4L2_PIX_FMT_SGRBG8,
112 .fmt_type = FMT_BAYER,
113 .bpp = { 8 },
114 .mplanes = 1,
115 }, {
116 .fourcc = V4L2_PIX_FMT_SGBRG8,
117 .fmt_type = FMT_BAYER,
118 .bpp = { 8 },
119 .mplanes = 1,
120 }, {
121 .fourcc = V4L2_PIX_FMT_SBGGR8,
122 .fmt_type = FMT_BAYER,
123 .bpp = { 8 },
124 .mplanes = 1,
125 }, {
126 .fourcc = V4L2_PIX_FMT_GREY,
127 .fmt_type = FMT_BAYER,
128 .bpp = { 8 },
129 .mplanes = 1,
130 }, {
131 .fourcc = V4L2_PIX_FMT_SRGGB10,
132 .fmt_type = FMT_BAYER,
133 .bpp = { 10 },
134 .mplanes = 1,
135 }, {
136 .fourcc = V4L2_PIX_FMT_SGRBG10,
137 .fmt_type = FMT_BAYER,
138 .bpp = { 10 },
139 .mplanes = 1,
140 }, {
141 .fourcc = V4L2_PIX_FMT_SGBRG10,
142 .fmt_type = FMT_BAYER,
143 .bpp = { 10 },
144 .mplanes = 1,
145 }, {
146 .fourcc = V4L2_PIX_FMT_SBGGR10,
147 .fmt_type = FMT_BAYER,
148 .bpp = { 10 },
149 .mplanes = 1,
150 }, {
151 .fourcc = V4L2_PIX_FMT_Y10,
152 .fmt_type = FMT_BAYER,
153 .bpp = { 10 },
154 .mplanes = 1,
155 }, {
156 .fourcc = V4L2_PIX_FMT_SRGGB12,
157 .fmt_type = FMT_BAYER,
158 .bpp = { 12 },
159 .mplanes = 1,
160 }, {
161 .fourcc = V4L2_PIX_FMT_SGRBG12,
162 .fmt_type = FMT_BAYER,
163 .bpp = { 12 },
164 .mplanes = 1,
165 }, {
166 .fourcc = V4L2_PIX_FMT_SGBRG12,
167 .fmt_type = FMT_BAYER,
168 .bpp = { 12 },
169 .mplanes = 1,
170 }, {
171 .fourcc = V4L2_PIX_FMT_SBGGR12,
172 .fmt_type = FMT_BAYER,
173 .bpp = { 12 },
174 .mplanes = 1,
175 }, {
176 .fourcc = V4L2_PIX_FMT_Y12,
177 .fmt_type = FMT_BAYER,
178 .bpp = { 12 },
179 .mplanes = 1,
180 }, {
181 .fourcc = V4L2_PIX_FMT_YUYV,
182 .fmt_type = FMT_YUV,
183 .bpp = { 16 },
184 .mplanes = 1,
185 }, {
186 .fourcc = V4L2_PIX_FMT_YVYU,
187 .fmt_type = FMT_YUV,
188 .bpp = { 16 },
189 .mplanes = 1,
190 }, {
191 .fourcc = V4L2_PIX_FMT_UYVY,
192 .fmt_type = FMT_YUV,
193 .bpp = { 16 },
194 .mplanes = 1,
195 }, {
196 .fourcc = V4L2_PIX_FMT_VYUY,
197 .fmt_type = FMT_YUV,
198 .bpp = { 16 },
199 .mplanes = 1,
200 }
201 };
202
203 static struct stream_config rkisp_dmarx_stream_config = {
204 .fmts = dmarx_fmts,
205 .fmt_size = ARRAY_SIZE(dmarx_fmts),
206 .mi = {
207 .y_size_init = CIF_MI_DMA_Y_PIC_SIZE,
208 .y_base_ad_init = CIF_MI_DMA_Y_PIC_START_AD,
209 .cb_base_ad_init = CIF_MI_DMA_CB_PIC_START_AD,
210 .cr_base_ad_init = CIF_MI_DMA_CR_PIC_START_AD,
211 },
212 };
213
214 static struct stream_config rkisp2_dmarx0_stream_config = {
215 .fmts = rawrd_fmts,
216 .fmt_size = ARRAY_SIZE(rawrd_fmts),
217 .frame_end_id = RAW0_RD_FRAME,
218 .mi = {
219 .y_base_ad_init = MI_RAW0_RD_BASE,
220 .y_base_ad_shd = MI_RAW0_RD_BASE_SHD,
221 .length = MI_RAW0_RD_LENGTH,
222 },
223 };
224
225 static struct stream_config rkisp2_dmarx1_stream_config = {
226 .fmts = rawrd_fmts,
227 .fmt_size = ARRAY_SIZE(rawrd_fmts),
228 .frame_end_id = RAW1_RD_FRAME,
229 .mi = {
230 .y_base_ad_init = MI_RAW1_RD_BASE,
231 .y_base_ad_shd = MI_RAW1_RD_BASE_SHD,
232 .length = MI_RAW1_RD_LENGTH,
233 },
234 };
235
236 static struct stream_config rkisp2_dmarx2_stream_config = {
237 .fmts = rawrd_fmts,
238 .fmt_size = ARRAY_SIZE(rawrd_fmts),
239 .frame_end_id = RAW2_RD_FRAME,
240 .mi = {
241 .y_base_ad_init = MI_RAW2_RD_BASE,
242 .y_base_ad_shd = MI_RAW2_RD_BASE_SHD,
243 .length = MI_RAW2_RD_LENGTH,
244 },
245 };
246
247 static const
find_fmt(struct rkisp_stream * stream,const u32 pixelfmt)248 struct capture_fmt *find_fmt(struct rkisp_stream *stream,
249 const u32 pixelfmt)
250 {
251 const struct capture_fmt *fmt;
252 int i;
253
254 for (i = 0; i < stream->config->fmt_size; i++) {
255 fmt = &stream->config->fmts[i];
256 if (fmt->fourcc == pixelfmt)
257 return fmt;
258 }
259 return NULL;
260 }
261
dmarx_config_mi(struct rkisp_stream * stream)262 static int dmarx_config_mi(struct rkisp_stream *stream)
263 {
264 struct rkisp_device *dev = stream->ispdev;
265 void __iomem *base = dev->base_addr;
266 struct capture_fmt *dmarx_in_fmt = &stream->out_isp_fmt;
267
268 v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
269 "%s %dx%d y_stride:%d\n", __func__,
270 stream->out_fmt.width,
271 stream->out_fmt.height,
272 stream->u.dmarx.y_stride);
273
274 mi_set_y_size(stream, stream->out_fmt.width *
275 stream->out_fmt.height);
276 dmarx_set_y_width(base, stream->out_fmt.width);
277 dmarx_set_y_line_length(base, stream->u.dmarx.y_stride);
278
279 mi_dmarx_ready_enable(stream);
280 if (dmarx_in_fmt->uv_swap)
281 dmarx_set_uv_swap(base);
282
283 dmarx_ctrl(base,
284 dmarx_in_fmt->write_format |
285 dmarx_in_fmt->output_format |
286 CIF_MI_DMA_CTRL_BURST_LEN_LUM_16 |
287 CIF_MI_DMA_CTRL_BURST_LEN_CHROM_16);
288 return 0;
289 }
290
update_dmarx(struct rkisp_stream * stream)291 static void update_dmarx(struct rkisp_stream *stream)
292 {
293 void __iomem *base = stream->ispdev->base_addr;
294
295 if (stream->curr_buf) {
296 mi_set_y_addr(stream,
297 stream->curr_buf->buff_addr[RKISP_PLANE_Y]);
298 mi_set_cb_addr(stream,
299 stream->curr_buf->buff_addr[RKISP_PLANE_CB]);
300 mi_set_cr_addr(stream,
301 stream->curr_buf->buff_addr[RKISP_PLANE_CR]);
302 mi_dmarx_start(base);
303 stream->frame_end = false;
304 }
305 }
306
dmarx_stop_mi(struct rkisp_stream * stream)307 static void dmarx_stop_mi(struct rkisp_stream *stream)
308 {
309 mi_dmarx_ready_disable(stream);
310 }
311
312 static struct streams_ops rkisp_dmarx_streams_ops = {
313 .config_mi = dmarx_config_mi,
314 .stop_mi = dmarx_stop_mi,
315 .update_mi = update_dmarx,
316 };
317
rawrd_config_mi(struct rkisp_stream * stream)318 static int rawrd_config_mi(struct rkisp_stream *stream)
319 {
320 struct rkisp_device *dev = stream->ispdev;
321 bool is_unite = dev->hw_dev->is_unite;
322 u32 val;
323
324 val = rkisp_read(dev, CSI2RX_DATA_IDS_1, true);
325 val &= ~SW_CSI_ID0(0xff);
326 switch (stream->out_isp_fmt.fourcc) {
327 case V4L2_PIX_FMT_SRGGB8:
328 case V4L2_PIX_FMT_SBGGR8:
329 case V4L2_PIX_FMT_SGRBG8:
330 case V4L2_PIX_FMT_SGBRG8:
331 case V4L2_PIX_FMT_GREY:
332 val |= CIF_CSI2_DT_RAW8;
333 break;
334 case V4L2_PIX_FMT_SRGGB10:
335 case V4L2_PIX_FMT_SBGGR10:
336 case V4L2_PIX_FMT_SGRBG10:
337 case V4L2_PIX_FMT_SGBRG10:
338 case V4L2_PIX_FMT_Y10:
339 val |= CIF_CSI2_DT_RAW10;
340 break;
341 case V4L2_PIX_FMT_YUYV:
342 case V4L2_PIX_FMT_YVYU:
343 case V4L2_PIX_FMT_UYVY:
344 case V4L2_PIX_FMT_VYUY:
345 val |= CIF_CSI2_DT_YUV422_8b;
346 break;
347 default:
348 val |= CIF_CSI2_DT_RAW12;
349 }
350 rkisp_unite_write(dev, CSI2RX_RAW_RD_CTRL,
351 stream->memory << 2, false, is_unite);
352 rkisp_unite_write(dev, CSI2RX_DATA_IDS_1, val, false, is_unite);
353 rkisp_rawrd_set_pic_size(dev, stream->out_fmt.width,
354 stream->out_fmt.height);
355 mi_raw_length(stream);
356 v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
357 "%s id:%d 0x%x %dx%d\n", __func__,
358 stream->id, val,
359 stream->out_fmt.width,
360 stream->out_fmt.height);
361 return 0;
362 }
363
update_rawrd(struct rkisp_stream * stream)364 static void update_rawrd(struct rkisp_stream *stream)
365 {
366 struct rkisp_device *dev = stream->ispdev;
367 void __iomem *base = dev->base_addr;
368 struct capture_fmt *fmt = &stream->out_isp_fmt;
369 u32 val = 0;
370
371 if (stream->curr_buf) {
372 if (dev->vicap_in.merge_num > 1) {
373 val = stream->out_fmt.plane_fmt[0].bytesperline;
374 val /= dev->vicap_in.merge_num;
375 val *= dev->vicap_in.index;
376 }
377 val += stream->curr_buf->buff_addr[RKISP_PLANE_Y];
378 rkisp_write(dev, stream->config->mi.y_base_ad_init, val, false);
379 if (dev->hw_dev->is_unite) {
380 u32 offs = stream->out_fmt.width / 2 - RKMOUDLE_UNITE_EXTEND_PIXEL;
381
382 if (stream->memory)
383 offs *= DIV_ROUND_UP(fmt->bpp[0], 8);
384 else
385 offs = offs * fmt->bpp[0] / 8;
386 val += offs;
387 rkisp_next_write(dev, stream->config->mi.y_base_ad_init, val, false);
388 }
389 stream->frame_end = false;
390 if (stream->id == RKISP_STREAM_RAWRD2 && stream->out_isp_fmt.fmt_type == FMT_YUV) {
391 struct vb2_v4l2_buffer *vbuf = &stream->curr_buf->vb;
392 struct isp2x_csi_trigger trigger = {
393 .frame_timestamp = vbuf->vb2_buf.timestamp,
394 .sof_timestamp = vbuf->vb2_buf.timestamp,
395 .frame_id = vbuf->sequence,
396 .mode = 0,
397 .times = 0,
398 };
399
400 if (!vbuf->sequence)
401 trigger.frame_id = atomic_inc_return(&dev->isp_sdev.frm_sync_seq) - 1;
402 rkisp_rdbk_trigger_event(dev, T_CMD_QUEUE, &trigger);
403 }
404 } else if (dev->dmarx_dev.trigger == T_AUTO) {
405 /* internal raw wr/rd buf rotate */
406 struct rkisp_dummy_buffer *buf;
407 u32 id, rawwr_addr, val;
408
409 switch (stream->id) {
410 case RKISP_STREAM_RAWRD2:
411 id = dev->hdr.index[HDR_DMA2];
412 rawwr_addr = MI_RAW2_WR_BASE_SHD;
413 break;
414 case RKISP_STREAM_RAWRD1:
415 id = dev->hdr.index[HDR_DMA1];
416 rawwr_addr = MI_RAW1_WR_BASE_SHD;
417 break;
418 case RKISP_STREAM_RAWRD0:
419 default:
420 id = dev->hdr.index[HDR_DMA0];
421 rawwr_addr = MI_RAW0_WR_BASE_SHD;
422 }
423 if (dev->hdr.rx_cur_buf[id]) {
424 hdr_qbuf(&dev->hdr.q_tx[id], dev->hdr.rx_cur_buf[id]);
425 dev->hdr.rx_cur_buf[id] = NULL;
426 }
427 buf = hdr_dqbuf(&dev->hdr.q_rx[id]);
428 if (buf) {
429 val = buf->dma_addr;
430 dev->hdr.rx_cur_buf[id] = buf;
431 } else {
432 val = readl(base + rawwr_addr);
433 }
434 mi_set_y_addr(stream, val);
435 }
436 }
437
438 static struct streams_ops rkisp2_dmarx_streams_ops = {
439 .config_mi = rawrd_config_mi,
440 .update_mi = update_rawrd,
441 };
442
dmarx_frame_end(struct rkisp_stream * stream)443 static int dmarx_frame_end(struct rkisp_stream *stream)
444 {
445 unsigned long lock_flags = 0;
446
447 spin_lock_irqsave(&stream->vbq_lock, lock_flags);
448 if (stream->curr_buf) {
449 if (stream->curr_buf->other) {
450 struct rkisp_device *dev = stream->ispdev;
451 struct v4l2_subdev *sd = dev->active_sensor->sd;
452 struct rkisp_rx_buf *rx_buf = stream->curr_buf->other;
453
454 if (rx_buf->is_switch && stream->id == RKISP_STREAM_RAWRD2) {
455 switch (dev->rd_mode) {
456 case HDR_RDBK_FRAME3:
457 dev->rd_mode = HDR_LINEX3_DDR;
458 break;
459 case HDR_RDBK_FRAME2:
460 dev->rd_mode = HDR_LINEX2_DDR;
461 break;
462 default:
463 dev->rd_mode = HDR_NORMAL;
464 }
465 dev->hdr.op_mode = dev->rd_mode;
466 rkisp_unite_write(dev, CSI2RX_CTRL0,
467 SW_IBUF_OP_MODE(dev->hdr.op_mode),
468 true, dev->hw_dev->is_unite);
469 rkisp_unite_set_bits(dev, CSI2RX_MASK_STAT,
470 0, ISP21_MIPI_DROP_FRM,
471 true, dev->hw_dev->is_unite);
472 rkisp_unite_clear_bits(dev, CIF_ISP_IMSC, CIF_ISP_FRAME_IN,
473 true, dev->hw_dev->is_unite);
474 dev_info(dev->dev,
475 "switch online seq:%d mode:0x%x\n",
476 rx_buf->sequence, dev->rd_mode);
477 }
478 rx_buf->runtime_us = dev->isp_sdev.dbg.interval / 1000;
479 v4l2_subdev_call(sd, video, s_rx_buffer, rx_buf, NULL);
480 } else {
481 vb2_buffer_done(&stream->curr_buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
482 }
483 stream->curr_buf = NULL;
484 }
485
486 if (!list_empty(&stream->buf_queue)) {
487 stream->curr_buf =
488 list_first_entry(&stream->buf_queue,
489 struct rkisp_buffer,
490 queue);
491 list_del(&stream->curr_buf->queue);
492 }
493
494 if (stream->curr_buf)
495 stream->ops->update_mi(stream);
496 spin_unlock_irqrestore(&stream->vbq_lock, lock_flags);
497 return 0;
498 }
499
500 /***************************** vb2 operations*******************************/
501
dmarx_stop(struct rkisp_stream * stream)502 static void dmarx_stop(struct rkisp_stream *stream)
503 {
504 struct rkisp_device *dev = stream->ispdev;
505 struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
506 int ret = 0;
507
508 stream->stopping = true;
509 if ((dev->isp_state & ISP_START) && !stream->frame_end &&
510 !dev->hw_dev->is_shutdown) {
511 ret = wait_event_timeout(stream->done,
512 !stream->streaming,
513 msecs_to_jiffies(300));
514 if (!ret)
515 v4l2_warn(v4l2_dev,
516 "dmarx:%d waiting on event return error %d\n",
517 stream->id, ret);
518 }
519 if (stream->ops->stop_mi)
520 stream->ops->stop_mi(stream);
521 stream->stopping = false;
522 stream->streaming = false;
523 stream->frame_end = false;
524 }
525
dmarx_start(struct rkisp_stream * stream)526 static int dmarx_start(struct rkisp_stream *stream)
527 {
528 int ret;
529
530 ret = stream->ops->config_mi(stream);
531 if (ret)
532 return ret;
533
534 stream->curr_buf = NULL;
535 stream->streaming = true;
536 dmarx_frame_end(stream);
537 return 0;
538 }
539
rkisp_queue_setup(struct vb2_queue * queue,unsigned int * num_buffers,unsigned int * num_planes,unsigned int sizes[],struct device * alloc_ctxs[])540 static int rkisp_queue_setup(struct vb2_queue *queue,
541 unsigned int *num_buffers,
542 unsigned int *num_planes,
543 unsigned int sizes[],
544 struct device *alloc_ctxs[])
545 {
546 struct rkisp_stream *stream = queue->drv_priv;
547 struct rkisp_device *dev = stream->ispdev;
548 const struct v4l2_pix_format_mplane *pixm = NULL;
549 const struct capture_fmt *isp_fmt = NULL;
550 u32 i;
551
552 pixm = &stream->out_fmt;
553 isp_fmt = &stream->out_isp_fmt;
554
555 *num_planes = isp_fmt->mplanes;
556
557 for (i = 0; i < isp_fmt->mplanes; i++) {
558 const struct v4l2_plane_pix_format *plane_fmt;
559
560 plane_fmt = &pixm->plane_fmt[i];
561 sizes[i] = plane_fmt->sizeimage;
562 }
563
564 rkisp_chk_tb_over(dev);
565 v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev, "%s %s count %d, size %d\n",
566 stream->vnode.vdev.name, v4l2_type_names[queue->type], *num_buffers, sizes[0]);
567
568 return 0;
569 }
570
571 /*
572 * The vb2_buffer are stored in rkisp_buffer, in order to unify
573 * mplane buffer and none-mplane buffer.
574 */
rkisp_buf_queue(struct vb2_buffer * vb)575 static void rkisp_buf_queue(struct vb2_buffer *vb)
576 {
577 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
578 struct rkisp_buffer *ispbuf = to_rkisp_buffer(vbuf);
579 struct vb2_queue *queue = vb->vb2_queue;
580 struct rkisp_stream *stream = queue->drv_priv;
581 unsigned long lock_flags = 0;
582 struct v4l2_pix_format_mplane *pixm = &stream->out_fmt;
583 struct capture_fmt *isp_fmt = &stream->out_isp_fmt;
584 struct sg_table *sgt;
585 int i;
586
587 ispbuf->other = NULL;
588 memset(ispbuf->buff_addr, 0, sizeof(ispbuf->buff_addr));
589 for (i = 0; i < isp_fmt->mplanes; i++) {
590 void *vaddr = vb2_plane_vaddr(vb, i);
591
592 if (vaddr && i == 0 &&
593 stream->ispdev->isp_ver == ISP_V20 &&
594 stream->ispdev->rd_mode == HDR_RDBK_FRAME1 &&
595 RKMODULE_EXTEND_LINE >= 8 &&
596 isp_fmt->fmt_type == FMT_BAYER &&
597 stream->id == RKISP_STREAM_RAWRD2) {
598 u32 line = pixm->plane_fmt[0].bytesperline;
599 u32 val = RKMODULE_EXTEND_LINE;
600
601 vaddr += line * (pixm->height - 2);
602 while (val) {
603 memcpy(vaddr + line * val, vaddr, line * 2);
604 val -= 2;
605 }
606 if (vb->vb2_queue->mem_ops->prepare)
607 vb->vb2_queue->mem_ops->prepare(vb->planes[0].mem_priv);
608 }
609
610 if (stream->ispdev->hw_dev->is_dma_sg_ops) {
611 sgt = vb2_dma_sg_plane_desc(vb, i);
612 ispbuf->buff_addr[i] = sg_dma_address(sgt->sgl);
613 } else {
614 ispbuf->buff_addr[i] = vb2_dma_contig_plane_dma_addr(vb, i);
615 }
616 }
617 /*
618 * NOTE: plane_fmt[0].sizeimage is total size of all planes for single
619 * memory plane formats, so calculate the size explicitly.
620 */
621 if (isp_fmt->mplanes == 1) {
622 for (i = 0; i < isp_fmt->cplanes - 1; i++) {
623 ispbuf->buff_addr[i + 1] = (i == 0) ?
624 ispbuf->buff_addr[i] +
625 pixm->plane_fmt[i].bytesperline *
626 pixm->height :
627 ispbuf->buff_addr[i] +
628 pixm->plane_fmt[i].sizeimage;
629 }
630 }
631
632 v4l2_dbg(2, rkisp_debug, &stream->ispdev->v4l2_dev,
633 "rx:%d queue buf:0x%x\n",
634 stream->id, ispbuf->buff_addr[0]);
635
636 spin_lock_irqsave(&stream->vbq_lock, lock_flags);
637 if (stream->streaming &&
638 list_empty(&stream->buf_queue) &&
639 !stream->curr_buf) {
640 stream->curr_buf = ispbuf;
641 stream->ops->update_mi(stream);
642 } else {
643 list_add_tail(&ispbuf->queue, &stream->buf_queue);
644 }
645 spin_unlock_irqrestore(&stream->vbq_lock, lock_flags);
646 }
647
destroy_buf_queue(struct rkisp_stream * stream,enum vb2_buffer_state state)648 static void destroy_buf_queue(struct rkisp_stream *stream,
649 enum vb2_buffer_state state)
650 {
651 struct rkisp_buffer *buf;
652 unsigned long lock_flags = 0;
653
654 spin_lock_irqsave(&stream->vbq_lock, lock_flags);
655 if (stream->curr_buf && !stream->curr_buf->other)
656 list_add_tail(&stream->curr_buf->queue, &stream->buf_queue);
657 stream->curr_buf = NULL;
658 while (!list_empty(&stream->buf_queue)) {
659 buf = list_first_entry(&stream->buf_queue,
660 struct rkisp_buffer, queue);
661 list_del(&buf->queue);
662 if (!buf->other)
663 vb2_buffer_done(&buf->vb.vb2_buf, state);
664 }
665 spin_unlock_irqrestore(&stream->vbq_lock, lock_flags);
666 }
667
dmarx_stop_streaming(struct vb2_queue * queue)668 static void dmarx_stop_streaming(struct vb2_queue *queue)
669 {
670 struct rkisp_stream *stream = queue->drv_priv;
671 struct v4l2_device *v4l2_dev = &stream->ispdev->v4l2_dev;
672
673 v4l2_dbg(1, rkisp_debug, v4l2_dev, "%s %s id:%d\n",
674 __func__, stream->vnode.vdev.name, stream->id);
675
676 if (!stream->streaming)
677 return;
678
679 dmarx_stop(stream);
680 destroy_buf_queue(stream, VB2_BUF_STATE_ERROR);
681
682 if (stream->id == RKISP_STREAM_RAWRD2 &&
683 stream->ispdev->isp_ver >= ISP_V20)
684 kfifo_reset(&stream->ispdev->rdbk_kfifo);
685 }
686
dmarx_start_streaming(struct vb2_queue * queue,unsigned int count)687 static int dmarx_start_streaming(struct vb2_queue *queue,
688 unsigned int count)
689 {
690 struct rkisp_stream *stream = queue->drv_priv;
691 struct rkisp_device *dev = stream->ispdev;
692 struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
693 int ret = -1;
694
695 v4l2_dbg(1, rkisp_debug, v4l2_dev, "%s %s id:%d\n",
696 __func__, stream->vnode.vdev.name, stream->id);
697
698 if (WARN_ON(stream->streaming))
699 return -EBUSY;
700
701 if (!stream->linked) {
702 v4l2_err(v4l2_dev, "check %s link\n", stream->vnode.vdev.name);
703 goto free_buf_queue;
704 }
705
706 ret = dmarx_start(stream);
707 if (ret < 0) {
708 v4l2_err(v4l2_dev, "start %s failed\n", stream->vnode.vdev.name);
709 goto free_buf_queue;
710 }
711 return 0;
712 free_buf_queue:
713 destroy_buf_queue(stream, VB2_BUF_STATE_QUEUED);
714 return ret;
715 }
716
717 static struct vb2_ops dmarx_vb2_ops = {
718 .queue_setup = rkisp_queue_setup,
719 .buf_queue = rkisp_buf_queue,
720 .wait_prepare = vb2_ops_wait_prepare,
721 .wait_finish = vb2_ops_wait_finish,
722 .stop_streaming = dmarx_stop_streaming,
723 .start_streaming = dmarx_start_streaming,
724 };
725
rkisp_init_vb2_queue(struct vb2_queue * q,struct rkisp_stream * stream,enum v4l2_buf_type buf_type)726 static int rkisp_init_vb2_queue(struct vb2_queue *q,
727 struct rkisp_stream *stream,
728 enum v4l2_buf_type buf_type)
729 {
730 q->type = buf_type;
731 q->io_modes = VB2_MMAP | VB2_DMABUF | VB2_USERPTR;
732 q->drv_priv = stream;
733 q->ops = &dmarx_vb2_ops;
734 q->mem_ops = stream->ispdev->hw_dev->mem_ops;
735 q->buf_struct_size = sizeof(struct rkisp_buffer);
736 q->min_buffers_needed = CIF_ISP_REQ_BUFS_MIN;
737 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
738 q->lock = &stream->apilock;
739 q->dev = stream->ispdev->hw_dev->dev;
740 q->allow_cache_hints = 1;
741 q->bidirectional = 1;
742 q->gfp_flags = GFP_DMA32;
743 if (stream->ispdev->hw_dev->is_dma_contig)
744 q->dma_attrs = DMA_ATTR_FORCE_CONTIGUOUS;
745 return vb2_queue_init(q);
746 }
747
rkisp_set_fmt(struct rkisp_stream * stream,struct v4l2_pix_format_mplane * pixm,bool try)748 static int rkisp_set_fmt(struct rkisp_stream *stream,
749 struct v4l2_pix_format_mplane *pixm,
750 bool try)
751 {
752 const struct capture_fmt *fmt;
753 unsigned int imagsize = 0;
754 unsigned int planes;
755 u32 xsubs = 1, ysubs = 1;
756 unsigned int i;
757
758 fmt = find_fmt(stream, pixm->pixelformat);
759 if (!fmt) {
760 v4l2_err(&stream->ispdev->v4l2_dev,
761 "nonsupport pixelformat:%c%c%c%c\n",
762 pixm->pixelformat,
763 pixm->pixelformat >> 8,
764 pixm->pixelformat >> 16,
765 pixm->pixelformat >> 24);
766 return -EINVAL;
767 }
768
769 pixm->num_planes = fmt->mplanes;
770 pixm->field = V4L2_FIELD_NONE;
771 if (!pixm->quantization)
772 pixm->quantization = V4L2_QUANTIZATION_FULL_RANGE;
773
774 /* calculate size */
775 rkisp_fcc_xysubs(fmt->fourcc, &xsubs, &ysubs);
776 planes = fmt->cplanes ? fmt->cplanes : fmt->mplanes;
777 for (i = 0; i < planes; i++) {
778 struct v4l2_plane_pix_format *plane_fmt;
779 unsigned int width, height, bytesperline;
780
781 plane_fmt = pixm->plane_fmt + i;
782
783 if (i == 0) {
784 width = pixm->width;
785 height = pixm->height;
786 } else {
787 width = pixm->width / xsubs;
788 height = pixm->height / ysubs;
789 }
790
791 if (stream->ispdev->isp_ver == ISP_V20 &&
792 stream->id == RKISP_STREAM_RAWRD2 &&
793 fmt->fmt_type == FMT_BAYER)
794 height += RKMODULE_EXTEND_LINE;
795
796 if (stream->ispdev->isp_ver >= ISP_V20 &&
797 fmt->fmt_type == FMT_BAYER &&
798 !stream->memory &&
799 stream->id != RKISP_STREAM_DMARX)
800 bytesperline = ALIGN(width * fmt->bpp[i] / 8, 256);
801 else
802 bytesperline = width * DIV_ROUND_UP(fmt->bpp[i], 8);
803
804 if (stream->ispdev->vicap_in.merge_num > 1)
805 bytesperline *= stream->ispdev->vicap_in.merge_num;
806
807 if (i != 0 ||
808 plane_fmt->bytesperline < bytesperline)
809 plane_fmt->bytesperline = bytesperline;
810
811 plane_fmt->sizeimage = plane_fmt->bytesperline * height;
812
813 imagsize += plane_fmt->sizeimage;
814 }
815
816 /* convert to non-MPLANE format.
817 * it's important since we want to unify none-MPLANE
818 * and MPLANE.
819 */
820 if (fmt->mplanes == 1)
821 pixm->plane_fmt[0].sizeimage = imagsize;
822
823 if (!try) {
824 stream->out_isp_fmt = *fmt;
825 stream->out_fmt = *pixm;
826
827 stream->u.dmarx.y_stride =
828 pixm->plane_fmt[0].bytesperline /
829 DIV_ROUND_UP(fmt->bpp[0], 8);
830
831 v4l2_dbg(1, rkisp_debug, &stream->ispdev->v4l2_dev,
832 "%s: rx:%d req(%d, %d) out(%d, %d)\n", __func__,
833 stream->id, pixm->width, pixm->height,
834 stream->out_fmt.width, stream->out_fmt.height);
835 }
836
837 return 0;
838 }
839
840 /************************* v4l2_file_operations***************************/
841
842 static const struct v4l2_file_operations rkisp_fops = {
843 .open = rkisp_fh_open,
844 .release = rkisp_fop_release,
845 .unlocked_ioctl = video_ioctl2,
846 .poll = vb2_fop_poll,
847 .mmap = vb2_fop_mmap,
848 #ifdef CONFIG_COMPAT
849 .compat_ioctl32 = video_ioctl2,
850 #endif
851 };
852
rkisp_try_fmt_vid_out_mplane(struct file * file,void * fh,struct v4l2_format * f)853 static int rkisp_try_fmt_vid_out_mplane(struct file *file, void *fh,
854 struct v4l2_format *f)
855 {
856 struct rkisp_stream *stream = video_drvdata(file);
857
858 return rkisp_set_fmt(stream, &f->fmt.pix_mp, true);
859 }
860
rkisp_enum_fmt_vid_out_mplane(struct file * file,void * priv,struct v4l2_fmtdesc * f)861 static int rkisp_enum_fmt_vid_out_mplane(struct file *file, void *priv,
862 struct v4l2_fmtdesc *f)
863 {
864 struct rkisp_stream *stream = video_drvdata(file);
865 const struct capture_fmt *fmt = NULL;
866
867 if (f->index >= stream->config->fmt_size)
868 return -EINVAL;
869
870 fmt = &stream->config->fmts[f->index];
871 f->pixelformat = fmt->fourcc;
872
873 return 0;
874 }
875
rkisp_s_fmt_vid_out_mplane(struct file * file,void * priv,struct v4l2_format * f)876 static int rkisp_s_fmt_vid_out_mplane(struct file *file,
877 void *priv, struct v4l2_format *f)
878 {
879 struct rkisp_stream *stream = video_drvdata(file);
880 struct video_device *vdev = &stream->vnode.vdev;
881 struct rkisp_vdev_node *node = vdev_to_node(vdev);
882 struct rkisp_device *dev = stream->ispdev;
883
884 if (vb2_is_busy(&node->buf_queue)) {
885 v4l2_err(&dev->v4l2_dev, "%s rx:%d queue busy\n",
886 __func__, stream->id);
887 return -EBUSY;
888 }
889
890 return rkisp_set_fmt(stream, &f->fmt.pix_mp, false);
891 }
892
rkisp_g_fmt_vid_out_mplane(struct file * file,void * fh,struct v4l2_format * f)893 static int rkisp_g_fmt_vid_out_mplane(struct file *file, void *fh,
894 struct v4l2_format *f)
895 {
896 struct rkisp_stream *stream = video_drvdata(file);
897
898 f->fmt.pix_mp = stream->out_fmt;
899
900 return 0;
901 }
902
rkisp_querycap(struct file * file,void * priv,struct v4l2_capability * cap)903 static int rkisp_querycap(struct file *file, void *priv,
904 struct v4l2_capability *cap)
905 {
906 struct rkisp_stream *stream = video_drvdata(file);
907 struct device *dev = stream->ispdev->dev;
908 struct video_device *vdev = video_devdata(file);
909
910 strlcpy(cap->card, vdev->name, sizeof(cap->card));
911 snprintf(cap->driver, sizeof(cap->driver),
912 "%s_v%d", dev->driver->name,
913 stream->ispdev->isp_ver >> 4);
914 snprintf(cap->bus_info, sizeof(cap->bus_info),
915 "platform:%s", dev_name(dev));
916 cap->version = RKISP_DRIVER_VERSION;
917 return 0;
918 }
919
rkisp_ioctl_default(struct file * file,void * fh,bool valid_prio,unsigned int cmd,void * arg)920 static long rkisp_ioctl_default(struct file *file, void *fh,
921 bool valid_prio, unsigned int cmd, void *arg)
922 {
923 struct rkisp_stream *stream = video_drvdata(file);
924 long ret = 0;
925
926 switch (cmd) {
927 case RKISP_CMD_GET_CSI_MEMORY_MODE:
928 if (stream->id != RKISP_STREAM_RAWRD0 &&
929 stream->id != RKISP_STREAM_RAWRD1 &&
930 stream->id != RKISP_STREAM_RAWRD2)
931 ret = -EINVAL;
932 else if (stream->memory == 0)
933 *(int *)arg = CSI_MEM_COMPACT;
934 else if (stream->memory == SW_CSI_RAW_WR_SIMG_MODE)
935 *(int *)arg = CSI_MEM_WORD_BIG_ALIGN;
936 else
937 *(int *)arg = CSI_MEM_WORD_LITTLE_ALIGN;
938 break;
939 case RKISP_CMD_SET_CSI_MEMORY_MODE:
940 if (stream->id != RKISP_STREAM_RAWRD0 &&
941 stream->id != RKISP_STREAM_RAWRD1 &&
942 stream->id != RKISP_STREAM_RAWRD2)
943 ret = -EINVAL;
944 else if (*(int *)arg == CSI_MEM_COMPACT)
945 stream->memory = 0;
946 else if (*(int *)arg == CSI_MEM_WORD_BIG_ALIGN)
947 stream->memory = SW_CSI_RAW_WR_SIMG_MODE;
948 else
949 stream->memory =
950 SW_CSI_RWA_WR_SIMG_SWP | SW_CSI_RAW_WR_SIMG_MODE;
951 break;
952 default:
953 ret = -EINVAL;
954 }
955
956 return ret;
957 }
958
959 static const struct v4l2_ioctl_ops rkisp_dmarx_ioctl = {
960 .vidioc_reqbufs = vb2_ioctl_reqbufs,
961 .vidioc_querybuf = vb2_ioctl_querybuf,
962 .vidioc_create_bufs = vb2_ioctl_create_bufs,
963 .vidioc_qbuf = vb2_ioctl_qbuf,
964 .vidioc_expbuf = vb2_ioctl_expbuf,
965 .vidioc_dqbuf = vb2_ioctl_dqbuf,
966 .vidioc_prepare_buf = vb2_ioctl_prepare_buf,
967 .vidioc_streamon = vb2_ioctl_streamon,
968 .vidioc_streamoff = vb2_ioctl_streamoff,
969 .vidioc_try_fmt_vid_out_mplane = rkisp_try_fmt_vid_out_mplane,
970 .vidioc_enum_fmt_vid_out = rkisp_enum_fmt_vid_out_mplane,
971 .vidioc_s_fmt_vid_out_mplane = rkisp_s_fmt_vid_out_mplane,
972 .vidioc_g_fmt_vid_out_mplane = rkisp_g_fmt_vid_out_mplane,
973 .vidioc_querycap = rkisp_querycap,
974 .vidioc_default = rkisp_ioctl_default,
975 };
976
rkisp_unregister_dmarx_video(struct rkisp_stream * stream)977 static void rkisp_unregister_dmarx_video(struct rkisp_stream *stream)
978 {
979 media_entity_cleanup(&stream->vnode.vdev.entity);
980 video_unregister_device(&stream->vnode.vdev);
981 }
982
rkisp_register_dmarx_video(struct rkisp_stream * stream)983 static int rkisp_register_dmarx_video(struct rkisp_stream *stream)
984 {
985 struct rkisp_device *dev = stream->ispdev;
986 struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
987 struct video_device *vdev = &stream->vnode.vdev;
988 struct rkisp_vdev_node *node;
989 int ret = 0;
990
991 mutex_init(&stream->apilock);
992 node = vdev_to_node(vdev);
993
994 vdev->release = video_device_release_empty;
995 vdev->fops = &rkisp_fops;
996 vdev->minor = -1;
997 vdev->v4l2_dev = v4l2_dev;
998 vdev->lock = &stream->apilock;
999 video_set_drvdata(vdev, stream);
1000
1001 vdev->ioctl_ops = &rkisp_dmarx_ioctl;
1002 vdev->device_caps = V4L2_CAP_VIDEO_OUTPUT_MPLANE |
1003 V4L2_CAP_STREAMING;
1004 vdev->vfl_dir = VFL_DIR_TX;
1005 node->pad.flags = MEDIA_PAD_FL_SOURCE;
1006
1007 rkisp_init_vb2_queue(&node->buf_queue, stream,
1008 V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
1009 vdev->queue = &node->buf_queue;
1010
1011 ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1);
1012 if (ret < 0) {
1013 v4l2_err(v4l2_dev,
1014 "%s failed with error %d\n", __func__, ret);
1015 return ret;
1016 }
1017
1018 ret = media_entity_pads_init(&vdev->entity, 1, &node->pad);
1019 if (ret < 0)
1020 goto unreg;
1021
1022 return 0;
1023 unreg:
1024 video_unregister_device(vdev);
1025 return ret;
1026 }
1027
1028 /**************** Interrupter Handler ****************/
1029
rkisp_dmarx_isr(u32 mis_val,struct rkisp_device * dev)1030 void rkisp_dmarx_isr(u32 mis_val, struct rkisp_device *dev)
1031 {
1032 void __iomem *base = dev->base_addr;
1033 struct rkisp_stream *stream;
1034
1035 if (mis_val & CIF_MI_DMA_READY) {
1036 stream = &dev->dmarx_dev.stream[RKISP_STREAM_DMARX];
1037 stream->frame_end = true;
1038 writel(CIF_MI_DMA_READY, base + CIF_MI_ICR);
1039
1040 if (stream->stopping) {
1041 stream->stopping = false;
1042 stream->streaming = false;
1043 wake_up(&stream->done);
1044 } else {
1045 dmarx_frame_end(stream);
1046 }
1047 }
1048 }
1049
rkisp2_rawrd_isr(u32 mis_val,struct rkisp_device * dev)1050 void rkisp2_rawrd_isr(u32 mis_val, struct rkisp_device *dev)
1051 {
1052 struct rkisp_stream *stream;
1053 int i;
1054
1055 for (i = RKISP_STREAM_RAWRD0; i < RKISP_MAX_DMARX_STREAM; i++) {
1056 stream = &dev->dmarx_dev.stream[i];
1057 if (!(mis_val & CIF_MI_FRAME(stream)))
1058 continue;
1059 stream->frame_end = true;
1060 if (stream->stopping) {
1061 stream->stopping = false;
1062 stream->streaming = false;
1063 wake_up(&stream->done);
1064 } else {
1065 dmarx_frame_end(stream);
1066 }
1067 }
1068 }
1069
dmarx_init(struct rkisp_device * dev,u32 id)1070 static int dmarx_init(struct rkisp_device *dev, u32 id)
1071 {
1072 struct rkisp_dmarx_device *dmarx_dev = &dev->dmarx_dev;
1073 struct rkisp_stream *stream;
1074 struct video_device *vdev;
1075 struct media_entity *source, *sink;
1076 int ret = 0;
1077
1078 stream = &dmarx_dev->stream[id];
1079 INIT_LIST_HEAD(&stream->buf_queue);
1080 init_waitqueue_head(&stream->done);
1081 spin_lock_init(&stream->vbq_lock);
1082 stream->id = id;
1083 stream->ispdev = dev;
1084 vdev = &stream->vnode.vdev;
1085 stream->linked = false;
1086
1087 switch (id) {
1088 case RKISP_STREAM_DMARX:
1089 strlcpy(vdev->name, DMA_VDEV_NAME,
1090 sizeof(vdev->name));
1091 stream->ops = &rkisp_dmarx_streams_ops;
1092 stream->config = &rkisp_dmarx_stream_config;
1093 break;
1094 case RKISP_STREAM_RAWRD0:
1095 strlcpy(vdev->name, DMARX0_VDEV_NAME,
1096 sizeof(vdev->name));
1097 stream->ops = &rkisp2_dmarx_streams_ops;
1098 stream->config = &rkisp2_dmarx0_stream_config;
1099 break;
1100 case RKISP_STREAM_RAWRD1:
1101 strlcpy(vdev->name, DMARX1_VDEV_NAME,
1102 sizeof(vdev->name));
1103 stream->ops = &rkisp2_dmarx_streams_ops;
1104 stream->config = &rkisp2_dmarx1_stream_config;
1105 break;
1106 case RKISP_STREAM_RAWRD2:
1107 strlcpy(vdev->name, DMARX2_VDEV_NAME,
1108 sizeof(vdev->name));
1109 stream->ops = &rkisp2_dmarx_streams_ops;
1110 stream->config = &rkisp2_dmarx2_stream_config;
1111 break;
1112 default:
1113 v4l2_err(&dev->v4l2_dev, "Invalid dmarx\n");
1114 return -EINVAL;
1115 }
1116 ret = rkisp_register_dmarx_video(stream);
1117 if (ret < 0)
1118 return ret;
1119
1120 /* dmarx link -> isp subdev */
1121 source = &vdev->entity;
1122 sink = &dev->isp_sdev.sd.entity;
1123 return media_create_pad_link(source, 0, sink,
1124 RKISP_ISP_PAD_SINK, stream->linked);
1125 }
1126
rkisp_dmarx_set_fmt(struct rkisp_stream * stream,struct v4l2_pix_format_mplane pixm)1127 void rkisp_dmarx_set_fmt(struct rkisp_stream *stream,
1128 struct v4l2_pix_format_mplane pixm)
1129 {
1130 rkisp_set_fmt(stream, &pixm, false);
1131 }
1132
rkisp_rawrd_set_pic_size(struct rkisp_device * dev,u32 width,u32 height)1133 void rkisp_rawrd_set_pic_size(struct rkisp_device *dev,
1134 u32 width, u32 height)
1135 {
1136 struct rkisp_isp_subdev *sdev = &dev->isp_sdev;
1137 u8 mult = sdev->in_fmt.fmt_type == FMT_YUV ? 2 : 1;
1138 bool is_unite = dev->hw_dev->is_unite;
1139 u32 w = !is_unite ? width : width / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL;
1140
1141 /* rx height should equal to isp height + offset for read back mode */
1142 height = sdev->in_crop.top + sdev->in_crop.height;
1143
1144 /* isp20 extend line for normal read back mode to fix internal bug */
1145 if (dev->isp_ver == ISP_V20 &&
1146 sdev->in_fmt.fmt_type == FMT_BAYER &&
1147 sdev->out_fmt.fmt_type != FMT_BAYER &&
1148 dev->rd_mode == HDR_RDBK_FRAME1)
1149 height += RKMODULE_EXTEND_LINE;
1150
1151 w *= mult;
1152 rkisp_unite_write(dev, CSI2RX_RAW_RD_PIC_SIZE, height << 16 | w, false, is_unite);
1153 }
1154
rkisp_dmarx_get_frame(struct rkisp_device * dev,u32 * id,u64 * sof_timestamp,u64 * timestamp,bool sync)1155 void rkisp_dmarx_get_frame(struct rkisp_device *dev, u32 *id,
1156 u64 *sof_timestamp, u64 *timestamp,
1157 bool sync)
1158 {
1159 unsigned long flag = 0;
1160 u64 sof_time = 0, frame_timestamp = 0;
1161 u32 frame_id = 0;
1162
1163 if (!IS_HDR_RDBK(dev->rd_mode) && id) {
1164 *id = atomic_read(&dev->isp_sdev.frm_sync_seq) - 1;
1165 return;
1166 }
1167
1168 spin_lock_irqsave(&dev->rdbk_lock, flag);
1169 if (sync) {
1170 frame_id = dev->dmarx_dev.cur_frame.id;
1171 sof_time = dev->dmarx_dev.cur_frame.sof_timestamp;
1172 frame_timestamp = dev->dmarx_dev.cur_frame.timestamp;
1173 } else {
1174 frame_id = dev->dmarx_dev.pre_frame.id;
1175 sof_time = dev->dmarx_dev.pre_frame.sof_timestamp;
1176 frame_timestamp = dev->dmarx_dev.pre_frame.timestamp;
1177 }
1178 spin_unlock_irqrestore(&dev->rdbk_lock, flag);
1179 if (id)
1180 *id = frame_id;
1181 if (sof_timestamp)
1182 *sof_timestamp = sof_time;
1183 if (timestamp)
1184 *timestamp = frame_timestamp;
1185 }
1186
rkisp_register_dmarx_vdev(struct rkisp_device * dev)1187 int rkisp_register_dmarx_vdev(struct rkisp_device *dev)
1188 {
1189 struct rkisp_dmarx_device *dmarx_dev = &dev->dmarx_dev;
1190 int ret = 0;
1191
1192 memset(dmarx_dev, 0, sizeof(*dmarx_dev));
1193 dmarx_dev->ispdev = dev;
1194
1195 #ifdef RKISP_DMAREAD_EN
1196 ret = dmarx_init(dev, RKISP_STREAM_DMARX);
1197 if (ret < 0)
1198 goto err;
1199 #endif
1200 if (dev->isp_ver >= ISP_V20) {
1201 ret = dmarx_init(dev, RKISP_STREAM_RAWRD0);
1202 if (ret < 0)
1203 goto err_free_dmarx;
1204 ret = dmarx_init(dev, RKISP_STREAM_RAWRD2);
1205 if (ret < 0)
1206 goto err_free_dmarx0;
1207 }
1208 if (dev->isp_ver == ISP_V20 || dev->isp_ver == ISP_V30) {
1209 ret = dmarx_init(dev, RKISP_STREAM_RAWRD1);
1210 if (ret < 0)
1211 goto err_free_dmarx2;
1212 }
1213
1214 return 0;
1215 err_free_dmarx2:
1216 rkisp_unregister_dmarx_video(&dmarx_dev->stream[RKISP_STREAM_RAWRD2]);
1217 err_free_dmarx0:
1218 rkisp_unregister_dmarx_video(&dmarx_dev->stream[RKISP_STREAM_RAWRD0]);
1219 err_free_dmarx:
1220 #ifdef RKISP_DMAREAD_EN
1221 rkisp_unregister_dmarx_video(&dmarx_dev->stream[RKISP_STREAM_DMARX]);
1222 err:
1223 #endif
1224 return ret;
1225 }
1226
rkisp_unregister_dmarx_vdev(struct rkisp_device * dev)1227 void rkisp_unregister_dmarx_vdev(struct rkisp_device *dev)
1228 {
1229 struct rkisp_dmarx_device *dmarx_dev = &dev->dmarx_dev;
1230 struct rkisp_stream *stream;
1231
1232 #ifdef RKISP_DMAREAD_EN
1233 stream = &dmarx_dev->stream[RKISP_STREAM_DMARX];
1234 rkisp_unregister_dmarx_video(stream);
1235 #endif
1236
1237 if (dev->isp_ver >= ISP_V20) {
1238 stream = &dmarx_dev->stream[RKISP_STREAM_RAWRD0];
1239 rkisp_unregister_dmarx_video(stream);
1240
1241 stream = &dmarx_dev->stream[RKISP_STREAM_RAWRD2];
1242 rkisp_unregister_dmarx_video(stream);
1243 }
1244 if (dev->isp_ver == ISP_V20 || dev->isp_ver == ISP_V30) {
1245 stream = &dmarx_dev->stream[RKISP_STREAM_RAWRD1];
1246 rkisp_unregister_dmarx_video(stream);
1247 }
1248 }
1249