1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (C) 2020 Rockchip Electronics Co., Ltd */
3
4 #include <linux/clk.h>
5 #include <linux/delay.h>
6 #include <linux/interrupt.h>
7 #include <linux/io.h>
8 #include <linux/iommu.h>
9 #include <linux/mfd/syscon.h>
10 #include <linux/module.h>
11 #include <linux/of.h>
12 #include <linux/of_address.h>
13 #include <linux/of_graph.h>
14 #include <linux/of_platform.h>
15 #include <linux/of_reserved_mem.h>
16 #include <linux/pinctrl/consumer.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/reset.h>
19 #include <media/videobuf2-cma-sg.h>
20 #include <media/videobuf2-dma-sg.h>
21 #include <soc/rockchip/rockchip_iommu.h>
22
23 #include "common.h"
24 #include "dev.h"
25 #include "hw.h"
26 #include "regs.h"
27
28 /*
29 * rkisp_hw share hardware resource with rkisp virtual device
30 * rkisp_device rkisp_device rkisp_device rkisp_device
31 * | | | |
32 * \ | | /
33 * --------------------------------------
34 * |
35 * rkisp_hw
36 */
37
38 struct isp_irqs_data {
39 const char *name;
40 irqreturn_t (*irq_hdl)(int irq, void *ctx);
41 };
42
43 /* using default value if reg no write for multi device */
default_sw_reg_flag(struct rkisp_device * dev)44 static void default_sw_reg_flag(struct rkisp_device *dev)
45 {
46 u32 v20_reg[] = {
47 CTRL_VI_ISP_PATH, IMG_EFF_CTRL, ISP_CCM_CTRL,
48 CPROC_CTRL, DUAL_CROP_CTRL, ISP_GAMMA_OUT_CTRL,
49 ISP_LSC_CTRL, ISP_DEBAYER_CONTROL, ISP_WDR_CTRL,
50 ISP_GIC_CONTROL, ISP_BLS_CTRL, ISP_DPCC0_MODE,
51 ISP_DPCC1_MODE, ISP_DPCC2_MODE, ISP_HDRMGE_CTRL,
52 ISP_HDRTMO_CTRL, ISP_RAWNR_CTRL, ISP_LDCH_STS,
53 ISP_DHAZ_CTRL, ISP_3DLUT_CTRL, ISP_GAIN_CTRL,
54 ISP_AFM_CTRL, ISP_HIST_HIST_CTRL, RAWAE_BIG1_BASE,
55 RAWAE_BIG2_BASE, RAWAE_BIG3_BASE, ISP_RAWAE_LITE_CTRL,
56 ISP_RAWHIST_LITE_CTRL, ISP_RAWHIST_BIG1_BASE,
57 ISP_RAWHIST_BIG2_BASE, ISP_RAWHIST_BIG3_BASE,
58 ISP_YUVAE_CTRL, ISP_RAWAF_CTRL, ISP_RAWAWB_CTRL,
59 };
60 u32 v21_reg[] = {
61 CTRL_VI_ISP_PATH, IMG_EFF_CTRL, ISP_CCM_CTRL,
62 CPROC_CTRL, DUAL_CROP_CTRL, ISP_GAMMA_OUT_CTRL,
63 SELF_RESIZE_CTRL, MAIN_RESIZE_CTRL, ISP_LSC_CTRL,
64 ISP_DEBAYER_CONTROL, ISP21_YNR_GLOBAL_CTRL,
65 ISP21_CNR_CTRL, ISP21_SHARP_SHARP_EN, ISP_GIC_CONTROL,
66 ISP_BLS_CTRL, ISP_DPCC0_MODE, ISP_DPCC1_MODE,
67 ISP_HDRMGE_CTRL, ISP21_DRC_CTRL0, ISP21_BAYNR_CTRL,
68 ISP21_BAY3D_CTRL, ISP_LDCH_STS, ISP21_DHAZ_CTRL,
69 ISP_3DLUT_CTRL, ISP_AFM_CTRL, ISP_HIST_HIST_CTRL,
70 RAWAE_BIG1_BASE, RAWAE_BIG2_BASE, RAWAE_BIG3_BASE,
71 ISP_RAWAE_LITE_CTRL, ISP_RAWHIST_LITE_CTRL,
72 ISP_RAWHIST_BIG1_BASE, ISP_RAWHIST_BIG2_BASE,
73 ISP_RAWHIST_BIG3_BASE, ISP_YUVAE_CTRL, ISP_RAWAF_CTRL,
74 ISP21_RAWAWB_CTRL,
75 };
76 u32 v30_reg[] = {
77 ISP3X_VI_ISP_PATH, ISP3X_IMG_EFF_CTRL, ISP3X_CMSK_CTRL0,
78 ISP3X_CCM_CTRL, ISP3X_CPROC_CTRL, ISP3X_DUAL_CROP_CTRL,
79 ISP3X_GAMMA_OUT_CTRL, ISP3X_SELF_RESIZE_CTRL, ISP3X_MAIN_RESIZE_CTRL,
80 ISP3X_LSC_CTRL, ISP3X_DEBAYER_CONTROL, ISP3X_CAC_CTRL,
81 ISP3X_YNR_GLOBAL_CTRL, ISP3X_CNR_CTRL, ISP3X_SHARP_EN,
82 ISP3X_BAY3D_CTRL, ISP3X_GIC_CONTROL, ISP3X_BLS_CTRL,
83 ISP3X_DPCC0_MODE, ISP3X_DPCC1_MODE, ISP3X_DPCC2_MODE,
84 ISP3X_HDRMGE_CTRL, ISP3X_DRC_CTRL0, ISP3X_BAYNR_CTRL,
85 ISP3X_LDCH_STS, ISP3X_DHAZ_CTRL, ISP3X_3DLUT_CTRL,
86 ISP3X_GAIN_CTRL, ISP3X_RAWAE_LITE_CTRL, ISP3X_RAWAE_BIG1_BASE,
87 ISP3X_RAWAE_BIG2_BASE, ISP3X_RAWAE_BIG3_BASE, ISP3X_RAWHIST_LITE_CTRL,
88 ISP3X_RAWHIST_BIG1_BASE, ISP3X_RAWHIST_BIG2_BASE, ISP3X_RAWHIST_BIG3_BASE,
89 ISP3X_RAWAF_CTRL, ISP3X_RAWAWB_CTRL,
90 };
91 u32 v32_reg[] = {
92 ISP3X_VI_ISP_PATH, ISP3X_IMG_EFF_CTRL, ISP3X_CMSK_CTRL0,
93 ISP3X_CCM_CTRL, ISP3X_CPROC_CTRL, ISP3X_DUAL_CROP_CTRL,
94 ISP3X_GAMMA_OUT_CTRL, ISP3X_SELF_RESIZE_CTRL, ISP3X_MAIN_RESIZE_CTRL,
95 ISP32_BP_RESIZE_BASE, ISP3X_MI_BP_WR_CTRL, ISP32_MI_MPDS_WR_CTRL,
96 ISP32_MI_BPDS_WR_CTRL, ISP32_MI_WR_WRAP_CTRL,
97 ISP3X_LSC_CTRL, ISP3X_DEBAYER_CONTROL, ISP3X_CAC_CTRL,
98 ISP3X_YNR_GLOBAL_CTRL, ISP3X_CNR_CTRL, ISP3X_SHARP_EN,
99 ISP3X_BAY3D_CTRL, ISP3X_GIC_CONTROL, ISP3X_BLS_CTRL,
100 ISP3X_DPCC0_MODE, ISP3X_DPCC1_MODE, ISP3X_DPCC2_MODE,
101 ISP3X_HDRMGE_CTRL, ISP3X_DRC_CTRL0, ISP3X_BAYNR_CTRL,
102 ISP3X_LDCH_STS, ISP3X_DHAZ_CTRL, ISP3X_3DLUT_CTRL,
103 ISP3X_GAIN_CTRL, ISP3X_RAWAE_LITE_CTRL, ISP3X_RAWAE_BIG1_BASE,
104 ISP3X_RAWAE_BIG2_BASE, ISP3X_RAWAE_BIG3_BASE, ISP3X_RAWHIST_LITE_CTRL,
105 ISP3X_RAWHIST_BIG1_BASE, ISP3X_RAWHIST_BIG2_BASE, ISP3X_RAWHIST_BIG3_BASE,
106 ISP3X_RAWAF_CTRL, ISP3X_RAWAWB_CTRL,
107 };
108 u32 i, *flag, *reg, size;
109
110 switch (dev->isp_ver) {
111 case ISP_V20:
112 reg = v20_reg;
113 size = ARRAY_SIZE(v20_reg);
114 break;
115 case ISP_V21:
116 reg = v21_reg;
117 size = ARRAY_SIZE(v21_reg);
118 break;
119 case ISP_V30:
120 reg = v30_reg;
121 size = ARRAY_SIZE(v30_reg);
122 break;
123 case ISP_V32:
124 case ISP_V32_L:
125 reg = v32_reg;
126 size = ARRAY_SIZE(v32_reg);
127 break;
128 default:
129 return;
130 }
131
132 for (i = 0; i < size; i++) {
133 flag = dev->sw_base_addr + reg[i] + RKISP_ISP_SW_REG_SIZE;
134 *flag = SW_REG_CACHE;
135 if (dev->hw_dev->is_unite) {
136 flag += RKISP_ISP_SW_MAX_SIZE / 4;
137 *flag = SW_REG_CACHE;
138 }
139 }
140 }
141
mipi_irq_hdl(int irq,void * ctx)142 static irqreturn_t mipi_irq_hdl(int irq, void *ctx)
143 {
144 struct device *dev = ctx;
145 struct rkisp_hw_dev *hw_dev = dev_get_drvdata(dev);
146 struct rkisp_device *isp = hw_dev->isp[hw_dev->mipi_dev_id];
147 void __iomem *base = !hw_dev->is_unite ?
148 hw_dev->base_addr : hw_dev->base_next_addr;
149 ktime_t t = 0;
150 s64 us;
151
152 if (hw_dev->is_thunderboot)
153 return IRQ_HANDLED;
154
155 if (rkisp_irq_dbg)
156 t = ktime_get();
157
158 if (hw_dev->isp_ver == ISP_V13 || hw_dev->isp_ver == ISP_V12) {
159 u32 err1, err2, err3;
160
161 err1 = readl(base + CIF_ISP_CSI0_ERR1);
162 err2 = readl(base + CIF_ISP_CSI0_ERR2);
163 err3 = readl(base + CIF_ISP_CSI0_ERR3);
164
165 if (err1 || err2 || err3)
166 rkisp_mipi_v13_isr(err1, err2, err3, isp);
167 } else if (hw_dev->isp_ver >= ISP_V20) {
168 u32 phy, packet, overflow, state;
169
170 state = readl(base + CSI2RX_ERR_STAT);
171 phy = readl(base + CSI2RX_ERR_PHY);
172 packet = readl(base + CSI2RX_ERR_PACKET);
173 overflow = readl(base + CSI2RX_ERR_OVERFLOW);
174 if (phy | packet | overflow | state) {
175 if (hw_dev->isp_ver == ISP_V20)
176 rkisp_mipi_v20_isr(phy, packet, overflow, state, isp);
177 else if (hw_dev->isp_ver == ISP_V21)
178 rkisp_mipi_v21_isr(phy, packet, overflow, state, isp);
179 else if (hw_dev->isp_ver == ISP_V30)
180 rkisp_mipi_v30_isr(phy, packet, overflow, state, isp);
181 else
182 rkisp_mipi_v32_isr(phy, packet, overflow, state, isp);
183 }
184 } else {
185 u32 mis_val = readl(base + CIF_MIPI_MIS);
186
187 if (mis_val)
188 rkisp_mipi_isr(mis_val, isp);
189 }
190
191 if (rkisp_irq_dbg) {
192 us = ktime_us_delta(ktime_get(), t);
193 v4l2_dbg(0, rkisp_debug, &isp->v4l2_dev,
194 "%s %lldus\n", __func__, us);
195 }
196 return IRQ_HANDLED;
197 }
198
mi_irq_hdl(int irq,void * ctx)199 static irqreturn_t mi_irq_hdl(int irq, void *ctx)
200 {
201 struct device *dev = ctx;
202 struct rkisp_hw_dev *hw_dev = dev_get_drvdata(dev);
203 struct rkisp_device *isp = hw_dev->isp[hw_dev->cur_dev_id];
204 void __iomem *base = !hw_dev->is_unite ?
205 hw_dev->base_addr : hw_dev->base_next_addr;
206 u32 mis_val, tx_isr = MI_RAW0_WR_FRAME | MI_RAW1_WR_FRAME |
207 MI_RAW2_WR_FRAME | MI_RAW3_WR_FRAME;
208 ktime_t t = 0;
209 s64 us;
210
211 if (hw_dev->is_thunderboot)
212 return IRQ_HANDLED;
213
214 if (rkisp_irq_dbg)
215 t = ktime_get();
216
217 mis_val = readl(base + CIF_MI_MIS);
218 if (mis_val) {
219 if (mis_val & ~tx_isr)
220 rkisp_mi_isr(mis_val & ~tx_isr, isp);
221 if (mis_val & tx_isr) {
222 isp = hw_dev->isp[hw_dev->mipi_dev_id];
223 rkisp_mi_isr(mis_val & tx_isr, isp);
224 }
225 }
226
227 if (rkisp_irq_dbg) {
228 us = ktime_us_delta(ktime_get(), t);
229 v4l2_dbg(0, rkisp_debug, &isp->v4l2_dev,
230 "%s:0x%x %lldus\n", __func__, mis_val, us);
231 }
232 return IRQ_HANDLED;
233 }
234
isp_irq_hdl(int irq,void * ctx)235 static irqreturn_t isp_irq_hdl(int irq, void *ctx)
236 {
237 struct device *dev = ctx;
238 struct rkisp_hw_dev *hw_dev = dev_get_drvdata(dev);
239 struct rkisp_device *isp = hw_dev->isp[hw_dev->cur_dev_id];
240 void __iomem *base = !hw_dev->is_unite ?
241 hw_dev->base_addr : hw_dev->base_next_addr;
242 unsigned int mis_val, mis_3a = 0;
243 ktime_t t = 0;
244 s64 us;
245
246 if (hw_dev->is_thunderboot)
247 return IRQ_HANDLED;
248
249 if (rkisp_irq_dbg)
250 t = ktime_get();
251
252 mis_val = readl(base + CIF_ISP_MIS);
253 if (hw_dev->isp_ver >= ISP_V20)
254 mis_3a = readl(base + ISP_ISP3A_MIS);
255 if (mis_val || mis_3a)
256 rkisp_isp_isr(mis_val, mis_3a, isp);
257
258 if (rkisp_irq_dbg) {
259 us = ktime_us_delta(ktime_get(), t);
260 v4l2_dbg(0, rkisp_debug, &isp->v4l2_dev,
261 "%s:0x%x %lldus\n", __func__, mis_val, us);
262 }
263 return IRQ_HANDLED;
264 }
265
irq_handler(int irq,void * ctx)266 static irqreturn_t irq_handler(int irq, void *ctx)
267 {
268 struct device *dev = ctx;
269 struct rkisp_hw_dev *hw_dev = dev_get_drvdata(dev);
270 struct rkisp_device *isp = hw_dev->isp[hw_dev->cur_dev_id];
271 unsigned int mis_val, mis_3a = 0;
272
273 mis_val = readl(hw_dev->base_addr + CIF_ISP_MIS);
274 if (hw_dev->isp_ver >= ISP_V20)
275 mis_3a = readl(hw_dev->base_addr + ISP_ISP3A_MIS);
276 if (mis_val || mis_3a)
277 rkisp_isp_isr(mis_val, mis_3a, isp);
278
279 mis_val = readl(hw_dev->base_addr + CIF_MIPI_MIS);
280 if (mis_val)
281 rkisp_mipi_isr(mis_val, isp);
282
283 mis_val = readl(hw_dev->base_addr + CIF_MI_MIS);
284 if (mis_val)
285 rkisp_mi_isr(mis_val, isp);
286
287 return IRQ_HANDLED;
288 }
289
rkisp_register_irq(struct rkisp_hw_dev * hw_dev)290 int rkisp_register_irq(struct rkisp_hw_dev *hw_dev)
291 {
292 const struct isp_match_data *match_data = hw_dev->match_data;
293 struct platform_device *pdev = hw_dev->pdev;
294 struct device *dev = &pdev->dev;
295 struct resource *res;
296 int i, ret, irq;
297
298 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
299 match_data->irqs[0].name);
300 if (res) {
301 /* there are irq names in dts */
302 for (i = 0; i < match_data->num_irqs; i++) {
303 irq = platform_get_irq_byname(pdev, match_data->irqs[i].name);
304 if (irq < 0) {
305 dev_err(dev, "no irq %s in dts\n",
306 match_data->irqs[i].name);
307 return irq;
308 }
309
310 if (!strcmp(match_data->irqs[i].name, "mipi_irq"))
311 hw_dev->mipi_irq = irq;
312
313 ret = devm_request_irq(dev, irq,
314 match_data->irqs[i].irq_hdl,
315 IRQF_SHARED,
316 dev_driver_string(dev),
317 dev);
318 if (ret < 0) {
319 dev_err(dev, "request %s failed: %d\n",
320 match_data->irqs[i].name, ret);
321 return ret;
322 }
323
324 if (hw_dev->mipi_irq == irq &&
325 (hw_dev->isp_ver == ISP_V12 ||
326 hw_dev->isp_ver == ISP_V13))
327 disable_irq(hw_dev->mipi_irq);
328 }
329 } else {
330 /* no irq names in dts */
331 irq = platform_get_irq(pdev, 0);
332 if (irq < 0) {
333 dev_err(dev, "no isp irq in dts\n");
334 return irq;
335 }
336
337 ret = devm_request_irq(dev, irq,
338 irq_handler,
339 IRQF_SHARED,
340 dev_driver_string(dev),
341 dev);
342 if (ret < 0) {
343 dev_err(dev, "request irq failed: %d\n", ret);
344 return ret;
345 }
346 }
347
348 return 0;
349 }
350
351 static const char * const rk3562_isp_clks[] = {
352 "clk_isp_core",
353 "aclk_isp",
354 "hclk_isp",
355 };
356
357 static const char * const rk3568_isp_clks[] = {
358 "clk_isp",
359 "aclk_isp",
360 "hclk_isp",
361 };
362
363 static const char * const rk3588_isp_clks[] = {
364 "clk_isp_core",
365 "aclk_isp",
366 "hclk_isp",
367 "clk_isp_core_marvin",
368 "clk_isp_core_vicap",
369 };
370
371 static const char * const rk3588_isp_unite_clks[] = {
372 "clk_isp_core0",
373 "aclk_isp0",
374 "hclk_isp0",
375 "clk_isp_core_marvin0",
376 "clk_isp_core_vicap0",
377 "clk_isp_core1",
378 "aclk_isp1",
379 "hclk_isp1",
380 "clk_isp_core_marvin1",
381 "clk_isp_core_vicap1",
382 };
383
384 static const char * const rv1106_isp_clks[] = {
385 "clk_isp_core",
386 "aclk_isp",
387 "hclk_isp",
388 "clk_isp_core_vicap",
389 };
390
391 static const char * const rv1126_isp_clks[] = {
392 "clk_isp",
393 "aclk_isp",
394 "hclk_isp",
395 };
396
397 static const struct isp_clk_info rk3562_isp_clk_rate[] = {
398 {
399 .clk_rate = 300,
400 .refer_data = 1920, //width
401 }, {
402 .clk_rate = 400,
403 .refer_data = 2688,
404 }, {
405 .clk_rate = 500,
406 .refer_data = 3072,
407 }, {
408 .clk_rate = 600,
409 .refer_data = 3840,
410 }
411 };
412
413 static const struct isp_clk_info rk3568_isp_clk_rate[] = {
414 {
415 .clk_rate = 300,
416 .refer_data = 1920, //width
417 }, {
418 .clk_rate = 400,
419 .refer_data = 2688,
420 }, {
421 .clk_rate = 500,
422 .refer_data = 3072,
423 }, {
424 .clk_rate = 600,
425 .refer_data = 3840,
426 }
427 };
428
429 static const struct isp_clk_info rk3588_isp_clk_rate[] = {
430 {
431 .clk_rate = 300,
432 .refer_data = 1920, //width
433 }, {
434 .clk_rate = 400,
435 .refer_data = 2688,
436 }, {
437 .clk_rate = 500,
438 .refer_data = 3072,
439 }, {
440 .clk_rate = 600,
441 .refer_data = 3840,
442 }, {
443 .clk_rate = 702,
444 .refer_data = 4672,
445 }
446 };
447
448 static const struct isp_clk_info rv1106_isp_clk_rate[] = {
449 {
450 .clk_rate = 200,
451 .refer_data = 1920, //width
452 }, {
453 .clk_rate = 200,
454 .refer_data = 2688,
455 }, {
456 .clk_rate = 350,
457 .refer_data = 3072,
458 }
459 };
460
461 static const struct isp_clk_info rv1126_isp_clk_rate[] = {
462 {
463 .clk_rate = 20,
464 .refer_data = 0,
465 }, {
466 .clk_rate = 300,
467 .refer_data = 1920, //width
468 }, {
469 .clk_rate = 400,
470 .refer_data = 2688,
471 }, {
472 .clk_rate = 500,
473 .refer_data = 3072,
474 }, {
475 .clk_rate = 600,
476 .refer_data = 3840,
477 }
478 };
479
480 static struct isp_irqs_data rk3562_isp_irqs[] = {
481 {"isp_irq", isp_irq_hdl},
482 {"mi_irq", mi_irq_hdl},
483 {"mipi_irq", mipi_irq_hdl}
484 };
485
486 static struct isp_irqs_data rk3568_isp_irqs[] = {
487 {"isp_irq", isp_irq_hdl},
488 {"mi_irq", mi_irq_hdl},
489 {"mipi_irq", mipi_irq_hdl}
490 };
491
492 static struct isp_irqs_data rk3588_isp_irqs[] = {
493 {"isp_irq", isp_irq_hdl},
494 {"mi_irq", mi_irq_hdl},
495 {"mipi_irq", mipi_irq_hdl}
496 };
497
498 static struct isp_irqs_data rv1106_isp_irqs[] = {
499 {"isp_irq", isp_irq_hdl},
500 {"mi_irq", mi_irq_hdl},
501 {"mipi_irq", mipi_irq_hdl}
502 };
503
504 static struct isp_irqs_data rv1126_isp_irqs[] = {
505 {"isp_irq", isp_irq_hdl},
506 {"mi_irq", mi_irq_hdl},
507 {"mipi_irq", mipi_irq_hdl}
508 };
509
510 static const struct isp_match_data rv1106_isp_match_data = {
511 .clks = rv1106_isp_clks,
512 .num_clks = ARRAY_SIZE(rv1106_isp_clks),
513 .isp_ver = ISP_V32,
514 .clk_rate_tbl = rv1106_isp_clk_rate,
515 .num_clk_rate_tbl = ARRAY_SIZE(rv1106_isp_clk_rate),
516 .irqs = rv1106_isp_irqs,
517 .num_irqs = ARRAY_SIZE(rv1106_isp_irqs),
518 .unite = false,
519 };
520
521 static const struct isp_match_data rv1126_isp_match_data = {
522 .clks = rv1126_isp_clks,
523 .num_clks = ARRAY_SIZE(rv1126_isp_clks),
524 .isp_ver = ISP_V20,
525 .clk_rate_tbl = rv1126_isp_clk_rate,
526 .num_clk_rate_tbl = ARRAY_SIZE(rv1126_isp_clk_rate),
527 .irqs = rv1126_isp_irqs,
528 .num_irqs = ARRAY_SIZE(rv1126_isp_irqs),
529 .unite = false,
530 };
531
532 static const struct isp_match_data rk3562_isp_match_data = {
533 .clks = rk3562_isp_clks,
534 .num_clks = ARRAY_SIZE(rk3562_isp_clks),
535 .isp_ver = ISP_V32_L,
536 .clk_rate_tbl = rk3562_isp_clk_rate,
537 .num_clk_rate_tbl = ARRAY_SIZE(rk3562_isp_clk_rate),
538 .irqs = rk3562_isp_irqs,
539 .num_irqs = ARRAY_SIZE(rk3562_isp_irqs),
540 .unite = false,
541 };
542
543 static const struct isp_match_data rk3568_isp_match_data = {
544 .clks = rk3568_isp_clks,
545 .num_clks = ARRAY_SIZE(rk3568_isp_clks),
546 .isp_ver = ISP_V21,
547 .clk_rate_tbl = rk3568_isp_clk_rate,
548 .num_clk_rate_tbl = ARRAY_SIZE(rk3568_isp_clk_rate),
549 .irqs = rk3568_isp_irqs,
550 .num_irqs = ARRAY_SIZE(rk3568_isp_irqs),
551 .unite = false,
552 };
553
554 static const struct isp_match_data rk3588_isp_match_data = {
555 .clks = rk3588_isp_clks,
556 .num_clks = ARRAY_SIZE(rk3588_isp_clks),
557 .isp_ver = ISP_V30,
558 .clk_rate_tbl = rk3588_isp_clk_rate,
559 .num_clk_rate_tbl = ARRAY_SIZE(rk3588_isp_clk_rate),
560 .irqs = rk3588_isp_irqs,
561 .num_irqs = ARRAY_SIZE(rk3588_isp_irqs),
562 .unite = false,
563 };
564
565 static const struct isp_match_data rk3588_isp_unite_match_data = {
566 .clks = rk3588_isp_unite_clks,
567 .num_clks = ARRAY_SIZE(rk3588_isp_unite_clks),
568 .isp_ver = ISP_V30,
569 .clk_rate_tbl = rk3588_isp_clk_rate,
570 .num_clk_rate_tbl = ARRAY_SIZE(rk3588_isp_clk_rate),
571 .irqs = rk3588_isp_irqs,
572 .num_irqs = ARRAY_SIZE(rk3588_isp_irqs),
573 .unite = true,
574 };
575
576 static const struct of_device_id rkisp_hw_of_match[] = {
577 #ifdef CONFIG_CPU_RK3562
578 {
579 .compatible = "rockchip,rk3562-rkisp",
580 .data = &rk3562_isp_match_data,
581 },
582 #endif
583 #ifdef CONFIG_CPU_RK3568
584 {
585 .compatible = "rockchip,rk3568-rkisp",
586 .data = &rk3568_isp_match_data,
587 },
588 #endif
589 #ifdef CONFIG_CPU_RK3588
590 {
591 .compatible = "rockchip,rk3588-rkisp",
592 .data = &rk3588_isp_match_data,
593 }, {
594 .compatible = "rockchip,rk3588-rkisp-unite",
595 .data = &rk3588_isp_unite_match_data,
596 },
597 #endif
598 #ifdef CONFIG_CPU_RV1106
599 {
600 .compatible = "rockchip,rv1106-rkisp",
601 .data = &rv1106_isp_match_data,
602 },
603 #endif
604 #ifdef CONFIG_CPU_RV1126
605 {
606 .compatible = "rockchip,rv1126-rkisp",
607 .data = &rv1126_isp_match_data,
608 },
609 #endif
610 {},
611 };
612
is_iommu_enable(struct device * dev)613 static inline bool is_iommu_enable(struct device *dev)
614 {
615 struct device_node *iommu;
616
617 iommu = of_parse_phandle(dev->of_node, "iommus", 0);
618 if (!iommu) {
619 dev_info(dev, "no iommu attached, using non-iommu buffers\n");
620 return false;
621 } else if (!of_device_is_available(iommu)) {
622 dev_info(dev, "iommu is disabled, using non-iommu buffers\n");
623 of_node_put(iommu);
624 return false;
625 }
626 of_node_put(iommu);
627
628 return true;
629 }
630
rkisp_soft_reset(struct rkisp_hw_dev * dev,bool is_secure)631 void rkisp_soft_reset(struct rkisp_hw_dev *dev, bool is_secure)
632 {
633 void __iomem *base = dev->base_addr;
634 u32 val, iccl0, iccl1, clk_ctrl0, clk_ctrl1;
635
636 /* record clk config and recover */
637 iccl0 = readl(base + CIF_ICCL);
638 clk_ctrl0 = readl(base + CTRL_VI_ISP_CLK_CTRL);
639 if (dev->is_unite) {
640 iccl1 = readl(dev->base_next_addr + CIF_ICCL);
641 clk_ctrl1 = readl(dev->base_next_addr + CTRL_VI_ISP_CLK_CTRL);
642 }
643
644 if (is_secure) {
645 /* if isp working, cru reset isn't secure.
646 * isp soft reset first to protect isp reset.
647 */
648 writel(0xffff, base + CIF_IRCL);
649 if (dev->is_unite)
650 writel(0xffff, dev->base_next_addr + CIF_IRCL);
651 udelay(10);
652 }
653
654 if (dev->reset) {
655 reset_control_assert(dev->reset);
656 udelay(10);
657 reset_control_deassert(dev->reset);
658 udelay(10);
659 }
660
661 /* reset for Dehaze */
662 if (dev->isp_ver == ISP_V20)
663 writel(CIF_ISP_CTRL_ISP_MODE_BAYER_ITU601, base + CIF_ISP_CTRL);
664 val = 0xffff;
665 if (dev->isp_ver == ISP_V32) {
666 val = 0x3fffffff;
667 rv1106_sdmmc_get_lock();
668 }
669 writel(val, base + CIF_IRCL);
670 if (dev->isp_ver == ISP_V32)
671 rv1106_sdmmc_put_lock();
672 if (dev->is_unite)
673 writel(0xffff, dev->base_next_addr + CIF_IRCL);
674 udelay(10);
675
676 /* refresh iommu after reset */
677 if (dev->is_mmu) {
678 rockchip_iommu_disable(dev->dev);
679 rockchip_iommu_enable(dev->dev);
680 }
681
682 writel(iccl0, base + CIF_ICCL);
683 writel(clk_ctrl0, base + CTRL_VI_ISP_CLK_CTRL);
684 if (dev->is_unite) {
685 writel(iccl1, dev->base_next_addr + CIF_ICCL);
686 writel(clk_ctrl1, dev->base_next_addr + CTRL_VI_ISP_CLK_CTRL);
687 }
688
689 /* default config */
690 if (dev->isp_ver == ISP_V12 || dev->isp_ver == ISP_V13) {
691 /* disable csi_rx interrupt */
692 writel(0, dev->base_addr + CIF_ISP_CSI0_CTRL0);
693 writel(0, dev->base_addr + CIF_ISP_CSI0_MASK1);
694 writel(0, dev->base_addr + CIF_ISP_CSI0_MASK2);
695 writel(0, dev->base_addr + CIF_ISP_CSI0_MASK3);
696 } else if (dev->isp_ver == ISP_V32) {
697 /* disable down samplling default */
698 writel(ISP32_DS_DS_DIS, dev->base_addr + ISP32_MI_MPDS_WR_CTRL);
699 writel(ISP32_DS_DS_DIS, dev->base_addr + ISP32_MI_BPDS_WR_CTRL);
700
701 writel(0, dev->base_addr + ISP32_BLS_ISP_OB_PREDGAIN);
702 writel(0x37, dev->base_addr + ISP32_MI_WR_WRAP_CTRL);
703 } else if (dev->isp_ver == ISP_V32_L) {
704 writel(0, dev->base_addr + ISP32_BLS_ISP_OB_PREDGAIN);
705 }
706 }
707
isp_config_clk(struct rkisp_hw_dev * dev,int on)708 static void isp_config_clk(struct rkisp_hw_dev *dev, int on)
709 {
710 u32 val = !on ? 0 :
711 CIF_ICCL_ISP_CLK | CIF_ICCL_CP_CLK | CIF_ICCL_MRSZ_CLK |
712 CIF_ICCL_SRSZ_CLK | CIF_ICCL_JPEG_CLK | CIF_ICCL_MI_CLK |
713 CIF_ICCL_IE_CLK | CIF_ICCL_MIPI_CLK | CIF_ICCL_DCROP_CLK;
714
715 if ((dev->isp_ver == ISP_V20 || dev->isp_ver >= ISP_V30) && on)
716 val |= ICCL_MPFBC_CLK;
717 if (dev->isp_ver >= ISP_V32) {
718 val |= ISP32_BRSZ_CLK_ENABLE | BIT(0) | BIT(16);
719 if (dev->isp_ver == ISP_V32)
720 rv1106_sdmmc_get_lock();
721 }
722 writel(val, dev->base_addr + CIF_ICCL);
723 if (dev->isp_ver == ISP_V32)
724 rv1106_sdmmc_put_lock();
725 if (dev->is_unite)
726 writel(val, dev->base_next_addr + CIF_ICCL);
727
728 if (dev->isp_ver == ISP_V12 || dev->isp_ver == ISP_V13) {
729 val = !on ? 0 :
730 CIF_CLK_CTRL_MI_Y12 | CIF_CLK_CTRL_MI_SP |
731 CIF_CLK_CTRL_MI_RAW0 | CIF_CLK_CTRL_MI_RAW1 |
732 CIF_CLK_CTRL_MI_READ | CIF_CLK_CTRL_MI_RAWRD |
733 CIF_CLK_CTRL_CP | CIF_CLK_CTRL_IE;
734
735 writel(val, dev->base_addr + CIF_VI_ISP_CLK_CTRL_V12);
736 } else if (dev->isp_ver >= ISP_V20) {
737 val = !on ? 0 :
738 CLK_CTRL_MI_LDC | CLK_CTRL_MI_MP |
739 CLK_CTRL_MI_JPEG | CLK_CTRL_MI_DP |
740 CLK_CTRL_MI_Y12 | CLK_CTRL_MI_SP |
741 CLK_CTRL_MI_RAW0 | CLK_CTRL_MI_RAW1 |
742 CLK_CTRL_MI_READ | CLK_CTRL_MI_RAWRD |
743 CLK_CTRL_ISP_RAW | CLK_CTRL_ISP_3A;
744
745 if (dev->isp_ver >= ISP_V30)
746 val = 0;
747
748 if ((dev->isp_ver == ISP_V20 || dev->isp_ver == ISP_V30) && on)
749 val |= CLK_CTRL_ISP_3A;
750 if (dev->isp_ver == ISP_V32)
751 rv1106_sdmmc_get_lock();
752 writel(val, dev->base_addr + CTRL_VI_ISP_CLK_CTRL);
753 if (dev->isp_ver == ISP_V32)
754 rv1106_sdmmc_put_lock();
755 if (dev->is_unite)
756 writel(val, dev->base_next_addr + CTRL_VI_ISP_CLK_CTRL);
757 }
758 }
759
disable_sys_clk(struct rkisp_hw_dev * dev)760 static void disable_sys_clk(struct rkisp_hw_dev *dev)
761 {
762 int i;
763
764 if (dev->isp_ver == ISP_V12 || dev->isp_ver == ISP_V13) {
765 if (dev->mipi_irq >= 0)
766 disable_irq(dev->mipi_irq);
767 }
768
769 isp_config_clk(dev, false);
770
771 for (i = dev->num_clks - 1; i >= 0; i--)
772 if (!IS_ERR(dev->clks[i]))
773 clk_disable_unprepare(dev->clks[i]);
774 }
775
enable_sys_clk(struct rkisp_hw_dev * dev)776 static int enable_sys_clk(struct rkisp_hw_dev *dev)
777 {
778 int i, ret = -EINVAL;
779 unsigned long rate;
780
781 for (i = 0; i < dev->num_clks; i++) {
782 if (!IS_ERR(dev->clks[i])) {
783 ret = clk_prepare_enable(dev->clks[i]);
784 if (ret < 0)
785 goto err;
786 }
787 }
788
789 if (!dev->is_assigned_clk) {
790 rate = dev->clk_rate_tbl[0].clk_rate * 1000000UL;
791 rkisp_set_clk_rate(dev->clks[0], rate);
792 if (dev->is_unite)
793 rkisp_set_clk_rate(dev->clks[5], rate);
794 }
795 rkisp_soft_reset(dev, false);
796 isp_config_clk(dev, true);
797 return 0;
798 err:
799 for (--i; i >= 0; --i)
800 if (!IS_ERR(dev->clks[i]))
801 clk_disable_unprepare(dev->clks[i]);
802 return ret;
803 }
804
rkisp_get_sram(struct rkisp_hw_dev * hw_dev)805 static int rkisp_get_sram(struct rkisp_hw_dev *hw_dev)
806 {
807 struct device *dev = hw_dev->dev;
808 struct rkisp_sram *sram = &hw_dev->sram;
809 struct device_node *np;
810 struct resource res;
811 int ret, size;
812
813 sram->size = 0;
814 np = of_parse_phandle(dev->of_node, "rockchip,sram", 0);
815 if (!np) {
816 dev_warn(dev, "no find phandle sram\n");
817 return -ENODEV;
818 }
819
820 ret = of_address_to_resource(np, 0, &res);
821 of_node_put(np);
822 if (ret) {
823 dev_err(dev, "get sram res error\n");
824 return ret;
825 }
826 size = resource_size(&res);
827 sram->dma_addr = dma_map_resource(dev, res.start, size, DMA_BIDIRECTIONAL, 0);
828 if (dma_mapping_error(dev, sram->dma_addr))
829 return -ENOMEM;
830 sram->size = size;
831 dev_info(dev, "get sram size:%d\n", size);
832 return 0;
833 }
834
rkisp_put_sram(struct rkisp_hw_dev * hw_dev)835 static void rkisp_put_sram(struct rkisp_hw_dev *hw_dev)
836 {
837 if (hw_dev->sram.size)
838 dma_unmap_resource(hw_dev->dev, hw_dev->sram.dma_addr,
839 hw_dev->sram.size, DMA_BIDIRECTIONAL, 0);
840 hw_dev->sram.size = 0;
841 }
842
rkisp_hw_probe(struct platform_device * pdev)843 static int rkisp_hw_probe(struct platform_device *pdev)
844 {
845 const struct of_device_id *match;
846 const struct isp_match_data *match_data;
847 struct device_node *node = pdev->dev.of_node;
848 struct device *dev = &pdev->dev;
849 struct rkisp_hw_dev *hw_dev;
850 struct resource *res;
851 int i, ret;
852 bool is_mem_reserved = true;
853 u32 clk_rate = 0;
854
855 match = of_match_node(rkisp_hw_of_match, node);
856 if (IS_ERR(match))
857 return PTR_ERR(match);
858
859 hw_dev = devm_kzalloc(dev, sizeof(*hw_dev), GFP_KERNEL);
860 if (!hw_dev)
861 return -ENOMEM;
862
863 match_data = match->data;
864 hw_dev->is_unite = match_data->unite;
865 dev_set_drvdata(dev, hw_dev);
866 hw_dev->dev = dev;
867 hw_dev->is_thunderboot = IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP);
868 dev_info(dev, "is_thunderboot: %d\n", hw_dev->is_thunderboot);
869 memset(&hw_dev->max_in, 0, sizeof(hw_dev->max_in));
870 if (!of_property_read_u32_array(node, "max-input", &hw_dev->max_in.w, 3)) {
871 hw_dev->max_in.is_fix = true;
872 if (hw_dev->is_unite) {
873 hw_dev->max_in.w /= 2;
874 hw_dev->max_in.w += RKMOUDLE_UNITE_EXTEND_PIXEL;
875 }
876 }
877 dev_info(dev, "max input:%dx%d@%dfps\n",
878 hw_dev->max_in.w, hw_dev->max_in.h, hw_dev->max_in.fps);
879 hw_dev->grf = syscon_regmap_lookup_by_phandle(node, "rockchip,grf");
880 if (IS_ERR(hw_dev->grf))
881 dev_warn(dev, "Missing rockchip,grf property\n");
882
883 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
884 if (!res) {
885 dev_err(dev, "get resource failed\n");
886 ret = -EINVAL;
887 goto err;
888 }
889 hw_dev->base_addr = devm_ioremap_resource(dev, res);
890 if (PTR_ERR(hw_dev->base_addr) == -EBUSY) {
891 resource_size_t offset = res->start;
892 resource_size_t size = resource_size(res);
893
894 hw_dev->base_addr = devm_ioremap(dev, offset, size);
895 }
896 if (IS_ERR(hw_dev->base_addr)) {
897 dev_err(dev, "ioremap failed\n");
898 ret = PTR_ERR(hw_dev->base_addr);
899 goto err;
900 }
901
902 hw_dev->base_next_addr = NULL;
903 if (match_data->unite) {
904 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
905 if (!res) {
906 dev_err(dev, "get next resource failed\n");
907 ret = -EINVAL;
908 goto err;
909 }
910 hw_dev->base_next_addr = devm_ioremap_resource(dev, res);
911 if (PTR_ERR(hw_dev->base_next_addr) == -EBUSY) {
912 resource_size_t offset = res->start;
913 resource_size_t size = resource_size(res);
914
915 hw_dev->base_next_addr = devm_ioremap(dev, offset, size);
916 }
917
918 if (IS_ERR(hw_dev->base_next_addr)) {
919 dev_err(dev, "ioremap next failed\n");
920 ret = PTR_ERR(hw_dev->base_next_addr);
921 goto err;
922 }
923 }
924
925 rkisp_monitor = device_property_read_bool(dev, "rockchip,restart-monitor-en");
926 hw_dev->mipi_irq = -1;
927
928 hw_dev->pdev = pdev;
929 hw_dev->match_data = match_data;
930 if (!hw_dev->is_thunderboot)
931 rkisp_register_irq(hw_dev);
932
933 for (i = 0; i < match_data->num_clks; i++) {
934 struct clk *clk = devm_clk_get(dev, match_data->clks[i]);
935
936 if (IS_ERR(clk)) {
937 dev_err(dev, "failed to get %s\n", match_data->clks[i]);
938 ret = PTR_ERR(clk);
939 goto err;
940 }
941 hw_dev->clks[i] = clk;
942 }
943 hw_dev->num_clks = match_data->num_clks;
944 hw_dev->clk_rate_tbl = match_data->clk_rate_tbl;
945 hw_dev->num_clk_rate_tbl = match_data->num_clk_rate_tbl;
946
947 hw_dev->is_assigned_clk = false;
948 ret = of_property_read_u32(node, "assigned-clock-rates", &clk_rate);
949 if (!ret && clk_rate)
950 hw_dev->is_assigned_clk = true;
951
952 hw_dev->reset = devm_reset_control_array_get(dev, false, false);
953 if (IS_ERR(hw_dev->reset)) {
954 dev_dbg(dev, "failed to get reset\n");
955 hw_dev->reset = NULL;
956 }
957
958 ret = of_property_read_u64(node, "rockchip,iq-feature", &hw_dev->iq_feature);
959 if (!ret)
960 hw_dev->is_feature_on = true;
961 else
962 hw_dev->is_feature_on = false;
963
964 rkisp_get_sram(hw_dev);
965
966 hw_dev->dev_num = 0;
967 hw_dev->dev_link_num = 0;
968 hw_dev->cur_dev_id = 0;
969 hw_dev->mipi_dev_id = 0;
970 hw_dev->pre_dev_id = 0;
971 hw_dev->is_multi_overflow = false;
972 hw_dev->isp_ver = match_data->isp_ver;
973 hw_dev->is_unite = match_data->unite;
974 mutex_init(&hw_dev->dev_lock);
975 spin_lock_init(&hw_dev->rdbk_lock);
976 atomic_set(&hw_dev->refcnt, 0);
977 spin_lock_init(&hw_dev->buf_lock);
978 INIT_LIST_HEAD(&hw_dev->list);
979 INIT_LIST_HEAD(&hw_dev->rpt_list);
980 hw_dev->buf_init_cnt = 0;
981 hw_dev->is_idle = true;
982 hw_dev->is_single = true;
983 hw_dev->is_mi_update = false;
984 hw_dev->is_dma_contig = true;
985 hw_dev->is_dma_sg_ops = true;
986 hw_dev->is_buf_init = false;
987 hw_dev->is_shutdown = false;
988 hw_dev->is_mmu = is_iommu_enable(dev);
989 ret = of_reserved_mem_device_init(dev);
990 if (ret) {
991 is_mem_reserved = false;
992 if (!hw_dev->is_mmu)
993 dev_info(dev, "No reserved memory region. default cma area!\n");
994 }
995 if (hw_dev->is_mmu && !is_mem_reserved)
996 hw_dev->is_dma_contig = false;
997 hw_dev->mem_ops = &vb2_cma_sg_memops;
998
999 pm_runtime_enable(dev);
1000
1001 return 0;
1002 err:
1003 return ret;
1004 }
1005
rkisp_hw_remove(struct platform_device * pdev)1006 static int rkisp_hw_remove(struct platform_device *pdev)
1007 {
1008 struct rkisp_hw_dev *hw_dev = platform_get_drvdata(pdev);
1009
1010 rkisp_put_sram(hw_dev);
1011 pm_runtime_disable(&pdev->dev);
1012 mutex_destroy(&hw_dev->dev_lock);
1013 return 0;
1014 }
1015
rkisp_hw_shutdown(struct platform_device * pdev)1016 static void rkisp_hw_shutdown(struct platform_device *pdev)
1017 {
1018 struct rkisp_hw_dev *hw_dev = platform_get_drvdata(pdev);
1019
1020 hw_dev->is_shutdown = true;
1021 if (pm_runtime_active(&pdev->dev)) {
1022 writel(0xffff, hw_dev->base_addr + CIF_IRCL);
1023 if (hw_dev->is_unite)
1024 writel(0xffff, hw_dev->base_next_addr + CIF_IRCL);
1025 }
1026 dev_info(&pdev->dev, "%s\n", __func__);
1027 }
1028
rkisp_runtime_suspend(struct device * dev)1029 static int __maybe_unused rkisp_runtime_suspend(struct device *dev)
1030 {
1031 struct rkisp_hw_dev *hw_dev = dev_get_drvdata(dev);
1032
1033 hw_dev->dev_link_num = 0;
1034 hw_dev->is_single = true;
1035 hw_dev->is_multi_overflow = false;
1036 hw_dev->is_frm_buf = false;
1037 disable_sys_clk(hw_dev);
1038 return pinctrl_pm_select_sleep_state(dev);
1039 }
1040
rkisp_hw_enum_isp_size(struct rkisp_hw_dev * hw_dev)1041 void rkisp_hw_enum_isp_size(struct rkisp_hw_dev *hw_dev)
1042 {
1043 struct rkisp_device *isp;
1044 u32 w, h, i;
1045
1046 memset(hw_dev->isp_size, 0, sizeof(hw_dev->isp_size));
1047 if (!hw_dev->max_in.is_fix) {
1048 hw_dev->max_in.w = 0;
1049 hw_dev->max_in.h = 0;
1050 }
1051 hw_dev->dev_link_num = 0;
1052 hw_dev->is_single = true;
1053 hw_dev->is_multi_overflow = false;
1054 hw_dev->is_frm_buf = false;
1055 for (i = 0; i < hw_dev->dev_num; i++) {
1056 isp = hw_dev->isp[i];
1057 if (!isp || (isp && !isp->is_hw_link))
1058 continue;
1059 if (hw_dev->dev_link_num++)
1060 hw_dev->is_single = false;
1061 w = isp->isp_sdev.in_crop.width;
1062 h = isp->isp_sdev.in_crop.height;
1063 if (hw_dev->is_unite)
1064 w = w / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL;
1065 hw_dev->isp_size[i].w = w;
1066 hw_dev->isp_size[i].h = h;
1067 hw_dev->isp_size[i].size = w * h;
1068 if (!hw_dev->max_in.is_fix) {
1069 if (hw_dev->max_in.w < w)
1070 hw_dev->max_in.w = w;
1071 if (hw_dev->max_in.h < h)
1072 hw_dev->max_in.h = h;
1073 }
1074 }
1075 for (i = 0; i < hw_dev->dev_num; i++) {
1076 isp = hw_dev->isp[i];
1077 if (!isp || (isp && !isp->is_hw_link))
1078 continue;
1079 rkisp_params_check_bigmode(&isp->params_vdev);
1080 }
1081 }
1082
rkisp_runtime_resume(struct device * dev)1083 static int __maybe_unused rkisp_runtime_resume(struct device *dev)
1084 {
1085 struct rkisp_hw_dev *hw_dev = dev_get_drvdata(dev);
1086 void __iomem *base = hw_dev->base_addr;
1087 struct rkisp_device *isp;
1088 int mult = hw_dev->is_unite ? 2 : 1;
1089 int ret, i;
1090 void *buf;
1091
1092 ret = pinctrl_pm_select_default_state(dev);
1093 if (ret < 0)
1094 return ret;
1095
1096 enable_sys_clk(hw_dev);
1097 for (i = 0; i < hw_dev->dev_num; i++) {
1098 isp = hw_dev->isp[i];
1099 if (!isp || !isp->sw_base_addr)
1100 continue;
1101 buf = isp->sw_base_addr;
1102 memset(buf, 0, RKISP_ISP_SW_MAX_SIZE * mult);
1103 memcpy_fromio(buf, base, RKISP_ISP_SW_REG_SIZE);
1104 if (hw_dev->is_unite) {
1105 buf += RKISP_ISP_SW_MAX_SIZE;
1106 base = hw_dev->base_next_addr;
1107 memcpy_fromio(buf, base, RKISP_ISP_SW_REG_SIZE);
1108 }
1109 default_sw_reg_flag(hw_dev->isp[i]);
1110 }
1111 rkisp_hw_enum_isp_size(hw_dev);
1112 hw_dev->monitor.is_en = rkisp_monitor;
1113 return 0;
1114 }
1115
1116 static const struct dev_pm_ops rkisp_hw_pm_ops = {
1117 SET_RUNTIME_PM_OPS(rkisp_runtime_suspend,
1118 rkisp_runtime_resume, NULL)
1119 };
1120
1121 static struct platform_driver rkisp_hw_drv = {
1122 .driver = {
1123 .name = "rkisp_hw",
1124 .of_match_table = of_match_ptr(rkisp_hw_of_match),
1125 .pm = &rkisp_hw_pm_ops,
1126 },
1127 .probe = rkisp_hw_probe,
1128 .remove = rkisp_hw_remove,
1129 .shutdown = rkisp_hw_shutdown,
1130 };
1131
rkisp_hw_drv_init(void)1132 static int __init rkisp_hw_drv_init(void)
1133 {
1134 int ret;
1135
1136 ret = platform_driver_register(&rkisp_hw_drv);
1137 if (!ret)
1138 ret = platform_driver_register(&rkisp_plat_drv);
1139 #if IS_BUILTIN(CONFIG_VIDEO_ROCKCHIP_ISP) && IS_BUILTIN(CONFIG_VIDEO_ROCKCHIP_ISPP)
1140 if (!ret)
1141 ret = rkispp_hw_drv_init();
1142 #endif
1143 return ret;
1144 }
1145
rkisp_hw_drv_exit(void)1146 static void __exit rkisp_hw_drv_exit(void)
1147 {
1148 platform_driver_unregister(&rkisp_plat_drv);
1149 platform_driver_unregister(&rkisp_hw_drv);
1150 }
1151
1152 #if defined(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP) && !defined(CONFIG_INITCALL_ASYNC)
1153 subsys_initcall(rkisp_hw_drv_init);
1154 #else
1155 module_init(rkisp_hw_drv_init);
1156 #endif
1157 module_exit(rkisp_hw_drv_exit);
1158