1 /*
2 * Rockchip isp1 driver
3 *
4 * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35 #include <linux/clk.h>
36 #include <linux/iopoll.h>
37 #include <linux/pm_runtime.h>
38 #include <linux/regmap.h>
39 #include <linux/videodev2.h>
40 #include <linux/vmalloc.h>
41 #include <linux/kfifo.h>
42 #include <linux/interrupt.h>
43 #include <linux/rk-preisp.h>
44 #include <linux/iommu.h>
45 #include <media/v4l2-event.h>
46 #include <media/media-entity.h>
47
48 #include "common.h"
49 #include "regs.h"
50
51 /*
52 * NOTE: MIPI controller and input MUX are also configured in this file,
53 * because ISP Subdev is not only describe ISP submodule(input size,format, output size, format),
54 * but also a virtual route device.
55 */
56
57 /*
58 * There are many variables named with format/frame in below code,
59 * please see here for their meaning.
60 *
61 * Cropping regions of ISP
62 *
63 * +---------------------------------------------------------+
64 * | Sensor image |
65 * | +---------------------------------------------------+ |
66 * | | ISP_ACQ (for black level) | |
67 * | | in_frm | |
68 * | | +--------------------------------------------+ | |
69 * | | | ISP_OUT | | |
70 * | | | in_crop | | |
71 * | | | +---------------------------------+ | | |
72 * | | | | ISP_IS | | | |
73 * | | | | rkisp1_isp_subdev: out_crop | | | |
74 * | | | +---------------------------------+ | | |
75 * | | +--------------------------------------------+ | |
76 * | +---------------------------------------------------+ |
77 * +---------------------------------------------------------+
78 */
79
sd_to_isp_dev(struct v4l2_subdev * sd)80 static inline struct rkisp1_device *sd_to_isp_dev(struct v4l2_subdev *sd)
81 {
82 return container_of(sd->v4l2_dev, struct rkisp1_device, v4l2_dev);
83 }
84
85 /* Get sensor by enabled media link */
get_remote_sensor(struct v4l2_subdev * sd)86 static struct v4l2_subdev *get_remote_sensor(struct v4l2_subdev *sd)
87 {
88 struct media_pad *local, *remote;
89 struct media_entity *sensor_me;
90
91 local = &sd->entity.pads[RKISP1_ISP_PAD_SINK];
92 if (!local)
93 return NULL;
94 remote = media_entity_remote_pad(local);
95 if (!remote)
96 return NULL;
97
98 sensor_me = remote->entity;
99
100 return media_entity_to_v4l2_subdev(sensor_me);
101 }
102
get_remote_mipi_sensor(struct rkisp1_device * dev,struct v4l2_subdev ** sensor_sd)103 static void get_remote_mipi_sensor(struct rkisp1_device *dev,
104 struct v4l2_subdev **sensor_sd)
105 {
106 struct media_graph graph;
107 struct media_entity *entity = &dev->isp_sdev.sd.entity;
108 struct media_device *mdev = entity->graph_obj.mdev;
109 int ret;
110
111 /* Walk the graph to locate sensor nodes. */
112 mutex_lock(&mdev->graph_mutex);
113 ret = media_graph_walk_init(&graph, mdev);
114 if (ret) {
115 mutex_unlock(&mdev->graph_mutex);
116 *sensor_sd = NULL;
117 return;
118 }
119
120 media_graph_walk_start(&graph, entity);
121 while ((entity = media_graph_walk_next(&graph))) {
122 if (entity->function == MEDIA_ENT_F_CAM_SENSOR)
123 break;
124 }
125 mutex_unlock(&mdev->graph_mutex);
126 media_graph_walk_cleanup(&graph);
127
128 if (entity)
129 *sensor_sd = media_entity_to_v4l2_subdev(entity);
130 else
131 *sensor_sd = NULL;
132 }
133
sd_to_sensor(struct rkisp1_device * dev,struct v4l2_subdev * sd)134 static struct rkisp1_sensor_info *sd_to_sensor(struct rkisp1_device *dev,
135 struct v4l2_subdev *sd)
136 {
137 int i;
138
139 for (i = 0; i < dev->num_sensors; ++i)
140 if (dev->sensors[i].sd == sd)
141 return &dev->sensors[i];
142
143 return NULL;
144 }
145
rkisp1_update_sensor_info(struct rkisp1_device * dev)146 int rkisp1_update_sensor_info(struct rkisp1_device *dev)
147 {
148 struct v4l2_subdev *sd = &dev->isp_sdev.sd;
149 struct rkisp1_sensor_info *sensor;
150 struct v4l2_subdev *sensor_sd;
151 int ret = 0;
152
153 sensor_sd = get_remote_sensor(sd);
154 if (!sensor_sd)
155 return -ENODEV;
156
157 sensor = sd_to_sensor(dev, sensor_sd);
158 if (!sensor)
159 return -ENODEV;
160
161 ret = v4l2_subdev_call(sensor->sd, pad, get_mbus_config,
162 0, &sensor->mbus);
163 if (ret && ret != -ENOIOCTLCMD)
164 return ret;
165
166 sensor->fmt.pad = 0;
167 sensor->fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
168 ret = v4l2_subdev_call(sensor->sd, pad, get_fmt,
169 &sensor->cfg, &sensor->fmt);
170 if (ret && ret != -ENOIOCTLCMD)
171 return ret;
172 dev->active_sensor = sensor;
173
174 return ret;
175 }
176
rkisp1_mbus_pixelcode_to_v4l2(u32 pixelcode)177 u32 rkisp1_mbus_pixelcode_to_v4l2(u32 pixelcode)
178 {
179 u32 pixelformat;
180
181 switch (pixelcode) {
182 case MEDIA_BUS_FMT_SBGGR8_1X8:
183 pixelformat = V4L2_PIX_FMT_SBGGR8;
184 break;
185 case MEDIA_BUS_FMT_SGBRG8_1X8:
186 pixelformat = V4L2_PIX_FMT_SGBRG8;
187 break;
188 case MEDIA_BUS_FMT_SGRBG8_1X8:
189 pixelformat = V4L2_PIX_FMT_SGRBG8;
190 break;
191 case MEDIA_BUS_FMT_SRGGB8_1X8:
192 pixelformat = V4L2_PIX_FMT_SRGGB8;
193 break;
194 case MEDIA_BUS_FMT_SBGGR10_1X10:
195 pixelformat = V4L2_PIX_FMT_SBGGR10;
196 break;
197 case MEDIA_BUS_FMT_SGBRG10_1X10:
198 pixelformat = V4L2_PIX_FMT_SGBRG10;
199 break;
200 case MEDIA_BUS_FMT_SGRBG10_1X10:
201 pixelformat = V4L2_PIX_FMT_SGRBG10;
202 break;
203 case MEDIA_BUS_FMT_SRGGB10_1X10:
204 pixelformat = V4L2_PIX_FMT_SRGGB10;
205 break;
206 case MEDIA_BUS_FMT_SBGGR12_1X12:
207 pixelformat = V4L2_PIX_FMT_SBGGR12;
208 break;
209 case MEDIA_BUS_FMT_SGBRG12_1X12:
210 pixelformat = V4L2_PIX_FMT_SGBRG12;
211 break;
212 case MEDIA_BUS_FMT_SGRBG12_1X12:
213 pixelformat = V4L2_PIX_FMT_SGRBG12;
214 break;
215 case MEDIA_BUS_FMT_SRGGB12_1X12:
216 pixelformat = V4L2_PIX_FMT_SRGGB12;
217 break;
218 default:
219 pixelformat = V4L2_PIX_FMT_SRGGB10;
220 }
221
222 return pixelformat;
223 }
224
225 /**************** register operations ****************/
226
rkisp1_config_clk(struct rkisp1_device * dev,int on)227 static void rkisp1_config_clk(struct rkisp1_device *dev, int on)
228 {
229 u32 val = !on ? 0 :
230 CIF_ICCL_ISP_CLK | CIF_ICCL_CP_CLK | CIF_ICCL_MRSZ_CLK |
231 CIF_ICCL_SRSZ_CLK | CIF_ICCL_JPEG_CLK | CIF_ICCL_MI_CLK |
232 CIF_ICCL_IE_CLK | CIF_ICCL_MIPI_CLK | CIF_ICCL_DCROP_CLK;
233
234 writel(val, dev->base_addr + CIF_ICCL);
235
236 #if RKISP1_RK3326_USE_OLDMIPI
237 if (dev->isp_ver == ISP_V13) {
238 #else
239 if (dev->isp_ver == ISP_V12 || dev->isp_ver == ISP_V13) {
240 #endif
241 val = !on ? 0 :
242 CIF_CLK_CTRL_MI_Y12 | CIF_CLK_CTRL_MI_SP |
243 CIF_CLK_CTRL_MI_RAW0 | CIF_CLK_CTRL_MI_RAW1 |
244 CIF_CLK_CTRL_MI_READ | CIF_CLK_CTRL_MI_RAWRD |
245 CIF_CLK_CTRL_CP | CIF_CLK_CTRL_IE;
246
247 writel(val, dev->base_addr + CIF_VI_ISP_CLK_CTRL_V12);
248 }
249 }
250
251 /*
252 * Image Stabilization.
253 * This should only be called when configuring CIF
254 * or at the frame end interrupt
255 */
256 static void rkisp1_config_ism(struct rkisp1_device *dev)
257 {
258 void __iomem *base = dev->base_addr;
259 struct v4l2_rect *out_crop = &dev->isp_sdev.out_crop;
260 u32 val;
261
262 writel(0, base + CIF_ISP_IS_RECENTER);
263 writel(0, base + CIF_ISP_IS_MAX_DX);
264 writel(0, base + CIF_ISP_IS_MAX_DY);
265 writel(0, base + CIF_ISP_IS_DISPLACE);
266 writel(out_crop->left, base + CIF_ISP_IS_H_OFFS);
267 writel(out_crop->top, base + CIF_ISP_IS_V_OFFS);
268 writel(out_crop->width, base + CIF_ISP_IS_H_SIZE);
269 if (dev->stream[RKISP1_STREAM_SP].interlaced)
270 writel(out_crop->height / 2, base + CIF_ISP_IS_V_SIZE);
271 else
272 writel(out_crop->height, base + CIF_ISP_IS_V_SIZE);
273
274 /* IS(Image Stabilization) is always on, working as output crop */
275 writel(1, base + CIF_ISP_IS_CTRL);
276 val = readl(base + CIF_ISP_CTRL);
277 val |= CIF_ISP_CTRL_ISP_CFG_UPD;
278 writel(val, base + CIF_ISP_CTRL);
279 }
280
281 /*
282 * configure isp blocks with input format, size......
283 */
284 static int rkisp1_config_isp(struct rkisp1_device *dev)
285 {
286 struct ispsd_in_fmt *in_fmt;
287 struct ispsd_out_fmt *out_fmt;
288 struct v4l2_mbus_framefmt *in_frm;
289 struct v4l2_rect *in_crop;
290 struct rkisp1_sensor_info *sensor;
291 void __iomem *base = dev->base_addr;
292 u32 isp_ctrl = 0;
293 u32 irq_mask = 0;
294 u32 signal = 0;
295 u32 acq_mult = 0;
296 u32 acq_prop = 0;
297
298 sensor = dev->active_sensor;
299 in_frm = &dev->isp_sdev.in_frm;
300 in_fmt = &dev->isp_sdev.in_fmt;
301 out_fmt = &dev->isp_sdev.out_fmt;
302 in_crop = &dev->isp_sdev.in_crop;
303
304 if (in_fmt->fmt_type == FMT_BAYER) {
305 acq_mult = 1;
306 if (out_fmt->fmt_type == FMT_BAYER) {
307 if (sensor && sensor->mbus.type == V4L2_MBUS_BT656)
308 isp_ctrl =
309 CIF_ISP_CTRL_ISP_MODE_RAW_PICT_ITU656;
310 else
311 isp_ctrl =
312 CIF_ISP_CTRL_ISP_MODE_RAW_PICT;
313 } else {
314 /* demosaicing bypass for grey sensor */
315 if (in_fmt->mbus_code == MEDIA_BUS_FMT_Y8_1X8 ||
316 in_fmt->mbus_code == MEDIA_BUS_FMT_Y10_1X10 ||
317 in_fmt->mbus_code == MEDIA_BUS_FMT_Y12_1X12)
318 writel(CIF_ISP_DEMOSAIC_BYPASS |
319 CIF_ISP_DEMOSAIC_TH(0xc),
320 base + CIF_ISP_DEMOSAIC);
321 else
322 writel(CIF_ISP_DEMOSAIC_TH(0xc),
323 base + CIF_ISP_DEMOSAIC);
324
325 if (sensor && sensor->mbus.type == V4L2_MBUS_BT656)
326 isp_ctrl = CIF_ISP_CTRL_ISP_MODE_BAYER_ITU656;
327 else
328 isp_ctrl = CIF_ISP_CTRL_ISP_MODE_BAYER_ITU601;
329 }
330
331 if (dev->isp_inp == INP_DMARX_ISP)
332 acq_prop = CIF_ISP_ACQ_PROP_DMA_RGB;
333 } else if (in_fmt->fmt_type == FMT_YUV) {
334 acq_mult = 2;
335 if (sensor && (sensor->mbus.type == V4L2_MBUS_CSI2_DPHY ||
336 sensor->mbus.type == V4L2_MBUS_CCP2)) {
337 isp_ctrl = CIF_ISP_CTRL_ISP_MODE_ITU601;
338 } else {
339 if (sensor && sensor->mbus.type == V4L2_MBUS_BT656)
340 isp_ctrl = CIF_ISP_CTRL_ISP_MODE_ITU656;
341 else
342 isp_ctrl = CIF_ISP_CTRL_ISP_MODE_ITU601;
343 }
344
345 irq_mask |= CIF_ISP_DATA_LOSS;
346 if (dev->isp_inp == INP_DMARX_ISP)
347 acq_prop = CIF_ISP_ACQ_PROP_DMA_YUV;
348 }
349
350 /* Set up input acquisition properties */
351 if (sensor && (sensor->mbus.type == V4L2_MBUS_BT656 ||
352 sensor->mbus.type == V4L2_MBUS_PARALLEL)) {
353 if (sensor->mbus.flags &
354 V4L2_MBUS_PCLK_SAMPLE_RISING)
355 signal = CIF_ISP_ACQ_PROP_POS_EDGE;
356 }
357
358 if (sensor && sensor->mbus.type == V4L2_MBUS_PARALLEL) {
359 if (sensor->mbus.flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)
360 signal |= CIF_ISP_ACQ_PROP_VSYNC_LOW;
361
362 if (sensor->mbus.flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
363 signal |= CIF_ISP_ACQ_PROP_HSYNC_LOW;
364 }
365
366 writel(isp_ctrl, base + CIF_ISP_CTRL);
367 acq_prop |= signal | in_fmt->yuv_seq |
368 CIF_ISP_ACQ_PROP_BAYER_PAT(in_fmt->bayer_pat) |
369 CIF_ISP_ACQ_PROP_FIELD_SEL_ALL;
370 writel(acq_prop, base + CIF_ISP_ACQ_PROP);
371 writel(0, base + CIF_ISP_ACQ_NR_FRAMES);
372
373 /* Acquisition Size */
374 writel(0, base + CIF_ISP_ACQ_H_OFFS);
375 writel(0, base + CIF_ISP_ACQ_V_OFFS);
376 writel(acq_mult * in_frm->width, base + CIF_ISP_ACQ_H_SIZE);
377
378 /* ISP Out Area */
379 writel(in_crop->left, base + CIF_ISP_OUT_H_OFFS);
380 writel(in_crop->top, base + CIF_ISP_OUT_V_OFFS);
381 writel(in_crop->width, base + CIF_ISP_OUT_H_SIZE);
382
383 if (dev->stream[RKISP1_STREAM_SP].interlaced) {
384 writel(in_frm->height / 2, base + CIF_ISP_ACQ_V_SIZE);
385 writel(in_crop->height / 2, base + CIF_ISP_OUT_V_SIZE);
386 } else {
387 writel(in_frm->height, base + CIF_ISP_ACQ_V_SIZE);
388 writel(in_crop->height, base + CIF_ISP_OUT_V_SIZE);
389 }
390
391 /* interrupt mask */
392 irq_mask |= CIF_ISP_FRAME | CIF_ISP_V_START | CIF_ISP_PIC_SIZE_ERROR |
393 CIF_ISP_FRAME_IN | CIF_ISP_AWB_DONE | CIF_ISP_AFM_FIN;
394 writel(irq_mask, base + CIF_ISP_IMSC);
395
396 if (out_fmt->fmt_type == FMT_BAYER)
397 rkisp1_params_disable_isp(&dev->params_vdev);
398 else
399 rkisp1_params_configure_isp(&dev->params_vdev, in_fmt,
400 dev->isp_sdev.quantization);
401
402 return 0;
403 }
404
405 static int rkisp1_config_dvp(struct rkisp1_device *dev)
406 {
407 struct ispsd_in_fmt *in_fmt = &dev->isp_sdev.in_fmt;
408 void __iomem *base = dev->base_addr;
409 u32 val, input_sel, data_width;
410
411 switch (in_fmt->bus_width) {
412 case 8:
413 input_sel = CIF_ISP_ACQ_PROP_IN_SEL_8B_ZERO;
414 data_width = ISP_CIF_DATA_WIDTH_8B;
415 break;
416 case 10:
417 input_sel = CIF_ISP_ACQ_PROP_IN_SEL_10B_ZERO;
418 data_width = ISP_CIF_DATA_WIDTH_10B;
419 break;
420 case 12:
421 input_sel = CIF_ISP_ACQ_PROP_IN_SEL_12B;
422 data_width = ISP_CIF_DATA_WIDTH_12B;
423 break;
424 default:
425 v4l2_err(&dev->v4l2_dev, "Invalid bus width\n");
426 return -EINVAL;
427 }
428
429 val = readl(base + CIF_ISP_ACQ_PROP);
430 writel(val | input_sel, base + CIF_ISP_ACQ_PROP);
431
432 if (!IS_ERR(dev->grf) &&
433 (dev->isp_ver == ISP_V12 ||
434 dev->isp_ver == ISP_V13))
435 regmap_update_bits(dev->grf,
436 GRF_VI_CON0,
437 ISP_CIF_DATA_WIDTH_MASK,
438 data_width);
439
440 return 0;
441 }
442
443 static int rkisp1_config_mipi(struct rkisp1_device *dev)
444 {
445 u32 mipi_ctrl;
446 void __iomem *base = dev->base_addr;
447 struct ispsd_in_fmt *in_fmt = &dev->isp_sdev.in_fmt;
448 struct rkisp1_sensor_info *sensor = dev->active_sensor;
449 struct v4l2_subdev *mipi_sensor;
450 struct v4l2_ctrl *ctrl;
451 u32 emd_vc, emd_dt;
452 int lanes, ret, i;
453
454 /*
455 * sensor->mbus is set in isp or d-phy notifier_bound function
456 */
457 switch (sensor->mbus.flags & V4L2_MBUS_CSI2_LANES) {
458 case V4L2_MBUS_CSI2_4_LANE:
459 lanes = 4;
460 break;
461 case V4L2_MBUS_CSI2_3_LANE:
462 lanes = 3;
463 break;
464 case V4L2_MBUS_CSI2_2_LANE:
465 lanes = 2;
466 break;
467 case V4L2_MBUS_CSI2_1_LANE:
468 lanes = 1;
469 break;
470 default:
471 return -EINVAL;
472 }
473
474 emd_vc = 0xFF;
475 emd_dt = 0;
476 dev->hdr_sensor = NULL;
477 get_remote_mipi_sensor(dev, &mipi_sensor);
478 if (mipi_sensor) {
479 ctrl = v4l2_ctrl_find(mipi_sensor->ctrl_handler,
480 CIFISP_CID_EMB_VC);
481 if (ctrl)
482 emd_vc = v4l2_ctrl_g_ctrl(ctrl);
483
484 ctrl = v4l2_ctrl_find(mipi_sensor->ctrl_handler,
485 CIFISP_CID_EMB_DT);
486 if (ctrl)
487 emd_dt = v4l2_ctrl_g_ctrl(ctrl);
488 dev->hdr_sensor = mipi_sensor;
489 }
490
491 dev->emd_dt = emd_dt;
492 dev->emd_vc = emd_vc;
493 dev->emd_data_idx = 0;
494 if (emd_vc <= CIF_ISP_ADD_DATA_VC_MAX) {
495 for (i = 0; i < RKISP1_EMDDATA_FIFO_MAX; i++) {
496 ret = kfifo_alloc(&dev->emd_data_fifo[i].mipi_kfifo,
497 CIFISP_ADD_DATA_FIFO_SIZE,
498 GFP_ATOMIC);
499 if (ret) {
500 v4l2_err(&dev->v4l2_dev,
501 "kfifo_alloc failed with error %d\n",
502 ret);
503 return ret;
504 }
505 }
506 }
507
508 #if RKISP1_RK3326_USE_OLDMIPI
509 if (dev->isp_ver == ISP_V13) {
510 #else
511 if (dev->isp_ver == ISP_V13 ||
512 dev->isp_ver == ISP_V12) {
513 #endif
514 /* lanes */
515 writel(lanes - 1, base + CIF_ISP_CSI0_CTRL1);
516
517 /* linecnt */
518 writel(0x3FFF, base + CIF_ISP_CSI0_CTRL2);
519
520 /* Configure Data Type and Virtual Channel */
521 writel(CIF_MIPI_DATA_SEL_DT(in_fmt->mipi_dt) | CIF_MIPI_DATA_SEL_VC(0),
522 base + CIF_ISP_CSI0_DATA_IDS_1);
523
524 /* clear interrupts state */
525 readl(base + CIF_ISP_CSI0_ERR1);
526 readl(base + CIF_ISP_CSI0_ERR2);
527 readl(base + CIF_ISP_CSI0_ERR3);
528 /* set interrupts mask */
529 writel(0x1FFFFFF0, base + CIF_ISP_CSI0_MASK1);
530 writel(0x03FFFFFF, base + CIF_ISP_CSI0_MASK2);
531 writel(CIF_ISP_CSI0_IMASK_FRAME_END(0x3F) |
532 CIF_ISP_CSI0_IMASK_RAW0_OUT_V_END |
533 CIF_ISP_CSI0_IMASK_RAW1_OUT_V_END |
534 CIF_ISP_CSI0_IMASK_LINECNT,
535 base + CIF_ISP_CSI0_MASK3);
536 } else {
537 mipi_ctrl = CIF_MIPI_CTRL_NUM_LANES(lanes - 1) |
538 CIF_MIPI_CTRL_SHUTDOWNLANES(0xf) |
539 CIF_MIPI_CTRL_ERR_SOT_SYNC_HS_SKIP |
540 CIF_MIPI_CTRL_CLOCKLANE_ENA;
541
542 #if RKISP1_RK3326_USE_OLDMIPI
543 if (dev->isp_ver == ISP_V12) {
544 writel(0, base + CIF_ISP_CSI0_CTRL0);
545 writel(0, base + CIF_ISP_CSI0_MASK1);
546 writel(0, base + CIF_ISP_CSI0_MASK2);
547 writel(0, base + CIF_ISP_CSI0_MASK3);
548 /* clear interrupts state */
549 readl(base + CIF_ISP_CSI0_ERR1);
550 readl(base + CIF_ISP_CSI0_ERR2);
551 readl(base + CIF_ISP_CSI0_ERR3);
552 }
553 #endif
554 writel(mipi_ctrl, base + CIF_MIPI_CTRL);
555
556 /* Configure Data Type and Virtual Channel */
557 writel(CIF_MIPI_DATA_SEL_DT(in_fmt->mipi_dt) | CIF_MIPI_DATA_SEL_VC(0),
558 base + CIF_MIPI_IMG_DATA_SEL);
559
560 writel(CIF_MIPI_DATA_SEL_DT(emd_dt) | CIF_MIPI_DATA_SEL_VC(emd_vc),
561 base + CIF_MIPI_ADD_DATA_SEL_1);
562 writel(CIF_MIPI_DATA_SEL_DT(emd_dt) | CIF_MIPI_DATA_SEL_VC(emd_vc),
563 base + CIF_MIPI_ADD_DATA_SEL_2);
564 writel(CIF_MIPI_DATA_SEL_DT(emd_dt) | CIF_MIPI_DATA_SEL_VC(emd_vc),
565 base + CIF_MIPI_ADD_DATA_SEL_3);
566 writel(CIF_MIPI_DATA_SEL_DT(emd_dt) | CIF_MIPI_DATA_SEL_VC(emd_vc),
567 base + CIF_MIPI_ADD_DATA_SEL_4);
568
569 /* Clear MIPI interrupts */
570 writel(~0, base + CIF_MIPI_ICR);
571 /*
572 * Disable CIF_MIPI_ERR_DPHY interrupt here temporary for
573 * isp bus may be dead when switch isp.
574 */
575 writel(CIF_MIPI_FRAME_END | CIF_MIPI_ERR_CSI | CIF_MIPI_ERR_DPHY |
576 CIF_MIPI_SYNC_FIFO_OVFLW(0x0F) | CIF_MIPI_ADD_DATA_OVFLW,
577 base + CIF_MIPI_IMSC);
578 }
579
580 v4l2_dbg(1, rkisp1_debug, &dev->v4l2_dev, "\n MIPI_CTRL 0x%08x\n"
581 " MIPI_IMG_DATA_SEL 0x%08x\n"
582 " MIPI_STATUS 0x%08x\n"
583 " MIPI_IMSC 0x%08x\n",
584 readl(base + CIF_MIPI_CTRL),
585 readl(base + CIF_MIPI_IMG_DATA_SEL),
586 readl(base + CIF_MIPI_STATUS),
587 readl(base + CIF_MIPI_IMSC));
588
589 return 0;
590 }
591
592 /* Configure MUX */
593 static int rkisp1_config_path(struct rkisp1_device *dev)
594 {
595 int ret = 0;
596 struct rkisp1_sensor_info *sensor = dev->active_sensor;
597 u32 dpcl = readl(dev->base_addr + CIF_VI_DPCL);
598
599 if (sensor && (sensor->mbus.type == V4L2_MBUS_BT656 ||
600 sensor->mbus.type == V4L2_MBUS_PARALLEL)) {
601 ret = rkisp1_config_dvp(dev);
602 dpcl |= CIF_VI_DPCL_IF_SEL_PARALLEL;
603 dev->isp_inp = INP_DVP;
604 } else if (sensor && sensor->mbus.type == V4L2_MBUS_CSI2_DPHY) {
605 ret = rkisp1_config_mipi(dev);
606 dpcl |= CIF_VI_DPCL_IF_SEL_MIPI;
607 dev->isp_inp = INP_CSI;
608 } else if (dev->isp_inp == INP_DMARX_ISP) {
609 dpcl |= CIF_VI_DPCL_DMA_SW_ISP;
610 }
611
612 writel(dpcl, dev->base_addr + CIF_VI_DPCL);
613
614 return ret;
615 }
616
617 /* Hareware configure Entry */
618 static int rkisp1_config_cif(struct rkisp1_device *dev)
619 {
620 int ret = 0;
621 u32 cif_id;
622
623 v4l2_dbg(1, rkisp1_debug, &dev->v4l2_dev,
624 "SP streaming = %d, MP streaming = %d\n",
625 dev->stream[RKISP1_STREAM_SP].streaming,
626 dev->stream[RKISP1_STREAM_MP].streaming);
627
628 cif_id = readl(dev->base_addr + CIF_VI_ID);
629 v4l2_dbg(1, rkisp1_debug, &dev->v4l2_dev, "CIF_ID 0x%08x\n", cif_id);
630
631 ret = rkisp1_config_isp(dev);
632 if (ret < 0)
633 return ret;
634 ret = rkisp1_config_path(dev);
635 if (ret < 0)
636 return ret;
637 rkisp1_config_ism(dev);
638
639 return 0;
640 }
641
642 static bool rkisp1_is_need_3a(struct rkisp1_device *dev)
643 {
644 struct rkisp1_isp_subdev *isp_sdev = &dev->isp_sdev;
645
646 return isp_sdev->in_fmt.fmt_type == FMT_BAYER &&
647 isp_sdev->out_fmt.fmt_type == FMT_YUV;
648 }
649
650 static void rkisp1_start_3a_run(struct rkisp1_device *dev)
651 {
652 struct rkisp1_isp_params_vdev *params_vdev = &dev->params_vdev;
653 struct video_device *vdev = ¶ms_vdev->vnode.vdev;
654 struct v4l2_event ev = {
655 .type = CIFISP_V4L2_EVENT_STREAM_START,
656 };
657 int ret;
658
659 if (!rkisp1_is_need_3a(dev))
660 return;
661
662 v4l2_event_queue(vdev, &ev);
663 /* rk3326/px30 require first params queued before
664 * rkisp1_params_configure_isp() called
665 */
666 ret = wait_event_timeout(dev->sync_onoff,
667 params_vdev->streamon && !params_vdev->first_params,
668 msecs_to_jiffies(1000));
669 if (!ret)
670 v4l2_warn(&dev->v4l2_dev,
671 "waiting on params stream on event timeout\n");
672 else
673 v4l2_dbg(1, rkisp1_debug, &dev->v4l2_dev,
674 "Waiting for 3A on use %d ms\n", 1000 - ret);
675 }
676
677 static void rkisp1_stop_3a_run(struct rkisp1_device *dev)
678 {
679 struct rkisp1_isp_params_vdev *params_vdev = &dev->params_vdev;
680 struct video_device *vdev = ¶ms_vdev->vnode.vdev;
681 struct v4l2_event ev = {
682 .type = CIFISP_V4L2_EVENT_STREAM_STOP,
683 };
684 int ret;
685
686 if (!rkisp1_is_need_3a(dev))
687 return;
688
689 v4l2_event_queue(vdev, &ev);
690 ret = wait_event_timeout(dev->sync_onoff, !params_vdev->streamon,
691 msecs_to_jiffies(1000));
692 if (!ret)
693 v4l2_warn(&dev->v4l2_dev,
694 "waiting on params stream off event timeout\n");
695 else
696 v4l2_dbg(1, rkisp1_debug, &dev->v4l2_dev,
697 "Waiting for 3A off use %d ms\n", 1000 - ret);
698 }
699
700 /* Mess register operations to stop isp */
701 static int rkisp1_isp_stop(struct rkisp1_device *dev)
702 {
703 void __iomem *base = dev->base_addr;
704 unsigned long old_rate, safe_rate;
705 u32 val;
706 u32 i;
707
708 v4l2_dbg(1, rkisp1_debug, &dev->v4l2_dev,
709 "SP streaming = %d, MP streaming = %d\n",
710 dev->stream[RKISP1_STREAM_SP].streaming,
711 dev->stream[RKISP1_STREAM_MP].streaming);
712
713 /*
714 * ISP(mi) stop in mi frame end -> Stop ISP(mipi) ->
715 * Stop ISP(isp) ->wait for ISP isp off
716 */
717 /* stop and clear MI, MIPI, and ISP interrupts */
718 #if RKISP1_RK3326_USE_OLDMIPI
719 if (dev->isp_ver == ISP_V13) {
720 #else
721 if (dev->isp_ver == ISP_V12 || dev->isp_ver == ISP_V13) {
722 #endif
723 writel(0, base + CIF_ISP_CSI0_MASK1);
724 writel(0, base + CIF_ISP_CSI0_MASK2);
725 writel(0, base + CIF_ISP_CSI0_MASK3);
726 readl(base + CIF_ISP_CSI0_ERR1);
727 readl(base + CIF_ISP_CSI0_ERR2);
728 readl(base + CIF_ISP_CSI0_ERR3);
729 } else {
730 writel(0, base + CIF_MIPI_IMSC);
731 writel(~0, base + CIF_MIPI_ICR);
732 }
733
734 writel(0, base + CIF_ISP_IMSC);
735 writel(~0, base + CIF_ISP_ICR);
736
737 writel(0, base + CIF_MI_IMSC);
738 writel(~0, base + CIF_MI_ICR);
739 #if RKISP1_RK3326_USE_OLDMIPI
740 if (dev->isp_ver == ISP_V13) {
741 #else
742 if (dev->isp_ver == ISP_V12 || dev->isp_ver == ISP_V13) {
743 #endif
744 writel(0, base + CIF_ISP_CSI0_CTRL0);
745 } else {
746 val = readl(base + CIF_MIPI_CTRL);
747 val = val & (~CIF_MIPI_CTRL_SHUTDOWNLANES(0xf));
748 writel(val & (~CIF_MIPI_CTRL_OUTPUT_ENA), base + CIF_MIPI_CTRL);
749 udelay(20);
750 }
751 /* stop ISP */
752 val = readl(base + CIF_ISP_CTRL);
753 val &= ~(CIF_ISP_CTRL_ISP_INFORM_ENABLE | CIF_ISP_CTRL_ISP_ENABLE);
754 writel(val, base + CIF_ISP_CTRL);
755
756 val = readl(base + CIF_ISP_CTRL);
757 writel(val | CIF_ISP_CTRL_ISP_CFG_UPD, base + CIF_ISP_CTRL);
758
759 readx_poll_timeout_atomic(readl, base + CIF_ISP_RIS,
760 val, val & CIF_ISP_OFF, 20, 100);
761 v4l2_dbg(1, rkisp1_debug, &dev->v4l2_dev,
762 "streaming(MP:%d, SP:%d), MI_CTRL:%x, ISP_CTRL:%x, MIPI_CTRL:%x\n",
763 dev->stream[RKISP1_STREAM_SP].streaming,
764 dev->stream[RKISP1_STREAM_MP].streaming,
765 readl(base + CIF_MI_CTRL),
766 readl(base + CIF_ISP_CTRL),
767 readl(base + CIF_MIPI_CTRL));
768
769 if (!in_interrupt()) {
770 /* normal case */
771 /* check the isp_clk before isp reset operation */
772 old_rate = clk_get_rate(dev->clks[0]);
773 safe_rate = dev->clk_rate_tbl[0] * 1000000UL;
774 if (old_rate > safe_rate) {
775 clk_set_rate(dev->clks[0], safe_rate);
776 udelay(100);
777 }
778 writel(CIF_IRCL_CIF_SW_RST, base + CIF_IRCL);
779 /* restore the old ispclk after reset */
780 if (old_rate != safe_rate)
781 clk_set_rate(dev->clks[0], old_rate);
782 } else {
783 /* abnormal case, in irq function */
784 writel(CIF_IRCL_CIF_SW_RST, base + CIF_IRCL);
785 }
786 if (dev->isp_ver == ISP_V12 || dev->isp_ver == ISP_V13) {
787 writel(0, base + CIF_ISP_CSI0_CSI2_RESETN);
788 writel(0, base + CIF_ISP_CSI0_CTRL0);
789 writel(0, base + CIF_ISP_CSI0_MASK1);
790 writel(0, base + CIF_ISP_CSI0_MASK2);
791 writel(0, base + CIF_ISP_CSI0_MASK3);
792 }
793
794 rkisp1_config_clk(dev, true);
795 if (!in_interrupt()) {
796 struct iommu_domain *domain;
797
798 domain = iommu_get_domain_for_dev(dev->dev);
799 if (domain) {
800 domain->ops->detach_dev(domain, dev->dev);
801 domain->ops->attach_dev(domain, dev->dev);
802 }
803 }
804 dev->isp_state = ISP_STOP;
805
806 if (dev->emd_vc <= CIF_ISP_ADD_DATA_VC_MAX) {
807 for (i = 0; i < RKISP1_EMDDATA_FIFO_MAX; i++)
808 kfifo_free(&dev->emd_data_fifo[i].mipi_kfifo);
809 dev->emd_vc = 0xFF;
810 }
811
812 if (dev->hdr_sensor)
813 dev->hdr_sensor = NULL;
814
815 return 0;
816 }
817
818 /* Mess register operations to start isp */
819 static int rkisp1_isp_start(struct rkisp1_device *dev)
820 {
821 struct rkisp1_sensor_info *sensor = dev->active_sensor;
822 void __iomem *base = dev->base_addr;
823 u32 val;
824
825 v4l2_dbg(1, rkisp1_debug, &dev->v4l2_dev,
826 "SP streaming = %d, MP streaming = %d\n",
827 dev->stream[RKISP1_STREAM_SP].streaming,
828 dev->stream[RKISP1_STREAM_MP].streaming);
829
830 /* Activate MIPI */
831 if (sensor && sensor->mbus.type == V4L2_MBUS_CSI2_DPHY) {
832 #if RKISP1_RK3326_USE_OLDMIPI
833 if (dev->isp_ver == ISP_V13) {
834 #else
835 if (dev->isp_ver == ISP_V12 || dev->isp_ver == ISP_V13) {
836 #endif
837 /* clear interrupts state */
838 readl(base + CIF_ISP_CSI0_ERR1);
839 readl(base + CIF_ISP_CSI0_ERR2);
840 readl(base + CIF_ISP_CSI0_ERR3);
841 /* csi2host enable */
842 writel(1, base + CIF_ISP_CSI0_CTRL0);
843 } else {
844 val = readl(base + CIF_MIPI_CTRL);
845 writel(val | CIF_MIPI_CTRL_OUTPUT_ENA,
846 base + CIF_MIPI_CTRL);
847 }
848 }
849 /* Activate ISP */
850 val = readl(base + CIF_ISP_CTRL);
851 val |= CIF_ISP_CTRL_ISP_CFG_UPD | CIF_ISP_CTRL_ISP_ENABLE |
852 CIF_ISP_CTRL_ISP_INFORM_ENABLE | CIF_ISP_CTRL_ISP_CFG_UPD_PERMANENT;
853 writel(val, base + CIF_ISP_CTRL);
854
855 dev->isp_err_cnt = 0;
856 dev->isp_state = ISP_START;
857
858 /* XXX: Is the 1000us too long?
859 * CIF spec says to wait for sufficient time after enabling
860 * the MIPI interface and before starting the sensor output.
861 */
862 usleep_range(1000, 1200);
863
864 v4l2_dbg(1, rkisp1_debug, &dev->v4l2_dev,
865 "SP streaming = %d, MP streaming = %d MI_CTRL 0x%08x\n"
866 " ISP_CTRL 0x%08x MIPI_CTRL 0x%08x\n",
867 dev->stream[RKISP1_STREAM_SP].streaming,
868 dev->stream[RKISP1_STREAM_MP].streaming,
869 readl(base + CIF_MI_CTRL),
870 readl(base + CIF_ISP_CTRL),
871 readl(base + CIF_MIPI_CTRL));
872
873 return 0;
874 }
875
876 /***************************** isp sub-devs *******************************/
877
878 static const struct ispsd_in_fmt rkisp1_isp_input_formats[] = {
879 {
880 .mbus_code = MEDIA_BUS_FMT_SBGGR10_1X10,
881 .fmt_type = FMT_BAYER,
882 .mipi_dt = CIF_CSI2_DT_RAW10,
883 .bayer_pat = RAW_BGGR,
884 .bus_width = 10,
885 }, {
886 .mbus_code = MEDIA_BUS_FMT_SRGGB10_1X10,
887 .fmt_type = FMT_BAYER,
888 .mipi_dt = CIF_CSI2_DT_RAW10,
889 .bayer_pat = RAW_RGGB,
890 .bus_width = 10,
891 }, {
892 .mbus_code = MEDIA_BUS_FMT_SGBRG10_1X10,
893 .fmt_type = FMT_BAYER,
894 .mipi_dt = CIF_CSI2_DT_RAW10,
895 .bayer_pat = RAW_GBRG,
896 .bus_width = 10,
897 }, {
898 .mbus_code = MEDIA_BUS_FMT_SGRBG10_1X10,
899 .fmt_type = FMT_BAYER,
900 .mipi_dt = CIF_CSI2_DT_RAW10,
901 .bayer_pat = RAW_GRBG,
902 .bus_width = 10,
903 }, {
904 .mbus_code = MEDIA_BUS_FMT_SRGGB12_1X12,
905 .fmt_type = FMT_BAYER,
906 .mipi_dt = CIF_CSI2_DT_RAW12,
907 .bayer_pat = RAW_RGGB,
908 .bus_width = 12,
909 }, {
910 .mbus_code = MEDIA_BUS_FMT_SBGGR12_1X12,
911 .fmt_type = FMT_BAYER,
912 .mipi_dt = CIF_CSI2_DT_RAW12,
913 .bayer_pat = RAW_BGGR,
914 .bus_width = 12,
915 }, {
916 .mbus_code = MEDIA_BUS_FMT_SGBRG12_1X12,
917 .fmt_type = FMT_BAYER,
918 .mipi_dt = CIF_CSI2_DT_RAW12,
919 .bayer_pat = RAW_GBRG,
920 .bus_width = 12,
921 }, {
922 .mbus_code = MEDIA_BUS_FMT_SGRBG12_1X12,
923 .fmt_type = FMT_BAYER,
924 .mipi_dt = CIF_CSI2_DT_RAW12,
925 .bayer_pat = RAW_GRBG,
926 .bus_width = 12,
927 }, {
928 .mbus_code = MEDIA_BUS_FMT_SRGGB8_1X8,
929 .fmt_type = FMT_BAYER,
930 .mipi_dt = CIF_CSI2_DT_RAW8,
931 .bayer_pat = RAW_RGGB,
932 .bus_width = 8,
933 }, {
934 .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8,
935 .fmt_type = FMT_BAYER,
936 .mipi_dt = CIF_CSI2_DT_RAW8,
937 .bayer_pat = RAW_BGGR,
938 .bus_width = 8,
939 }, {
940 .mbus_code = MEDIA_BUS_FMT_SGBRG8_1X8,
941 .fmt_type = FMT_BAYER,
942 .mipi_dt = CIF_CSI2_DT_RAW8,
943 .bayer_pat = RAW_GBRG,
944 .bus_width = 8,
945 }, {
946 .mbus_code = MEDIA_BUS_FMT_SGRBG8_1X8,
947 .fmt_type = FMT_BAYER,
948 .mipi_dt = CIF_CSI2_DT_RAW8,
949 .bayer_pat = RAW_GRBG,
950 .bus_width = 8,
951 }, {
952 .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8,
953 .fmt_type = FMT_YUV,
954 .mipi_dt = CIF_CSI2_DT_YUV422_8b,
955 .yuv_seq = CIF_ISP_ACQ_PROP_YCBYCR,
956 .bus_width = 8,
957 }, {
958 .mbus_code = MEDIA_BUS_FMT_YVYU8_2X8,
959 .fmt_type = FMT_YUV,
960 .mipi_dt = CIF_CSI2_DT_YUV422_8b,
961 .yuv_seq = CIF_ISP_ACQ_PROP_YCRYCB,
962 .bus_width = 8,
963 }, {
964 .mbus_code = MEDIA_BUS_FMT_UYVY8_2X8,
965 .fmt_type = FMT_YUV,
966 .mipi_dt = CIF_CSI2_DT_YUV422_8b,
967 .yuv_seq = CIF_ISP_ACQ_PROP_CBYCRY,
968 .bus_width = 8,
969 }, {
970 .mbus_code = MEDIA_BUS_FMT_VYUY8_2X8,
971 .fmt_type = FMT_YUV,
972 .mipi_dt = CIF_CSI2_DT_YUV422_8b,
973 .yuv_seq = CIF_ISP_ACQ_PROP_CRYCBY,
974 .bus_width = 8,
975 }, {
976 .mbus_code = MEDIA_BUS_FMT_YUYV10_2X10,
977 .fmt_type = FMT_YUV,
978 .mipi_dt = CIF_CSI2_DT_YUV422_8b,
979 .yuv_seq = CIF_ISP_ACQ_PROP_YCBYCR,
980 .bus_width = 10,
981 }, {
982 .mbus_code = MEDIA_BUS_FMT_YVYU10_2X10,
983 .fmt_type = FMT_YUV,
984 .mipi_dt = CIF_CSI2_DT_YUV422_8b,
985 .yuv_seq = CIF_ISP_ACQ_PROP_YCRYCB,
986 .bus_width = 10,
987 }, {
988 .mbus_code = MEDIA_BUS_FMT_UYVY10_2X10,
989 .fmt_type = FMT_YUV,
990 .mipi_dt = CIF_CSI2_DT_YUV422_8b,
991 .yuv_seq = CIF_ISP_ACQ_PROP_CBYCRY,
992 .bus_width = 10,
993 }, {
994 .mbus_code = MEDIA_BUS_FMT_VYUY10_2X10,
995 .fmt_type = FMT_YUV,
996 .mipi_dt = CIF_CSI2_DT_YUV422_8b,
997 .yuv_seq = CIF_ISP_ACQ_PROP_CRYCBY,
998 .bus_width = 10,
999 }, {
1000 .mbus_code = MEDIA_BUS_FMT_YUYV12_2X12,
1001 .fmt_type = FMT_YUV,
1002 .mipi_dt = CIF_CSI2_DT_YUV422_8b,
1003 .yuv_seq = CIF_ISP_ACQ_PROP_YCBYCR,
1004 .bus_width = 12,
1005 }, {
1006 .mbus_code = MEDIA_BUS_FMT_YVYU12_2X12,
1007 .fmt_type = FMT_YUV,
1008 .mipi_dt = CIF_CSI2_DT_YUV422_8b,
1009 .yuv_seq = CIF_ISP_ACQ_PROP_YCRYCB,
1010 .bus_width = 12,
1011 }, {
1012 .mbus_code = MEDIA_BUS_FMT_UYVY12_2X12,
1013 .fmt_type = FMT_YUV,
1014 .mipi_dt = CIF_CSI2_DT_YUV422_8b,
1015 .yuv_seq = CIF_ISP_ACQ_PROP_CBYCRY,
1016 .bus_width = 12,
1017 }, {
1018 .mbus_code = MEDIA_BUS_FMT_VYUY12_2X12,
1019 .fmt_type = FMT_YUV,
1020 .mipi_dt = CIF_CSI2_DT_YUV422_8b,
1021 .yuv_seq = CIF_ISP_ACQ_PROP_CRYCBY,
1022 .bus_width = 12,
1023 }, {
1024 .mbus_code = MEDIA_BUS_FMT_Y8_1X8,
1025 .fmt_type = FMT_BAYER,
1026 .mipi_dt = CIF_CSI2_DT_RAW8,
1027 .yuv_seq = CIF_ISP_ACQ_PROP_YCBYCR,
1028 .bus_width = 8,
1029 }, {
1030 .mbus_code = MEDIA_BUS_FMT_Y10_1X10,
1031 .fmt_type = FMT_BAYER,
1032 .mipi_dt = CIF_CSI2_DT_RAW10,
1033 .yuv_seq = CIF_ISP_ACQ_PROP_YCBYCR,
1034 .bus_width = 10,
1035 }, {
1036 .mbus_code = MEDIA_BUS_FMT_Y12_1X12,
1037 .fmt_type = FMT_BAYER,
1038 .mipi_dt = CIF_CSI2_DT_RAW12,
1039 .yuv_seq = CIF_ISP_ACQ_PROP_YCBYCR,
1040 .bus_width = 12,
1041 }
1042 };
1043
1044 static const struct ispsd_out_fmt rkisp1_isp_output_formats[] = {
1045 {
1046 .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8,
1047 .fmt_type = FMT_YUV,
1048 }, {
1049 .mbus_code = MEDIA_BUS_FMT_SRGGB12_1X12,
1050 .fmt_type = FMT_BAYER,
1051 }, {
1052 .mbus_code = MEDIA_BUS_FMT_SBGGR12_1X12,
1053 .fmt_type = FMT_BAYER,
1054 }, {
1055 .mbus_code = MEDIA_BUS_FMT_SGBRG12_1X12,
1056 .fmt_type = FMT_BAYER,
1057 }, {
1058 .mbus_code = MEDIA_BUS_FMT_SGRBG12_1X12,
1059 .fmt_type = FMT_BAYER,
1060 }, {
1061 .mbus_code = MEDIA_BUS_FMT_SRGGB10_1X10,
1062 .fmt_type = FMT_BAYER,
1063 }, {
1064 .mbus_code = MEDIA_BUS_FMT_SBGGR10_1X10,
1065 .fmt_type = FMT_BAYER,
1066 }, {
1067 .mbus_code = MEDIA_BUS_FMT_SGBRG10_1X10,
1068 .fmt_type = FMT_BAYER,
1069 }, {
1070 .mbus_code = MEDIA_BUS_FMT_SGRBG10_1X10,
1071 .fmt_type = FMT_BAYER,
1072 }, {
1073 .mbus_code = MEDIA_BUS_FMT_SRGGB8_1X8,
1074 .fmt_type = FMT_BAYER,
1075 }, {
1076 .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8,
1077 .fmt_type = FMT_BAYER,
1078 }, {
1079 .mbus_code = MEDIA_BUS_FMT_SGBRG8_1X8,
1080 .fmt_type = FMT_BAYER,
1081 }, {
1082 .mbus_code = MEDIA_BUS_FMT_SGRBG8_1X8,
1083 .fmt_type = FMT_BAYER,
1084 },
1085 };
1086
1087 static const struct ispsd_in_fmt *find_in_fmt(u32 mbus_code)
1088 {
1089 const struct ispsd_in_fmt *fmt;
1090 int i, array_size = ARRAY_SIZE(rkisp1_isp_input_formats);
1091
1092 for (i = 0; i < array_size; i++) {
1093 fmt = &rkisp1_isp_input_formats[i];
1094 if (fmt->mbus_code == mbus_code)
1095 return fmt;
1096 }
1097
1098 return NULL;
1099 }
1100
1101 static const struct ispsd_out_fmt *find_out_fmt(u32 mbus_code)
1102 {
1103 const struct ispsd_out_fmt *fmt;
1104 int i, array_size = ARRAY_SIZE(rkisp1_isp_output_formats);
1105
1106 for (i = 0; i < array_size; i++) {
1107 fmt = &rkisp1_isp_output_formats[i];
1108 if (fmt->mbus_code == mbus_code)
1109 return fmt;
1110 }
1111
1112 return NULL;
1113 }
1114
1115 static int rkisp1_isp_sd_enum_mbus_code(struct v4l2_subdev *sd,
1116 struct v4l2_subdev_pad_config *cfg,
1117 struct v4l2_subdev_mbus_code_enum *code)
1118 {
1119 int i = code->index;
1120
1121 if (code->pad == RKISP1_ISP_PAD_SINK) {
1122 if (i >= ARRAY_SIZE(rkisp1_isp_input_formats))
1123 return -EINVAL;
1124 code->code = rkisp1_isp_input_formats[i].mbus_code;
1125 } else {
1126 if (i >= ARRAY_SIZE(rkisp1_isp_output_formats))
1127 return -EINVAL;
1128 code->code = rkisp1_isp_output_formats[i].mbus_code;
1129 }
1130
1131 return 0;
1132 }
1133
1134 #define sd_to_isp_sd(_sd) container_of(_sd, struct rkisp1_isp_subdev, sd)
1135 static int rkisp1_isp_sd_get_fmt(struct v4l2_subdev *sd,
1136 struct v4l2_subdev_pad_config *cfg,
1137 struct v4l2_subdev_format *fmt)
1138 {
1139 struct rkisp1_isp_subdev *isp_sd = sd_to_isp_sd(sd);
1140 struct v4l2_mbus_framefmt *mf;
1141
1142 if (!fmt)
1143 goto err;
1144
1145 if (fmt->pad != RKISP1_ISP_PAD_SINK &&
1146 fmt->pad != RKISP1_ISP_PAD_SOURCE_PATH)
1147 goto err;
1148
1149 mf = &fmt->format;
1150 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1151 if (!cfg)
1152 goto err;
1153 mf = v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
1154 }
1155
1156 if (fmt->pad == RKISP1_ISP_PAD_SINK) {
1157 *mf = isp_sd->in_frm;
1158 } else if (fmt->pad == RKISP1_ISP_PAD_SOURCE_PATH) {
1159 /* format of source pad */
1160 mf->code = isp_sd->out_fmt.mbus_code;
1161 /* window size of source pad */
1162 mf->width = isp_sd->out_crop.width;
1163 mf->height = isp_sd->out_crop.height;
1164 mf->quantization = isp_sd->quantization;
1165 }
1166 mf->field = V4L2_FIELD_NONE;
1167
1168 return 0;
1169 err:
1170 return -EINVAL;
1171 }
1172
1173 static void rkisp1_isp_sd_try_fmt(struct v4l2_subdev *sd,
1174 unsigned int pad,
1175 struct v4l2_mbus_framefmt *fmt)
1176 {
1177 struct rkisp1_device *isp_dev = sd_to_isp_dev(sd);
1178 struct rkisp1_isp_subdev *isp_sd = &isp_dev->isp_sdev;
1179 const struct ispsd_in_fmt *in_fmt;
1180 const struct ispsd_out_fmt *out_fmt;
1181
1182 switch (pad) {
1183 case RKISP1_ISP_PAD_SINK:
1184 in_fmt = find_in_fmt(fmt->code);
1185 if (in_fmt)
1186 fmt->code = in_fmt->mbus_code;
1187 else
1188 fmt->code = MEDIA_BUS_FMT_SRGGB10_1X10;
1189
1190 if (isp_dev->isp_ver == ISP_V12) {
1191 fmt->width = clamp_t(u32, fmt->width,
1192 CIF_ISP_INPUT_W_MIN,
1193 CIF_ISP_INPUT_W_MAX_V12);
1194 fmt->height = clamp_t(u32, fmt->height,
1195 CIF_ISP_INPUT_H_MIN,
1196 CIF_ISP_INPUT_H_MAX_V12);
1197 } else if (isp_dev->isp_ver == ISP_V13) {
1198 fmt->width = clamp_t(u32, fmt->width,
1199 CIF_ISP_INPUT_W_MIN,
1200 CIF_ISP_INPUT_W_MAX_V13);
1201 fmt->height = clamp_t(u32, fmt->height,
1202 CIF_ISP_INPUT_H_MIN,
1203 CIF_ISP_INPUT_H_MAX_V13);
1204 } else {
1205 fmt->width = clamp_t(u32, fmt->width,
1206 CIF_ISP_INPUT_W_MIN,
1207 CIF_ISP_INPUT_W_MAX);
1208 fmt->height = clamp_t(u32, fmt->height,
1209 CIF_ISP_INPUT_H_MIN,
1210 CIF_ISP_INPUT_H_MAX);
1211 }
1212 break;
1213 case RKISP1_ISP_PAD_SOURCE_PATH:
1214 out_fmt = find_out_fmt(fmt->code);
1215 if (out_fmt)
1216 fmt->code = out_fmt->mbus_code;
1217 else
1218 fmt->code = MEDIA_BUS_FMT_YUYV8_2X8;
1219 /* window size is set in s_selection */
1220 fmt->width = isp_sd->out_crop.width;
1221 fmt->height = isp_sd->out_crop.height;
1222 /* full range by default */
1223 if (!fmt->quantization)
1224 fmt->quantization = V4L2_QUANTIZATION_FULL_RANGE;
1225 break;
1226 }
1227
1228 fmt->field = V4L2_FIELD_NONE;
1229 }
1230
1231 static int rkisp1_isp_sd_set_fmt(struct v4l2_subdev *sd,
1232 struct v4l2_subdev_pad_config *cfg,
1233 struct v4l2_subdev_format *fmt)
1234 {
1235 struct rkisp1_device *isp_dev = sd_to_isp_dev(sd);
1236 struct rkisp1_isp_subdev *isp_sd = &isp_dev->isp_sdev;
1237 struct v4l2_mbus_framefmt *mf;
1238
1239 if (!fmt)
1240 goto err;
1241
1242 if (fmt->pad != RKISP1_ISP_PAD_SINK &&
1243 fmt->pad != RKISP1_ISP_PAD_SOURCE_PATH)
1244 goto err;
1245
1246 mf = &fmt->format;
1247 rkisp1_isp_sd_try_fmt(sd, fmt->pad, mf);
1248
1249 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1250 if (!cfg)
1251 goto err;
1252 mf = v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
1253 }
1254
1255 if (fmt->pad == RKISP1_ISP_PAD_SINK) {
1256 const struct ispsd_in_fmt *in_fmt;
1257
1258 in_fmt = find_in_fmt(mf->code);
1259 if (!in_fmt)
1260 goto err;
1261 isp_sd->in_fmt = *in_fmt;
1262 isp_sd->in_frm = *mf;
1263 } else if (fmt->pad == RKISP1_ISP_PAD_SOURCE_PATH) {
1264 const struct ispsd_out_fmt *out_fmt;
1265
1266 /* Ignore width/height */
1267 out_fmt = find_out_fmt(mf->code);
1268 if (!out_fmt)
1269 goto err;
1270 isp_sd->out_fmt = *out_fmt;
1271 /*
1272 * It is quantization for output,
1273 * isp use bt601 limit-range in internal
1274 */
1275 isp_sd->quantization = mf->quantization;
1276 }
1277
1278 return 0;
1279 err:
1280 return -EINVAL;
1281 }
1282
1283 static void rkisp1_isp_sd_try_crop(struct v4l2_subdev *sd,
1284 struct v4l2_subdev_pad_config *cfg,
1285 struct v4l2_subdev_selection *sel)
1286 {
1287 struct rkisp1_isp_subdev *isp_sd = sd_to_isp_sd(sd);
1288 struct v4l2_mbus_framefmt in_frm = isp_sd->in_frm;
1289 struct v4l2_rect in_crop = isp_sd->in_crop;
1290 struct v4l2_rect *input = &sel->r;
1291
1292 if (sel->which == V4L2_SUBDEV_FORMAT_TRY) {
1293 in_frm = *v4l2_subdev_get_try_format(sd, cfg, RKISP1_ISP_PAD_SINK);
1294 in_crop = *v4l2_subdev_get_try_crop(sd, cfg, RKISP1_ISP_PAD_SINK);
1295 }
1296
1297 input->left = ALIGN(input->left, 2);
1298 input->width = ALIGN(input->width, 2);
1299
1300 if (sel->pad == RKISP1_ISP_PAD_SINK) {
1301 input->left = clamp_t(u32, input->left, 0, in_frm.width);
1302 input->top = clamp_t(u32, input->top, 0, in_frm.height);
1303 input->width = clamp_t(u32, input->width, CIF_ISP_INPUT_W_MIN,
1304 in_frm.width - input->left);
1305 input->height = clamp_t(u32, input->height,
1306 CIF_ISP_INPUT_H_MIN,
1307 in_frm.height - input->top);
1308 } else if (sel->pad == RKISP1_ISP_PAD_SOURCE_PATH) {
1309 input->left = clamp_t(u32, input->left, 0, in_crop.width);
1310 input->top = clamp_t(u32, input->top, 0, in_crop.height);
1311 input->width = clamp_t(u32, input->width, CIF_ISP_OUTPUT_W_MIN,
1312 in_crop.width - input->left);
1313 input->height = clamp_t(u32, input->height, CIF_ISP_OUTPUT_H_MIN,
1314 in_crop.height - input->top);
1315 }
1316 }
1317
1318 static int rkisp1_isp_sd_get_selection(struct v4l2_subdev *sd,
1319 struct v4l2_subdev_pad_config *cfg,
1320 struct v4l2_subdev_selection *sel)
1321 {
1322 struct rkisp1_isp_subdev *isp_sd = sd_to_isp_sd(sd);
1323 struct v4l2_rect *crop;
1324
1325 if (!sel)
1326 goto err;
1327
1328 if (sel->pad != RKISP1_ISP_PAD_SOURCE_PATH &&
1329 sel->pad != RKISP1_ISP_PAD_SINK)
1330 goto err;
1331
1332 crop = &sel->r;
1333 if (sel->which == V4L2_SUBDEV_FORMAT_TRY) {
1334 if (!cfg)
1335 goto err;
1336 crop = v4l2_subdev_get_try_crop(sd, cfg, sel->pad);
1337 }
1338
1339 switch (sel->target) {
1340 case V4L2_SEL_TGT_CROP_BOUNDS:
1341 if (sel->pad == RKISP1_ISP_PAD_SINK) {
1342 crop->height = isp_sd->in_frm.height;
1343 crop->width = isp_sd->in_frm.width;
1344 crop->left = 0;
1345 crop->top = 0;
1346 } else {
1347 *crop = isp_sd->in_crop;
1348 }
1349 break;
1350 case V4L2_SEL_TGT_CROP:
1351 if (sel->pad == RKISP1_ISP_PAD_SINK)
1352 *crop = isp_sd->in_crop;
1353 else
1354 *crop = isp_sd->out_crop;
1355 break;
1356 default:
1357 goto err;
1358 }
1359
1360 return 0;
1361 err:
1362 return -EINVAL;
1363 }
1364
1365 static int rkisp1_isp_sd_set_selection(struct v4l2_subdev *sd,
1366 struct v4l2_subdev_pad_config *cfg,
1367 struct v4l2_subdev_selection *sel)
1368 {
1369 struct rkisp1_isp_subdev *isp_sd = sd_to_isp_sd(sd);
1370 struct rkisp1_device *dev = sd_to_isp_dev(sd);
1371 struct v4l2_rect *crop;
1372
1373 if (!sel)
1374 goto err;
1375
1376 if (sel->pad != RKISP1_ISP_PAD_SOURCE_PATH &&
1377 sel->pad != RKISP1_ISP_PAD_SINK)
1378 goto err;
1379 if (sel->target != V4L2_SEL_TGT_CROP)
1380 goto err;
1381
1382 v4l2_dbg(1, rkisp1_debug, &dev->v4l2_dev,
1383 "%s: pad: %d sel(%d,%d)/%dx%d\n", __func__, sel->pad,
1384 sel->r.left, sel->r.top, sel->r.width, sel->r.height);
1385 rkisp1_isp_sd_try_crop(sd, cfg, sel);
1386
1387 crop = &sel->r;
1388 if (sel->which == V4L2_SUBDEV_FORMAT_TRY) {
1389 if (!cfg)
1390 goto err;
1391 crop = v4l2_subdev_get_try_crop(sd, cfg, sel->pad);
1392 }
1393
1394 if (sel->pad == RKISP1_ISP_PAD_SINK)
1395 isp_sd->in_crop = *crop;
1396 else
1397 isp_sd->out_crop = *crop;
1398
1399 return 0;
1400 err:
1401 goto err;
1402 }
1403
1404 static void rkisp1_isp_read_add_fifo_data(struct rkisp1_device *dev)
1405 {
1406 struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
1407 void __iomem *base = dev->base_addr;
1408 u32 mipi_status = 0;
1409 u32 data_len = 0;
1410 u32 fifo_data = 0;
1411 u32 i, idx, cur_frame_id;
1412
1413 cur_frame_id = atomic_read(&dev->isp_sdev.frm_sync_seq) - 1;
1414 idx = dev->emd_data_idx;
1415 dev->emd_data_fifo[idx].frame_id = 0;
1416 kfifo_reset_out(&dev->emd_data_fifo[idx].mipi_kfifo);
1417 for (i = 0; i < CIFISP_ADD_DATA_FIFO_SIZE / 4; i++) {
1418 mipi_status = readl(base + CIF_MIPI_STATUS);
1419 if (!(mipi_status & 0x01))
1420 break;
1421
1422 fifo_data = readl(base + CIF_MIPI_ADD_DATA_FIFO);
1423 kfifo_in(&dev->emd_data_fifo[idx].mipi_kfifo,
1424 &fifo_data, sizeof(fifo_data));
1425 data_len += 4;
1426
1427 if (kfifo_is_full(&dev->emd_data_fifo[idx].mipi_kfifo))
1428 v4l2_warn(v4l2_dev, "%s: mipi_kfifo is full!\n",
1429 __func__);
1430 }
1431
1432 if (data_len) {
1433 dev->emd_data_fifo[idx].frame_id = cur_frame_id;
1434 dev->emd_data_fifo[idx].data_len = data_len;
1435 dev->emd_data_idx = (idx + 1) % RKISP1_EMDDATA_FIFO_MAX;
1436 }
1437
1438 v4l2_dbg(1, rkisp1_debug, &dev->v4l2_dev,
1439 "emd kfifo size: %d, frame_id %d\n",
1440 kfifo_len(&dev->emd_data_fifo[idx].mipi_kfifo),
1441 dev->emd_data_fifo[idx].frame_id);
1442 }
1443
1444 static int rkisp1_isp_sd_s_stream(struct v4l2_subdev *sd, int on)
1445 {
1446 struct rkisp1_device *isp_dev = sd_to_isp_dev(sd);
1447 int ret = 0;
1448
1449 if (!on) {
1450 rkisp1_stop_3a_run(isp_dev);
1451
1452 return rkisp1_isp_stop(isp_dev);
1453 }
1454
1455 rkisp1_start_3a_run(isp_dev);
1456
1457 atomic_set(&isp_dev->isp_sdev.frm_sync_seq, 0);
1458 ret = rkisp1_config_cif(isp_dev);
1459 if (ret < 0)
1460 return ret;
1461
1462 return rkisp1_isp_start(isp_dev);
1463 }
1464
1465 static int rkisp1_isp_sd_s_power(struct v4l2_subdev *sd, int on)
1466 {
1467 struct rkisp1_device *isp_dev = sd_to_isp_dev(sd);
1468 void __iomem *base = isp_dev->base_addr;
1469 int ret;
1470
1471 v4l2_dbg(1, rkisp1_debug, &isp_dev->v4l2_dev, "s_power: %d\n", on);
1472
1473 if (on) {
1474 ret = pm_runtime_get_sync(isp_dev->dev);
1475 if (ret < 0)
1476 return ret;
1477
1478 rkisp1_config_clk(isp_dev, on);
1479 if (isp_dev->isp_ver == ISP_V12 ||
1480 isp_dev->isp_ver == ISP_V13) {
1481 /* disable csi_rx interrupt */
1482 writel(0, base + CIF_ISP_CSI0_CTRL0);
1483 writel(0, base + CIF_ISP_CSI0_MASK1);
1484 writel(0, base + CIF_ISP_CSI0_MASK2);
1485 writel(0, base + CIF_ISP_CSI0_MASK3);
1486 }
1487 } else {
1488 rkisp1_config_clk(isp_dev, on);
1489 ret = pm_runtime_put_sync(isp_dev->dev);
1490 if (ret < 0)
1491 return ret;
1492 }
1493
1494 return 0;
1495 }
1496
1497 static int rkisp1_subdev_link_setup(struct media_entity *entity,
1498 const struct media_pad *local,
1499 const struct media_pad *remote,
1500 u32 flags)
1501 {
1502 struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity);
1503 struct rkisp1_device *dev;
1504
1505 if (!sd)
1506 return -ENODEV;
1507 dev = sd_to_isp_dev(sd);
1508 if (!dev)
1509 return -ENODEV;
1510
1511 if (!strcmp(remote->entity->name, DMA_VDEV_NAME)) {
1512 if (flags & MEDIA_LNK_FL_ENABLED)
1513 dev->isp_inp = INP_DMARX_ISP;
1514 else
1515 dev->isp_inp = INP_INVAL;
1516 }
1517
1518 return 0;
1519 }
1520
1521 static int rkisp1_subdev_link_validate(struct media_link *link)
1522 {
1523 if (link->source->index == RKISP1_ISP_PAD_SINK_PARAMS)
1524 return 0;
1525
1526 return v4l2_subdev_link_validate(link);
1527 }
1528
1529 static int rkisp1_subdev_fmt_link_validate(struct v4l2_subdev *sd,
1530 struct media_link *link,
1531 struct v4l2_subdev_format *source_fmt,
1532 struct v4l2_subdev_format *sink_fmt)
1533 {
1534 if (source_fmt->format.code != sink_fmt->format.code)
1535 return -EINVAL;
1536
1537 /* Crop is available */
1538 if (source_fmt->format.width < sink_fmt->format.width ||
1539 source_fmt->format.height < sink_fmt->format.height)
1540 return -EINVAL;
1541
1542 return 0;
1543 }
1544
1545 static void
1546 riksp1_isp_queue_event_sof(struct rkisp1_isp_subdev *isp)
1547 {
1548 struct v4l2_event event = {
1549 .type = V4L2_EVENT_FRAME_SYNC,
1550 .u.frame_sync.frame_sequence =
1551 atomic_inc_return(&isp->frm_sync_seq) - 1,
1552 };
1553 v4l2_event_queue(isp->sd.devnode, &event);
1554 }
1555
1556 static int rkisp1_isp_sd_subs_evt(struct v4l2_subdev *sd, struct v4l2_fh *fh,
1557 struct v4l2_event_subscription *sub)
1558 {
1559 if (sub->type != V4L2_EVENT_FRAME_SYNC)
1560 return -EINVAL;
1561
1562 /* Line number. For now only zero accepted. */
1563 if (sub->id != 0)
1564 return -EINVAL;
1565
1566 return v4l2_event_subscribe(fh, sub, 0, NULL);
1567 }
1568
1569 static const struct v4l2_subdev_pad_ops rkisp1_isp_sd_pad_ops = {
1570 .enum_mbus_code = rkisp1_isp_sd_enum_mbus_code,
1571 .get_selection = rkisp1_isp_sd_get_selection,
1572 .set_selection = rkisp1_isp_sd_set_selection,
1573 .get_fmt = rkisp1_isp_sd_get_fmt,
1574 .set_fmt = rkisp1_isp_sd_set_fmt,
1575 .link_validate = rkisp1_subdev_fmt_link_validate,
1576 };
1577
1578 static const struct media_entity_operations rkisp1_isp_sd_media_ops = {
1579 .link_setup = rkisp1_subdev_link_setup,
1580 .link_validate = rkisp1_subdev_link_validate,
1581 };
1582
1583 static const struct v4l2_subdev_video_ops rkisp1_isp_sd_video_ops = {
1584 .s_stream = rkisp1_isp_sd_s_stream,
1585 };
1586
1587 static const struct v4l2_subdev_core_ops rkisp1_isp_core_ops = {
1588 .subscribe_event = rkisp1_isp_sd_subs_evt,
1589 .unsubscribe_event = v4l2_event_subdev_unsubscribe,
1590 .s_power = rkisp1_isp_sd_s_power,
1591 };
1592
1593 static struct v4l2_subdev_ops rkisp1_isp_sd_ops = {
1594 .core = &rkisp1_isp_core_ops,
1595 .video = &rkisp1_isp_sd_video_ops,
1596 .pad = &rkisp1_isp_sd_pad_ops,
1597 };
1598
1599 static void rkisp1_isp_sd_init_default_fmt(struct rkisp1_isp_subdev *isp_sd)
1600 {
1601 struct v4l2_mbus_framefmt *in_frm = &isp_sd->in_frm;
1602 struct v4l2_rect *in_crop = &isp_sd->in_crop;
1603 struct v4l2_rect *out_crop = &isp_sd->out_crop;
1604 struct ispsd_in_fmt *in_fmt = &isp_sd->in_fmt;
1605 struct ispsd_out_fmt *out_fmt = &isp_sd->out_fmt;
1606
1607 *in_fmt = rkisp1_isp_input_formats[0];
1608 in_frm->width = RKISP1_DEFAULT_WIDTH;
1609 in_frm->height = RKISP1_DEFAULT_HEIGHT;
1610 in_frm->code = in_fmt->mbus_code;
1611
1612 in_crop->width = in_frm->width;
1613 in_crop->height = in_frm->height;
1614 in_crop->left = 0;
1615 in_crop->top = 0;
1616
1617 /* propagate to source */
1618 *out_crop = *in_crop;
1619 *out_fmt = rkisp1_isp_output_formats[0];
1620 }
1621
1622 int rkisp1_register_isp_subdev(struct rkisp1_device *isp_dev,
1623 struct v4l2_device *v4l2_dev)
1624 {
1625 struct rkisp1_isp_subdev *isp_sdev = &isp_dev->isp_sdev;
1626 struct v4l2_subdev *sd = &isp_sdev->sd;
1627 int ret;
1628
1629 v4l2_subdev_init(sd, &rkisp1_isp_sd_ops);
1630 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
1631 sd->entity.ops = &rkisp1_isp_sd_media_ops;
1632 sd->entity.function = MEDIA_ENT_F_V4L2_SUBDEV_UNKNOWN;
1633 snprintf(sd->name, sizeof(sd->name), "rkisp1-isp-subdev");
1634
1635 isp_sdev->pads[RKISP1_ISP_PAD_SINK].flags =
1636 MEDIA_PAD_FL_SINK | MEDIA_PAD_FL_MUST_CONNECT;
1637 isp_sdev->pads[RKISP1_ISP_PAD_SINK_PARAMS].flags = MEDIA_PAD_FL_SINK;
1638 isp_sdev->pads[RKISP1_ISP_PAD_SOURCE_PATH].flags = MEDIA_PAD_FL_SOURCE;
1639 isp_sdev->pads[RKISP1_ISP_PAD_SOURCE_STATS].flags = MEDIA_PAD_FL_SOURCE;
1640 ret = media_entity_pads_init(&sd->entity, RKISP1_ISP_PAD_MAX,
1641 isp_sdev->pads);
1642 if (ret < 0)
1643 return ret;
1644
1645 sd->owner = THIS_MODULE;
1646 v4l2_set_subdevdata(sd, isp_dev);
1647
1648 sd->grp_id = GRP_ID_ISP;
1649 ret = v4l2_device_register_subdev(v4l2_dev, sd);
1650 if (ret < 0) {
1651 v4l2_err(sd, "Failed to register isp subdev\n");
1652 goto err_cleanup_media_entity;
1653 }
1654
1655 rkisp1_isp_sd_init_default_fmt(isp_sdev);
1656 isp_dev->hdr_sensor = NULL;
1657 isp_dev->isp_state = ISP_STOP;
1658
1659 return 0;
1660 err_cleanup_media_entity:
1661 media_entity_cleanup(&sd->entity);
1662 return ret;
1663 }
1664
1665 void rkisp1_unregister_isp_subdev(struct rkisp1_device *isp_dev)
1666 {
1667 struct v4l2_subdev *sd = &isp_dev->isp_sdev.sd;
1668
1669 v4l2_device_unregister_subdev(sd);
1670 media_entity_cleanup(&sd->entity);
1671 }
1672
1673 /**************** Interrupter Handler ****************/
1674
1675 void rkisp1_mipi_isr(unsigned int mis, struct rkisp1_device *dev)
1676 {
1677 struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
1678 void __iomem *base = dev->base_addr;
1679 u32 val;
1680
1681 writel(~0, base + CIF_MIPI_ICR);
1682
1683 /*
1684 * Disable DPHY errctrl interrupt, because this dphy
1685 * erctrl signal is asserted until the next changes
1686 * of line state. This time is may be too long and cpu
1687 * is hold in this interrupt.
1688 */
1689 if (mis & CIF_MIPI_ERR_DPHY) {
1690 val = readl(base + CIF_MIPI_IMSC);
1691 writel(val & ~CIF_MIPI_ERR_DPHY, base + CIF_MIPI_IMSC);
1692 dev->isp_sdev.dphy_errctrl_disabled = true;
1693 }
1694
1695 /*
1696 * Enable DPHY errctrl interrupt again, if mipi have receive
1697 * the whole frame without any error.
1698 */
1699 if (mis == CIF_MIPI_FRAME_END) {
1700 /*
1701 * Enable DPHY errctrl interrupt again, if mipi have receive
1702 * the whole frame without any error.
1703 */
1704 if (dev->isp_sdev.dphy_errctrl_disabled) {
1705 val = readl(base + CIF_MIPI_IMSC);
1706 val |= CIF_MIPI_ERR_DPHY;
1707 writel(val, base + CIF_MIPI_IMSC);
1708 dev->isp_sdev.dphy_errctrl_disabled = false;
1709 }
1710 } else {
1711 v4l2_warn(v4l2_dev, "MIPI mis error: 0x%08x\n", mis);
1712 val = readl(base + CIF_MIPI_CTRL);
1713 writel(val | CIF_MIPI_CTRL_FLUSH_FIFO, base + CIF_MIPI_CTRL);
1714 }
1715 }
1716
1717 void rkisp1_mipi_v13_isr(unsigned int err1, unsigned int err2,
1718 unsigned int err3, struct rkisp1_device *dev)
1719 {
1720 struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
1721 void __iomem *base = dev->base_addr;
1722 u32 val, mask;
1723
1724 /*
1725 * Disable DPHY errctrl interrupt, because this dphy
1726 * erctrl signal is asserted until the next changes
1727 * of line state. This time is may be too long and cpu
1728 * is hold in this interrupt.
1729 */
1730 mask = CIF_ISP_CSI0_IMASK1_PHY_ERRSOTSYNC(0x0F) |
1731 CIF_ISP_CSI0_IMASK1_PHY_ERREOTSYNC(0x0F);
1732 if (mask & err1) {
1733 val = readl(base + CIF_ISP_CSI0_MASK1);
1734 writel(val & ~mask, base + CIF_ISP_CSI0_MASK1);
1735 dev->isp_sdev.dphy_errctrl_disabled = true;
1736 }
1737
1738 mask = CIF_ISP_CSI0_IMASK2_PHY_ERRSOTHS(0x0F) |
1739 CIF_ISP_CSI0_IMASK2_PHY_ERRCONTROL(0x0F);
1740 if (mask & err2) {
1741 val = readl(base + CIF_ISP_CSI0_MASK2);
1742 writel(val & ~mask, base + CIF_ISP_CSI0_MASK2);
1743 dev->isp_sdev.dphy_errctrl_disabled = true;
1744 }
1745
1746 mask = CIF_ISP_CSI0_IMASK_FRAME_END(0x3F);
1747 if ((err3 & mask) && !err1 && !err2) {
1748 /*
1749 * Enable DPHY errctrl interrupt again, if mipi have receive
1750 * the whole frame without any error.
1751 */
1752 if (dev->isp_sdev.dphy_errctrl_disabled) {
1753 writel(0x1FFFFFF0, base + CIF_ISP_CSI0_MASK1);
1754 writel(0x03FFFFFF, base + CIF_ISP_CSI0_MASK2);
1755 dev->isp_sdev.dphy_errctrl_disabled = false;
1756 }
1757 }
1758
1759 if (err1)
1760 v4l2_warn(v4l2_dev, "MIPI error: err1: 0x%08x\n", err1);
1761
1762 if (err2)
1763 v4l2_warn(v4l2_dev, "MIPI error: err2: 0x%08x\n", err2);
1764 }
1765
1766 void rkisp1_isp_isr(unsigned int isp_mis, struct rkisp1_device *dev)
1767 {
1768 void __iomem *base = dev->base_addr;
1769 unsigned int isp_mis_tmp = 0;
1770 unsigned int isp_err = 0;
1771
1772 /* start edge of v_sync */
1773 if (isp_mis & CIF_ISP_V_START) {
1774 if (dev->stream[RKISP1_STREAM_SP].interlaced) {
1775 /* 0 = ODD 1 = EVEN */
1776 if (dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_DPHY) {
1777 void __iomem *addr = NULL;
1778
1779 if (dev->isp_ver == ISP_V10 ||
1780 dev->isp_ver == ISP_V10_1)
1781 addr = base + CIF_MIPI_FRAME;
1782 else if (dev->isp_ver == ISP_V12 ||
1783 dev->isp_ver == ISP_V13)
1784 addr = base + CIF_ISP_CSI0_FRAME_NUM_RO;
1785
1786 if (addr)
1787 dev->stream[RKISP1_STREAM_SP].u.sp.field =
1788 (readl(addr) >> 16) % 2;
1789 } else {
1790 dev->stream[RKISP1_STREAM_SP].u.sp.field =
1791 (readl(base + CIF_ISP_FLAGS_SHD) >> 2) & BIT(0);
1792 }
1793 }
1794
1795 if (dev->vs_irq < 0)
1796 riksp1_isp_queue_event_sof(&dev->isp_sdev);
1797
1798 writel(CIF_ISP_V_START, base + CIF_ISP_ICR);
1799 isp_mis_tmp = readl(base + CIF_ISP_MIS);
1800 if (isp_mis_tmp & CIF_ISP_V_START)
1801 v4l2_err(&dev->v4l2_dev, "isp icr v_statr err: 0x%x\n",
1802 isp_mis_tmp);
1803 }
1804
1805 if ((isp_mis & (CIF_ISP_DATA_LOSS | CIF_ISP_PIC_SIZE_ERROR))) {
1806 if ((isp_mis & CIF_ISP_PIC_SIZE_ERROR)) {
1807 /* Clear pic_size_error */
1808 writel(CIF_ISP_PIC_SIZE_ERROR, base + CIF_ISP_ICR);
1809 isp_err = readl(base + CIF_ISP_ERR);
1810 v4l2_err(&dev->v4l2_dev,
1811 "CIF_ISP_PIC_SIZE_ERROR (0x%08x)", isp_err);
1812 writel(isp_err, base + CIF_ISP_ERR_CLR);
1813 }
1814
1815 if ((isp_mis & CIF_ISP_DATA_LOSS)) {
1816 /* Clear data_loss */
1817 writel(CIF_ISP_DATA_LOSS, base + CIF_ISP_ICR);
1818 v4l2_err(&dev->v4l2_dev, "CIF_ISP_DATA_LOSS\n");
1819 writel(CIF_ISP_DATA_LOSS, base + CIF_ISP_ICR);
1820 }
1821
1822 if (dev->isp_err_cnt++ > RKISP1_CONTI_ERR_MAX) {
1823 rkisp1_isp_stop(dev);
1824 dev->isp_state = ISP_ERROR;
1825 v4l2_err(&dev->v4l2_dev,
1826 "Too many isp error, stop isp!\n");
1827 }
1828 }
1829
1830 /* sampled input frame is complete */
1831 if (isp_mis & CIF_ISP_FRAME_IN) {
1832 writel(CIF_ISP_FRAME_IN, base + CIF_ISP_ICR);
1833 isp_mis_tmp = readl(base + CIF_ISP_MIS);
1834 if (isp_mis_tmp & CIF_ISP_FRAME_IN)
1835 v4l2_err(&dev->v4l2_dev, "isp icr frame_in err: 0x%x\n",
1836 isp_mis_tmp);
1837
1838 dev->isp_err_cnt = 0;
1839 }
1840
1841 /* frame was completely put out */
1842 if (isp_mis & CIF_ISP_FRAME) {
1843 /* Clear Frame In (ISP) */
1844 writel(CIF_ISP_FRAME, base + CIF_ISP_ICR);
1845 isp_mis_tmp = readl(base + CIF_ISP_MIS);
1846 if (isp_mis_tmp & CIF_ISP_FRAME)
1847 v4l2_err(&dev->v4l2_dev,
1848 "isp icr frame end err: 0x%x\n", isp_mis_tmp);
1849
1850 rkisp1_isp_read_add_fifo_data(dev);
1851 }
1852
1853 if (isp_mis & (CIF_ISP_FRAME | CIF_ISP_AWB_DONE | CIF_ISP_AFM_FIN)) {
1854 u32 irq = isp_mis;
1855
1856 /* FRAME to get EXP and HIST together */
1857 if (isp_mis & CIF_ISP_FRAME)
1858 irq |= ((CIF_ISP_EXP_END |
1859 CIF_ISP_HIST_MEASURE_RDY) &
1860 readl(base + CIF_ISP_RIS));
1861
1862 rkisp1_stats_isr(&dev->stats_vdev, irq);
1863 }
1864
1865 /*
1866 * Then update changed configs. Some of them involve
1867 * lot of register writes. Do those only one per frame.
1868 * Do the updates in the order of the processing flow.
1869 */
1870 rkisp1_params_isr(&dev->params_vdev, isp_mis);
1871 }
1872
1873 irqreturn_t rkisp1_vs_isr_handler(int irq, void *ctx)
1874 {
1875 struct device *dev = ctx;
1876 struct rkisp1_device *rkisp1_dev = dev_get_drvdata(dev);
1877
1878 if (rkisp1_dev->vs_irq >= 0)
1879 riksp1_isp_queue_event_sof(&rkisp1_dev->isp_sdev);
1880
1881 return IRQ_HANDLED;
1882 }
1883
1884