1 /*
2 * Copyright (c) 2024-2025, Rockchip Electronics Co., Ltd. All rights reserved..
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <common/debug.h>
8 #include <drivers/delay_timer.h>
9
10 #include "otp.h"
11 #include <plat_private.h>
12 #include <platform_def.h>
13 #include <rk3568_clk.h>
14 #include <rk3568_def.h>
15 #include <soc.h>
16
17 /* default SBPI_READ mode */
18 #define OTP_USER_READ 0
19 #define USEC_PER_SEC 1000000
20
21 enum clk_type {
22 PCLK_PHY = 0,
23 PCLK_NS,
24 PCLK_S,
25 CLK_NS_USER,
26 CLK_NS_SBPI,
27 CLK_S_USER,
28 CLK_S_SBPI
29 };
30
31 static uint8_t otp_ns_ecc_flag[OTP_NS_BYTE_SIZE / 2];
32
enable_otp_clk(int clk)33 static uint32_t enable_otp_clk(int clk)
34 {
35 uint32_t reg = 0;
36
37 switch (clk) {
38 case CLK_NS_USER:
39 reg = mmio_read_32(CRU_BASE + CRU_CLKGATES_CON(26));
40 if (reg & CLK_NS_OTP_USER_EN)
41 mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(26),
42 CLK_NS_OTP_USER_EN << WRITE_MASK);
43
44 break;
45 case CLK_NS_SBPI:
46 reg = mmio_read_32(CRU_BASE + CRU_CLKGATES_CON(26));
47 if (reg & CLK_NS_OTP_SBPI_EN)
48 mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(26),
49 CLK_NS_OTP_SBPI_EN << WRITE_MASK);
50
51 break;
52 case PCLK_NS:
53 reg = mmio_read_32(CRU_BASE + CRU_CLKGATES_CON(26));
54 if (reg & PCLK_NS_OTP_EN)
55 mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(26),
56 PCLK_NS_OTP_EN << WRITE_MASK);
57
58 break;
59 case PCLK_PHY:
60 reg = mmio_read_32(CRU_BASE + CRU_CLKGATES_CON(34));
61 if (reg & PCLK_PHY_OTP_EN)
62 mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(34),
63 PCLK_PHY_OTP_EN << WRITE_MASK);
64
65 break;
66 case CLK_S_USER:
67 reg = mmio_read_32(SCRU_BASE + SCRU_GATE_CON01);
68 if (reg & CLK_S_OTP_USER_EN)
69 mmio_write_32(SCRU_BASE + SCRU_GATE_CON01,
70 CLK_S_OTP_USER_EN << WRITE_MASK);
71
72 break;
73 case CLK_S_SBPI:
74 reg = mmio_read_32(SCRU_BASE + SCRU_GATE_CON01);
75 if (reg & CLK_S_OTP_SBPI_EN)
76 mmio_write_32(SCRU_BASE + SCRU_GATE_CON01,
77 CLK_S_OTP_SBPI_EN << WRITE_MASK);
78
79 break;
80 case PCLK_S:
81 reg = mmio_read_32(SCRU_BASE + SCRU_GATE_CON01);
82 if (reg & PCLK_S_OTP_EN)
83 mmio_write_32(SCRU_BASE + SCRU_GATE_CON01,
84 PCLK_S_OTP_EN << WRITE_MASK);
85
86 break;
87 default:
88 break;
89 }
90
91 return reg;
92 }
93
restore_otp_clk(int clk,uint32_t reg)94 static void restore_otp_clk(int clk, uint32_t reg)
95 {
96 switch (clk) {
97 case CLK_NS_USER:
98 if (reg & CLK_NS_OTP_USER_EN)
99 mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(26),
100 (CLK_NS_OTP_USER_EN << WRITE_MASK) | reg);
101 break;
102 case CLK_NS_SBPI:
103 if (reg & CLK_NS_OTP_SBPI_EN)
104 mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(26),
105 (CLK_NS_OTP_SBPI_EN << WRITE_MASK) | reg);
106 break;
107 case PCLK_NS:
108 if (reg & PCLK_NS_OTP_EN)
109 mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(26),
110 (PCLK_NS_OTP_EN << WRITE_MASK) | reg);
111 break;
112 case PCLK_PHY:
113 if (reg & PCLK_PHY_OTP_EN)
114 mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(34),
115 (PCLK_PHY_OTP_EN << WRITE_MASK) | reg);
116 break;
117 case CLK_S_USER:
118 if (reg & CLK_S_OTP_USER_EN)
119 mmio_write_32(SCRU_BASE + SCRU_GATE_CON01,
120 (CLK_S_OTP_USER_EN << WRITE_MASK) | reg);
121 break;
122 case CLK_S_SBPI:
123 if (reg & CLK_S_OTP_SBPI_EN)
124 mmio_write_32(SCRU_BASE + SCRU_GATE_CON01,
125 (CLK_S_OTP_SBPI_EN << WRITE_MASK) | reg);
126 break;
127 case PCLK_S:
128 if (reg & PCLK_S_OTP_EN)
129 mmio_write_32(SCRU_BASE + SCRU_GATE_CON01,
130 (PCLK_S_OTP_EN << WRITE_MASK) | reg);
131 break;
132 default:
133 return;
134 }
135 }
136
check_sbpi_done_int(uint32_t otp_base)137 static int check_sbpi_done_int(uint32_t otp_base)
138 {
139 /* wait max 10ms */
140 uint32_t timeout = 10000;
141
142 while (1) {
143 /* check sbpi DONE INT */
144 if (((mmio_read_32(otp_base + REG_OTPC_INT_STATUS) >> 1) & 0x01) == 0x01) {
145 mmio_write_32(otp_base + REG_OTPC_INT_STATUS,
146 0xffff0002); /* clear sbpi DONE INT */
147 break;
148 }
149
150 if (timeout == 0) {
151 WARN("---OTP---Check sbpi int done TIMEOUT");
152 return -1;
153 }
154
155 timeout--;
156 udelay(1);
157 }
158
159 return 0;
160 }
161
otp_select(uint32_t addr)162 static uint32_t otp_select(uint32_t addr)
163 {
164 uint32_t otp_base = 0;
165
166 if (addr < 0x1c0) { /* 0-447 otp0 S */
167 otp_base = OTP_S_BASE;
168 mmio_write_32(SGRF_BASE + SGRF_SOC_CON2,
169 (SGRF_CON_OTP_SECURE << WRITE_MASK) |
170 SGRF_CON_OTP_SECURE); /* secure */
171 } else if (addr >= 0x1c0 && addr < 0x200) { /* 448-511 otp0 NS */
172 otp_base = OTP_NS_BASE;
173 mmio_write_32(SGRF_BASE + SGRF_SOC_CON2,
174 SGRF_CON_OTP_SECURE << WRITE_MASK); /* non secure */
175 }
176
177 return otp_base;
178 }
179
rk_otp_ecc_enable(uint32_t otp_base,bool enable)180 static int rk_otp_ecc_enable(uint32_t otp_base, bool enable)
181 {
182 mmio_write_32(otp_base + REG_OTPC_SBPI_CTRL,
183 BITS_WITH_WMASK(0x2, 0xffu, SBPI_DEV_ID_SHIFT)); /* device id */
184 /* a value define number of sbpi valid command */
185 mmio_write_32(otp_base + REG_OTPC_SBPI_CMD_VALID_PRE, SBPI_VAILI_COMMAND(1));
186 /* SBPI_CMD will be programmable from offset 0x1000 to 0x2000,
187 * which is 4kBAnd there are 1024 registers totally, which are
188 * correspond to a sertain command.The address of these registers
189 * are: 0x10000x1004...0x1ffc
190 */
191 mmio_write_32(otp_base + REG_OTPC_SBPI_CMD_OFFSET(0), 0xfa); /* sbpi cmd */
192
193 if (enable)
194 mmio_write_32(otp_base + REG_OTPC_SBPI_CMD_OFFSET(1),
195 0x00); /* sbpi cmd enable ecc*/
196 else
197 mmio_write_32(otp_base + REG_OTPC_SBPI_CMD_OFFSET(1),
198 0x09); /* sbpi cmd disable ecc*/
199
200 mmio_write_32(otp_base + REG_OTPC_SBPI_CTRL,
201 (SBPI_ENABLE << WRITE_MASK) | SBPI_ENABLE); /* sbpi enable */
202
203 if (check_sbpi_done_int(otp_base))
204 return -1;
205
206 return 0;
207 }
208
rk_otp_sbpi_read(uint32_t addr,uint16_t * read_data,bool is_need_ecc)209 static int rk_otp_sbpi_read(uint32_t addr, uint16_t *read_data, bool is_need_ecc)
210 {
211 uint32_t otp_base = 0;
212 uint32_t otp_qp;
213
214 otp_base = otp_select(addr);
215
216 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(28),
217 (OTP_PHY_SRSTN << WRITE_MASK) | OTP_PHY_SRSTN); /* reset otp phy */
218 udelay(2);
219 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(28),
220 OTP_PHY_SRSTN << WRITE_MASK);
221 udelay(1);
222
223 mmio_write_32(SGRF_BASE + SGRF_SOC_CON2,
224 (SGRF_CON_OTP_CKE << WRITE_MASK) | SGRF_CON_OTP_CKE); /* CKE = 1 */
225 udelay(2);
226 mmio_write_32(otp_base + REG_OTPC_USER_CTRL, USER_DCTRL << WRITE_MASK);
227 udelay(2);
228
229 rk_otp_ecc_enable(otp_base, is_need_ecc);
230
231 mmio_write_32(otp_base + REG_OTPC_SBPI_CTRL,
232 (SBPI_CS_AUTO << WRITE_MASK) | SBPI_CS_AUTO); /* cs auto */
233 mmio_write_32(otp_base + REG_OTPC_SBPI_CS_VALID_PRE,
234 0xffff0000); /* cs valid number */
235
236 mmio_write_32(otp_base + REG_OTPC_SBPI_CTRL,
237 BITS_WITH_WMASK(0x2, 0xffu, SBPI_DEV_ID_SHIFT)); /* device id */
238 /* a value define number of sbpi valid command */
239 mmio_write_32(otp_base + REG_OTPC_SBPI_CMD_VALID_PRE, SBPI_VAILI_COMMAND(2));
240 /* SBPI_CMD will be programmable from offset 0x1000 to 0x2000,
241 * which is 4kBAnd there are 1024 registers totally, which are
242 * correspond to a sertain command.The address of these registers
243 * are: 0x10000x1004...0x1ffc
244 */
245 mmio_write_32(otp_base + REG_OTPC_SBPI_CMD_OFFSET(0), 0xfc); /* sbpi cmd */
246 mmio_write_32(otp_base + REG_OTPC_SBPI_CMD_OFFSET(1), addr & 0xff); /* sbpi cmd 3c addr */
247 mmio_write_32(otp_base + REG_OTPC_SBPI_CMD_OFFSET(2),
248 (addr >> 8) & 0xff); /* sbpi cmd 3d addr */
249 mmio_write_32(otp_base + REG_OTPC_SBPI_CTRL,
250 (SBPI_ENABLE << WRITE_MASK) | SBPI_ENABLE); /* sbpi enable */
251
252 if (check_sbpi_done_int(otp_base))
253 return -1;
254
255 /* a value define number of sbpi valid command */
256 mmio_write_32(otp_base + REG_OTPC_SBPI_CMD_VALID_PRE, SBPI_VAILI_COMMAND(7));
257 /* SBPI_CMD will be programmable from offset 0x1000 to 0x2000,
258 * which is 4kBAnd there are 1024 registers totally, which are
259 * correspond to a sertain command.The address of these registers
260 * are: 0x10000x1004...0x1ffc
261 */
262 mmio_write_32(otp_base + REG_OTPC_SBPI_CMD_OFFSET(0), 0x00);
263 mmio_write_32(otp_base + REG_OTPC_SBPI_CMD_OFFSET(1), 0x00);
264 mmio_write_32(otp_base + REG_OTPC_SBPI_CMD_OFFSET(2), 0x40);
265 mmio_write_32(otp_base + REG_OTPC_SBPI_CMD_OFFSET(3), 0x40);
266 mmio_write_32(otp_base + REG_OTPC_SBPI_CMD_OFFSET(4), 0x00);
267 mmio_write_32(otp_base + REG_OTPC_SBPI_CMD_OFFSET(5), 0x02);
268 mmio_write_32(otp_base + REG_OTPC_SBPI_CMD_OFFSET(6), 0x80);
269 mmio_write_32(otp_base + REG_OTPC_SBPI_CMD_OFFSET(7), 0x81);
270 /* sbpi enable */
271 mmio_write_32(otp_base + REG_OTPC_SBPI_CTRL,
272 (SBPI_ENABLE << WRITE_MASK) | SBPI_ENABLE);
273
274 if (check_sbpi_done_int(otp_base))
275 return -1;
276
277 if (is_need_ecc) {
278 otp_qp = mmio_read_32(otp_base + REG_OTPC_USER_QP);
279 VERBOSE("otp_addr:0x%x, otp_qp:0x%x\n", addr, otp_qp);
280 if (((otp_qp & 0xc0) == 0xc0) || (otp_qp & 0x20)) {
281 otp_ns_ecc_flag[addr - OTP_S_BYTE_SIZE / 2] = 1;
282 ERROR("ecc otp_addr:0x%x, otp_qp failed 0x%x\n", addr, otp_qp);
283 }
284 }
285
286 *read_data =
287 (uint16_t)mmio_read_32(otp_base + REG_OTPC_SBPI_READ_DATA_BASE + 0x20);
288 *read_data +=
289 (uint16_t)(mmio_read_32(otp_base + REG_OTPC_SBPI_READ_DATA_BASE + 0x24) << 8);
290 /* a value define number of sbpi valid command */
291 mmio_write_32(otp_base + REG_OTPC_SBPI_CMD_VALID_PRE, SBPI_VAILI_COMMAND(1));
292 /* SBPI_CMD will be programmable from offset 0x1000 to 0x2000,
293 * which is 4kBAnd there are 1024 registers totally, which are
294 * correspond to a sertain command.The address of these registers
295 * are: 0x10000x1004...0x1ffc
296 */
297 mmio_write_32(otp_base + REG_OTPC_SBPI_CMD_OFFSET(0), 0xa0);
298 mmio_write_32(otp_base + REG_OTPC_SBPI_CMD_OFFSET(1), 0x0);
299 mmio_write_32(otp_base + REG_OTPC_SBPI_CTRL,
300 (SBPI_ENABLE << WRITE_MASK) | SBPI_ENABLE);
301
302 if (check_sbpi_done_int(otp_base))
303 return -1;
304
305 mmio_write_32(otp_base + REG_OTPC_INT_STATUS, 0xffff0003); /* clear sbpi INT */
306
307 mmio_write_32(SGRF_BASE + SGRF_SOC_CON2,
308 SGRF_CON_OTP_SECURE << WRITE_MASK); /* non secure */
309
310 return 0;
311 }
312
rk_otp_read(uint32_t byte_addr,uint32_t byte_len,uint16_t * buf,bool is_need_ecc)313 int rk_otp_read(uint32_t byte_addr, uint32_t byte_len, uint16_t *buf, bool is_need_ecc)
314 {
315 int ret = 0;
316 uint32_t i = 0;
317 uint32_t clk_ns_user = 0, clk_ns_sbpi = 0, pclk_ns = 0, pclk_phy = 0;
318 uint32_t clk_s_user = 0, clk_s_sbpi = 0, pclk_s = 0;
319 uint32_t addr, length;
320
321 /*
322 * RK3568 platform OTP R&W by halfword
323 * Address and Length must be an integral multiple of 2
324 */
325 if ((byte_addr % 2) != 0 || (byte_len % 2) != 0) {
326 ERROR("byte addr and byte length must be even numbers!");
327 return -1;
328 }
329
330 addr = byte_addr / 2;
331 length = byte_len / 2;
332
333 if (addr >= OTP_MAX_SIZE || length <= 0 || length > OTP_MAX_SIZE || !buf)
334 return -1;
335
336 if ((addr + length) > OTP_MAX_SIZE)
337 return -1;
338
339 if (addr < OTP_S_SIZE && (addr + length) > OTP_S_SIZE) {
340 ERROR("Both read secure and non secure otp are not supported!");
341 return -1;
342 }
343
344 /* enable otp clk if clk is disabled */
345 pclk_phy = enable_otp_clk(PCLK_PHY);
346 if (addr < 0x1C0) { /* 0-447 otp0 S */
347 pclk_s = enable_otp_clk(PCLK_S);
348 clk_s_sbpi = enable_otp_clk(CLK_S_SBPI);
349 clk_s_user = enable_otp_clk(CLK_S_USER);
350 } else if (addr >= 0x1C0 && addr < 0x200) { /* 448-511 otp0 NS */
351 pclk_ns = enable_otp_clk(PCLK_NS);
352 clk_ns_sbpi = enable_otp_clk(CLK_NS_SBPI);
353 clk_ns_user = enable_otp_clk(CLK_NS_USER);
354 }
355
356 for (i = 0; i < length; i++) {
357
358 ret = rk_otp_sbpi_read(addr + i, buf + i, is_need_ecc);
359 if (ret) {
360 ERROR("---OTP---sbpi read otp failed! addr: 0x%x", addr + i);
361 goto out;
362 }
363 }
364
365 out:
366 /* restore otp clk state */
367 restore_otp_clk(PCLK_PHY, pclk_phy);
368 if (addr < 0x1C0) { /* 0-447 otp0 S */
369 restore_otp_clk(PCLK_S, pclk_s);
370 restore_otp_clk(CLK_S_SBPI, clk_s_sbpi);
371 restore_otp_clk(CLK_S_USER, clk_s_user);
372 } else if (addr >= 0x1C0 && addr < 0x200) { /* 448-511 otp0 NS */
373 restore_otp_clk(PCLK_NS, pclk_ns);
374 restore_otp_clk(CLK_NS_SBPI, clk_ns_sbpi);
375 restore_otp_clk(CLK_NS_USER, clk_ns_user);
376 }
377
378 return ret;
379 }
380
rk_otp_ns_ecc_flag(uint32_t addr)381 int rk_otp_ns_ecc_flag(uint32_t addr)
382 {
383 if (addr >= OTP_NS_BYTE_SIZE)
384 return 0;
385
386 return otp_ns_ecc_flag[addr / 2];
387 }
388