1 /* 2 * Copyright (c) 2019-2022 Rockchip Eletronics Co., Ltd. 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 #ifndef __CALIBDBV2_ABLC_UAPI_HEADER_V32_H__ 17 #define __CALIBDBV2_ABLC_UAPI_HEADER_V32_H__ 18 19 #include "rk_aiq_comm.h" 20 21 RKAIQ_BEGIN_DECLARE 22 typedef struct AblcSelect_V32_s { 23 // M4_BOOL_DESC("enable", "1") 24 bool enable; 25 // M4_NUMBER_DESC("blc_r", "f32", M4_RANGE(0,4095), "0",M4_DIGIT(4)) 26 float blc_r; 27 // M4_NUMBER_DESC("blc_gr", "f32", M4_RANGE(0,4095), "0",M4_DIGIT(4)) 28 float blc_gr; 29 // M4_NUMBER_DESC("blc_gb", "f32", M4_RANGE(0,4095), "0",M4_DIGIT(4)) 30 float blc_gb; 31 // M4_NUMBER_DESC("blc_b", "f32", M4_RANGE(0,4095), "0",M4_DIGIT(4)) 32 float blc_b; 33 } AblcSelect_V32_t; 34 35 typedef struct AblcOBSelect_V32_s { 36 // M4_BOOL_DESC("enable", "1") 37 bool enable; 38 // M4_NUMBER_DESC("ob_offset", "f32", M4_RANGE(0,4095), "0",M4_DIGIT(4)) 39 float ob_offset; 40 // M4_NUMBER_DESC("ob_predgain", "f32", M4_RANGE(0,4095), "0",M4_DIGIT(4)) 41 float ob_predgain; 42 } AblcOBSelect_V32_t; 43 44 typedef struct AblcManualSetting_s { 45 // M4_STRUCT_DESC("blc0_para", "normal_ui_style") 46 AblcSelect_V32_t blc0_para; 47 48 // M4_STRUCT_DESC("blc1_para", "normal_ui_style") 49 AblcSelect_V32_t blc1_para; 50 51 // M4_STRUCT_DESC("blc_ob_para", "normal_ui_style") 52 AblcOBSelect_V32_t blc_ob_para; 53 } AblcManualSetting_t; 54 55 typedef struct AblcExpInfo_V32_s { 56 // M4_NUMBER_DESC("hdr_mode", "u8", M4_RANGE(0, 2), "0", M4_DIGIT(0)) 57 int hdr_mode; 58 59 // M4_NUMBER_DESC("snr_mode", "s8", M4_RANGE(0, 2), "0", M4_DIGIT(0)) 60 int snr_mode; 61 62 // M4_NUMBER_DESC("bayertnr_en", "s8", M4_RANGE(0, 1), "0", M4_DIGIT(0)) 63 int bayertnr_en; 64 65 // M4_ARRAY_DESC("time", "f32", M4_SIZE(1,3), M4_RANGE(0, 1024), "0.01", M4_DIGIT(6)) 66 float arTime[3]; 67 // M4_ARRAY_DESC("again", "f32", M4_SIZE(1,3), M4_RANGE(0, 204800), "1", M4_DIGIT(3)) 68 float arAGain[3]; 69 // M4_ARRAY_DESC("dgain", "f32", M4_SIZE(1,3), M4_RANGE(0, 204800), "1", M4_DIGIT(3)) 70 float arDGain[3]; 71 // M4_ARRAY_DESC("isp_dgain", "f32", M4_SIZE(1,3), M4_RANGE(0, 204800), "1", M4_DIGIT(3)) 72 float isp_dgain[3]; 73 // M4_ARRAY_DESC("iso", "u32", M4_SIZE(1,3), M4_RANGE(0, 204800), "1", M4_DIGIT(0)) 74 int arIso[3]; 75 76 // M4_NUMBER_DESC("isoLevelLow", "u8", M4_RANGE(0, 12), "0", M4_DIGIT(0)) 77 int isoLevelLow; 78 // M4_NUMBER_DESC("isoLevelHig", "u8", M4_RANGE(0, 12), "0", M4_DIGIT(0)) 79 int isoLevelHig; 80 81 } AblcExpInfo_V32_t; 82 83 typedef struct rk_aiq_blc_info_v32_s { 84 // M4_ARRAY_TABLE_DESC("sync", "array_table_ui", "none", "1") 85 rk_aiq_uapi_sync_t sync; 86 // M4_NUMBER_DESC("iso", "u32", M4_RANGE(0, 204800), "50", M4_DIGIT(0), "0", "0") 87 int iso; 88 // M4_ARRAY_TABLE_DESC("expo_info", "normal_ui_style", "none", "0", "0") 89 AblcExpInfo_V32_t expo_info; 90 } rk_aiq_blc_info_v32_t; 91 92 RKAIQ_END_DECLARE 93 94 #endif 95